Staging: rtl8192e: Code style fix for r819xE_phyreg.h

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Changed all the comments to conform to the standard, aligned register values.

Signed-off-by: Radu Voicilas <rvoicilas@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

authored by

Radu Voicilas and committed by

Greg Kroah-Hartman 16 years ago 1719e119 8f266841

+559 -525

1 changed file

expand all

drivers

staging

rtl8192e

r819xE_phyreg.h

+559 -525

drivers/staging/rtl8192e/r819xE_phyreg.h

··· 81 81 #define rFPGA0_XB_LSSIReadBack 0x8a4 82 82 #define rFPGA0_XC_LSSIReadBack 0x8a8 83 83 #define rFPGA0_XD_LSSIReadBack 0x8ac 84 - #define rFPGA0_PSDReport 0x8b4 84 + #define rFPGA0_PSDReport 0x8b4 85 85 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 86 86 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 87 87 88 - //page 9 89 - #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC 90 - #define rFPGA1_TxBlock 0x904 91 - #define rFPGA1_DebugSelect 0x908 92 - #define rFPGA1_TxInfo 0x90c 88 + /* Page 9 - RF mode & OFDM TxSC */ 89 + #define rFPGA1_RFMOD 0x900 90 + #define rFPGA1_TxBlock 0x904 91 + #define rFPGA1_DebugSelect 0x908 92 + #define rFPGA1_TxInfo 0x90c 93 93 94 - //page a 95 - #define rCCK0_System 0xa00 96 - #define rCCK0_AFESetting 0xa04 97 - #define rCCK0_CCA 0xa08 98 - #define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level 99 - #define rCCK0_RxAGC2 0xa10 //AGC & DAGC 100 - #define rCCK0_RxHP 0xa14 101 - #define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold 102 - #define rCCK0_DSPParameter2 0xa1c //SQ threshold 103 - #define rCCK0_TxFilter1 0xa20 104 - #define rCCK0_TxFilter2 0xa24 105 - #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 106 - #define rCCK0_FalseAlarmReport 0xa2c //0xa2d 107 - #define rCCK0_TRSSIReport 0xa50 108 - #define rCCK0_RxReport 0xa54 //0xa57 109 - #define rCCK0_FACounterLower 0xa5c //0xa5b 110 - #define rCCK0_FACounterUpper 0xa58 //0xa5c 94 + /* Page a */ 95 + #define rCCK0_System 0xa00 96 + #define rCCK0_AFESetting 0xa04 97 + #define rCCK0_CCA 0xa08 98 + /* AGC default value, saturation level */ 99 + #define rCCK0_RxAGC1 0xa0c 100 + /* AGC & DAGC */ 101 + #define rCCK0_RxAGC2 0xa10 102 + #define rCCK0_RxHP 0xa14 103 + /* Timing recovery & channel estimation threshold */ 104 + #define rCCK0_DSPParameter1 0xa18 105 + /* SQ threshold */ 106 + #define rCCK0_DSPParameter2 0xa1c 107 + #define rCCK0_TxFilter1 0xa20 108 + #define rCCK0_TxFilter2 0xa24 109 + /* Debug port and TX filter 3 */ 110 + #define rCCK0_DebugPort 0xa28 111 + #define rCCK0_FalseAlarmReport 0xa2c 112 + #define rCCK0_TRSSIReport 0xa50 113 + #define rCCK0_RxReport 0xa54 114 + #define rCCK0_FACounterLower 0xa5c 115 + #define rCCK0_FACounterUpper 0xa58 111 116 112 - //page c 113 - #define rOFDM0_LSTF 0xc00 117 + /* Page c */ 118 + #define rOFDM0_LSTF 0xc00 114 119 #define rOFDM0_TRxPathEnable 0xc04 115 - #define rOFDM0_TRMuxPar 0xc08 116 - #define rOFDM0_TRSWIsolation 0xc0c 117 - #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter 118 - #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix 119 - #define rOFDM0_XBRxAFE 0xc18 120 + #define rOFDM0_TRMuxPar 0xc08 121 + #define rOFDM0_TRSWIsolation 0xc0c 122 + /* RxIQ DC offset, Rx digital filter, DC notch filter */ 123 + #define rOFDM0_XARxAFE 0xc10 124 + /* RxIQ imblance matrix */ 125 + #define rOFDM0_XARxIQImbalance 0xc14 126 + #define rOFDM0_XBRxAFE 0xc18 120 127 #define rOFDM0_XBRxIQImbalance 0xc1c 121 - #define rOFDM0_XCRxAFE 0xc20 128 + #define rOFDM0_XCRxAFE 0xc20 122 129 #define rOFDM0_XCRxIQImbalance 0xc24 123 - #define rOFDM0_XDRxAFE 0xc28 130 + #define rOFDM0_XDRxAFE 0xc28 124 131 #define rOFDM0_XDRxIQImbalance 0xc2c 125 - #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD 126 - #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. 127 - #define rOFDM0_RxDetector3 0xc38 //Frame Sync. 128 - #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI 129 - #define rOFDM0_RxDSP 0xc40 //Rx Sync Path 130 - #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC 131 - #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold 132 - #define rOFDM0_ECCAThreshold 0xc4c // energy CCA 132 + /* PD, BW & SBD */ 133 + #define rOFDM0_RxDetector1 0xc30 134 + /* SBD */ 135 + #define rOFDM0_RxDetector2 0xc34 136 + /* Frame Sync */ 137 + #define rOFDM0_RxDetector3 0xc38 138 + /* PD, SBD, Frame Sync & Short-GI */ 139 + #define rOFDM0_RxDetector4 0xc3c 140 + /* Rx Sync Path */ 141 + #define rOFDM0_RxDSP 0xc40 142 + /* CFO & DAGC */ 143 + #define rOFDM0_CFOandDAGC 0xc44 144 + /* CCA Drop threshold */ 145 + #define rOFDM0_CCADropThreshold 0xc48 146 + /* Energy CCA */ 147 + #define rOFDM0_ECCAThreshold 0xc4c 133 148 #define rOFDM0_XAAGCCore1 0xc50 134 149 #define rOFDM0_XAAGCCore2 0xc54 135 150 #define rOFDM0_XBAGCCore1 0xc58 ··· 156 141 #define rOFDM0_AGCParameter1 0xc70 157 142 #define rOFDM0_AGCParameter2 0xc74 158 143 #define rOFDM0_AGCRSSITable 0xc78 159 - #define rOFDM0_HTSTFAGC 0xc7c 144 + #define rOFDM0_HTSTFAGC 0xc7c 160 145 #define rOFDM0_XATxIQImbalance 0xc80 161 - #define rOFDM0_XATxAFE 0xc84 146 + #define rOFDM0_XATxAFE 0xc84 162 147 #define rOFDM0_XBTxIQImbalance 0xc88 163 - #define rOFDM0_XBTxAFE 0xc8c 148 + #define rOFDM0_XBTxAFE 0xc8c 164 149 #define rOFDM0_XCTxIQImbalance 0xc90 165 - #define rOFDM0_XCTxAFE 0xc94 150 + #define rOFDM0_XCTxAFE 0xc94 166 151 #define rOFDM0_XDTxIQImbalance 0xc98 167 - #define rOFDM0_XDTxAFE 0xc9c 152 + #define rOFDM0_XDTxAFE 0xc9c 168 153 #define rOFDM0_RxHPParameter 0xce0 169 154 #define rOFDM0_TxPseudoNoiseWgt 0xce4 170 - #define rOFDM0_FrameSync 0xcf0 171 - #define rOFDM0_DFSReport 0xcf4 172 - #define rOFDM0_TxCoeff1 0xca4 173 - #define rOFDM0_TxCoeff2 0xca8 174 - #define rOFDM0_TxCoeff3 0xcac 175 - #define rOFDM0_TxCoeff4 0xcb0 176 - #define rOFDM0_TxCoeff5 0xcb4 177 - #define rOFDM0_TxCoeff6 0xcb8 155 + #define rOFDM0_FrameSync 0xcf0 156 + #define rOFDM0_DFSReport 0xcf4 157 + #define rOFDM0_TxCoeff1 0xca4 158 + #define rOFDM0_TxCoeff2 0xca8 159 + #define rOFDM0_TxCoeff3 0xcac 160 + #define rOFDM0_TxCoeff4 0xcb0 161 + #define rOFDM0_TxCoeff5 0xcb4 162 + #define rOFDM0_TxCoeff6 0xcb8 178 163 179 164 180 - //page d 181 - #define rOFDM1_LSTF 0xd00 165 + /* Page d */ 166 + #define rOFDM1_LSTF 0xd00 182 167 #define rOFDM1_TRxPathEnable 0xd04 183 - #define rOFDM1_CFO 0xd08 184 - #define rOFDM1_CSI1 0xd10 185 - #define rOFDM1_SBD 0xd14 186 - #define rOFDM1_CSI2 0xd18 187 - #define rOFDM1_CFOTracking 0xd2c 168 + #define rOFDM1_CFO 0xd08 169 + #define rOFDM1_CSI1 0xd10 170 + #define rOFDM1_SBD 0xd14 171 + #define rOFDM1_CSI2 0xd18 172 + #define rOFDM1_CFOTracking 0xd2c 188 173 #define rOFDM1_TRxMesaure1 0xd34 189 - #define rOFDM1_IntfDet 0xd3c 190 - #define rOFDM1_PseudoNoiseStateAB 0xd50 191 - #define rOFDM1_PseudoNoiseStateCD 0xd54 192 - #define rOFDM1_RxPseudoNoiseWgt 0xd58 193 - #define rOFDM_PHYCounter1 0xda0 //cca, parity fail 194 - #define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail 195 - #define rOFDM_PHYCounter3 0xda8 //MCS not support 196 - #define rOFDM_ShortCFOAB 0xdac 197 - #define rOFDM_ShortCFOCD 0xdb0 198 - #define rOFDM_LongCFOAB 0xdb4 199 - #define rOFDM_LongCFOCD 0xdb8 200 - #define rOFDM_TailCFOAB 0xdbc 201 - #define rOFDM_TailCFOCD 0xdc0 174 + #define rOFDM1_IntfDet 0xd3c 175 + #define rOFDM1_PseudoNoiseStateAB 0xd50 176 + #define rOFDM1_PseudoNoiseStateCD 0xd54 177 + #define rOFDM1_RxPseudoNoiseWgt 0xd58 178 + /* cca, parity fail */ 179 + #define rOFDM_PHYCounter1 0xda0 180 + /* rate illegal, crc8 fail */ 181 + #define rOFDM_PHYCounter2 0xda4 182 + /* MCS not supported */ 183 + #define rOFDM_PHYCounter3 0xda8 184 + #define rOFDM_ShortCFOAB 0xdac 185 + #define rOFDM_ShortCFOCD 0xdb0 186 + #define rOFDM_LongCFOAB 0xdb4 187 + #define rOFDM_LongCFOCD 0xdb8 188 + #define rOFDM_TailCFOAB 0xdbc 189 + #define rOFDM_TailCFOCD 0xdc0 202 190 #define rOFDM_PWMeasure1 0xdc4 203 191 #define rOFDM_PWMeasure2 0xdc8 204 - #define rOFDM_BWReport 0xdcc 205 - #define rOFDM_AGCReport 0xdd0 206 - #define rOFDM_RxSNR 0xdd4 207 - #define rOFDM_RxEVMCSI 0xdd8 208 - #define rOFDM_SIGReport 0xddc 192 + #define rOFDM_BWReport 0xdcc 193 + #define rOFDM_AGCReport 0xdd0 194 + #define rOFDM_RxSNR 0xdd4 195 + #define rOFDM_RxEVMCSI 0xdd8 196 + #define rOFDM_SIGReport 0xddc 209 197 210 - //page e 211 - #define rTxAGC_Rate18_06 0xe00 212 - #define rTxAGC_Rate54_24 0xe04 213 - #define rTxAGC_CCK_Mcs32 0xe08 214 - #define rTxAGC_Mcs03_Mcs00 0xe10 215 - #define rTxAGC_Mcs07_Mcs04 0xe14 216 - #define rTxAGC_Mcs11_Mcs08 0xe18 217 - #define rTxAGC_Mcs15_Mcs12 0xe1c 198 + /* Page e */ 199 + #define rTxAGC_Rate18_06 0xe00 200 + #define rTxAGC_Rate54_24 0xe04 201 + #define rTxAGC_CCK_Mcs32 0xe08 202 + #define rTxAGC_Mcs03_Mcs00 0xe10 203 + #define rTxAGC_Mcs07_Mcs04 0xe14 204 + #define rTxAGC_Mcs11_Mcs08 0xe18 205 + #define rTxAGC_Mcs15_Mcs12 0xe1c 218 206 219 207 220 - //RF 221 - //Zebra1 208 + /* RF Zebra 1 */ 222 209 #define rZebra1_HSSIEnable 0x0 223 210 #define rZebra1_TRxEnable1 0x1 224 211 #define rZebra1_TRxEnable2 0x2 225 - #define rZebra1_AGC 0x4 212 + #define rZebra1_AGC 0x4 226 213 #define rZebra1_ChargePump 0x5 227 - #define rZebra1_Channel 0x7 228 - #define rZebra1_TxGain 0x8 229 - #define rZebra1_TxLPF 0x9 230 - #define rZebra1_RxLPF 0xb 214 + #define rZebra1_Channel 0x7 215 + #define rZebra1_TxGain 0x8 216 + #define rZebra1_TxLPF 0x9 217 + #define rZebra1_RxLPF 0xb 231 218 #define rZebra1_RxHPFCorner 0xc 232 219 233 - //Zebra4 234 - #define rGlobalCtrl 0 235 - #define rRTL8256_TxLPF 19 236 - #define rRTL8256_RxLPF 11 220 + /* Zebra 4 */ 221 + #define rGlobalCtrl 0 222 + #define rRTL8256_TxLPF 19 223 + #define rRTL8256_RxLPF 11 237 224 238 - //RTL8258 239 - #define rRTL8258_TxLPF 0x11 240 - #define rRTL8258_RxLPF 0x13 225 + /* RTL8258 */ 226 + #define rRTL8258_TxLPF 0x11 227 + #define rRTL8258_RxLPF 0x13 241 228 #define rRTL8258_RSSILPF 0xa 242 229 243 - //Bit Mask 244 - //page-1 245 - #define bBBResetB 0x100 246 - #define bGlobalResetB 0x200 247 - #define bOFDMTxStart 0x4 248 - #define bCCKTxStart 0x8 249 - #define bCRC32Debug 0x100 250 - #define bPMACLoopback 0x10 251 - #define bTxLSIG 0xffffff 252 - #define bOFDMTxRate 0xf 253 - #define bOFDMTxReserved 0x10 254 - #define bOFDMTxLength 0x1ffe0 255 - #define bOFDMTxParity 0x20000 256 - #define bTxHTSIG1 0xffffff 257 - #define bTxHTMCSRate 0x7f 258 - #define bTxHTBW 0x80 259 - #define bTxHTLength 0xffff00 260 - #define bTxHTSIG2 0xffffff 261 - #define bTxHTSmoothing 0x1 262 - #define bTxHTSounding 0x2 263 - #define bTxHTReserved 0x4 264 - #define bTxHTAggreation 0x8 265 - #define bTxHTSTBC 0x30 266 - #define bTxHTAdvanceCoding 0x40 267 - #define bTxHTShortGI 0x80 268 - #define bTxHTNumberHT_LTF 0x300 269 - #define bTxHTCRC8 0x3fc00 270 - #define bCounterReset 0x10000 271 - #define bNumOfOFDMTx 0xffff 272 - #define bNumOfCCKTx 0xffff0000 273 - #define bTxIdleInterval 0xffff 274 - #define bOFDMService 0xffff0000 275 - #define bTxMACHeader 0xffffffff 276 - #define bTxDataInit 0xff 277 - #define bTxHTMode 0x100 278 - #define bTxDataType 0x30000 279 - #define bTxRandomSeed 0xffffffff 280 - #define bCCKTxPreamble 0x1 281 - #define bCCKTxSFD 0xffff0000 282 - #define bCCKTxSIG 0xff 283 - #define bCCKTxService 0xff00 284 - #define bCCKLengthExt 0x8000 285 - #define bCCKTxLength 0xffff0000 286 - #define bCCKTxCRC16 0xffff 287 - #define bCCKTxStatus 0x1 288 - #define bOFDMTxStatus 0x2 230 + /* Bit Mask */ 231 + /* Page 1 */ 232 + #define bBBResetB 0x100 233 + #define bGlobalResetB 0x200 234 + #define bOFDMTxStart 0x4 235 + #define bCCKTxStart 0x8 236 + #define bCRC32Debug 0x100 237 + #define bPMACLoopback 0x10 238 + #define bTxLSIG 0xffffff 239 + #define bOFDMTxRate 0xf 240 + #define bOFDMTxReserved 0x10 241 + #define bOFDMTxLength 0x1ffe0 242 + #define bOFDMTxParity 0x20000 243 + #define bTxHTSIG1 0xffffff 244 + #define bTxHTMCSRate 0x7f 245 + #define bTxHTBW 0x80 246 + #define bTxHTLength 0xffff00 247 + #define bTxHTSIG2 0xffffff 248 + #define bTxHTSmoothing 0x1 249 + #define bTxHTSounding 0x2 250 + #define bTxHTReserved 0x4 251 + #define bTxHTAggreation 0x8 252 + #define bTxHTSTBC 0x30 253 + #define bTxHTAdvanceCoding 0x40 254 + #define bTxHTShortGI 0x80 255 + #define bTxHTNumberHT_LTF 0x300 256 + #define bTxHTCRC8 0x3fc00 257 + #define bCounterReset 0x10000 258 + #define bNumOfOFDMTx 0xffff 259 + #define bNumOfCCKTx 0xffff0000 260 + #define bTxIdleInterval 0xffff 261 + #define bOFDMService 0xffff0000 262 + #define bTxMACHeader 0xffffffff 263 + #define bTxDataInit 0xff 264 + #define bTxHTMode 0x100 265 + #define bTxDataType 0x30000 266 + #define bTxRandomSeed 0xffffffff 267 + #define bCCKTxPreamble 0x1 268 + #define bCCKTxSFD 0xffff0000 269 + #define bCCKTxSIG 0xff 270 + #define bCCKTxService 0xff00 271 + #define bCCKLengthExt 0x8000 272 + #define bCCKTxLength 0xffff0000 273 + #define bCCKTxCRC16 0xffff 274 + #define bCCKTxStatus 0x1 275 + #define bOFDMTxStatus 0x2 289 276 290 - //page-8 291 - #define bRFMOD 0x1 292 - #define bJapanMode 0x2 293 - #define bCCKTxSC 0x30 294 - #define bCCKEn 0x1000000 295 - #define bOFDMEn 0x2000000 296 - #define bOFDMRxADCPhase 0x10000 297 - #define bOFDMTxDACPhase 0x40000 298 - #define bXATxAGC 0x3f 299 - #define bXBTxAGC 0xf00 300 - #define bXCTxAGC 0xf000 301 - #define bXDTxAGC 0xf0000 302 - #define bPAStart 0xf0000000 303 - #define bTRStart 0x00f00000 304 - #define bRFStart 0x0000f000 305 - #define bBBStart 0x000000f0 306 - #define bBBCCKStart 0x0000000f 307 - #define bPAEnd 0xf //Reg0x814 308 - #define bTREnd 0x0f000000 309 - #define bRFEnd 0x000f0000 310 - #define bCCAMask 0x000000f0 //T2R 311 - #define bR2RCCAMask 0x00000f00 312 - #define bHSSI_R2TDelay 0xf8000000 313 - #define bHSSI_T2RDelay 0xf80000 314 - #define bContTxHSSI 0x400 //channel gain at continue Tx 315 - #define bIGFromCCK 0x200 316 - #define bAGCAddress 0x3f 317 - #define bRxHPTx 0x7000 318 - #define bRxHPT2R 0x38000 319 - #define bRxHPCCKIni 0xc0000 320 - #define bAGCTxCode 0xc00000 321 - #define bAGCRxCode 0x300000 322 - #define b3WireDataLength 0x800 323 - #define b3WireAddressLength 0x400 324 - #define b3WireRFPowerDown 0x1 325 - //#define bHWSISelect 0x8 326 - #define b5GPAPEPolarity 0x40000000 327 - #define b2GPAPEPolarity 0x80000000 328 - #define bRFSW_TxDefaultAnt 0x3 329 - #define bRFSW_TxOptionAnt 0x30 330 - #define bRFSW_RxDefaultAnt 0x300 331 - #define bRFSW_RxOptionAnt 0x3000 332 - #define bRFSI_3WireData 0x1 333 - #define bRFSI_3WireClock 0x2 334 - #define bRFSI_3WireLoad 0x4 335 - #define bRFSI_3WireRW 0x8 336 - #define bRFSI_3Wire 0xf //3-wire total control 337 - #define bRFSI_RFENV 0x10 338 - #define bRFSI_TRSW 0x20 339 - #define bRFSI_TRSWB 0x40 340 - #define bRFSI_ANTSW 0x100 341 - #define bRFSI_ANTSWB 0x200 342 - #define bRFSI_PAPE 0x400 343 - #define bRFSI_PAPE5G 0x800 344 - #define bBandSelect 0x1 345 - #define bHTSIG2_GI 0x80 346 - #define bHTSIG2_Smoothing 0x01 347 - #define bHTSIG2_Sounding 0x02 348 - #define bHTSIG2_Aggreaton 0x08 349 - #define bHTSIG2_STBC 0x30 350 - #define bHTSIG2_AdvCoding 0x40 277 + /* Page 8 */ 278 + #define bRFMOD 0x1 279 + #define bJapanMode 0x2 280 + #define bCCKTxSC 0x30 281 + #define bCCKEn 0x1000000 282 + #define bOFDMEn 0x2000000 283 + #define bOFDMRxADCPhase 0x10000 284 + #define bOFDMTxDACPhase 0x40000 285 + #define bXATxAGC 0x3f 286 + #define bXBTxAGC 0xf00 287 + #define bXCTxAGC 0xf000 288 + #define bXDTxAGC 0xf0000 289 + #define bPAStart 0xf0000000 290 + #define bTRStart 0x00f00000 291 + #define bRFStart 0x0000f000 292 + #define bBBStart 0x000000f0 293 + #define bBBCCKStart 0x0000000f 294 + /* Reg)x814 */ 295 + #define bPAEnd 0xf 296 + #define bTREnd 0x0f000000 297 + #define bRFEnd 0x000f0000 298 + /* T2R */ 299 + #define bCCAMask 0x000000f0 300 + #define bR2RCCAMask 0x00000f00 301 + #define bHSSI_R2TDelay 0xf8000000 302 + #define bHSSI_T2RDelay 0xf80000 303 + /* Channel gain at continue TX. */ 304 + #define bContTxHSSI 0x400 305 + #define bIGFromCCK 0x200 306 + #define bAGCAddress 0x3f 307 + #define bRxHPTx 0x7000 308 + #define bRxHPT2R 0x38000 309 + #define bRxHPCCKIni 0xc0000 310 + #define bAGCTxCode 0xc00000 311 + #define bAGCRxCode 0x300000 312 + #define b3WireDataLength 0x800 313 + #define b3WireAddressLength 0x400 314 + #define b3WireRFPowerDown 0x1 315 + /*#define bHWSISelect 0x8 */ 316 + #define b5GPAPEPolarity 0x40000000 317 + #define b2GPAPEPolarity 0x80000000 318 + #define bRFSW_TxDefaultAnt 0x3 319 + #define bRFSW_TxOptionAnt 0x30 320 + #define bRFSW_RxDefaultAnt 0x300 321 + #define bRFSW_RxOptionAnt 0x3000 322 + #define bRFSI_3WireData 0x1 323 + #define bRFSI_3WireClock 0x2 324 + #define bRFSI_3WireLoad 0x4 325 + #define bRFSI_3WireRW 0x8 326 + /* 3-wire total control */ 327 + #define bRFSI_3Wire 0xf 328 + #define bRFSI_RFENV 0x10 329 + #define bRFSI_TRSW 0x20 330 + #define bRFSI_TRSWB 0x40 331 + #define bRFSI_ANTSW 0x100 332 + #define bRFSI_ANTSWB 0x200 333 + #define bRFSI_PAPE 0x400 334 + #define bRFSI_PAPE5G 0x800 335 + #define bBandSelect 0x1 336 + #define bHTSIG2_GI 0x80 337 + #define bHTSIG2_Smoothing 0x01 338 + #define bHTSIG2_Sounding 0x02 339 + #define bHTSIG2_Aggreaton 0x08 340 + #define bHTSIG2_STBC 0x30 341 + #define bHTSIG2_AdvCoding 0x40 351 342 #define bHTSIG2_NumOfHTLTF 0x300 352 - #define bHTSIG2_CRC8 0x3fc 353 - #define bHTSIG1_MCS 0x7f 354 - #define bHTSIG1_BandWidth 0x80 355 - #define bHTSIG1_HTLength 0xffff 356 - #define bLSIG_Rate 0xf 357 - #define bLSIG_Reserved 0x10 358 - #define bLSIG_Length 0x1fffe 359 - #define bLSIG_Parity 0x20 360 - #define bCCKRxPhase 0x4 361 - #define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address 362 - #define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal 363 - #define bLSSIReadBackData 0xfff 364 - #define bLSSIReadOKFlag 0x1000 365 - #define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz 343 + #define bHTSIG2_CRC8 0x3fc 344 + #define bHTSIG1_MCS 0x7f 345 + #define bHTSIG1_BandWidth 0x80 346 + #define bHTSIG1_HTLength 0xffff 347 + #define bLSIG_Rate 0xf 348 + #define bLSIG_Reserved 0x10 349 + #define bLSIG_Length 0x1fffe 350 + #define bLSIG_Parity 0x20 351 + #define bCCKRxPhase 0x4 352 + /* LSSI "read" address */ 353 + #define bLSSIReadAddress 0x3f000000 354 + /* LSSI "read" edge signal */ 355 + #define bLSSIReadEdge 0x80000000 356 + #define bLSSIReadBackData 0xfff 357 + #define bLSSIReadOKFlag 0x1000 358 + /* 0: 44 MHz, 1: 88MHz */ 359 + #define bCCKSampleRate 0x8 366 360 367 - #define bRegulator0Standby 0x1 368 - #define bRegulatorPLLStandby 0x2 369 - #define bRegulator1Standby 0x4 370 - #define bPLLPowerUp 0x8 371 - #define bDPLLPowerUp 0x10 372 - #define bDA10PowerUp 0x20 373 - #define bAD7PowerUp 0x200 374 - #define bDA6PowerUp 0x2000 375 - #define bXtalPowerUp 0x4000 376 - #define b40MDClkPowerUP 0x8000 377 - #define bDA6DebugMode 0x20000 378 - #define bDA6Swing 0x380000 379 - #define bADClkPhase 0x4000000 380 - #define b80MClkDelay 0x18000000 381 - #define bAFEWatchDogEnable 0x20000000 382 - #define bXtalCap 0x0f000000 383 - #define bXtalCap01 0xc0000000 384 - #define bXtalCap23 0x3 385 - #define bXtalCap92x 0x0f000000 386 - #define bIntDifClkEnable 0x400 387 - #define bExtSigClkEnable 0x800 361 + #define bRegulator0Standby 0x1 362 + #define bRegulatorPLLStandby 0x2 363 + #define bRegulator1Standby 0x4 364 + #define bPLLPowerUp 0x8 365 + #define bDPLLPowerUp 0x10 366 + #define bDA10PowerUp 0x20 367 + #define bAD7PowerUp 0x200 368 + #define bDA6PowerUp 0x2000 369 + #define bXtalPowerUp 0x4000 370 + #define b40MDClkPowerUP 0x8000 371 + #define bDA6DebugMode 0x20000 372 + #define bDA6Swing 0x380000 373 + #define bADClkPhase 0x4000000 374 + #define b80MClkDelay 0x18000000 375 + #define bAFEWatchDogEnable 0x20000000 376 + #define bXtalCap 0x0f000000 377 + #define bXtalCap01 0xc0000000 378 + #define bXtalCap23 0x3 379 + #define bXtalCap92x 0x0f000000 380 + #define bIntDifClkEnable 0x400 381 + #define bExtSigClkEnable 0x800 388 382 #define bBandgapMbiasPowerUp 0x10000 389 - #define bAD11SHGain 0xc0000 390 - #define bAD11InputRange 0x700000 391 - #define bAD11OPCurrent 0x3800000 392 - #define bIPathLoopback 0x4000000 393 - #define bQPathLoopback 0x8000000 394 - #define bAFELoopback 0x10000000 395 - #define bDA10Swing 0x7e0 396 - #define bDA10Reverse 0x800 397 - #define bDAClkSource 0x1000 398 - #define bAD7InputRange 0x6000 399 - #define bAD7Gain 0x38000 400 - #define bAD7OutputCMMode 0x40000 401 - #define bAD7InputCMMode 0x380000 402 - #define bAD7Current 0xc00000 403 - #define bRegulatorAdjust 0x7000000 404 - #define bAD11PowerUpAtTx 0x1 405 - #define bDA10PSAtTx 0x10 406 - #define bAD11PowerUpAtRx 0x100 407 - #define bDA10PSAtRx 0x1000 383 + #define bAD11SHGain 0xc0000 384 + #define bAD11InputRange 0x700000 385 + #define bAD11OPCurrent 0x3800000 386 + #define bIPathLoopback 0x4000000 387 + #define bQPathLoopback 0x8000000 388 + #define bAFELoopback 0x10000000 389 + #define bDA10Swing 0x7e0 390 + #define bDA10Reverse 0x800 391 + #define bDAClkSource 0x1000 392 + #define bAD7InputRange 0x6000 393 + #define bAD7Gain 0x38000 394 + #define bAD7OutputCMMode 0x40000 395 + #define bAD7InputCMMode 0x380000 396 + #define bAD7Current 0xc00000 397 + #define bRegulatorAdjust 0x7000000 398 + #define bAD11PowerUpAtTx 0x1 399 + #define bDA10PSAtTx 0x10 400 + #define bAD11PowerUpAtRx 0x100 401 + #define bDA10PSAtRx 0x1000 408 402 409 - #define bCCKRxAGCFormat 0x200 403 + #define bCCKRxAGCFormat 0x200 410 404 411 - #define bPSDFFTSamplepPoint 0xc000 412 - #define bPSDAverageNum 0x3000 413 - #define bIQPathControl 0xc00 414 - #define bPSDFreq 0x3ff 415 - #define bPSDAntennaPath 0x30 416 - #define bPSDIQSwitch 0x40 417 - #define bPSDRxTrigger 0x400000 418 - #define bPSDTxTrigger 0x80000000 419 - #define bPSDSineToneScale 0x7f000000 420 - #define bPSDReport 0xffff 405 + #define bPSDFFTSamplepPoint 0xc000 406 + #define bPSDAverageNum 0x3000 407 + #define bIQPathControl 0xc00 408 + #define bPSDFreq 0x3ff 409 + #define bPSDAntennaPath 0x30 410 + #define bPSDIQSwitch 0x40 411 + #define bPSDRxTrigger 0x400000 412 + #define bPSDTxTrigger 0x80000000 413 + #define bPSDSineToneScale 0x7f000000 414 + #define bPSDReport 0xffff 421 415 422 - //page-9 423 - #define bOFDMTxSC 0x30000000 424 - #define bCCKTxOn 0x1 425 - #define bOFDMTxOn 0x2 426 - #define bDebugPage 0xfff //reset debug page and also HWord, LWord 427 - #define bDebugItem 0xff //reset debug page and LWord 428 - #define bAntL 0x10 429 - #define bAntNonHT 0x100 430 - #define bAntHT1 0x1000 431 - #define bAntHT2 0x10000 432 - #define bAntHT1S1 0x100000 433 - #define bAntNonHTS1 0x1000000 416 + /* Page 8 */ 417 + #define bOFDMTxSC 0x30000000 418 + #define bCCKTxOn 0x1 419 + #define bOFDMTxOn 0x2 420 + /* Reset debug page and also HWord, LWord */ 421 + #define bDebugPage 0xfff 422 + /* Reset debug page and LWord */ 423 + #define bDebugItem 0xff 424 + #define bAntL 0x10 425 + #define bAntNonHT 0x100 426 + #define bAntHT1 0x1000 427 + #define bAntHT2 0x10000 428 + #define bAntHT1S1 0x100000 429 + #define bAntNonHTS1 0x1000000 434 430 435 - //page-a 436 - #define bCCKBBMode 0x3 437 - #define bCCKTxPowerSaving 0x80 438 - #define bCCKRxPowerSaving 0x40 439 - #define bCCKSideBand 0x10 440 - #define bCCKScramble 0x8 441 - #define bCCKAntDiversity 0x8000 431 + /* Page a */ 432 + #define bCCKBBMode 0x3 433 + #define bCCKTxPowerSaving 0x80 434 + #define bCCKRxPowerSaving 0x40 435 + #define bCCKSideBand 0x10 436 + #define bCCKScramble 0x8 437 + #define bCCKAntDiversity 0x8000 442 438 #define bCCKCarrierRecovery 0x4000 443 - #define bCCKTxRate 0x3000 444 - #define bCCKDCCancel 0x0800 445 - #define bCCKISICancel 0x0400 446 - #define bCCKMatchFilter 0x0200 447 - #define bCCKEqualizer 0x0100 448 - #define bCCKPreambleDetect 0x800000 449 - #define bCCKFastFalseCCA 0x400000 450 - #define bCCKChEstStart 0x300000 451 - #define bCCKCCACount 0x080000 452 - #define bCCKcs_lim 0x070000 453 - #define bCCKBistMode 0x80000000 454 - #define bCCKCCAMask 0x40000000 439 + #define bCCKTxRate 0x3000 440 + #define bCCKDCCancel 0x0800 441 + #define bCCKISICancel 0x0400 442 + #define bCCKMatchFilter 0x0200 443 + #define bCCKEqualizer 0x0100 444 + #define bCCKPreambleDetect 0x800000 445 + #define bCCKFastFalseCCA 0x400000 446 + #define bCCKChEstStart 0x300000 447 + #define bCCKCCACount 0x080000 448 + #define bCCKcs_lim 0x070000 449 + #define bCCKBistMode 0x80000000 450 + #define bCCKCCAMask 0x40000000 455 451 #define bCCKTxDACPhase 0x4 456 - #define bCCKRxADCPhase 0x20000000 //r_rx_clk 452 + /* r_rx_clk */ 453 + #define bCCKRxADCPhase 0x20000000 457 454 #define bCCKr_cp_mode0 0x0100 458 - #define bCCKTxDCOffset 0xf0 459 - #define bCCKRxDCOffset 0xf 460 - #define bCCKCCAMode 0xc000 461 - #define bCCKFalseCS_lim 0x3f00 462 - #define bCCKCS_ratio 0xc00000 463 - #define bCCKCorgBit_sel 0x300000 464 - #define bCCKPD_lim 0x0f0000 465 - #define bCCKNewCCA 0x80000000 466 - #define bCCKRxHPofIG 0x8000 467 - #define bCCKRxIG 0x7f00 468 - #define bCCKLNAPolarity 0x800000 469 - #define bCCKRx1stGain 0x7f0000 470 - #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity 471 - #define bCCKRxAGCSatLevel 0x1f000000 472 - #define bCCKRxAGCSatCount 0xe0 473 - #define bCCKRxRFSettle 0x1f //AGCsamp_dly 474 - #define bCCKFixedRxAGC 0x8000 475 - //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 476 - #define bCCKAntennaPolarity 0x2000 477 - #define bCCKTxFilterType 0x0c00 455 + #define bCCKTxDCOffset 0xf0 456 + #define bCCKRxDCOffset 0xf 457 + #define bCCKCCAMode 0xc000 458 + #define bCCKFalseCS_lim 0x3f00 459 + #define bCCKCS_ratio 0xc00000 460 + #define bCCKCorgBit_sel 0x300000 461 + #define bCCKPD_lim 0x0f0000 462 + #define bCCKNewCCA 0x80000000 463 + #define bCCKRxHPofIG 0x8000 464 + #define bCCKRxIG 0x7f00 465 + #define bCCKLNAPolarity 0x800000 466 + #define bCCKRx1stGain 0x7f0000 467 + /* CCK Rx Initial gain polarity */ 468 + #define bCCKRFExtend 0x20000000 469 + #define bCCKRxAGCSatLevel 0x1f000000 470 + #define bCCKRxAGCSatCount 0xe0 471 + /* AGCSAmp_dly */ 472 + #define bCCKRxRFSettle 0x1f 473 + #define bCCKFixedRxAGC 0x8000 474 + /*#define bCCKRxAGCFormat 0x4000 remove to HSSI register 0x824 */ 475 + #define bCCKAntennaPolarity 0x2000 476 + #define bCCKTxFilterType 0x0c00 478 477 #define bCCKRxAGCReportType 0x0300 479 - #define bCCKRxDAGCEn 0x80000000 480 - #define bCCKRxDAGCPeriod 0x20000000 478 + #define bCCKRxDAGCEn 0x80000000 479 + #define bCCKRxDAGCPeriod 0x20000000 481 480 #define bCCKRxDAGCSatLevel 0x1f000000 482 - #define bCCKTimingRecovery 0x800000 483 - #define bCCKTxC0 0x3f0000 484 - #define bCCKTxC1 0x3f000000 485 - #define bCCKTxC2 0x3f 486 - #define bCCKTxC3 0x3f00 487 - #define bCCKTxC4 0x3f0000 488 - #define bCCKTxC5 0x3f000000 489 - #define bCCKTxC6 0x3f 490 - #define bCCKTxC7 0x3f00 491 - #define bCCKDebugPort 0xff0000 492 - #define bCCKDACDebug 0x0f000000 493 - #define bCCKFalseAlarmEnable 0x8000 494 - #define bCCKFalseAlarmRead 0x4000 495 - #define bCCKTRSSI 0x7f 496 - #define bCCKRxAGCReport 0xfe 497 - #define bCCKRxReport_AntSel 0x80000000 498 - #define bCCKRxReport_MFOff 0x40000000 481 + #define bCCKTimingRecovery 0x800000 482 + #define bCCKTxC0 0x3f0000 483 + #define bCCKTxC1 0x3f000000 484 + #define bCCKTxC2 0x3f 485 + #define bCCKTxC3 0x3f00 486 + #define bCCKTxC4 0x3f0000 487 + #define bCCKTxC5 0x3f000000 488 + #define bCCKTxC6 0x3f 489 + #define bCCKTxC7 0x3f00 490 + #define bCCKDebugPort 0xff0000 491 + #define bCCKDACDebug 0x0f000000 492 + #define bCCKFalseAlarmEnable 0x8000 493 + #define bCCKFalseAlarmRead 0x4000 494 + #define bCCKTRSSI 0x7f 495 + #define bCCKRxAGCReport 0xfe 496 + #define bCCKRxReport_AntSel 0x80000000 497 + #define bCCKRxReport_MFOff 0x40000000 499 498 #define bCCKRxRxReport_SQLoss 0x20000000 500 - #define bCCKRxReport_Pktloss 0x10000000 499 + #define bCCKRxReport_Pktloss 0x10000000 501 500 #define bCCKRxReport_Lockedbit 0x08000000 502 501 #define bCCKRxReport_RateError 0x04000000 503 - #define bCCKRxReport_RxRate 0x03000000 502 + #define bCCKRxReport_RxRate 0x03000000 504 503 #define bCCKRxFACounterLower 0xff 505 504 #define bCCKRxFACounterUpper 0xff000000 506 - #define bCCKRxHPAGCStart 0xe000 507 - #define bCCKRxHPAGCFinal 0x1c00 505 + #define bCCKRxHPAGCStart 0xe000 506 + #define bCCKRxHPAGCFinal 0x1c00 508 507 509 508 #define bCCKRxFalseAlarmEnable 0x8000 510 - #define bCCKFACounterFreeze 0x4000 509 + #define bCCKFACounterFreeze 0x4000 511 510 512 - #define bCCKTxPathSel 0x10000000 513 - #define bCCKDefaultRxPath 0xc000000 514 - #define bCCKOptionRxPath 0x3000000 511 + #define bCCKTxPathSel 0x10000000 512 + #define bCCKDefaultRxPath 0xc000000 513 + #define bCCKOptionRxPath 0x3000000 515 514 516 - //page c 517 - #define bNumOfSTF 0x3 518 - #define bShift_L 0xc0 519 - #define bGI_TH 0xc 520 - #define bRxPathA 0x1 521 - #define bRxPathB 0x2 522 - #define bRxPathC 0x4 523 - #define bRxPathD 0x8 524 - #define bTxPathA 0x1 525 - #define bTxPathB 0x2 526 - #define bTxPathC 0x4 527 - #define bTxPathD 0x8 528 - #define bTRSSIFreq 0x200 529 - #define bADCBackoff 0x3000 530 - #define bDFIRBackoff 0xc000 531 - #define bTRSSILatchPhase 0x10000 532 - #define bRxIDCOffset 0xff 533 - #define bRxQDCOffset 0xff00 534 - #define bRxDFIRMode 0x1800000 535 - #define bRxDCNFType 0xe000000 536 - #define bRXIQImb_A 0x3ff 537 - #define bRXIQImb_B 0xfc00 538 - #define bRXIQImb_C 0x3f0000 539 - #define bRXIQImb_D 0xffc00000 540 - #define bDC_dc_Notch 0x60000 541 - #define bRxNBINotch 0x1f000000 542 - #define bPD_TH 0xf 543 - #define bPD_TH_Opt2 0xc000 544 - #define bPWED_TH 0x700 545 - #define bIfMF_Win_L 0x800 546 - #define bPD_Option 0x1000 547 - #define bMF_Win_L 0xe000 548 - #define bBW_Search_L 0x30000 549 - #define bwin_enh_L 0xc0000 550 - #define bBW_TH 0x700000 551 - #define bED_TH2 0x3800000 552 - #define bBW_option 0x4000000 553 - #define bRatio_TH 0x18000000 554 - #define bWindow_L 0xe0000000 555 - #define bSBD_Option 0x1 556 - #define bFrame_TH 0x1c 557 - #define bFS_Option 0x60 558 - #define bDC_Slope_check 0x80 559 - #define bFGuard_Counter_DC_L 0xe00 560 - #define bFrame_Weight_Short 0x7000 561 - #define bSub_Tune 0xe00000 562 - #define bFrame_DC_Length 0xe000000 563 - #define bSBD_start_offset 0x30000000 564 - #define bFrame_TH_2 0x7 565 - #define bFrame_GI2_TH 0x38 566 - #define bGI2_Sync_en 0x40 567 - #define bSarch_Short_Early 0x300 568 - #define bSarch_Short_Late 0xc00 569 - #define bSarch_GI2_Late 0x70000 570 - #define bCFOAntSum 0x1 571 - #define bCFOAcc 0x2 572 - #define bCFOStartOffset 0xc 573 - #define bCFOLookBack 0x70 574 - #define bCFOSumWeight 0x80 575 - #define bDAGCEnable 0x10000 576 - #define bTXIQImb_A 0x3ff 577 - #define bTXIQImb_B 0xfc00 578 - #define bTXIQImb_C 0x3f0000 579 - #define bTXIQImb_D 0xffc00000 580 - #define bTxIDCOffset 0xff 581 - #define bTxQDCOffset 0xff00 582 - #define bTxDFIRMode 0x10000 583 - #define bTxPesudoNoiseOn 0x4000000 584 - #define bTxPesudoNoise_A 0xff 585 - #define bTxPesudoNoise_B 0xff00 586 - #define bTxPesudoNoise_C 0xff0000 587 - #define bTxPesudoNoise_D 0xff000000 588 - #define bCCADropOption 0x20000 589 - #define bCCADropThres 0xfff00000 590 - #define bEDCCA_H 0xf 591 - #define bEDCCA_L 0xf0 592 - #define bLambda_ED 0x300 593 - #define bRxInitialGain 0x7f 594 - #define bRxAntDivEn 0x80 595 - #define bRxAGCAddressForLNA 0x7f00 596 - #define bRxHighPowerFlow 0x8000 597 - #define bRxAGCFreezeThres 0xc0000 598 - #define bRxFreezeStep_AGC1 0x300000 599 - #define bRxFreezeStep_AGC2 0xc00000 600 - #define bRxFreezeStep_AGC3 0x3000000 601 - #define bRxFreezeStep_AGC0 0xc000000 602 - #define bRxRssi_Cmp_En 0x10000000 603 - #define bRxQuickAGCEn 0x20000000 604 - #define bRxAGCFreezeThresMode 0x40000000 605 - #define bRxOverFlowCheckType 0x80000000 606 - #define bRxAGCShift 0x7f 607 - #define bTRSW_Tri_Only 0x80 608 - #define bPowerThres 0x300 609 - #define bRxAGCEn 0x1 610 - #define bRxAGCTogetherEn 0x2 611 - #define bRxAGCMin 0x4 612 - #define bRxHP_Ini 0x7 613 - #define bRxHP_TRLNA 0x70 614 - #define bRxHP_RSSI 0x700 615 - #define bRxHP_BBP1 0x7000 616 - #define bRxHP_BBP2 0x70000 617 - #define bRxHP_BBP3 0x700000 618 - #define bRSSI_H 0x7f0000 //the threshold for high power 619 - #define bRSSI_Gen 0x7f000000 //the threshold for ant diversity 620 - #define bRxSettle_TRSW 0x7 621 - #define bRxSettle_LNA 0x38 622 - #define bRxSettle_RSSI 0x1c0 623 - #define bRxSettle_BBP 0xe00 624 - #define bRxSettle_RxHP 0x7000 625 - #define bRxSettle_AntSW_RSSI 0x38000 626 - #define bRxSettle_AntSW 0xc0000 627 - #define bRxProcessTime_DAGC 0x300000 628 - #define bRxSettle_HSSI 0x400000 629 - #define bRxProcessTime_BBPPW 0x800000 630 - #define bRxAntennaPowerShift 0x3000000 631 - #define bRSSITableSelect 0xc000000 632 - #define bRxHP_Final 0x7000000 633 - #define bRxHTSettle_BBP 0x7 634 - #define bRxHTSettle_HSSI 0x8 635 - #define bRxHTSettle_RxHP 0x70 636 - #define bRxHTSettle_BBPPW 0x80 637 - #define bRxHTSettle_Idle 0x300 638 - #define bRxHTSettle_Reserved 0x1c00 639 - #define bRxHTRxHPEn 0x8000 640 - #define bRxHTAGCFreezeThres 0x30000 641 - #define bRxHTAGCTogetherEn 0x40000 642 - #define bRxHTAGCMin 0x80000 643 - #define bRxHTAGCEn 0x100000 644 - #define bRxHTDAGCEn 0x200000 645 - #define bRxHTRxHP_BBP 0x1c00000 646 - #define bRxHTRxHP_Final 0xe0000000 647 - #define bRxPWRatioTH 0x3 648 - #define bRxPWRatioEn 0x4 649 - #define bRxMFHold 0x3800 650 - #define bRxPD_Delay_TH1 0x38 651 - #define bRxPD_Delay_TH2 0x1c0 652 - #define bRxPD_DC_COUNT_MAX 0x600 653 - //#define bRxMF_Hold 0x3800 515 + /* Page c */ 516 + #define bNumOfSTF 0x3 517 + #define bShift_L 0xc0 518 + #define bGI_TH 0xc 519 + #define bRxPathA 0x1 520 + #define bRxPathB 0x2 521 + #define bRxPathC 0x4 522 + #define bRxPathD 0x8 523 + #define bTxPathA 0x1 524 + #define bTxPathB 0x2 525 + #define bTxPathC 0x4 526 + #define bTxPathD 0x8 527 + #define bTRSSIFreq 0x200 528 + #define bADCBackoff 0x3000 529 + #define bDFIRBackoff 0xc000 530 + #define bTRSSILatchPhase 0x10000 531 + #define bRxIDCOffset 0xff 532 + #define bRxQDCOffset 0xff00 533 + #define bRxDFIRMode 0x1800000 534 + #define bRxDCNFType 0xe000000 535 + #define bRXIQImb_A 0x3ff 536 + #define bRXIQImb_B 0xfc00 537 + #define bRXIQImb_C 0x3f0000 538 + #define bRXIQImb_D 0xffc00000 539 + #define bDC_dc_Notch 0x60000 540 + #define bRxNBINotch 0x1f000000 541 + #define bPD_TH 0xf 542 + #define bPD_TH_Opt2 0xc000 543 + #define bPWED_TH 0x700 544 + #define bIfMF_Win_L 0x800 545 + #define bPD_Option 0x1000 546 + #define bMF_Win_L 0xe000 547 + #define bBW_Search_L 0x30000 548 + #define bwin_enh_L 0xc0000 549 + #define bBW_TH 0x700000 550 + #define bED_TH2 0x3800000 551 + #define bBW_option 0x4000000 552 + #define bRatio_TH 0x18000000 553 + #define bWindow_L 0xe0000000 554 + #define bSBD_Option 0x1 555 + #define bFrame_TH 0x1c 556 + #define bFS_Option 0x60 557 + #define bDC_Slope_check 0x80 558 + #define bFGuard_Counter_DC_L 0xe00 559 + #define bFrame_Weight_Short 0x7000 560 + #define bSub_Tune 0xe00000 561 + #define bFrame_DC_Length 0xe000000 562 + #define bSBD_start_offset 0x30000000 563 + #define bFrame_TH_2 0x7 564 + #define bFrame_GI2_TH 0x38 565 + #define bGI2_Sync_en 0x40 566 + #define bSarch_Short_Early 0x300 567 + #define bSarch_Short_Late 0xc00 568 + #define bSarch_GI2_Late 0x70000 569 + #define bCFOAntSum 0x1 570 + #define bCFOAcc 0x2 571 + #define bCFOStartOffset 0xc 572 + #define bCFOLookBack 0x70 573 + #define bCFOSumWeight 0x80 574 + #define bDAGCEnable 0x10000 575 + #define bTXIQImb_A 0x3ff 576 + #define bTXIQImb_B 0xfc00 577 + #define bTXIQImb_C 0x3f0000 578 + #define bTXIQImb_D 0xffc00000 579 + #define bTxIDCOffset 0xff 580 + #define bTxQDCOffset 0xff00 581 + #define bTxDFIRMode 0x10000 582 + #define bTxPesudoNoiseOn 0x4000000 583 + #define bTxPesudoNoise_A 0xff 584 + #define bTxPesudoNoise_B 0xff00 585 + #define bTxPesudoNoise_C 0xff0000 586 + #define bTxPesudoNoise_D 0xff000000 587 + #define bCCADropOption 0x20000 588 + #define bCCADropThres 0xfff00000 589 + #define bEDCCA_H 0xf 590 + #define bEDCCA_L 0xf0 591 + #define bLambda_ED 0x300 592 + #define bRxInitialGain 0x7f 593 + #define bRxAntDivEn 0x80 594 + #define bRxAGCAddressForLNA 0x7f00 595 + #define bRxHighPowerFlow 0x8000 596 + #define bRxAGCFreezeThres 0xc0000 597 + #define bRxFreezeStep_AGC1 0x300000 598 + #define bRxFreezeStep_AGC2 0xc00000 599 + #define bRxFreezeStep_AGC3 0x3000000 600 + #define bRxFreezeStep_AGC0 0xc000000 601 + #define bRxRssi_Cmp_En 0x10000000 602 + #define bRxQuickAGCEn 0x20000000 603 + #define bRxAGCFreezeThresMode 0x40000000 604 + #define bRxOverFlowCheckType 0x80000000 605 + #define bRxAGCShift 0x7f 606 + #define bTRSW_Tri_Only 0x80 607 + #define bPowerThres 0x300 608 + #define bRxAGCEn 0x1 609 + #define bRxAGCTogetherEn 0x2 610 + #define bRxAGCMin 0x4 611 + #define bRxHP_Ini 0x7 612 + #define bRxHP_TRLNA 0x70 613 + #define bRxHP_RSSI 0x700 614 + #define bRxHP_BBP1 0x7000 615 + #define bRxHP_BBP2 0x70000 616 + #define bRxHP_BBP3 0x700000 617 + /* The threshold for high power */ 618 + #define bRSSI_H 0x7f0000 619 + /* The threshold for ant diversity */ 620 + #define bRSSI_Gen 0x7f000000 621 + #define bRxSettle_TRSW 0x7 622 + #define bRxSettle_LNA 0x38 623 + #define bRxSettle_RSSI 0x1c0 624 + #define bRxSettle_BBP 0xe00 625 + #define bRxSettle_RxHP 0x7000 626 + #define bRxSettle_AntSW_RSSI 0x38000 627 + #define bRxSettle_AntSW 0xc0000 628 + #define bRxProcessTime_DAGC 0x300000 629 + #define bRxSettle_HSSI 0x400000 630 + #define bRxProcessTime_BBPPW 0x800000 631 + #define bRxAntennaPowerShift 0x3000000 632 + #define bRSSITableSelect 0xc000000 633 + #define bRxHP_Final 0x7000000 634 + #define bRxHTSettle_BBP 0x7 635 + #define bRxHTSettle_HSSI 0x8 636 + #define bRxHTSettle_RxHP 0x70 637 + #define bRxHTSettle_BBPPW 0x80 638 + #define bRxHTSettle_Idle 0x300 639 + #define bRxHTSettle_Reserved 0x1c00 640 + #define bRxHTRxHPEn 0x8000 641 + #define bRxHTAGCFreezeThres 0x30000 642 + #define bRxHTAGCTogetherEn 0x40000 643 + #define bRxHTAGCMin 0x80000 644 + #define bRxHTAGCEn 0x100000 645 + #define bRxHTDAGCEn 0x200000 646 + #define bRxHTRxHP_BBP 0x1c00000 647 + #define bRxHTRxHP_Final 0xe0000000 648 + #define bRxPWRatioTH 0x3 649 + #define bRxPWRatioEn 0x4 650 + #define bRxMFHold 0x3800 651 + #define bRxPD_Delay_TH1 0x38 652 + #define bRxPD_Delay_TH2 0x1c0 653 + #define bRxPD_DC_COUNT_MAX 0x600 654 + /*#define bRxMF_Hold 0x3800*/ 654 655 #define bRxPD_Delay_TH 0x8000 655 656 #define bRxProcess_Delay 0xf0000 656 657 #define bRxSearchrange_GI2_Early 0x700000 ··· 692 661 693 662 #define bExtLNAGain 0x7c00 694 663 695 - //page d 664 + /* Page d */ 696 665 #define bSTBCEn 0x4 697 666 #define bAntennaMapping 0x10 698 667 #define bNss 0x20 ··· 702 671 #define bOFDMContinueTx 0x10000000 703 672 #define bOFDMSingleCarrier 0x20000000 704 673 #define bOFDMSingleTone 0x40000000 705 - //#define bRxPath1 0x01 706 - //#define bRxPath2 0x02 707 - //#define bRxPath3 0x04 708 - //#define bRxPath4 0x08 709 - //#define bTxPath1 0x10 710 - //#define bTxPath2 0x20 674 + /*#define bRxPath1 0x01 675 + #define bRxPath2 0x02 676 + #define bRxPath3 0x04 677 + #define bRxPath4 0x08 678 + #define bTxPath1 0x10 679 + #define bTxPath2 0x20*/ 711 680 #define bHTDetect 0x100 712 681 #define bCFOEn 0x10000 713 682 #define bCFOValue 0xfff00000 ··· 720 689 #define bCounter_MCSNoSupport 0xffff 721 690 #define bCounter_FastSync 0xffff 722 691 #define bShortCFO 0xfff 723 - #define bShortCFOTLength 12 //total 724 - #define bShortCFOFLength 11 //fraction 692 + /* total */ 693 + #define bShortCFOTLength 12 694 + /* fraction */ 695 + #define bShortCFOFLength 11 725 696 #define bLongCFO 0x7ff 726 697 #define bLongCFOTLength 11 727 698 #define bLongCFOFLength 11 ··· 800 767 #define bUChCfg 0x7000000 801 768 #define bUpdEqz 0x8000000 802 769 803 - //page e 804 - #define bTxAGCRate18_06 0x7f7f7f7f 805 - #define bTxAGCRate54_24 0x7f7f7f7f 770 + /* Page e */ 771 + #define bTxAGCRate18_06 0x7f7f7f7f 772 + #define bTxAGCRate54_24 0x7f7f7f7f 806 773 #define bTxAGCRateMCS32 0x7f 807 - #define bTxAGCRateCCK 0x7f00 774 + #define bTxAGCRateCCK 0x7f00 808 775 #define bTxAGCRateMCS3_MCS0 0x7f7f7f7f 809 776 #define bTxAGCRateMCS7_MCS4 0x7f7f7f7f 810 777 #define bTxAGCRateMCS11_MCS8 0x7f7f7f7f 811 778 #define bTxAGCRateMCS15_MCS12 0x7f7f7f7f 812 779 813 780 814 - //Rx Pseduo noise 781 + /* Rx Pseduo noise */ 815 782 #define bRxPesudoNoiseOn 0x20000000 816 783 #define bRxPesudoNoise_A 0xff 817 784 #define bRxPesudoNoise_B 0xff00 ··· 822 789 #define bPesudoNoiseState_C 0xffff 823 790 #define bPesudoNoiseState_D 0xffff0000 824 791 825 - //RF 826 - //Zebra1 792 + /* RF Zebra 1 */ 827 793 #define bZebra1_HSSIEnable 0x8 828 794 #define bZebra1_TRxControl 0xc00 829 795 #define bZebra1_TRxGainSetting 0x07f ··· 833 801 #define bZebra1_TxLPFBW 0x400 834 802 #define bZebra1_RxLPFBW 0x600 835 803 836 - //Zebra4 804 + /* Zebra4 */ 837 805 #define bRTL8256RegModeCtrl1 0x100 838 806 #define bRTL8256RegModeCtrl0 0x40 839 807 #define bRTL8256_TxLPFBW 0x18 ··· 844 812 #define bRTL8258_RxLPFBW 0xc00 845 813 #define bRTL8258_RSSILPFBW 0xc0 846 814 847 - //byte endable for sb_write 815 + /* byte endable for sb_write */ 848 816 #define bByte0 0x1 849 817 #define bByte1 0x2 850 818 #define bByte2 0x4 ··· 853 821 #define bWord1 0xc 854 822 #define bDWord 0xf 855 823 856 - //for PutRegsetting & GetRegSetting BitMask 824 + /* for PutRegsetting & GetRegSetting BitMask */ 857 825 #define bMaskByte0 0xff 858 826 #define bMaskByte1 0xff00 859 827 #define bMaskByte2 0xff0000 ··· 862 830 #define bMaskLWord 0x0000ffff 863 831 #define bMaskDWord 0xffffffff 864 832 865 - //for PutRFRegsetting & GetRFRegSetting BitMask 833 + /* for PutRFRegsetting & GetRFRegSetting BitMask */ 866 834 #define bMask12Bits 0xfff 867 835 868 836 #define bEnable 0x1 ··· 871 839 #define LeftAntenna 0x0 872 840 #define RightAntenna 0x1 873 841 874 - #define tCheckTxStatus 500 //500ms 875 - #define tUpdateRxCounter 100 //100ms 842 + /* 500 ms */ 843 + #define tCheckTxStatus 500 844 + /* 100 ms */ 845 + #define tUpdateRxCounter 100 876 846 877 847 #define rateCCK 0 878 848 #define rateOFDM 1 879 849 #define rateHT 2 880 850 881 - //define Register-End 851 + /* define Register-End */ 882 852 #define bPMAC_End 0x1ff 883 853 #define bFPGAPHY0_End 0x8ff 884 854 #define bFPGAPHY1_End 0x9ff ··· 888 854 #define bOFDMPHY0_End 0xcff 889 855 #define bOFDMPHY1_End 0xdff 890 856 891 - //define max debug item in each debug page 892 - //#define bMaxItem_FPGA_PHY0 0x9 893 - //#define bMaxItem_FPGA_PHY1 0x3 894 - //#define bMaxItem_PHY_11B 0x16 895 - //#define bMaxItem_OFDM_PHY0 0x29 896 - //#define bMaxItem_OFDM_PHY1 0x0 857 + /*#define max debug item in each debug page 858 + #define bMaxItem_FPGA_PHY0 0x9 859 + #define bMaxItem_FPGA_PHY1 0x3 860 + #define bMaxItem_PHY_11B 0x16 861 + #define bMaxItem_OFDM_PHY0 0x29 862 + #define bMaxItem_OFDM_PHY1 0x0 */ 897 863 898 864 #define bPMACControl 0x0 899 865 #define bWMACControl 0x1 ··· 904 870 #define PathC 0x2 905 871 #define PathD 0x3 906 872 907 - #define rRTL8256RxMixerPole 0xb 908 - #define bZebraRxMixerPole 0x6 909 - #define rRTL8256TxBBOPBias 0x9 910 - #define bRTL8256TxBBOPBias 0x400 911 - #define rRTL8256TxBBBW 19 912 - #define bRTL8256TxBBBW 0x18 873 + #define rRTL8256RxMixerPole 0xb 874 + #define bZebraRxMixerPole 0x6 875 + #define rRTL8256TxBBOPBias 0x9 876 + #define bRTL8256TxBBOPBias 0x400 877 + #define rRTL8256TxBBBW 19 878 + #define bRTL8256TxBBBW 0x18 913 879 914 880 915 - #endif //__INC_HAL8190PCIPHYREG_H 881 + #endif /* __INC_HAL8190PCIPHYREG_H */