Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

ixgbe: IEEE 802.1Qaz, implement priority assignment table

This patch adds support to use the priority assignment
table in the ieee_ets structure to map priorities to
traffic classes. Previously ixgbe only supported a
1:1 mapping. Now we can enable and disable hardware
DCB support when multiple traffic classes are actually
being used. This allows the default case all priorities
mapped to traffic class 0 to work in normal hardware
mode and utilize the full packet buffer.

This patch does not address putting the hardware in
4TC mode so packet buffer space may be underutilized
in this case. A follow up patch can address this
optimization. But at least we have the hooks to do
this now.

Also CEE will behave as it always has and map priorities
1:1 with traffic classes.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

authored by

John Fastabend and committed by
Jeff Kirsher
17049d30 3b97fd69

+36 -19
+8 -5
drivers/net/ixgbe/ixgbe_dcb.c
··· 246 246 u8 bwgid[MAX_TRAFFIC_CLASS]; 247 247 u16 refill[MAX_TRAFFIC_CLASS]; 248 248 u16 max[MAX_TRAFFIC_CLASS]; 249 + /* CEE does not define a priority to tc mapping so map 1:1 */ 250 + u8 prio_tc[MAX_TRAFFIC_CLASS] = {0, 1, 2, 3, 4, 5, 6, 7}; 249 251 250 252 /* Unpack CEE standard containers */ 251 253 ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en); ··· 266 264 case ixgbe_mac_X540: 267 265 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->rx_pba_cfg, 268 266 pfc_en, refill, max, bwgid, 269 - ptype); 267 + ptype, prio_tc); 270 268 break; 271 269 default: 272 270 break; ··· 294 292 } 295 293 296 294 s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, 297 - u16 *refill, u16 *max, u8 *bwg_id, u8 *prio_type) 295 + u16 *refill, u16 *max, u8 *bwg_id, 296 + u8 *prio_type, u8 *prio_tc) 298 297 { 299 298 switch (hw->mac.type) { 300 299 case ixgbe_mac_82598EB: ··· 309 306 case ixgbe_mac_82599EB: 310 307 case ixgbe_mac_X540: 311 308 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, 312 - bwg_id, prio_type); 309 + bwg_id, prio_type, prio_tc); 313 310 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 314 311 bwg_id, prio_type); 315 - ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 316 - bwg_id, prio_type); 312 + ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, 313 + prio_type, prio_tc); 317 314 break; 318 315 default: 319 316 break;
+2 -2
drivers/net/ixgbe/ixgbe_dcb.h
··· 159 159 struct ixgbe_dcb_config *, int, u8); 160 160 161 161 /* DCB hw initialization */ 162 - s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, 163 - u16 *refill, u16 *max, u8 *bwg_id, u8 *prio_type); 162 + s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, u16 *refill, u16 *max, 163 + u8 *bwg_id, u8 *prio_type, u8 *tc_prio); 164 164 s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en); 165 165 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *); 166 166
+10 -7
drivers/net/ixgbe/ixgbe_dcb_82599.c
··· 85 85 u16 *refill, 86 86 u16 *max, 87 87 u8 *bwg_id, 88 - u8 *prio_type) 88 + u8 *prio_type, 89 + u8 *prio_tc) 89 90 { 90 91 u32 reg = 0; 91 92 u32 credit_refill = 0; ··· 103 102 /* Map all traffic classes to their UP, 1 to 1 */ 104 103 reg = 0; 105 104 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) 106 - reg |= (i << (i * IXGBE_RTRUP2TC_UP_SHIFT)); 105 + reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); 107 106 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 108 107 109 108 /* Configure traffic class credits and priority */ ··· 195 194 u16 *refill, 196 195 u16 *max, 197 196 u8 *bwg_id, 198 - u8 *prio_type) 197 + u8 *prio_type, 198 + u8 *prio_tc) 199 199 { 200 200 u32 reg; 201 201 u8 i; ··· 213 211 /* Map all traffic classes to their UP, 1 to 1 */ 214 212 reg = 0; 215 213 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) 216 - reg |= (i << (i * IXGBE_RTTUP2TC_UP_SHIFT)); 214 + reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT)); 217 215 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); 218 216 219 217 /* Configure traffic class credits and priority */ ··· 426 424 */ 427 425 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, 428 426 u8 rx_pba, u8 pfc_en, u16 *refill, 429 - u16 *max, u8 *bwg_id, u8 *prio_type) 427 + u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc) 430 428 { 431 429 ixgbe_dcb_config_packet_buffers_82599(hw, rx_pba); 432 430 ixgbe_dcb_config_82599(hw); 433 - ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, prio_type); 431 + ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, 432 + prio_type, prio_tc); 434 433 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 435 434 bwg_id, prio_type); 436 435 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 437 - bwg_id, prio_type); 436 + bwg_id, prio_type, prio_tc); 438 437 ixgbe_dcb_config_pfc_82599(hw, pfc_en); 439 438 ixgbe_dcb_config_tc_stats_82599(hw); 440 439
+6 -3
drivers/net/ixgbe/ixgbe_dcb_82599.h
··· 109 109 u16 *refill, 110 110 u16 *max, 111 111 u8 *bwg_id, 112 - u8 *prio_type); 112 + u8 *prio_type, 113 + u8 *prio_tc); 113 114 114 115 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, 115 116 u16 *refill, ··· 122 121 u16 *refill, 123 122 u16 *max, 124 123 u8 *bwg_id, 125 - u8 *prio_type); 124 + u8 *prio_type, 125 + u8 *prio_tc); 126 126 127 127 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, 128 128 u8 rx_pba, u8 pfc_en, u16 *refill, 129 - u16 *max, u8 *bwg_id, u8 *prio_type); 129 + u16 *max, u8 *bwg_id, u8 *prio_type, 130 + u8 *prio_tc); 130 131 131 132 #endif /* _DCB_82599_CONFIG_H */
+10 -2
drivers/net/ixgbe/ixgbe_dcb_nl.c
··· 416 416 if (adapter->dcb_set_bitmap & (BIT_PG_TX|BIT_PG_RX)) { 417 417 u16 refill[MAX_TRAFFIC_CLASS], max[MAX_TRAFFIC_CLASS]; 418 418 u8 bwg_id[MAX_TRAFFIC_CLASS], prio_type[MAX_TRAFFIC_CLASS]; 419 + /* Priority to TC mapping in CEE case default to 1:1 */ 420 + u8 prio_tc[MAX_TRAFFIC_CLASS] = {0, 1, 2, 3, 4, 5, 6, 7}; 419 421 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 420 422 421 423 #ifdef CONFIG_FCOE ··· 439 437 DCB_TX_CONFIG, prio_type); 440 438 441 439 ixgbe_dcb_hw_ets_config(&adapter->hw, refill, max, 442 - bwg_id, prio_type); 440 + bwg_id, prio_type, prio_tc); 443 441 } 444 442 445 443 if (adapter->dcb_cfg.pfc_mode_enable) ··· 647 645 __u8 prio_type[IEEE_8021QAZ_MAX_TCS]; 648 646 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 649 647 int i, err; 648 + __u64 *p = (__u64 *) ets->prio_tc; 650 649 /* naively give each TC a bwg to map onto CEE hardware */ 651 650 __u8 bwg_id[IEEE_8021QAZ_MAX_TCS] = {0, 1, 2, 3, 4, 5, 6, 7}; 652 651 ··· 682 679 } 683 680 } 684 681 682 + if (*p) 683 + ixgbe_dcbnl_set_state(dev, 1); 684 + else 685 + ixgbe_dcbnl_set_state(dev, 0); 686 + 685 687 ixgbe_ieee_credits(ets->tc_tx_bw, refill, max, max_frame); 686 688 err = ixgbe_dcb_hw_ets_config(&adapter->hw, refill, max, 687 - bwg_id, prio_type); 689 + bwg_id, prio_type, ets->prio_tc); 688 690 return err; 689 691 } 690 692