tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
MIPS: ralink: Add missing pinmux.
The mt7620 has a pin that can be used to generate an external reference
clock. The pinmux setup was missing the definition of said pin. This patch
adds it.
Signed-off-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14898/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
John Crispin
and committed by
Ralf Baechle
16eccef6
2517caf1
+12
-3
+6
-1
arch/mips/include/asm/mach-ralink/mt7620.h
+6
-1
arch/mips/include/asm/mach-ralink/mt7620.h
···
115
115
#define MT7620_GPIO_MODE_WDT_MASK 0x3
116
116
#define MT7620_GPIO_MODE_WDT_SHIFT 21
117
117
118
+
#define MT7620_GPIO_MODE_MDIO 0
119
+
#define MT7620_GPIO_MODE_MDIO_REFCLK 1
120
+
#define MT7620_GPIO_MODE_MDIO_GPIO 2
121
+
#define MT7620_GPIO_MODE_MDIO_MASK 0x3
122
+
#define MT7620_GPIO_MODE_MDIO_SHIFT 7
123
+
118
124
#define MT7620_GPIO_MODE_I2C 0
119
125
#define MT7620_GPIO_MODE_UART1 5
120
-
#define MT7620_GPIO_MODE_MDIO 8
121
126
#define MT7620_GPIO_MODE_RGMII1 9
122
127
#define MT7620_GPIO_MODE_RGMII2 10
123
128
#define MT7620_GPIO_MODE_SPI 11
+6
-2
arch/mips/ralink/mt7620.c
+6
-2
arch/mips/ralink/mt7620.c
···
55
55
static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
56
56
static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
57
57
static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
58
-
static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
58
+
static struct rt2880_pmx_func mdio_grp[] = {
59
+
FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
60
+
FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
61
+
};
59
62
static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
60
63
static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
61
64
static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
···
95
92
GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
96
93
GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
97
94
MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
98
-
GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
95
+
GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
96
+
MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT),
99
97
GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
100
98
GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
101
99
GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,