Merge tag 'v5.17-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

+1

Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml

··· 29 29 - mediatek,mt8167-mmsys 30 30 - mediatek,mt8173-mmsys 31 31 - mediatek,mt8183-mmsys 32 + - mediatek,mt8186-mmsys 32 33 - mediatek,mt8192-mmsys 33 34 - mediatek,mt8365-mmsys 34 35 - const: syscon

+3

Documentation/devicetree/bindings/power/mediatek,power-controller.yaml

··· 26 26 - mediatek,mt8167-power-controller 27 27 - mediatek,mt8173-power-controller 28 28 - mediatek,mt8183-power-controller 29 + - mediatek,mt8186-power-controller 29 30 - mediatek,mt8192-power-controller 31 + - mediatek,mt8195-power-controller 30 32 31 33 '#power-domain-cells': 32 34 const: 1 ··· 66 64 "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. 67 65 "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. 68 66 "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. 67 + "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. 69 68 maxItems: 1 70 69 71 70 clocks:

+1

Documentation/devicetree/bindings/soc/mediatek/pwrap.txt

··· 27 27 "mediatek,mt8135-pwrap" for MT8135 SoCs 28 28 "mediatek,mt8173-pwrap" for MT8173 SoCs 29 29 "mediatek,mt8183-pwrap" for MT8183 SoCs 30 + "mediatek,mt8186-pwrap" for MT8186 SoCs 30 31 "mediatek,mt8195-pwrap" for MT8195 SoCs 31 32 "mediatek,mt8516-pwrap" for MT8516 SoCs 32 33 - interrupts: IRQ for pwrap in SOC

+14 -2

drivers/soc/mediatek/mt8167-pm-domains.h

··· 18 18 .name = "mm", 19 19 .sta_mask = PWR_STATUS_DISP, 20 20 .ctl_offs = SPM_DIS_PWR_CON, 21 + .pwr_sta_offs = SPM_PWR_STATUS, 22 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 21 23 .sram_pdn_bits = GENMASK(11, 8), 22 24 .sram_pdn_ack_bits = GENMASK(12, 12), 23 25 .bp_infracfg = { ··· 32 30 .name = "vdec", 33 31 .sta_mask = PWR_STATUS_VDEC, 34 32 .ctl_offs = SPM_VDE_PWR_CON, 33 + .pwr_sta_offs = SPM_PWR_STATUS, 34 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 35 35 .sram_pdn_bits = GENMASK(8, 8), 36 36 .sram_pdn_ack_bits = GENMASK(12, 12), 37 37 .caps = MTK_SCPD_ACTIVE_WAKEUP, ··· 42 38 .name = "isp", 43 39 .sta_mask = PWR_STATUS_ISP, 44 40 .ctl_offs = SPM_ISP_PWR_CON, 41 + .pwr_sta_offs = SPM_PWR_STATUS, 42 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 45 43 .sram_pdn_bits = GENMASK(11, 8), 46 44 .sram_pdn_ack_bits = GENMASK(13, 12), 47 45 .caps = MTK_SCPD_ACTIVE_WAKEUP, ··· 52 46 .name = "mfg_async", 53 47 .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC, 54 48 .ctl_offs = SPM_MFG_ASYNC_PWR_CON, 49 + .pwr_sta_offs = SPM_PWR_STATUS, 50 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 55 51 .sram_pdn_bits = 0, 56 52 .sram_pdn_ack_bits = 0, 57 53 .bp_infracfg = { ··· 65 57 .name = "mfg_2d", 66 58 .sta_mask = MT8167_PWR_STATUS_MFG_2D, 67 59 .ctl_offs = SPM_MFG_2D_PWR_CON, 60 + .pwr_sta_offs = SPM_PWR_STATUS, 61 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 68 62 .sram_pdn_bits = GENMASK(11, 8), 69 63 .sram_pdn_ack_bits = GENMASK(15, 12), 70 64 }, ··· 74 64 .name = "mfg", 75 65 .sta_mask = PWR_STATUS_MFG, 76 66 .ctl_offs = SPM_MFG_PWR_CON, 67 + .pwr_sta_offs = SPM_PWR_STATUS, 68 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 77 69 .sram_pdn_bits = GENMASK(11, 8), 78 70 .sram_pdn_ack_bits = GENMASK(15, 12), 79 71 }, ··· 83 71 .name = "conn", 84 72 .sta_mask = PWR_STATUS_CONN, 85 73 .ctl_offs = SPM_CONN_PWR_CON, 74 + .pwr_sta_offs = SPM_PWR_STATUS, 75 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 86 76 .sram_pdn_bits = GENMASK(8, 8), 87 77 .sram_pdn_ack_bits = 0, 88 78 .caps = MTK_SCPD_ACTIVE_WAKEUP, ··· 99 85 static const struct scpsys_soc_data mt8167_scpsys_data = { 100 86 .domains_data = scpsys_domain_data_mt8167, 101 87 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167), 102 - .pwr_sta_offs = SPM_PWR_STATUS, 103 - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 104 88 }; 105 89 106 90 #endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */

+20 -2

drivers/soc/mediatek/mt8173-pm-domains.h

··· 15 15 .name = "vdec", 16 16 .sta_mask = PWR_STATUS_VDEC, 17 17 .ctl_offs = SPM_VDE_PWR_CON, 18 + .pwr_sta_offs = SPM_PWR_STATUS, 19 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 18 20 .sram_pdn_bits = GENMASK(11, 8), 19 21 .sram_pdn_ack_bits = GENMASK(12, 12), 20 22 }, ··· 24 22 .name = "venc", 25 23 .sta_mask = PWR_STATUS_VENC, 26 24 .ctl_offs = SPM_VEN_PWR_CON, 25 + .pwr_sta_offs = SPM_PWR_STATUS, 26 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 27 27 .sram_pdn_bits = GENMASK(11, 8), 28 28 .sram_pdn_ack_bits = GENMASK(15, 12), 29 29 }, ··· 33 29 .name = "isp", 34 30 .sta_mask = PWR_STATUS_ISP, 35 31 .ctl_offs = SPM_ISP_PWR_CON, 32 + .pwr_sta_offs = SPM_PWR_STATUS, 33 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 36 34 .sram_pdn_bits = GENMASK(11, 8), 37 35 .sram_pdn_ack_bits = GENMASK(13, 12), 38 36 }, ··· 42 36 .name = "mm", 43 37 .sta_mask = PWR_STATUS_DISP, 44 38 .ctl_offs = SPM_DIS_PWR_CON, 39 + .pwr_sta_offs = SPM_PWR_STATUS, 40 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 45 41 .sram_pdn_bits = GENMASK(11, 8), 46 42 .sram_pdn_ack_bits = GENMASK(12, 12), 47 43 .bp_infracfg = { ··· 55 47 .name = "venc_lt", 56 48 .sta_mask = PWR_STATUS_VENC_LT, 57 49 .ctl_offs = SPM_VEN2_PWR_CON, 50 + .pwr_sta_offs = SPM_PWR_STATUS, 51 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 58 52 .sram_pdn_bits = GENMASK(11, 8), 59 53 .sram_pdn_ack_bits = GENMASK(15, 12), 60 54 }, ··· 64 54 .name = "audio", 65 55 .sta_mask = PWR_STATUS_AUDIO, 66 56 .ctl_offs = SPM_AUDIO_PWR_CON, 57 + .pwr_sta_offs = SPM_PWR_STATUS, 58 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 67 59 .sram_pdn_bits = GENMASK(11, 8), 68 60 .sram_pdn_ack_bits = GENMASK(15, 12), 69 61 }, ··· 73 61 .name = "usb", 74 62 .sta_mask = PWR_STATUS_USB, 75 63 .ctl_offs = SPM_USB_PWR_CON, 64 + .pwr_sta_offs = SPM_PWR_STATUS, 65 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 76 66 .sram_pdn_bits = GENMASK(11, 8), 77 67 .sram_pdn_ack_bits = GENMASK(15, 12), 78 68 .caps = MTK_SCPD_ACTIVE_WAKEUP, ··· 83 69 .name = "mfg_async", 84 70 .sta_mask = PWR_STATUS_MFG_ASYNC, 85 71 .ctl_offs = SPM_MFG_ASYNC_PWR_CON, 72 + .pwr_sta_offs = SPM_PWR_STATUS, 73 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 86 74 .sram_pdn_bits = GENMASK(11, 8), 87 75 .sram_pdn_ack_bits = 0, 88 76 .caps = MTK_SCPD_DOMAIN_SUPPLY, ··· 93 77 .name = "mfg_2d", 94 78 .sta_mask = PWR_STATUS_MFG_2D, 95 79 .ctl_offs = SPM_MFG_2D_PWR_CON, 80 + .pwr_sta_offs = SPM_PWR_STATUS, 81 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 96 82 .sram_pdn_bits = GENMASK(11, 8), 97 83 .sram_pdn_ack_bits = GENMASK(13, 12), 98 84 }, ··· 102 84 .name = "mfg", 103 85 .sta_mask = PWR_STATUS_MFG, 104 86 .ctl_offs = SPM_MFG_PWR_CON, 87 + .pwr_sta_offs = SPM_PWR_STATUS, 88 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 105 89 .sram_pdn_bits = GENMASK(13, 8), 106 90 .sram_pdn_ack_bits = GENMASK(21, 16), 107 91 .bp_infracfg = { ··· 118 98 static const struct scpsys_soc_data mt8173_scpsys_data = { 119 99 .domains_data = scpsys_domain_data_mt8173, 120 100 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173), 121 - .pwr_sta_offs = SPM_PWR_STATUS, 122 - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 123 101 }; 124 102 125 103 #endif /* __SOC_MEDIATEK_MT8173_PM_DOMAINS_H */

+30 -2

drivers/soc/mediatek/mt8183-pm-domains.h

··· 15 15 .name = "audio", 16 16 .sta_mask = PWR_STATUS_AUDIO, 17 17 .ctl_offs = 0x0314, 18 + .pwr_sta_offs = 0x0180, 19 + .pwr_sta2nd_offs = 0x0184, 18 20 .sram_pdn_bits = GENMASK(11, 8), 19 21 .sram_pdn_ack_bits = GENMASK(15, 12), 20 22 }, ··· 24 22 .name = "conn", 25 23 .sta_mask = PWR_STATUS_CONN, 26 24 .ctl_offs = 0x032c, 25 + .pwr_sta_offs = 0x0180, 26 + .pwr_sta2nd_offs = 0x0184, 27 27 .sram_pdn_bits = 0, 28 28 .sram_pdn_ack_bits = 0, 29 29 .bp_infracfg = { ··· 37 33 .name = "mfg_async", 38 34 .sta_mask = PWR_STATUS_MFG_ASYNC, 39 35 .ctl_offs = 0x0334, 36 + .pwr_sta_offs = 0x0180, 37 + .pwr_sta2nd_offs = 0x0184, 40 38 .sram_pdn_bits = 0, 41 39 .sram_pdn_ack_bits = 0, 42 40 }, ··· 46 40 .name = "mfg", 47 41 .sta_mask = PWR_STATUS_MFG, 48 42 .ctl_offs = 0x0338, 43 + .pwr_sta_offs = 0x0180, 44 + .pwr_sta2nd_offs = 0x0184, 49 45 .sram_pdn_bits = GENMASK(8, 8), 50 46 .sram_pdn_ack_bits = GENMASK(12, 12), 51 47 .caps = MTK_SCPD_DOMAIN_SUPPLY, ··· 56 48 .name = "mfg_core0", 57 49 .sta_mask = BIT(7), 58 50 .ctl_offs = 0x034c, 51 + .pwr_sta_offs = 0x0180, 52 + .pwr_sta2nd_offs = 0x0184, 59 53 .sram_pdn_bits = GENMASK(8, 8), 60 54 .sram_pdn_ack_bits = GENMASK(12, 12), 61 55 }, ··· 65 55 .name = "mfg_core1", 66 56 .sta_mask = BIT(20), 67 57 .ctl_offs = 0x0310, 58 + .pwr_sta_offs = 0x0180, 59 + .pwr_sta2nd_offs = 0x0184, 68 60 .sram_pdn_bits = GENMASK(8, 8), 69 61 .sram_pdn_ack_bits = GENMASK(12, 12), 70 62 }, ··· 74 62 .name = "mfg_2d", 75 63 .sta_mask = PWR_STATUS_MFG_2D, 76 64 .ctl_offs = 0x0348, 65 + .pwr_sta_offs = 0x0180, 66 + .pwr_sta2nd_offs = 0x0184, 77 67 .sram_pdn_bits = GENMASK(8, 8), 78 68 .sram_pdn_ack_bits = GENMASK(12, 12), 79 69 .bp_infracfg = { ··· 89 75 .name = "disp", 90 76 .sta_mask = PWR_STATUS_DISP, 91 77 .ctl_offs = 0x030c, 78 + .pwr_sta_offs = 0x0180, 79 + .pwr_sta2nd_offs = 0x0184, 92 80 .sram_pdn_bits = GENMASK(8, 8), 93 81 .sram_pdn_ack_bits = GENMASK(12, 12), 94 82 .bp_infracfg = { ··· 110 94 .name = "cam", 111 95 .sta_mask = BIT(25), 112 96 .ctl_offs = 0x0344, 97 + .pwr_sta_offs = 0x0180, 98 + .pwr_sta2nd_offs = 0x0184, 113 99 .sram_pdn_bits = GENMASK(9, 8), 114 100 .sram_pdn_ack_bits = GENMASK(13, 12), 115 101 .bp_infracfg = { ··· 135 117 .name = "isp", 136 118 .sta_mask = PWR_STATUS_ISP, 137 119 .ctl_offs = 0x0308, 120 + .pwr_sta_offs = 0x0180, 121 + .pwr_sta2nd_offs = 0x0184, 138 122 .sram_pdn_bits = GENMASK(9, 8), 139 123 .sram_pdn_ack_bits = GENMASK(13, 12), 140 124 .bp_infracfg = { ··· 160 140 .name = "vdec", 161 141 .sta_mask = BIT(31), 162 142 .ctl_offs = 0x0300, 143 + .pwr_sta_offs = 0x0180, 144 + .pwr_sta2nd_offs = 0x0184, 163 145 .sram_pdn_bits = GENMASK(8, 8), 164 146 .sram_pdn_ack_bits = GENMASK(12, 12), 165 147 .bp_smi = { ··· 175 153 .name = "venc", 176 154 .sta_mask = PWR_STATUS_VENC, 177 155 .ctl_offs = 0x0304, 156 + .pwr_sta_offs = 0x0180, 157 + .pwr_sta2nd_offs = 0x0184, 178 158 .sram_pdn_bits = GENMASK(11, 8), 179 159 .sram_pdn_ack_bits = GENMASK(15, 12), 180 160 .bp_smi = { ··· 190 166 .name = "vpu_top", 191 167 .sta_mask = BIT(26), 192 168 .ctl_offs = 0x0324, 169 + .pwr_sta_offs = 0x0180, 170 + .pwr_sta2nd_offs = 0x0184, 193 171 .sram_pdn_bits = GENMASK(8, 8), 194 172 .sram_pdn_ack_bits = GENMASK(12, 12), 195 173 .bp_infracfg = { ··· 219 193 .name = "vpu_core0", 220 194 .sta_mask = BIT(27), 221 195 .ctl_offs = 0x33c, 196 + .pwr_sta_offs = 0x0180, 197 + .pwr_sta2nd_offs = 0x0184, 222 198 .sram_pdn_bits = GENMASK(11, 8), 223 199 .sram_pdn_ack_bits = GENMASK(13, 12), 224 200 .bp_infracfg = { ··· 239 211 .name = "vpu_core1", 240 212 .sta_mask = BIT(28), 241 213 .ctl_offs = 0x0340, 214 + .pwr_sta_offs = 0x0180, 215 + .pwr_sta2nd_offs = 0x0184, 242 216 .sram_pdn_bits = GENMASK(11, 8), 243 217 .sram_pdn_ack_bits = GENMASK(13, 12), 244 218 .bp_infracfg = { ··· 260 230 static const struct scpsys_soc_data mt8183_scpsys_data = { 261 231 .domains_data = scpsys_domain_data_mt8183, 262 232 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183), 263 - .pwr_sta_offs = 0x0180, 264 - .pwr_sta2nd_offs = 0x0184 265 233 }; 266 234 267 235 #endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */

+115

drivers/soc/mediatek/mt8186-mmsys.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + 3 + #ifndef __SOC_MEDIATEK_MT8186_MMSYS_H 4 + #define __SOC_MEDIATEK_MT8186_MMSYS_H 5 + 6 + #define MT8186_MMSYS_OVL_CON 0xF04 7 + #define MT8186_MMSYS_OVL0_CON_MASK 0x3 8 + #define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC 9 + #define MT8186_OVL0_GO_BLEND BIT(0) 10 + #define MT8186_OVL0_GO_BG BIT(1) 11 + #define MT8186_OVL0_2L_GO_BLEND BIT(2) 12 + #define MT8186_OVL0_2L_GO_BG BIT(3) 13 + #define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C 14 + #define MT8186_RDMA0_SOUT_SEL_MASK 0xF 15 + #define MT8186_RDMA0_SOUT_TO_DSI0 (0) 16 + #define MT8186_RDMA0_SOUT_TO_COLOR0 (1) 17 + #define MT8186_RDMA0_SOUT_TO_DPI0 (2) 18 + #define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14 19 + #define MT8186_OVL0_2L_MOUT_EN_MASK 0xF 20 + #define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0) 21 + #define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3) 22 + #define MT8186_DISP_OVL0_MOUT_EN 0xF18 23 + #define MT8186_OVL0_MOUT_EN_MASK 0xF 24 + #define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0) 25 + #define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3) 26 + #define MT8186_DISP_DITHER0_MOUT_EN 0xF20 27 + #define MT8186_DITHER0_MOUT_EN_MASK 0xF 28 + #define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0) 29 + #define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2) 30 + #define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3) 31 + #define MT8186_DISP_RDMA0_SEL_IN 0xF28 32 + #define MT8186_RDMA0_SEL_IN_MASK 0xF 33 + #define MT8186_RDMA0_FROM_OVL0 0 34 + #define MT8186_RDMA0_FROM_OVL0_2L 2 35 + #define MT8186_DISP_DSI0_SEL_IN 0xF30 36 + #define MT8186_DSI0_SEL_IN_MASK 0xF 37 + #define MT8186_DSI0_FROM_RDMA0 0 38 + #define MT8186_DSI0_FROM_DITHER0 1 39 + #define MT8186_DSI0_FROM_RDMA1 2 40 + #define MT8186_DISP_RDMA1_MOUT_EN 0xF3C 41 + #define MT8186_RDMA1_MOUT_EN_MASK 0xF 42 + #define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0) 43 + #define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2) 44 + #define MT8186_DISP_RDMA1_SEL_IN 0xF40 45 + #define MT8186_RDMA1_SEL_IN_MASK 0xF 46 + #define MT8186_RDMA1_FROM_OVL0 0 47 + #define MT8186_RDMA1_FROM_OVL0_2L 2 48 + #define MT8186_RDMA1_FROM_DITHER0 3 49 + #define MT8186_DISP_DPI0_SEL_IN 0xF44 50 + #define MT8186_DPI0_SEL_IN_MASK 0xF 51 + #define MT8186_DPI0_FROM_RDMA1 0 52 + #define MT8186_DPI0_FROM_DITHER0 1 53 + #define MT8186_DPI0_FROM_RDMA0 2 54 + 55 + #define MT8186_MMSYS_SW0_RST_B 0x160 56 + 57 + static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = { 58 + { 59 + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 60 + MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK, 61 + MT8186_OVL0_MOUT_TO_RDMA0 62 + }, 63 + { 64 + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 65 + MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK, 66 + MT8186_RDMA0_FROM_OVL0 67 + }, 68 + { 69 + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 70 + MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK, 71 + MT8186_OVL0_GO_BLEND 72 + }, 73 + { 74 + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, 75 + MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK, 76 + MT8186_RDMA0_SOUT_TO_COLOR0 77 + }, 78 + { 79 + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, 80 + MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK, 81 + MT8186_DITHER0_MOUT_TO_DSI0, 82 + }, 83 + { 84 + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, 85 + MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK, 86 + MT8186_DSI0_FROM_DITHER0 87 + }, 88 + { 89 + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, 90 + MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK, 91 + MT8186_OVL0_2L_MOUT_TO_RDMA1 92 + }, 93 + { 94 + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, 95 + MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK, 96 + MT8186_RDMA1_FROM_OVL0_2L 97 + }, 98 + { 99 + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, 100 + MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK, 101 + MT8186_OVL0_2L_GO_BLEND 102 + }, 103 + { 104 + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 105 + MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK, 106 + MT8186_RDMA1_MOUT_TO_DPI0_SEL 107 + }, 108 + { 109 + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 110 + MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK, 111 + MT8186_DPI0_FROM_RDMA1 112 + }, 113 + }; 114 + 115 + #endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */

+344

drivers/soc/mediatek/mt8186-pm-domains.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* 3 + * Copyright (c) 2022 MediaTek Inc. 4 + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 + */ 6 + 7 + #ifndef __SOC_MEDIATEK_MT8186_PM_DOMAINS_H 8 + #define __SOC_MEDIATEK_MT8186_PM_DOMAINS_H 9 + 10 + #include "mtk-pm-domains.h" 11 + #include <dt-bindings/power/mt8186-power.h> 12 + 13 + /* 14 + * MT8186 power domain support 15 + */ 16 + 17 + static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { 18 + [MT8186_POWER_DOMAIN_MFG0] = { 19 + .name = "mfg0", 20 + .sta_mask = BIT(2), 21 + .ctl_offs = 0x308, 22 + .pwr_sta_offs = 0x16C, 23 + .pwr_sta2nd_offs = 0x170, 24 + .sram_pdn_bits = BIT(8), 25 + .sram_pdn_ack_bits = BIT(12), 26 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 27 + }, 28 + [MT8186_POWER_DOMAIN_MFG1] = { 29 + .name = "mfg1", 30 + .sta_mask = BIT(3), 31 + .ctl_offs = 0x30c, 32 + .pwr_sta_offs = 0x16C, 33 + .pwr_sta2nd_offs = 0x170, 34 + .sram_pdn_bits = BIT(8), 35 + .sram_pdn_ack_bits = BIT(12), 36 + .bp_infracfg = { 37 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1, 38 + MT8186_TOP_AXI_PROT_EN_1_SET, 39 + MT8186_TOP_AXI_PROT_EN_1_CLR, 40 + MT8186_TOP_AXI_PROT_EN_1_STA), 41 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2, 42 + MT8186_TOP_AXI_PROT_EN_SET, 43 + MT8186_TOP_AXI_PROT_EN_CLR, 44 + MT8186_TOP_AXI_PROT_EN_STA), 45 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3, 46 + MT8186_TOP_AXI_PROT_EN_SET, 47 + MT8186_TOP_AXI_PROT_EN_CLR, 48 + MT8186_TOP_AXI_PROT_EN_STA), 49 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4, 50 + MT8186_TOP_AXI_PROT_EN_1_SET, 51 + MT8186_TOP_AXI_PROT_EN_1_CLR, 52 + MT8186_TOP_AXI_PROT_EN_1_STA), 53 + }, 54 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 55 + }, 56 + [MT8186_POWER_DOMAIN_MFG2] = { 57 + .name = "mfg2", 58 + .sta_mask = BIT(4), 59 + .ctl_offs = 0x310, 60 + .pwr_sta_offs = 0x16C, 61 + .pwr_sta2nd_offs = 0x170, 62 + .sram_pdn_bits = BIT(8), 63 + .sram_pdn_ack_bits = BIT(12), 64 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 65 + }, 66 + [MT8186_POWER_DOMAIN_MFG3] = { 67 + .name = "mfg3", 68 + .sta_mask = BIT(5), 69 + .ctl_offs = 0x314, 70 + .pwr_sta_offs = 0x16C, 71 + .pwr_sta2nd_offs = 0x170, 72 + .sram_pdn_bits = BIT(8), 73 + .sram_pdn_ack_bits = BIT(12), 74 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 75 + }, 76 + [MT8186_POWER_DOMAIN_SSUSB] = { 77 + .name = "ssusb", 78 + .sta_mask = BIT(20), 79 + .ctl_offs = 0x9F0, 80 + .pwr_sta_offs = 0x16C, 81 + .pwr_sta2nd_offs = 0x170, 82 + .sram_pdn_bits = BIT(8), 83 + .sram_pdn_ack_bits = BIT(12), 84 + .caps = MTK_SCPD_ACTIVE_WAKEUP, 85 + }, 86 + [MT8186_POWER_DOMAIN_SSUSB_P1] = { 87 + .name = "ssusb_p1", 88 + .sta_mask = BIT(19), 89 + .ctl_offs = 0x9F4, 90 + .pwr_sta_offs = 0x16C, 91 + .pwr_sta2nd_offs = 0x170, 92 + .sram_pdn_bits = BIT(8), 93 + .sram_pdn_ack_bits = BIT(12), 94 + .caps = MTK_SCPD_ACTIVE_WAKEUP, 95 + }, 96 + [MT8186_POWER_DOMAIN_DIS] = { 97 + .name = "dis", 98 + .sta_mask = BIT(21), 99 + .ctl_offs = 0x354, 100 + .pwr_sta_offs = 0x16C, 101 + .pwr_sta2nd_offs = 0x170, 102 + .sram_pdn_bits = BIT(8), 103 + .sram_pdn_ack_bits = BIT(12), 104 + .bp_infracfg = { 105 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1, 106 + MT8186_TOP_AXI_PROT_EN_1_SET, 107 + MT8186_TOP_AXI_PROT_EN_1_CLR, 108 + MT8186_TOP_AXI_PROT_EN_1_STA), 109 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2, 110 + MT8186_TOP_AXI_PROT_EN_SET, 111 + MT8186_TOP_AXI_PROT_EN_CLR, 112 + MT8186_TOP_AXI_PROT_EN_STA), 113 + }, 114 + }, 115 + [MT8186_POWER_DOMAIN_IMG] = { 116 + .name = "img", 117 + .sta_mask = BIT(13), 118 + .ctl_offs = 0x334, 119 + .pwr_sta_offs = 0x16C, 120 + .pwr_sta2nd_offs = 0x170, 121 + .sram_pdn_bits = BIT(8), 122 + .sram_pdn_ack_bits = BIT(12), 123 + .bp_infracfg = { 124 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1, 125 + MT8186_TOP_AXI_PROT_EN_1_SET, 126 + MT8186_TOP_AXI_PROT_EN_1_CLR, 127 + MT8186_TOP_AXI_PROT_EN_1_STA), 128 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2, 129 + MT8186_TOP_AXI_PROT_EN_1_SET, 130 + MT8186_TOP_AXI_PROT_EN_1_CLR, 131 + MT8186_TOP_AXI_PROT_EN_1_STA), 132 + }, 133 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 134 + }, 135 + [MT8186_POWER_DOMAIN_IMG2] = { 136 + .name = "img2", 137 + .sta_mask = BIT(14), 138 + .ctl_offs = 0x338, 139 + .pwr_sta_offs = 0x16C, 140 + .pwr_sta2nd_offs = 0x170, 141 + .sram_pdn_bits = BIT(8), 142 + .sram_pdn_ack_bits = BIT(12), 143 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 144 + }, 145 + [MT8186_POWER_DOMAIN_IPE] = { 146 + .name = "ipe", 147 + .sta_mask = BIT(15), 148 + .ctl_offs = 0x33C, 149 + .pwr_sta_offs = 0x16C, 150 + .pwr_sta2nd_offs = 0x170, 151 + .sram_pdn_bits = BIT(8), 152 + .sram_pdn_ack_bits = BIT(12), 153 + .bp_infracfg = { 154 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1, 155 + MT8186_TOP_AXI_PROT_EN_1_SET, 156 + MT8186_TOP_AXI_PROT_EN_1_CLR, 157 + MT8186_TOP_AXI_PROT_EN_1_STA), 158 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2, 159 + MT8186_TOP_AXI_PROT_EN_1_SET, 160 + MT8186_TOP_AXI_PROT_EN_1_CLR, 161 + MT8186_TOP_AXI_PROT_EN_1_STA), 162 + }, 163 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 164 + }, 165 + [MT8186_POWER_DOMAIN_CAM] = { 166 + .name = "cam", 167 + .sta_mask = BIT(23), 168 + .ctl_offs = 0x35C, 169 + .pwr_sta_offs = 0x16C, 170 + .pwr_sta2nd_offs = 0x170, 171 + .sram_pdn_bits = BIT(8), 172 + .sram_pdn_ack_bits = BIT(12), 173 + .bp_infracfg = { 174 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1, 175 + MT8186_TOP_AXI_PROT_EN_1_SET, 176 + MT8186_TOP_AXI_PROT_EN_1_CLR, 177 + MT8186_TOP_AXI_PROT_EN_1_STA), 178 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2, 179 + MT8186_TOP_AXI_PROT_EN_1_SET, 180 + MT8186_TOP_AXI_PROT_EN_1_CLR, 181 + MT8186_TOP_AXI_PROT_EN_1_STA), 182 + }, 183 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 184 + }, 185 + [MT8186_POWER_DOMAIN_CAM_RAWA] = { 186 + .name = "cam_rawa", 187 + .sta_mask = BIT(24), 188 + .ctl_offs = 0x360, 189 + .pwr_sta_offs = 0x16C, 190 + .pwr_sta2nd_offs = 0x170, 191 + .sram_pdn_bits = BIT(8), 192 + .sram_pdn_ack_bits = BIT(12), 193 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 194 + }, 195 + [MT8186_POWER_DOMAIN_CAM_RAWB] = { 196 + .name = "cam_rawb", 197 + .sta_mask = BIT(25), 198 + .ctl_offs = 0x364, 199 + .pwr_sta_offs = 0x16C, 200 + .pwr_sta2nd_offs = 0x170, 201 + .sram_pdn_bits = BIT(8), 202 + .sram_pdn_ack_bits = BIT(12), 203 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 204 + }, 205 + [MT8186_POWER_DOMAIN_VENC] = { 206 + .name = "venc", 207 + .sta_mask = BIT(18), 208 + .ctl_offs = 0x348, 209 + .pwr_sta_offs = 0x16C, 210 + .pwr_sta2nd_offs = 0x170, 211 + .sram_pdn_bits = BIT(8), 212 + .sram_pdn_ack_bits = BIT(12), 213 + .bp_infracfg = { 214 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1, 215 + MT8186_TOP_AXI_PROT_EN_1_SET, 216 + MT8186_TOP_AXI_PROT_EN_1_CLR, 217 + MT8186_TOP_AXI_PROT_EN_1_STA), 218 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2, 219 + MT8186_TOP_AXI_PROT_EN_1_SET, 220 + MT8186_TOP_AXI_PROT_EN_1_CLR, 221 + MT8186_TOP_AXI_PROT_EN_1_STA), 222 + }, 223 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 224 + }, 225 + [MT8186_POWER_DOMAIN_VDEC] = { 226 + .name = "vdec", 227 + .sta_mask = BIT(16), 228 + .ctl_offs = 0x340, 229 + .pwr_sta_offs = 0x16C, 230 + .pwr_sta2nd_offs = 0x170, 231 + .sram_pdn_bits = BIT(8), 232 + .sram_pdn_ack_bits = BIT(12), 233 + .bp_infracfg = { 234 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1, 235 + MT8186_TOP_AXI_PROT_EN_1_SET, 236 + MT8186_TOP_AXI_PROT_EN_1_CLR, 237 + MT8186_TOP_AXI_PROT_EN_1_STA), 238 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2, 239 + MT8186_TOP_AXI_PROT_EN_1_SET, 240 + MT8186_TOP_AXI_PROT_EN_1_CLR, 241 + MT8186_TOP_AXI_PROT_EN_1_STA), 242 + }, 243 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 244 + }, 245 + [MT8186_POWER_DOMAIN_WPE] = { 246 + .name = "wpe", 247 + .sta_mask = BIT(0), 248 + .ctl_offs = 0x3F8, 249 + .pwr_sta_offs = 0x16C, 250 + .pwr_sta2nd_offs = 0x170, 251 + .sram_pdn_bits = BIT(8), 252 + .sram_pdn_ack_bits = BIT(12), 253 + .bp_infracfg = { 254 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1, 255 + MT8186_TOP_AXI_PROT_EN_2_SET, 256 + MT8186_TOP_AXI_PROT_EN_2_CLR, 257 + MT8186_TOP_AXI_PROT_EN_2_STA), 258 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2, 259 + MT8186_TOP_AXI_PROT_EN_2_SET, 260 + MT8186_TOP_AXI_PROT_EN_2_CLR, 261 + MT8186_TOP_AXI_PROT_EN_2_STA), 262 + }, 263 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 264 + }, 265 + [MT8186_POWER_DOMAIN_CONN_ON] = { 266 + .name = "conn_on", 267 + .sta_mask = BIT(1), 268 + .ctl_offs = 0x304, 269 + .pwr_sta_offs = 0x16C, 270 + .pwr_sta2nd_offs = 0x170, 271 + .bp_infracfg = { 272 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1, 273 + MT8186_TOP_AXI_PROT_EN_1_SET, 274 + MT8186_TOP_AXI_PROT_EN_1_CLR, 275 + MT8186_TOP_AXI_PROT_EN_1_STA), 276 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2, 277 + MT8186_TOP_AXI_PROT_EN_SET, 278 + MT8186_TOP_AXI_PROT_EN_CLR, 279 + MT8186_TOP_AXI_PROT_EN_STA), 280 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3, 281 + MT8186_TOP_AXI_PROT_EN_SET, 282 + MT8186_TOP_AXI_PROT_EN_CLR, 283 + MT8186_TOP_AXI_PROT_EN_STA), 284 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4, 285 + MT8186_TOP_AXI_PROT_EN_SET, 286 + MT8186_TOP_AXI_PROT_EN_CLR, 287 + MT8186_TOP_AXI_PROT_EN_STA), 288 + }, 289 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 290 + }, 291 + [MT8186_POWER_DOMAIN_CSIRX_TOP] = { 292 + .name = "csirx_top", 293 + .sta_mask = BIT(6), 294 + .ctl_offs = 0x318, 295 + .pwr_sta_offs = 0x16C, 296 + .pwr_sta2nd_offs = 0x170, 297 + .sram_pdn_bits = BIT(8), 298 + .sram_pdn_ack_bits = BIT(12), 299 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 300 + }, 301 + [MT8186_POWER_DOMAIN_ADSP_AO] = { 302 + .name = "adsp_ao", 303 + .sta_mask = BIT(17), 304 + .ctl_offs = 0x9FC, 305 + .pwr_sta_offs = 0x16C, 306 + .pwr_sta2nd_offs = 0x170, 307 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 308 + }, 309 + [MT8186_POWER_DOMAIN_ADSP_INFRA] = { 310 + .name = "adsp_infra", 311 + .sta_mask = BIT(10), 312 + .ctl_offs = 0x9F8, 313 + .pwr_sta_offs = 0x16C, 314 + .pwr_sta2nd_offs = 0x170, 315 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 316 + }, 317 + [MT8186_POWER_DOMAIN_ADSP_TOP] = { 318 + .name = "adsp_top", 319 + .sta_mask = BIT(31), 320 + .ctl_offs = 0x3E4, 321 + .pwr_sta_offs = 0x16C, 322 + .pwr_sta2nd_offs = 0x170, 323 + .sram_pdn_bits = BIT(8), 324 + .sram_pdn_ack_bits = BIT(12), 325 + .bp_infracfg = { 326 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1, 327 + MT8186_TOP_AXI_PROT_EN_3_SET, 328 + MT8186_TOP_AXI_PROT_EN_3_CLR, 329 + MT8186_TOP_AXI_PROT_EN_3_STA), 330 + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2, 331 + MT8186_TOP_AXI_PROT_EN_3_SET, 332 + MT8186_TOP_AXI_PROT_EN_3_CLR, 333 + MT8186_TOP_AXI_PROT_EN_3_STA), 334 + }, 335 + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 336 + }, 337 + }; 338 + 339 + static const struct scpsys_soc_data mt8186_scpsys_data = { 340 + .domains_data = scpsys_domain_data_mt8186, 341 + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8186), 342 + }; 343 + 344 + #endif /* __SOC_MEDIATEK_MT8186_PM_DOMAINS_H */

+42 -2

drivers/soc/mediatek/mt8192-pm-domains.h

··· 15 15 .name = "audio", 16 16 .sta_mask = BIT(21), 17 17 .ctl_offs = 0x0354, 18 + .pwr_sta_offs = 0x016c, 19 + .pwr_sta2nd_offs = 0x0170, 18 20 .sram_pdn_bits = GENMASK(8, 8), 19 21 .sram_pdn_ack_bits = GENMASK(12, 12), 20 22 .bp_infracfg = { ··· 30 28 .name = "conn", 31 29 .sta_mask = PWR_STATUS_CONN, 32 30 .ctl_offs = 0x0304, 31 + .pwr_sta_offs = 0x016c, 32 + .pwr_sta2nd_offs = 0x0170, 33 33 .sram_pdn_bits = 0, 34 34 .sram_pdn_ack_bits = 0, 35 35 .bp_infracfg = { ··· 54 50 .name = "mfg0", 55 51 .sta_mask = BIT(2), 56 52 .ctl_offs = 0x0308, 53 + .pwr_sta_offs = 0x016c, 54 + .pwr_sta2nd_offs = 0x0170, 57 55 .sram_pdn_bits = GENMASK(8, 8), 58 56 .sram_pdn_ack_bits = GENMASK(12, 12), 59 57 }, ··· 63 57 .name = "mfg1", 64 58 .sta_mask = BIT(3), 65 59 .ctl_offs = 0x030c, 60 + .pwr_sta_offs = 0x016c, 61 + .pwr_sta2nd_offs = 0x0170, 66 62 .sram_pdn_bits = GENMASK(8, 8), 67 63 .sram_pdn_ack_bits = GENMASK(12, 12), 68 64 .bp_infracfg = { ··· 90 82 .name = "mfg2", 91 83 .sta_mask = BIT(4), 92 84 .ctl_offs = 0x0310, 85 + .pwr_sta_offs = 0x016c, 86 + .pwr_sta2nd_offs = 0x0170, 93 87 .sram_pdn_bits = GENMASK(8, 8), 94 88 .sram_pdn_ack_bits = GENMASK(12, 12), 95 89 }, ··· 99 89 .name = "mfg3", 100 90 .sta_mask = BIT(5), 101 91 .ctl_offs = 0x0314, 92 + .pwr_sta_offs = 0x016c, 93 + .pwr_sta2nd_offs = 0x0170, 102 94 .sram_pdn_bits = GENMASK(8, 8), 103 95 .sram_pdn_ack_bits = GENMASK(12, 12), 104 96 }, ··· 108 96 .name = "mfg4", 109 97 .sta_mask = BIT(6), 110 98 .ctl_offs = 0x0318, 99 + .pwr_sta_offs = 0x016c, 100 + .pwr_sta2nd_offs = 0x0170, 111 101 .sram_pdn_bits = GENMASK(8, 8), 112 102 .sram_pdn_ack_bits = GENMASK(12, 12), 113 103 }, ··· 117 103 .name = "mfg5", 118 104 .sta_mask = BIT(7), 119 105 .ctl_offs = 0x031c, 106 + .pwr_sta_offs = 0x016c, 107 + .pwr_sta2nd_offs = 0x0170, 120 108 .sram_pdn_bits = GENMASK(8, 8), 121 109 .sram_pdn_ack_bits = GENMASK(12, 12), 122 110 }, ··· 126 110 .name = "mfg6", 127 111 .sta_mask = BIT(8), 128 112 .ctl_offs = 0x0320, 113 + .pwr_sta_offs = 0x016c, 114 + .pwr_sta2nd_offs = 0x0170, 129 115 .sram_pdn_bits = GENMASK(8, 8), 130 116 .sram_pdn_ack_bits = GENMASK(12, 12), 131 117 }, ··· 135 117 .name = "disp", 136 118 .sta_mask = BIT(20), 137 119 .ctl_offs = 0x0350, 120 + .pwr_sta_offs = 0x016c, 121 + .pwr_sta2nd_offs = 0x0170, 138 122 .sram_pdn_bits = GENMASK(8, 8), 139 123 .sram_pdn_ack_bits = GENMASK(12, 12), 140 124 .bp_infracfg = { ··· 166 146 .name = "ipe", 167 147 .sta_mask = BIT(14), 168 148 .ctl_offs = 0x0338, 149 + .pwr_sta_offs = 0x016c, 150 + .pwr_sta2nd_offs = 0x0170, 169 151 .sram_pdn_bits = GENMASK(8, 8), 170 152 .sram_pdn_ack_bits = GENMASK(12, 12), 171 153 .bp_infracfg = { ··· 185 163 .name = "isp", 186 164 .sta_mask = BIT(12), 187 165 .ctl_offs = 0x0330, 166 + .pwr_sta_offs = 0x016c, 167 + .pwr_sta2nd_offs = 0x0170, 188 168 .sram_pdn_bits = GENMASK(8, 8), 189 169 .sram_pdn_ack_bits = GENMASK(12, 12), 190 170 .bp_infracfg = { ··· 204 180 .name = "isp2", 205 181 .sta_mask = BIT(13), 206 182 .ctl_offs = 0x0334, 183 + .pwr_sta_offs = 0x016c, 184 + .pwr_sta2nd_offs = 0x0170, 207 185 .sram_pdn_bits = GENMASK(8, 8), 208 186 .sram_pdn_ack_bits = GENMASK(12, 12), 209 187 .bp_infracfg = { ··· 223 197 .name = "mdp", 224 198 .sta_mask = BIT(19), 225 199 .ctl_offs = 0x034c, 200 + .pwr_sta_offs = 0x016c, 201 + .pwr_sta2nd_offs = 0x0170, 226 202 .sram_pdn_bits = GENMASK(8, 8), 227 203 .sram_pdn_ack_bits = GENMASK(12, 12), 228 204 .bp_infracfg = { ··· 242 214 .name = "venc", 243 215 .sta_mask = BIT(17), 244 216 .ctl_offs = 0x0344, 217 + .pwr_sta_offs = 0x016c, 218 + .pwr_sta2nd_offs = 0x0170, 245 219 .sram_pdn_bits = GENMASK(8, 8), 246 220 .sram_pdn_ack_bits = GENMASK(12, 12), 247 221 .bp_infracfg = { ··· 261 231 .name = "vdec", 262 232 .sta_mask = BIT(15), 263 233 .ctl_offs = 0x033c, 234 + .pwr_sta_offs = 0x016c, 235 + .pwr_sta2nd_offs = 0x0170, 264 236 .sram_pdn_bits = GENMASK(8, 8), 265 237 .sram_pdn_ack_bits = GENMASK(12, 12), 266 238 .bp_infracfg = { ··· 280 248 .name = "vdec2", 281 249 .sta_mask = BIT(16), 282 250 .ctl_offs = 0x0340, 251 + .pwr_sta_offs = 0x016c, 252 + .pwr_sta2nd_offs = 0x0170, 283 253 .sram_pdn_bits = GENMASK(8, 8), 284 254 .sram_pdn_ack_bits = GENMASK(12, 12), 285 255 }, ··· 289 255 .name = "cam", 290 256 .sta_mask = BIT(23), 291 257 .ctl_offs = 0x035c, 258 + .pwr_sta_offs = 0x016c, 259 + .pwr_sta2nd_offs = 0x0170, 292 260 .sram_pdn_bits = GENMASK(8, 8), 293 261 .sram_pdn_ack_bits = GENMASK(12, 12), 294 262 .bp_infracfg = { ··· 320 284 .name = "cam_rawa", 321 285 .sta_mask = BIT(24), 322 286 .ctl_offs = 0x0360, 287 + .pwr_sta_offs = 0x016c, 288 + .pwr_sta2nd_offs = 0x0170, 323 289 .sram_pdn_bits = GENMASK(8, 8), 324 290 .sram_pdn_ack_bits = GENMASK(12, 12), 325 291 }, ··· 329 291 .name = "cam_rawb", 330 292 .sta_mask = BIT(25), 331 293 .ctl_offs = 0x0364, 294 + .pwr_sta_offs = 0x016c, 295 + .pwr_sta2nd_offs = 0x0170, 332 296 .sram_pdn_bits = GENMASK(8, 8), 333 297 .sram_pdn_ack_bits = GENMASK(12, 12), 334 298 }, ··· 338 298 .name = "cam_rawc", 339 299 .sta_mask = BIT(26), 340 300 .ctl_offs = 0x0368, 301 + .pwr_sta_offs = 0x016c, 302 + .pwr_sta2nd_offs = 0x0170, 341 303 .sram_pdn_bits = GENMASK(8, 8), 342 304 .sram_pdn_ack_bits = GENMASK(12, 12), 343 305 }, ··· 348 306 static const struct scpsys_soc_data mt8192_scpsys_data = { 349 307 .domains_data = scpsys_domain_data_mt8192, 350 308 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192), 351 - .pwr_sta_offs = 0x016c, 352 - .pwr_sta2nd_offs = 0x0170, 353 309 }; 354 310 355 311 #endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */

+613

drivers/soc/mediatek/mt8195-pm-domains.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* 3 + * Copyright (c) 2021 MediaTek Inc. 4 + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 + */ 6 + 7 + #ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H 8 + #define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H 9 + 10 + #include "mtk-pm-domains.h" 11 + #include <dt-bindings/power/mt8195-power.h> 12 + 13 + /* 14 + * MT8195 power domain support 15 + */ 16 + 17 + static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { 18 + [MT8195_POWER_DOMAIN_PCIE_MAC_P0] = { 19 + .name = "pcie_mac_p0", 20 + .sta_mask = BIT(11), 21 + .ctl_offs = 0x328, 22 + .pwr_sta_offs = 0x174, 23 + .pwr_sta2nd_offs = 0x178, 24 + .sram_pdn_bits = GENMASK(8, 8), 25 + .sram_pdn_ack_bits = GENMASK(12, 12), 26 + .bp_infracfg = { 27 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, 28 + MT8195_TOP_AXI_PROT_EN_VDNR_SET, 29 + MT8195_TOP_AXI_PROT_EN_VDNR_CLR, 30 + MT8195_TOP_AXI_PROT_EN_VDNR_STA1), 31 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, 32 + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 33 + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 34 + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 35 + }, 36 + }, 37 + [MT8195_POWER_DOMAIN_PCIE_MAC_P1] = { 38 + .name = "pcie_mac_p1", 39 + .sta_mask = BIT(12), 40 + .ctl_offs = 0x32C, 41 + .pwr_sta_offs = 0x174, 42 + .pwr_sta2nd_offs = 0x178, 43 + .sram_pdn_bits = GENMASK(8, 8), 44 + .sram_pdn_ack_bits = GENMASK(12, 12), 45 + .bp_infracfg = { 46 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, 47 + MT8195_TOP_AXI_PROT_EN_VDNR_SET, 48 + MT8195_TOP_AXI_PROT_EN_VDNR_CLR, 49 + MT8195_TOP_AXI_PROT_EN_VDNR_STA1), 50 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, 51 + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 52 + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 53 + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 54 + }, 55 + }, 56 + [MT8195_POWER_DOMAIN_PCIE_PHY] = { 57 + .name = "pcie_phy", 58 + .sta_mask = BIT(13), 59 + .ctl_offs = 0x330, 60 + .pwr_sta_offs = 0x174, 61 + .pwr_sta2nd_offs = 0x178, 62 + .caps = MTK_SCPD_ACTIVE_WAKEUP, 63 + }, 64 + [MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY] = { 65 + .name = "ssusb_pcie_phy", 66 + .sta_mask = BIT(14), 67 + .ctl_offs = 0x334, 68 + .pwr_sta_offs = 0x174, 69 + .pwr_sta2nd_offs = 0x178, 70 + .caps = MTK_SCPD_ACTIVE_WAKEUP, 71 + }, 72 + [MT8195_POWER_DOMAIN_CSI_RX_TOP] = { 73 + .name = "csi_rx_top", 74 + .sta_mask = BIT(18), 75 + .ctl_offs = 0x3C4, 76 + .pwr_sta_offs = 0x174, 77 + .pwr_sta2nd_offs = 0x178, 78 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 79 + }, 80 + [MT8195_POWER_DOMAIN_ETHER] = { 81 + .name = "ether", 82 + .sta_mask = BIT(3), 83 + .ctl_offs = 0x344, 84 + .pwr_sta_offs = 0x16c, 85 + .pwr_sta2nd_offs = 0x170, 86 + .sram_pdn_bits = GENMASK(8, 8), 87 + .sram_pdn_ack_bits = GENMASK(12, 12), 88 + .caps = MTK_SCPD_ACTIVE_WAKEUP, 89 + }, 90 + [MT8195_POWER_DOMAIN_ADSP] = { 91 + .name = "adsp", 92 + .sta_mask = BIT(10), 93 + .ctl_offs = 0x360, 94 + .pwr_sta_offs = 0x16c, 95 + .pwr_sta2nd_offs = 0x170, 96 + .sram_pdn_bits = GENMASK(8, 8), 97 + .sram_pdn_ack_bits = GENMASK(12, 12), 98 + .bp_infracfg = { 99 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP, 100 + MT8195_TOP_AXI_PROT_EN_2_SET, 101 + MT8195_TOP_AXI_PROT_EN_2_CLR, 102 + MT8195_TOP_AXI_PROT_EN_2_STA1), 103 + }, 104 + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, 105 + }, 106 + [MT8195_POWER_DOMAIN_AUDIO] = { 107 + .name = "audio", 108 + .sta_mask = BIT(8), 109 + .ctl_offs = 0x358, 110 + .pwr_sta_offs = 0x16c, 111 + .pwr_sta2nd_offs = 0x170, 112 + .sram_pdn_bits = GENMASK(8, 8), 113 + .sram_pdn_ack_bits = GENMASK(12, 12), 114 + .bp_infracfg = { 115 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO, 116 + MT8195_TOP_AXI_PROT_EN_2_SET, 117 + MT8195_TOP_AXI_PROT_EN_2_CLR, 118 + MT8195_TOP_AXI_PROT_EN_2_STA1), 119 + }, 120 + }, 121 + [MT8195_POWER_DOMAIN_MFG0] = { 122 + .name = "mfg0", 123 + .sta_mask = BIT(1), 124 + .ctl_offs = 0x300, 125 + .pwr_sta_offs = 0x174, 126 + .pwr_sta2nd_offs = 0x178, 127 + .sram_pdn_bits = GENMASK(8, 8), 128 + .sram_pdn_ack_bits = GENMASK(12, 12), 129 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 130 + }, 131 + [MT8195_POWER_DOMAIN_MFG1] = { 132 + .name = "mfg1", 133 + .sta_mask = BIT(2), 134 + .ctl_offs = 0x304, 135 + .pwr_sta_offs = 0x174, 136 + .pwr_sta2nd_offs = 0x178, 137 + .sram_pdn_bits = GENMASK(8, 8), 138 + .sram_pdn_ack_bits = GENMASK(12, 12), 139 + .bp_infracfg = { 140 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1, 141 + MT8195_TOP_AXI_PROT_EN_SET, 142 + MT8195_TOP_AXI_PROT_EN_CLR, 143 + MT8195_TOP_AXI_PROT_EN_STA1), 144 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1, 145 + MT8195_TOP_AXI_PROT_EN_2_SET, 146 + MT8195_TOP_AXI_PROT_EN_2_CLR, 147 + MT8195_TOP_AXI_PROT_EN_2_STA1), 148 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1, 149 + MT8195_TOP_AXI_PROT_EN_1_SET, 150 + MT8195_TOP_AXI_PROT_EN_1_CLR, 151 + MT8195_TOP_AXI_PROT_EN_1_STA1), 152 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, 153 + MT8195_TOP_AXI_PROT_EN_2_SET, 154 + MT8195_TOP_AXI_PROT_EN_2_CLR, 155 + MT8195_TOP_AXI_PROT_EN_2_STA1), 156 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND, 157 + MT8195_TOP_AXI_PROT_EN_SET, 158 + MT8195_TOP_AXI_PROT_EN_CLR, 159 + MT8195_TOP_AXI_PROT_EN_STA1), 160 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, 161 + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 162 + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 163 + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), 164 + }, 165 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 166 + }, 167 + [MT8195_POWER_DOMAIN_MFG2] = { 168 + .name = "mfg2", 169 + .sta_mask = BIT(3), 170 + .ctl_offs = 0x308, 171 + .pwr_sta_offs = 0x174, 172 + .pwr_sta2nd_offs = 0x178, 173 + .sram_pdn_bits = GENMASK(8, 8), 174 + .sram_pdn_ack_bits = GENMASK(12, 12), 175 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 176 + }, 177 + [MT8195_POWER_DOMAIN_MFG3] = { 178 + .name = "mfg3", 179 + .sta_mask = BIT(4), 180 + .ctl_offs = 0x30C, 181 + .pwr_sta_offs = 0x174, 182 + .pwr_sta2nd_offs = 0x178, 183 + .sram_pdn_bits = GENMASK(8, 8), 184 + .sram_pdn_ack_bits = GENMASK(12, 12), 185 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 186 + }, 187 + [MT8195_POWER_DOMAIN_MFG4] = { 188 + .name = "mfg4", 189 + .sta_mask = BIT(5), 190 + .ctl_offs = 0x310, 191 + .pwr_sta_offs = 0x174, 192 + .pwr_sta2nd_offs = 0x178, 193 + .sram_pdn_bits = GENMASK(8, 8), 194 + .sram_pdn_ack_bits = GENMASK(12, 12), 195 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 196 + }, 197 + [MT8195_POWER_DOMAIN_MFG5] = { 198 + .name = "mfg5", 199 + .sta_mask = BIT(6), 200 + .ctl_offs = 0x314, 201 + .pwr_sta_offs = 0x174, 202 + .pwr_sta2nd_offs = 0x178, 203 + .sram_pdn_bits = GENMASK(8, 8), 204 + .sram_pdn_ack_bits = GENMASK(12, 12), 205 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 206 + }, 207 + [MT8195_POWER_DOMAIN_MFG6] = { 208 + .name = "mfg6", 209 + .sta_mask = BIT(7), 210 + .ctl_offs = 0x318, 211 + .pwr_sta_offs = 0x174, 212 + .pwr_sta2nd_offs = 0x178, 213 + .sram_pdn_bits = GENMASK(8, 8), 214 + .sram_pdn_ack_bits = GENMASK(12, 12), 215 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 216 + }, 217 + [MT8195_POWER_DOMAIN_VPPSYS0] = { 218 + .name = "vppsys0", 219 + .sta_mask = BIT(11), 220 + .ctl_offs = 0x364, 221 + .pwr_sta_offs = 0x16c, 222 + .pwr_sta2nd_offs = 0x170, 223 + .sram_pdn_bits = GENMASK(8, 8), 224 + .sram_pdn_ack_bits = GENMASK(12, 12), 225 + .bp_infracfg = { 226 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0, 227 + MT8195_TOP_AXI_PROT_EN_SET, 228 + MT8195_TOP_AXI_PROT_EN_CLR, 229 + MT8195_TOP_AXI_PROT_EN_STA1), 230 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, 231 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 232 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 233 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 234 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, 235 + MT8195_TOP_AXI_PROT_EN_SET, 236 + MT8195_TOP_AXI_PROT_EN_CLR, 237 + MT8195_TOP_AXI_PROT_EN_STA1), 238 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, 239 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 240 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 241 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 242 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, 243 + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 244 + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 245 + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), 246 + }, 247 + }, 248 + [MT8195_POWER_DOMAIN_VDOSYS0] = { 249 + .name = "vdosys0", 250 + .sta_mask = BIT(13), 251 + .ctl_offs = 0x36C, 252 + .pwr_sta_offs = 0x16c, 253 + .pwr_sta2nd_offs = 0x170, 254 + .sram_pdn_bits = GENMASK(8, 8), 255 + .sram_pdn_ack_bits = GENMASK(12, 12), 256 + .bp_infracfg = { 257 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, 258 + MT8195_TOP_AXI_PROT_EN_MM_SET, 259 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 260 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 261 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0, 262 + MT8195_TOP_AXI_PROT_EN_SET, 263 + MT8195_TOP_AXI_PROT_EN_CLR, 264 + MT8195_TOP_AXI_PROT_EN_STA1), 265 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, 266 + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 267 + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 268 + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), 269 + }, 270 + }, 271 + [MT8195_POWER_DOMAIN_VPPSYS1] = { 272 + .name = "vppsys1", 273 + .sta_mask = BIT(12), 274 + .ctl_offs = 0x368, 275 + .pwr_sta_offs = 0x16c, 276 + .pwr_sta2nd_offs = 0x170, 277 + .sram_pdn_bits = GENMASK(8, 8), 278 + .sram_pdn_ack_bits = GENMASK(12, 12), 279 + .bp_infracfg = { 280 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, 281 + MT8195_TOP_AXI_PROT_EN_MM_SET, 282 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 283 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 284 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, 285 + MT8195_TOP_AXI_PROT_EN_MM_SET, 286 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 287 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 288 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, 289 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 290 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 291 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 292 + }, 293 + }, 294 + [MT8195_POWER_DOMAIN_VDOSYS1] = { 295 + .name = "vdosys1", 296 + .sta_mask = BIT(14), 297 + .ctl_offs = 0x370, 298 + .pwr_sta_offs = 0x16c, 299 + .pwr_sta2nd_offs = 0x170, 300 + .sram_pdn_bits = GENMASK(8, 8), 301 + .sram_pdn_ack_bits = GENMASK(12, 12), 302 + .bp_infracfg = { 303 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, 304 + MT8195_TOP_AXI_PROT_EN_MM_SET, 305 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 306 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 307 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, 308 + MT8195_TOP_AXI_PROT_EN_MM_SET, 309 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 310 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 311 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, 312 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 313 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 314 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 315 + }, 316 + }, 317 + [MT8195_POWER_DOMAIN_DP_TX] = { 318 + .name = "dp_tx", 319 + .sta_mask = BIT(16), 320 + .ctl_offs = 0x378, 321 + .pwr_sta_offs = 0x16c, 322 + .pwr_sta2nd_offs = 0x170, 323 + .sram_pdn_bits = GENMASK(8, 8), 324 + .sram_pdn_ack_bits = GENMASK(12, 12), 325 + .bp_infracfg = { 326 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, 327 + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 328 + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 329 + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 330 + }, 331 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 332 + }, 333 + [MT8195_POWER_DOMAIN_EPD_TX] = { 334 + .name = "epd_tx", 335 + .sta_mask = BIT(17), 336 + .ctl_offs = 0x37C, 337 + .pwr_sta_offs = 0x16c, 338 + .pwr_sta2nd_offs = 0x170, 339 + .sram_pdn_bits = GENMASK(8, 8), 340 + .sram_pdn_ack_bits = GENMASK(12, 12), 341 + .bp_infracfg = { 342 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, 343 + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 344 + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 345 + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 346 + }, 347 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 348 + }, 349 + [MT8195_POWER_DOMAIN_HDMI_TX] = { 350 + .name = "hdmi_tx", 351 + .sta_mask = BIT(18), 352 + .ctl_offs = 0x380, 353 + .pwr_sta_offs = 0x16c, 354 + .pwr_sta2nd_offs = 0x170, 355 + .sram_pdn_bits = GENMASK(8, 8), 356 + .sram_pdn_ack_bits = GENMASK(12, 12), 357 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 358 + }, 359 + [MT8195_POWER_DOMAIN_WPESYS] = { 360 + .name = "wpesys", 361 + .sta_mask = BIT(15), 362 + .ctl_offs = 0x374, 363 + .pwr_sta_offs = 0x16c, 364 + .pwr_sta2nd_offs = 0x170, 365 + .sram_pdn_bits = GENMASK(8, 8), 366 + .sram_pdn_ack_bits = GENMASK(12, 12), 367 + .bp_infracfg = { 368 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, 369 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 370 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 371 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 372 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS, 373 + MT8195_TOP_AXI_PROT_EN_MM_SET, 374 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 375 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 376 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, 377 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 378 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 379 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 380 + }, 381 + }, 382 + [MT8195_POWER_DOMAIN_VDEC0] = { 383 + .name = "vdec0", 384 + .sta_mask = BIT(20), 385 + .ctl_offs = 0x388, 386 + .pwr_sta_offs = 0x16c, 387 + .pwr_sta2nd_offs = 0x170, 388 + .sram_pdn_bits = GENMASK(8, 8), 389 + .sram_pdn_ack_bits = GENMASK(12, 12), 390 + .bp_infracfg = { 391 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0, 392 + MT8195_TOP_AXI_PROT_EN_MM_SET, 393 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 394 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 395 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, 396 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 397 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 398 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 399 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, 400 + MT8195_TOP_AXI_PROT_EN_MM_SET, 401 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 402 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 403 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, 404 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 405 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 406 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 407 + }, 408 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 409 + }, 410 + [MT8195_POWER_DOMAIN_VDEC1] = { 411 + .name = "vdec1", 412 + .sta_mask = BIT(21), 413 + .ctl_offs = 0x38C, 414 + .pwr_sta_offs = 0x16c, 415 + .pwr_sta2nd_offs = 0x170, 416 + .sram_pdn_bits = GENMASK(8, 8), 417 + .sram_pdn_ack_bits = GENMASK(12, 12), 418 + .bp_infracfg = { 419 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1, 420 + MT8195_TOP_AXI_PROT_EN_MM_SET, 421 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 422 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 423 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, 424 + MT8195_TOP_AXI_PROT_EN_MM_SET, 425 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 426 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 427 + }, 428 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 429 + }, 430 + [MT8195_POWER_DOMAIN_VDEC2] = { 431 + .name = "vdec2", 432 + .sta_mask = BIT(22), 433 + .ctl_offs = 0x390, 434 + .pwr_sta_offs = 0x16c, 435 + .pwr_sta2nd_offs = 0x170, 436 + .sram_pdn_bits = GENMASK(8, 8), 437 + .sram_pdn_ack_bits = GENMASK(12, 12), 438 + .bp_infracfg = { 439 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, 440 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 441 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 442 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 443 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, 444 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 445 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 446 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 447 + }, 448 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 449 + }, 450 + [MT8195_POWER_DOMAIN_VENC] = { 451 + .name = "venc", 452 + .sta_mask = BIT(23), 453 + .ctl_offs = 0x394, 454 + .pwr_sta_offs = 0x16c, 455 + .pwr_sta2nd_offs = 0x170, 456 + .sram_pdn_bits = GENMASK(8, 8), 457 + .sram_pdn_ack_bits = GENMASK(12, 12), 458 + .bp_infracfg = { 459 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC, 460 + MT8195_TOP_AXI_PROT_EN_MM_SET, 461 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 462 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 463 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, 464 + MT8195_TOP_AXI_PROT_EN_MM_SET, 465 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 466 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 467 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC, 468 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 469 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 470 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 471 + }, 472 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 473 + }, 474 + [MT8195_POWER_DOMAIN_VENC_CORE1] = { 475 + .name = "venc_core1", 476 + .sta_mask = BIT(24), 477 + .ctl_offs = 0x398, 478 + .pwr_sta_offs = 0x16c, 479 + .pwr_sta2nd_offs = 0x170, 480 + .sram_pdn_bits = GENMASK(8, 8), 481 + .sram_pdn_ack_bits = GENMASK(12, 12), 482 + .bp_infracfg = { 483 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, 484 + MT8195_TOP_AXI_PROT_EN_MM_SET, 485 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 486 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 487 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, 488 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 489 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 490 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 491 + }, 492 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 493 + }, 494 + [MT8195_POWER_DOMAIN_IMG] = { 495 + .name = "img", 496 + .sta_mask = BIT(29), 497 + .ctl_offs = 0x3AC, 498 + .pwr_sta_offs = 0x16c, 499 + .pwr_sta2nd_offs = 0x170, 500 + .sram_pdn_bits = GENMASK(8, 8), 501 + .sram_pdn_ack_bits = GENMASK(12, 12), 502 + .bp_infracfg = { 503 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG, 504 + MT8195_TOP_AXI_PROT_EN_MM_SET, 505 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 506 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 507 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, 508 + MT8195_TOP_AXI_PROT_EN_MM_SET, 509 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 510 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 511 + }, 512 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 513 + }, 514 + [MT8195_POWER_DOMAIN_DIP] = { 515 + .name = "dip", 516 + .sta_mask = BIT(30), 517 + .ctl_offs = 0x3B0, 518 + .pwr_sta_offs = 0x16c, 519 + .pwr_sta2nd_offs = 0x170, 520 + .sram_pdn_bits = GENMASK(8, 8), 521 + .sram_pdn_ack_bits = GENMASK(12, 12), 522 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 523 + }, 524 + [MT8195_POWER_DOMAIN_IPE] = { 525 + .name = "ipe", 526 + .sta_mask = BIT(31), 527 + .ctl_offs = 0x3B4, 528 + .pwr_sta_offs = 0x16c, 529 + .pwr_sta2nd_offs = 0x170, 530 + .sram_pdn_bits = GENMASK(8, 8), 531 + .sram_pdn_ack_bits = GENMASK(12, 12), 532 + .bp_infracfg = { 533 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE, 534 + MT8195_TOP_AXI_PROT_EN_MM_SET, 535 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 536 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 537 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE, 538 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 539 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 540 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 541 + }, 542 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 543 + }, 544 + [MT8195_POWER_DOMAIN_CAM] = { 545 + .name = "cam", 546 + .sta_mask = BIT(25), 547 + .ctl_offs = 0x39C, 548 + .pwr_sta_offs = 0x16c, 549 + .pwr_sta2nd_offs = 0x170, 550 + .sram_pdn_bits = GENMASK(8, 8), 551 + .sram_pdn_ack_bits = GENMASK(12, 12), 552 + .bp_infracfg = { 553 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM, 554 + MT8195_TOP_AXI_PROT_EN_2_SET, 555 + MT8195_TOP_AXI_PROT_EN_2_CLR, 556 + MT8195_TOP_AXI_PROT_EN_2_STA1), 557 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM, 558 + MT8195_TOP_AXI_PROT_EN_MM_SET, 559 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 560 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 561 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM, 562 + MT8195_TOP_AXI_PROT_EN_1_SET, 563 + MT8195_TOP_AXI_PROT_EN_1_CLR, 564 + MT8195_TOP_AXI_PROT_EN_1_STA1), 565 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, 566 + MT8195_TOP_AXI_PROT_EN_MM_SET, 567 + MT8195_TOP_AXI_PROT_EN_MM_CLR, 568 + MT8195_TOP_AXI_PROT_EN_MM_STA1), 569 + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM, 570 + MT8195_TOP_AXI_PROT_EN_MM_2_SET, 571 + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 572 + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 573 + }, 574 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 575 + }, 576 + [MT8195_POWER_DOMAIN_CAM_RAWA] = { 577 + .name = "cam_rawa", 578 + .sta_mask = BIT(26), 579 + .ctl_offs = 0x3A0, 580 + .pwr_sta_offs = 0x16c, 581 + .pwr_sta2nd_offs = 0x170, 582 + .sram_pdn_bits = GENMASK(8, 8), 583 + .sram_pdn_ack_bits = GENMASK(12, 12), 584 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 585 + }, 586 + [MT8195_POWER_DOMAIN_CAM_RAWB] = { 587 + .name = "cam_rawb", 588 + .sta_mask = BIT(27), 589 + .ctl_offs = 0x3A4, 590 + .pwr_sta_offs = 0x16c, 591 + .pwr_sta2nd_offs = 0x170, 592 + .sram_pdn_bits = GENMASK(8, 8), 593 + .sram_pdn_ack_bits = GENMASK(12, 12), 594 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 595 + }, 596 + [MT8195_POWER_DOMAIN_CAM_MRAW] = { 597 + .name = "cam_mraw", 598 + .sta_mask = BIT(28), 599 + .ctl_offs = 0x3A8, 600 + .pwr_sta_offs = 0x16c, 601 + .pwr_sta2nd_offs = 0x170, 602 + .sram_pdn_bits = GENMASK(8, 8), 603 + .sram_pdn_ack_bits = GENMASK(12, 12), 604 + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 605 + }, 606 + }; 607 + 608 + static const struct scpsys_soc_data mt8195_scpsys_data = { 609 + .domains_data = scpsys_domain_data_mt8195, 610 + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8195), 611 + }; 612 + 613 + #endif /* __SOC_MEDIATEK_MT8195_PM_DOMAINS_H */

+19

drivers/soc/mediatek/mtk-infracfg.c

··· 6 6 #include <linux/export.h> 7 7 #include <linux/jiffies.h> 8 8 #include <linux/regmap.h> 9 + #include <linux/mfd/syscon.h> 9 10 #include <linux/soc/mediatek/infracfg.h> 10 11 #include <asm/processor.h> 11 12 ··· 73 72 74 73 return ret; 75 74 } 75 + 76 + static int __init mtk_infracfg_init(void) 77 + { 78 + struct regmap *infracfg; 79 + 80 + /* 81 + * MT8192 has an experimental path to route GPU traffic to the DSU's 82 + * Accelerator Coherency Port, which is inadvertently enabled by 83 + * default. It turns out not to work, so disable it to prevent spurious 84 + * GPU faults. 85 + */ 86 + infracfg = syscon_regmap_lookup_by_compatible("mediatek,mt8192-infracfg"); 87 + if (!IS_ERR(infracfg)) 88 + regmap_set_bits(infracfg, MT8192_INFRA_CTRL, 89 + MT8192_INFRA_CTRL_DISABLE_MFG2ACP); 90 + return 0; 91 + } 92 + postcore_initcall(mtk_infracfg_init);

+12

drivers/soc/mediatek/mtk-mmsys.c

··· 15 15 #include "mtk-mmsys.h" 16 16 #include "mt8167-mmsys.h" 17 17 #include "mt8183-mmsys.h" 18 + #include "mt8186-mmsys.h" 18 19 #include "mt8192-mmsys.h" 19 20 #include "mt8365-mmsys.h" 20 21 ··· 55 54 .clk_driver = "clk-mt8183-mm", 56 55 .routes = mmsys_mt8183_routing_table, 57 56 .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), 57 + }; 58 + 59 + static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 60 + .clk_driver = "clk-mt8186-mm", 61 + .routes = mmsys_mt8186_routing_table, 62 + .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), 63 + .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, 58 64 }; 59 65 60 66 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { ··· 249 241 { 250 242 .compatible = "mediatek,mt8183-mmsys", 251 243 .data = &mt8183_mmsys_driver_data, 244 + }, 245 + { 246 + .compatible = "mediatek,mt8186-mmsys", 247 + .data = &mt8186_mmsys_driver_data, 252 248 }, 253 249 { 254 250 .compatible = "mediatek,mt8192-mmsys",

+45

drivers/soc/mediatek/mtk-mutex.c

··· 26 26 27 27 #define INT_MUTEX BIT(1) 28 28 29 + #define MT8186_MUTEX_MOD_DISP_OVL0 0 30 + #define MT8186_MUTEX_MOD_DISP_OVL0_2L 1 31 + #define MT8186_MUTEX_MOD_DISP_RDMA0 2 32 + #define MT8186_MUTEX_MOD_DISP_COLOR0 4 33 + #define MT8186_MUTEX_MOD_DISP_CCORR0 5 34 + #define MT8186_MUTEX_MOD_DISP_AAL0 7 35 + #define MT8186_MUTEX_MOD_DISP_GAMMA0 8 36 + #define MT8186_MUTEX_MOD_DISP_POSTMASK0 9 37 + #define MT8186_MUTEX_MOD_DISP_DITHER0 10 38 + #define MT8186_MUTEX_MOD_DISP_RDMA1 17 39 + 40 + #define MT8186_MUTEX_SOF_SINGLE_MODE 0 41 + #define MT8186_MUTEX_SOF_DSI0 1 42 + #define MT8186_MUTEX_SOF_DPI0 2 43 + #define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6) 44 + #define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6) 45 + 29 46 #define MT8167_MUTEX_MOD_DISP_PWM 1 30 47 #define MT8167_MUTEX_MOD_DISP_OVL0 6 31 48 #define MT8167_MUTEX_MOD_DISP_OVL1 7 ··· 243 226 [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, 244 227 }; 245 228 229 + static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = { 230 + [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0, 231 + [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0, 232 + [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0, 233 + [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0, 234 + [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0, 235 + [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0, 236 + [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L, 237 + [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0, 238 + [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0, 239 + [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1, 240 + }; 241 + 246 242 static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { 247 243 [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, 248 244 [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, ··· 294 264 [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, 295 265 }; 296 266 267 + static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = { 268 + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 269 + [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0, 270 + [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0, 271 + }; 272 + 297 273 static const struct mtk_mutex_data mt2701_mutex_driver_data = { 298 274 .mutex_mod = mt2701_mutex_mod, 299 275 .mutex_sof = mt2712_mutex_sof, ··· 335 299 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 336 300 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 337 301 .no_clk = true, 302 + }; 303 + 304 + static const struct mtk_mutex_data mt8186_mutex_driver_data = { 305 + .mutex_mod = mt8186_mutex_mod, 306 + .mutex_sof = mt8186_mutex_sof, 307 + .mutex_mod_reg = MT8183_MUTEX0_MOD0, 308 + .mutex_sof_reg = MT8183_MUTEX0_SOF0, 338 309 }; 339 310 340 311 static const struct mtk_mutex_data mt8192_mutex_driver_data = { ··· 583 540 .data = &mt8173_mutex_driver_data}, 584 541 { .compatible = "mediatek,mt8183-disp-mutex", 585 542 .data = &mt8183_mutex_driver_data}, 543 + { .compatible = "mediatek,mt8186-disp-mutex", 544 + .data = &mt8186_mutex_driver_data}, 586 545 { .compatible = "mediatek,mt8192-disp-mutex", 587 546 .data = &mt8192_mutex_driver_data}, 588 547 {},

+15 -2

drivers/soc/mediatek/mtk-pm-domains.c

··· 19 19 #include "mt8167-pm-domains.h" 20 20 #include "mt8173-pm-domains.h" 21 21 #include "mt8183-pm-domains.h" 22 + #include "mt8186-pm-domains.h" 22 23 #include "mt8192-pm-domains.h" 24 + #include "mt8195-pm-domains.h" 23 25 24 26 #define MTK_POLL_DELAY_US 10 25 27 #define MTK_POLL_TIMEOUT USEC_PER_SEC ··· 62 60 struct scpsys *scpsys = pd->scpsys; 63 61 u32 status, status2; 64 62 65 - regmap_read(scpsys->base, scpsys->soc_data->pwr_sta_offs, &status); 63 + regmap_read(scpsys->base, pd->data->pwr_sta_offs, &status); 66 64 status &= pd->data->sta_mask; 67 65 68 - regmap_read(scpsys->base, scpsys->soc_data->pwr_sta2nd_offs, &status2); 66 + regmap_read(scpsys->base, pd->data->pwr_sta2nd_offs, &status2); 69 67 status2 &= pd->data->sta_mask; 70 68 71 69 /* A domain is on when both status bits are set. */ ··· 445 443 pd->genpd.power_off = scpsys_power_off; 446 444 pd->genpd.power_on = scpsys_power_on; 447 445 446 + if (MTK_SCPD_CAPS(pd, MTK_SCPD_ACTIVE_WAKEUP)) 447 + pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; 448 + 448 449 if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF)) 449 450 pm_genpd_init(&pd->genpd, NULL, true); 450 451 else ··· 568 563 .data = &mt8183_scpsys_data, 569 564 }, 570 565 { 566 + .compatible = "mediatek,mt8186-power-controller", 567 + .data = &mt8186_scpsys_data, 568 + }, 569 + { 571 570 .compatible = "mediatek,mt8192-power-controller", 572 571 .data = &mt8192_scpsys_data, 572 + }, 573 + { 574 + .compatible = "mediatek,mt8195-power-controller", 575 + .data = &mt8195_scpsys_data, 573 576 }, 574 577 { } 575 578 };

+3 -5

drivers/soc/mediatek/mtk-pm-domains.h

··· 37 37 #define PWR_STATUS_AUDIO BIT(24) 38 38 #define PWR_STATUS_USB BIT(25) 39 39 40 - #define SPM_MAX_BUS_PROT_DATA 5 40 + #define SPM_MAX_BUS_PROT_DATA 6 41 41 42 42 #define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ 43 43 .bus_prot_mask = (_mask), \ ··· 72 72 bool ignore_clr_ack; 73 73 }; 74 74 75 - #define MAX_SUBSYS_CLKS 10 76 - 77 75 /** 78 76 * struct scpsys_domain_data - scp domain data for power on/off flow 79 77 * @name: The name of the power domain. ··· 92 94 u8 caps; 93 95 const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA]; 94 96 const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA]; 97 + int pwr_sta_offs; 98 + int pwr_sta2nd_offs; 95 99 }; 96 100 97 101 struct scpsys_soc_data { 98 102 const struct scpsys_domain_data *domains_data; 99 103 int num_domains; 100 - int pwr_sta_offs; 101 - int pwr_sta2nd_offs; 102 104 }; 103 105 104 106 #endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */

+71

drivers/soc/mediatek/mtk-pmic-wrap.c

··· 30 30 #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001) 31 31 #define PWRAP_STATE_SYNC_IDLE0 BIT(20) 32 32 #define PWRAP_STATE_INIT_DONE0 BIT(21) 33 + #define PWRAP_STATE_INIT_DONE0_MT8186 BIT(22) 33 34 #define PWRAP_STATE_INIT_DONE1 BIT(15) 34 35 35 36 /* macro for WACS FSM */ ··· 78 77 #define PWRAP_CAP_INT1_EN BIT(3) 79 78 #define PWRAP_CAP_WDT_SRC1 BIT(4) 80 79 #define PWRAP_CAP_ARB BIT(5) 80 + #define PWRAP_CAP_ARB_MT8186 BIT(8) 81 81 82 82 /* defines for slave device wrapper registers */ 83 83 enum dew_regs { ··· 1065 1063 [PWRAP_MSB_FIRST] = 0x170, 1066 1064 }; 1067 1065 1066 + static int mt8186_regs[] = { 1067 + [PWRAP_MUX_SEL] = 0x0, 1068 + [PWRAP_WRAP_EN] = 0x4, 1069 + [PWRAP_DIO_EN] = 0x8, 1070 + [PWRAP_RDDMY] = 0x20, 1071 + [PWRAP_CSHEXT_WRITE] = 0x24, 1072 + [PWRAP_CSHEXT_READ] = 0x28, 1073 + [PWRAP_CSLEXT_WRITE] = 0x2C, 1074 + [PWRAP_CSLEXT_READ] = 0x30, 1075 + [PWRAP_EXT_CK_WRITE] = 0x34, 1076 + [PWRAP_STAUPD_CTRL] = 0x3C, 1077 + [PWRAP_STAUPD_GRPEN] = 0x40, 1078 + [PWRAP_EINT_STA0_ADR] = 0x44, 1079 + [PWRAP_EINT_STA1_ADR] = 0x48, 1080 + [PWRAP_INT_CLR] = 0xC8, 1081 + [PWRAP_INT_FLG] = 0xC4, 1082 + [PWRAP_MAN_EN] = 0x7C, 1083 + [PWRAP_MAN_CMD] = 0x80, 1084 + [PWRAP_WACS0_EN] = 0x8C, 1085 + [PWRAP_WACS1_EN] = 0x94, 1086 + [PWRAP_WACS2_EN] = 0x9C, 1087 + [PWRAP_INIT_DONE0] = 0x90, 1088 + [PWRAP_INIT_DONE1] = 0x98, 1089 + [PWRAP_INIT_DONE2] = 0xA0, 1090 + [PWRAP_INT_EN] = 0xBC, 1091 + [PWRAP_INT1_EN] = 0xCC, 1092 + [PWRAP_INT1_FLG] = 0xD4, 1093 + [PWRAP_INT1_CLR] = 0xD8, 1094 + [PWRAP_TIMER_EN] = 0xF0, 1095 + [PWRAP_WDT_UNIT] = 0xF8, 1096 + [PWRAP_WDT_SRC_EN] = 0xFC, 1097 + [PWRAP_WDT_SRC_EN_1] = 0x100, 1098 + [PWRAP_WDT_FLG] = 0x104, 1099 + [PWRAP_SPMINF_STA] = 0x1B4, 1100 + [PWRAP_DCM_EN] = 0x1EC, 1101 + [PWRAP_DCM_DBC_PRD] = 0x1F0, 1102 + [PWRAP_GPSINF_0_STA] = 0x204, 1103 + [PWRAP_GPSINF_1_STA] = 0x208, 1104 + [PWRAP_WACS0_CMD] = 0xC00, 1105 + [PWRAP_WACS0_RDATA] = 0xC04, 1106 + [PWRAP_WACS0_VLDCLR] = 0xC08, 1107 + [PWRAP_WACS1_CMD] = 0xC10, 1108 + [PWRAP_WACS1_RDATA] = 0xC14, 1109 + [PWRAP_WACS1_VLDCLR] = 0xC18, 1110 + [PWRAP_WACS2_CMD] = 0xC20, 1111 + [PWRAP_WACS2_RDATA] = 0xC24, 1112 + [PWRAP_WACS2_VLDCLR] = 0xC28, 1113 + }; 1114 + 1068 1115 enum pmic_type { 1069 1116 PMIC_MT6323, 1070 1117 PMIC_MT6351, ··· 1134 1083 PWRAP_MT8135, 1135 1084 PWRAP_MT8173, 1136 1085 PWRAP_MT8183, 1086 + PWRAP_MT8186, 1137 1087 PWRAP_MT8195, 1138 1088 PWRAP_MT8516, 1139 1089 }; ··· 1587 1535 case PWRAP_MT6779: 1588 1536 case PWRAP_MT6797: 1589 1537 case PWRAP_MT8173: 1538 + case PWRAP_MT8186: 1590 1539 case PWRAP_MT8516: 1591 1540 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); 1592 1541 break; ··· 2122 2069 .init_soc_specific = NULL, 2123 2070 }; 2124 2071 2072 + static struct pmic_wrapper_type pwrap_mt8186 = { 2073 + .regs = mt8186_regs, 2074 + .type = PWRAP_MT8186, 2075 + .arb_en_all = 0xfb27f, 2076 + .int_en_all = 0xfffffffe, /* disable WatchDog Timeout for bit 1 */ 2077 + .int1_en_all = 0x000017ff, /* disable Matching interrupt for bit 13 */ 2078 + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2079 + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2080 + .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB_MT8186, 2081 + .init_reg_clock = pwrap_common_init_reg_clock, 2082 + .init_soc_specific = NULL, 2083 + }; 2084 + 2125 2085 static const struct of_device_id of_pwrap_match_tbl[] = { 2126 2086 { 2127 2087 .compatible = "mediatek,mt2701-pwrap", ··· 2163 2097 }, { 2164 2098 .compatible = "mediatek,mt8183-pwrap", 2165 2099 .data = &pwrap_mt8183, 2100 + }, { 2101 + .compatible = "mediatek,mt8186-pwrap", 2102 + .data = &pwrap_mt8186, 2166 2103 }, { 2167 2104 .compatible = "mediatek,mt8195-pwrap", 2168 2105 .data = &pwrap_mt8195, ··· 2278 2209 2279 2210 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 2280 2211 mask_done = PWRAP_STATE_INIT_DONE1; 2212 + else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186)) 2213 + mask_done = PWRAP_STATE_INIT_DONE0_MT8186; 2281 2214 else 2282 2215 mask_done = PWRAP_STATE_INIT_DONE0; 2283 2216

+32

include/dt-bindings/power/mt8186-power.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 + /* 3 + * Copyright (c) 2022 MediaTek Inc. 4 + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_POWER_MT8186_POWER_H 8 + #define _DT_BINDINGS_POWER_MT8186_POWER_H 9 + 10 + #define MT8186_POWER_DOMAIN_MFG0 0 11 + #define MT8186_POWER_DOMAIN_MFG1 1 12 + #define MT8186_POWER_DOMAIN_MFG2 2 13 + #define MT8186_POWER_DOMAIN_MFG3 3 14 + #define MT8186_POWER_DOMAIN_SSUSB 4 15 + #define MT8186_POWER_DOMAIN_SSUSB_P1 5 16 + #define MT8186_POWER_DOMAIN_DIS 6 17 + #define MT8186_POWER_DOMAIN_IMG 7 18 + #define MT8186_POWER_DOMAIN_IMG2 8 19 + #define MT8186_POWER_DOMAIN_IPE 9 20 + #define MT8186_POWER_DOMAIN_CAM 10 21 + #define MT8186_POWER_DOMAIN_CAM_RAWA 11 22 + #define MT8186_POWER_DOMAIN_CAM_RAWB 12 23 + #define MT8186_POWER_DOMAIN_VENC 13 24 + #define MT8186_POWER_DOMAIN_VDEC 14 25 + #define MT8186_POWER_DOMAIN_WPE 15 26 + #define MT8186_POWER_DOMAIN_CONN_ON 16 27 + #define MT8186_POWER_DOMAIN_CSIRX_TOP 17 28 + #define MT8186_POWER_DOMAIN_ADSP_AO 18 29 + #define MT8186_POWER_DOMAIN_ADSP_INFRA 19 30 + #define MT8186_POWER_DOMAIN_ADSP_TOP 20 31 + 32 + #endif /* _DT_BINDINGS_POWER_MT8186_POWER_H */

+46

include/dt-bindings/power/mt8195-power.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 + /* 3 + * Copyright (c) 2021 MediaTek Inc. 4 + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_POWER_MT8195_POWER_H 8 + #define _DT_BINDINGS_POWER_MT8195_POWER_H 9 + 10 + #define MT8195_POWER_DOMAIN_PCIE_MAC_P0 0 11 + #define MT8195_POWER_DOMAIN_PCIE_MAC_P1 1 12 + #define MT8195_POWER_DOMAIN_PCIE_PHY 2 13 + #define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY 3 14 + #define MT8195_POWER_DOMAIN_CSI_RX_TOP 4 15 + #define MT8195_POWER_DOMAIN_ETHER 5 16 + #define MT8195_POWER_DOMAIN_ADSP 6 17 + #define MT8195_POWER_DOMAIN_AUDIO 7 18 + #define MT8195_POWER_DOMAIN_MFG0 8 19 + #define MT8195_POWER_DOMAIN_MFG1 9 20 + #define MT8195_POWER_DOMAIN_MFG2 10 21 + #define MT8195_POWER_DOMAIN_MFG3 11 22 + #define MT8195_POWER_DOMAIN_MFG4 12 23 + #define MT8195_POWER_DOMAIN_MFG5 13 24 + #define MT8195_POWER_DOMAIN_MFG6 14 25 + #define MT8195_POWER_DOMAIN_VPPSYS0 15 26 + #define MT8195_POWER_DOMAIN_VDOSYS0 16 27 + #define MT8195_POWER_DOMAIN_VPPSYS1 17 28 + #define MT8195_POWER_DOMAIN_VDOSYS1 18 29 + #define MT8195_POWER_DOMAIN_DP_TX 19 30 + #define MT8195_POWER_DOMAIN_EPD_TX 20 31 + #define MT8195_POWER_DOMAIN_HDMI_TX 21 32 + #define MT8195_POWER_DOMAIN_WPESYS 22 33 + #define MT8195_POWER_DOMAIN_VDEC0 23 34 + #define MT8195_POWER_DOMAIN_VDEC1 24 35 + #define MT8195_POWER_DOMAIN_VDEC2 25 36 + #define MT8195_POWER_DOMAIN_VENC 26 37 + #define MT8195_POWER_DOMAIN_VENC_CORE1 27 38 + #define MT8195_POWER_DOMAIN_IMG 28 39 + #define MT8195_POWER_DOMAIN_DIP 29 40 + #define MT8195_POWER_DOMAIN_IPE 30 41 + #define MT8195_POWER_DOMAIN_CAM 31 42 + #define MT8195_POWER_DOMAIN_CAM_RAWA 32 43 + #define MT8195_POWER_DOMAIN_CAM_RAWB 33 44 + #define MT8195_POWER_DOMAIN_CAM_MRAW 34 45 + 46 + #endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */

+133

include/linux/soc/mediatek/infracfg.h

··· 2 2 #ifndef __SOC_MEDIATEK_INFRACFG_H 3 3 #define __SOC_MEDIATEK_INFRACFG_H 4 4 5 + #define MT8195_TOP_AXI_PROT_EN_STA1 0x228 6 + #define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258 7 + #define MT8195_TOP_AXI_PROT_EN_SET 0x2a0 8 + #define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4 9 + #define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8 10 + #define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac 11 + #define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4 12 + #define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8 13 + #define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec 14 + #define MT8195_TOP_AXI_PROT_EN_2_SET 0x714 15 + #define MT8195_TOP_AXI_PROT_EN_2_CLR 0x718 16 + #define MT8195_TOP_AXI_PROT_EN_2_STA1 0x724 17 + #define MT8195_TOP_AXI_PROT_EN_VDNR_SET 0xb84 18 + #define MT8195_TOP_AXI_PROT_EN_VDNR_CLR 0xb88 19 + #define MT8195_TOP_AXI_PROT_EN_VDNR_STA1 0xb90 20 + #define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4 21 + #define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8 22 + #define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0 23 + #define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET 0xbb8 24 + #define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR 0xbbc 25 + #define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1 0xbc4 26 + #define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbcc 27 + #define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbd0 28 + #define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbd8 29 + #define MT8195_TOP_AXI_PROT_EN_MM_2_SET 0xdcc 30 + #define MT8195_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0 31 + #define MT8195_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8 32 + 33 + #define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6) 34 + #define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10) 35 + #define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11) 36 + #define MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK(22, 21) 37 + #define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23) 38 + #define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK(20, 19) 39 + #define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22) 40 + #define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0) 41 + #define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, 5) 42 + #define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7) 43 + #define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11)) 44 + #define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14)) 45 + #define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2) | BIT(4)) 46 + #define MT8195_TOP_AXI_PROT_EN_MM_IPE BIT(1) 47 + #define MT8195_TOP_AXI_PROT_EN_MM_IMG BIT(3) 48 + #define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0 GENMASK(21, 17) 49 + #define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, 5) 50 + #define MT8195_TOP_AXI_PROT_EN_MM_VENC (BIT(9) | BIT(11)) 51 + #define MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1 (BIT(10) | BIT(12)) 52 + #define MT8195_TOP_AXI_PROT_EN_MM_VDEC0 BIT(13) 53 + #define MT8195_TOP_AXI_PROT_EN_MM_VDEC1 BIT(14) 54 + #define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND BIT(22) 55 + #define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND BIT(23) 56 + #define MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(24) 57 + #define MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND BIT(25) 58 + #define MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(26) 59 + #define MT8195_TOP_AXI_PROT_EN_MM_WPESYS BIT(27) 60 + #define MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND BIT(28) 61 + #define MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND BIT(29) 62 + #define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1 GENMASK(31, 30) 63 + #define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMASK(1, 0) | BIT(4) | BIT(11)) 64 + #define MT8195_TOP_AXI_PROT_EN_MM_2_VENC BIT(2) 65 + #define MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1 (BIT(3) | BIT(15)) 66 + #define MT8195_TOP_AXI_PROT_EN_MM_2_CAM (BIT(5) | BIT(17)) 67 + #define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 (GENMASK(7, 6) | BIT(18)) 68 + #define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 GENMASK(9, 8) 69 + #define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1 BIT(10) 70 + #define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND BIT(12) 71 + #define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND BIT(13) 72 + #define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND BIT(14) 73 + #define MT8195_TOP_AXI_PROT_EN_MM_2_IPE BIT(16) 74 + #define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2 BIT(21) 75 + #define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0 BIT(22) 76 + #define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS GENMASK(24, 23) 77 + #define MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX BIT(1) 78 + #define MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX BIT(2) 79 + #define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0 (BIT(11) | BIT(28)) 80 + #define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1 (BIT(12) | BIT(29)) 81 + #define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0 BIT(13) 82 + #define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1 BIT(14) 83 + #define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1 (BIT(17) | BIT(19)) 84 + #define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0 BIT(20) 85 + #define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0 BIT(21) 86 + 5 87 #define MT8192_TOP_AXI_PROT_EN_STA1 0x228 6 88 #define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258 7 89 #define MT8192_TOP_AXI_PROT_EN_SET 0x2a0 ··· 139 57 #define MT8192_TOP_AXI_PROT_EN_MM_2_MDP BIT(12) 140 58 #define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13) 141 59 #define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21) 60 + 61 + #define MT8186_TOP_AXI_PROT_EN_SET (0x2A0) 62 + #define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4) 63 + #define MT8186_TOP_AXI_PROT_EN_STA (0x228) 64 + #define MT8186_TOP_AXI_PROT_EN_1_SET (0x2A8) 65 + #define MT8186_TOP_AXI_PROT_EN_1_CLR (0x2AC) 66 + #define MT8186_TOP_AXI_PROT_EN_1_STA (0x258) 67 + #define MT8186_TOP_AXI_PROT_EN_2_SET (0x2B0) 68 + #define MT8186_TOP_AXI_PROT_EN_2_CLR (0x2B4) 69 + #define MT8186_TOP_AXI_PROT_EN_2_STA (0x26C) 70 + #define MT8186_TOP_AXI_PROT_EN_3_SET (0x2B8) 71 + #define MT8186_TOP_AXI_PROT_EN_3_CLR (0x2BC) 72 + #define MT8186_TOP_AXI_PROT_EN_3_STA (0x2C8) 73 + 74 + /* MFG1 */ 75 + #define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1 (GENMASK(28, 27)) 76 + #define MT8186_TOP_AXI_PROT_EN_MFG1_STEP2 (GENMASK(22, 21)) 77 + #define MT8186_TOP_AXI_PROT_EN_MFG1_STEP3 (BIT(25)) 78 + #define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4 (BIT(29)) 79 + /* DIS */ 80 + #define MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1 (GENMASK(12, 11)) 81 + #define MT8186_TOP_AXI_PROT_EN_DIS_STEP2 (GENMASK(2, 1) | GENMASK(11, 10)) 82 + /* IMG */ 83 + #define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1 (BIT(23)) 84 + #define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2 (BIT(15)) 85 + /* IPE */ 86 + #define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1 (BIT(24)) 87 + #define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2 (BIT(16)) 88 + /* CAM */ 89 + #define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1 (GENMASK(22, 21)) 90 + #define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2 (GENMASK(14, 13)) 91 + /* VENC */ 92 + #define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1 (BIT(31)) 93 + #define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2 (BIT(19)) 94 + /* VDEC */ 95 + #define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1 (BIT(30)) 96 + #define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2 (BIT(17)) 97 + /* WPE */ 98 + #define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1 (BIT(17)) 99 + #define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2 (BIT(16)) 100 + /* CONN_ON */ 101 + #define MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1 (BIT(18)) 102 + #define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2 (BIT(14)) 103 + #define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3 (BIT(13)) 104 + #define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4 (BIT(16)) 105 + /* ADSP_TOP */ 106 + #define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1 (GENMASK(12, 11)) 107 + #define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2 (GENMASK(1, 0)) 142 108 143 109 #define MT8183_TOP_AXI_PROT_EN_STA1 0x228 144 110 #define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258 ··· 276 146 #define INFRA_TOPAXI_PROTECTSTA1 0x0228 277 147 #define INFRA_TOPAXI_PROTECTEN_SET 0x0260 278 148 #define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 149 + 150 + #define MT8192_INFRA_CTRL 0x290 151 + #define MT8192_INFRA_CTRL_DISABLE_MFG2ACP BIT(9) 279 152 280 153 #define REG_INFRA_MISC 0xf00 281 154 #define F_DDR_4GB_SUPPORT_EN BIT(13)