tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/nouveau/fifo: make external class definitions into pointers

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Ben Skeggs 16c4f227 aabf19c2

+86 -86
+2 -2
drivers/gpu/drm/nouveau/core/engine/device/nv04.c
··· 57 57 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 58 58 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 59 59 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 60 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv04_fifo_oclass; 60 + device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; 61 61 device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; 62 62 device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; 63 63 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; ··· 75 75 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 76 76 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 77 77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 78 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv04_fifo_oclass; 78 + device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; 79 79 device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; 80 80 device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; 81 81 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
+7 -7
drivers/gpu/drm/nouveau/core/engine/device/nv10.c
··· 76 76 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 77 77 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 78 78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 79 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass; 79 + device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 80 80 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 81 81 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 82 82 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; ··· 95 95 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 96 96 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 97 97 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 98 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass; 98 + device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 99 99 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 100 100 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 101 101 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; ··· 114 114 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 115 115 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 116 116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 117 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass; 117 + device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 118 118 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 119 119 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 120 120 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; ··· 133 133 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 134 134 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 135 135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 136 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass; 136 + device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 137 137 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 138 138 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 139 139 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; ··· 152 152 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 153 153 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 154 154 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 155 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 155 + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 156 156 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 157 157 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 158 158 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; ··· 171 171 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 172 172 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 173 173 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 174 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 174 + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 175 175 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 176 176 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 177 177 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; ··· 190 190 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 191 191 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 192 192 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 193 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 193 + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 194 194 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 195 195 device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; 196 196 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
+4 -4
drivers/gpu/drm/nouveau/core/engine/device/nv20.c
··· 60 60 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 61 61 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 62 62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 63 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 63 + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 64 64 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 65 65 device->oclass[NVDEV_ENGINE_GR ] = &nv20_graph_oclass; 66 66 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; ··· 79 79 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 80 80 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 81 81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 82 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 82 + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 83 83 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 84 84 device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; 85 85 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; ··· 98 98 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 99 99 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 100 100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 101 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 101 + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 102 102 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 103 103 device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; 104 104 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; ··· 117 117 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 118 118 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 119 119 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 120 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 120 + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 121 121 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 122 122 device->oclass[NVDEV_ENGINE_GR ] = &nv2a_graph_oclass; 123 123 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
+5 -5
drivers/gpu/drm/nouveau/core/engine/device/nv30.c
··· 60 60 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 61 61 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 62 62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 63 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 63 + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 64 64 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 65 65 device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; 66 66 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; ··· 79 79 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 80 80 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 81 81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 82 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 82 + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 83 83 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 84 84 device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; 85 85 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; ··· 98 98 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 99 99 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 100 100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 101 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 101 + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 102 102 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 103 103 device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; 104 104 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; ··· 118 118 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 119 119 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 120 120 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 121 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 121 + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 122 122 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 123 123 device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; 124 124 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; ··· 138 138 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 139 139 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 140 140 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 141 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; 141 + device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 142 142 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 143 143 device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass; 144 144 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
+16 -16
drivers/gpu/drm/nouveau/core/engine/device/nv40.c
··· 63 63 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 64 64 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 65 65 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 66 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 66 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 67 67 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 68 68 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 69 69 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; ··· 84 84 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 85 85 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 86 86 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 87 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 87 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 88 88 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 89 89 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 90 90 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; ··· 105 105 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 106 106 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 107 107 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 108 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 108 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 109 109 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 110 110 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 111 111 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; ··· 126 126 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 127 127 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 128 128 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 129 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 129 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 130 130 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 131 131 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 132 132 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; ··· 147 147 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 148 148 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; 149 149 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 150 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 150 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 151 151 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 152 152 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 153 153 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; ··· 168 168 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 169 169 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 170 170 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 171 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 171 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 172 172 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 173 173 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 174 174 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; ··· 189 189 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 190 190 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 191 191 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 192 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 192 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 193 193 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 194 194 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 195 195 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; ··· 210 210 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 211 211 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; 212 212 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 213 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 213 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 214 214 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 215 215 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 216 216 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; ··· 231 231 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 232 232 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 233 233 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 234 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 234 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 235 235 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 236 236 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 237 237 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; ··· 252 252 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 253 253 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 254 254 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 255 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 255 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 256 256 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 257 257 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 258 258 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; ··· 273 273 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 274 274 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 275 275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 276 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 276 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 277 277 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 278 278 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 279 279 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; ··· 294 294 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 295 295 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 296 296 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 297 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 297 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 298 298 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 299 299 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 300 300 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; ··· 315 315 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 316 316 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 317 317 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 318 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 318 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 319 319 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 320 320 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 321 321 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; ··· 336 336 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 337 337 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 338 338 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 339 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 339 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 340 340 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 341 341 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 342 342 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; ··· 357 357 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 358 358 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 359 359 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 360 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 360 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 361 361 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 362 362 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 363 363 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; ··· 378 378 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 379 379 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; 380 380 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; 381 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; 381 + device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 382 382 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 383 383 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; 384 384 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
+14 -14
drivers/gpu/drm/nouveau/core/engine/device/nv50.c
··· 71 71 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 72 72 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 73 73 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 74 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv50_fifo_oclass; 74 + device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; 75 75 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 76 76 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 77 77 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; ··· 94 94 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 95 95 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 96 96 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 97 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 97 + device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 98 98 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 99 99 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 100 100 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; ··· 120 120 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 121 121 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 122 122 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 123 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 123 + device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 124 124 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 125 125 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 126 126 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; ··· 146 146 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 147 147 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 148 148 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 149 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 149 + device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 150 150 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 151 151 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 152 152 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; ··· 172 172 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 173 173 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 174 174 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 175 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 175 + device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 176 176 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 177 177 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 178 178 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; ··· 198 198 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 199 199 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 200 200 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 201 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 201 + device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 202 202 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 203 203 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 204 204 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; ··· 224 224 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 225 225 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 226 226 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 227 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 227 + device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 228 228 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 229 229 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 230 230 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; ··· 250 250 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 251 251 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 252 252 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 253 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 253 + device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 254 254 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 255 255 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 256 256 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; ··· 276 276 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 277 277 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 278 278 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 279 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 279 + device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 280 280 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 281 281 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 282 282 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; ··· 302 302 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 303 303 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 304 304 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 305 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 305 + device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 306 306 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 307 307 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 308 308 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; ··· 328 328 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 329 329 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 330 330 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 331 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 331 + device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 332 332 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 333 333 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 334 334 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; ··· 355 355 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 356 356 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 357 357 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 358 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 358 + device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 359 359 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 360 360 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 361 361 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; ··· 381 381 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 382 382 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 383 383 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 384 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 384 + device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 385 385 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 386 386 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 387 387 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; ··· 407 407 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 408 408 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 409 409 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 410 - device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass; 410 + device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 411 411 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 412 412 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; 413 413 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+9 -9
drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
··· 73 73 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 74 74 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 75 75 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 76 - device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 76 + device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 77 77 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 78 78 device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass; 79 79 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; ··· 102 102 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 103 103 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 104 104 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 105 - device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 105 + device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 106 106 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 107 107 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; 108 108 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; ··· 131 131 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 132 132 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 133 133 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 134 - device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 134 + device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 135 135 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 136 136 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; 137 137 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; ··· 159 159 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 160 160 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 161 161 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 162 - device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 162 + device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 163 163 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 164 164 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; 165 165 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; ··· 188 188 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 189 189 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 190 190 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 191 - device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 191 + device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 192 192 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 193 193 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; 194 194 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; ··· 217 217 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 218 218 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 219 219 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 220 - device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 220 + device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 221 221 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 222 222 device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass; 223 223 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; ··· 245 245 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 246 246 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 247 247 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 248 - device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 248 + device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 249 249 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 250 250 device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass; 251 251 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; ··· 274 274 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 275 275 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 276 276 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 277 - device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 277 + device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 278 278 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 279 279 device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass; 280 280 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; ··· 302 302 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 303 303 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 304 304 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 305 - device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 305 + device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 306 306 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 307 307 device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass; 308 308 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+5 -5
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
··· 73 73 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 74 74 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 75 75 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 76 - device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 76 + device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 77 77 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 78 78 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; 79 79 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; ··· 103 103 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 104 104 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 105 105 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 106 - device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 106 + device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 107 107 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 108 108 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; 109 109 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; ··· 133 133 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 134 134 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 135 135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 136 - device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 136 + device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 137 137 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 138 138 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; 139 139 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; ··· 163 163 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 164 164 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 165 165 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 166 - device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 166 + device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 167 167 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 168 168 device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; 169 169 device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; ··· 196 196 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 197 197 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 198 198 #if 0 199 - device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 199 + device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 200 200 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 201 201 device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; 202 202 #endif
+2 -2
drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
··· 632 632 return 0; 633 633 } 634 634 635 - struct nouveau_oclass 636 - nv04_fifo_oclass = { 635 + struct nouveau_oclass * 636 + nv04_fifo_oclass = &(struct nouveau_oclass) { 637 637 .handle = NV_ENGINE(FIFO, 0x04), 638 638 .ofuncs = &(struct nouveau_ofuncs) { 639 639 .ctor = nv04_fifo_ctor,
+2 -2
drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
··· 159 159 return 0; 160 160 } 161 161 162 - struct nouveau_oclass 163 - nv10_fifo_oclass = { 162 + struct nouveau_oclass * 163 + nv10_fifo_oclass = &(struct nouveau_oclass) { 164 164 .handle = NV_ENGINE(FIFO, 0x10), 165 165 .ofuncs = &(struct nouveau_ofuncs) { 166 166 .ctor = nv10_fifo_ctor,
+2 -2
drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
··· 196 196 return 0; 197 197 } 198 198 199 - struct nouveau_oclass 200 - nv17_fifo_oclass = { 199 + struct nouveau_oclass * 200 + nv17_fifo_oclass = &(struct nouveau_oclass) { 201 201 .handle = NV_ENGINE(FIFO, 0x17), 202 202 .ofuncs = &(struct nouveau_ofuncs) { 203 203 .ctor = nv17_fifo_ctor,
+2 -2
drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
··· 337 337 return 0; 338 338 } 339 339 340 - struct nouveau_oclass 341 - nv40_fifo_oclass = { 340 + struct nouveau_oclass * 341 + nv40_fifo_oclass = &(struct nouveau_oclass) { 342 342 .handle = NV_ENGINE(FIFO, 0x40), 343 343 .ofuncs = &(struct nouveau_ofuncs) { 344 344 .ctor = nv40_fifo_ctor,
+2 -2
drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
··· 502 502 return 0; 503 503 } 504 504 505 - struct nouveau_oclass 506 - nv50_fifo_oclass = { 505 + struct nouveau_oclass * 506 + nv50_fifo_oclass = &(struct nouveau_oclass) { 507 507 .handle = NV_ENGINE(FIFO, 0x50), 508 508 .ofuncs = &(struct nouveau_ofuncs) { 509 509 .ctor = nv50_fifo_ctor,
+2 -2
drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
··· 435 435 return 0; 436 436 } 437 437 438 - struct nouveau_oclass 439 - nv84_fifo_oclass = { 438 + struct nouveau_oclass * 439 + nv84_fifo_oclass = &(struct nouveau_oclass) { 440 440 .handle = NV_ENGINE(FIFO, 0x84), 441 441 .ofuncs = &(struct nouveau_ofuncs) { 442 442 .ctor = nv84_fifo_ctor,
+2 -2
drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
··· 720 720 return 0; 721 721 } 722 722 723 - struct nouveau_oclass 724 - nvc0_fifo_oclass = { 723 + struct nouveau_oclass * 724 + nvc0_fifo_oclass = &(struct nouveau_oclass) { 725 725 .handle = NV_ENGINE(FIFO, 0xc0), 726 726 .ofuncs = &(struct nouveau_ofuncs) { 727 727 .ctor = nvc0_fifo_ctor,
+2 -2
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
··· 675 675 return 0; 676 676 } 677 677 678 - struct nouveau_oclass 679 - nve0_fifo_oclass = { 678 + struct nouveau_oclass * 679 + nve0_fifo_oclass = &(struct nouveau_oclass) { 680 680 .handle = NV_ENGINE(FIFO, 0xe0), 681 681 .ofuncs = &(struct nouveau_ofuncs) { 682 682 .ctor = nve0_fifo_ctor,
+8 -8
drivers/gpu/drm/nouveau/core/include/engine/fifo.h
··· 101 101 #define _nouveau_fifo_init _nouveau_engine_init 102 102 #define _nouveau_fifo_fini _nouveau_engine_fini 103 103 104 - extern struct nouveau_oclass nv04_fifo_oclass; 105 - extern struct nouveau_oclass nv10_fifo_oclass; 106 - extern struct nouveau_oclass nv17_fifo_oclass; 107 - extern struct nouveau_oclass nv40_fifo_oclass; 108 - extern struct nouveau_oclass nv50_fifo_oclass; 109 - extern struct nouveau_oclass nv84_fifo_oclass; 110 - extern struct nouveau_oclass nvc0_fifo_oclass; 111 - extern struct nouveau_oclass nve0_fifo_oclass; 104 + extern struct nouveau_oclass *nv04_fifo_oclass; 105 + extern struct nouveau_oclass *nv10_fifo_oclass; 106 + extern struct nouveau_oclass *nv17_fifo_oclass; 107 + extern struct nouveau_oclass *nv40_fifo_oclass; 108 + extern struct nouveau_oclass *nv50_fifo_oclass; 109 + extern struct nouveau_oclass *nv84_fifo_oclass; 110 + extern struct nouveau_oclass *nvc0_fifo_oclass; 111 + extern struct nouveau_oclass *nve0_fifo_oclass; 112 112 113 113 void nv04_fifo_intr(struct nouveau_subdev *); 114 114 int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *);