tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/i915/lvds: Extract intel_lvds_regs.h

Extract the integrated LVDS port register definitions
into their own header file.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230130180540.8972-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Ville Syrjälä 16bede13 9dd56e97

+71 -54
+1
drivers/gpu/drm/i915/display/intel_display.c
··· 94 94 #include "intel_hotplug.h" 95 95 #include "intel_hti.h" 96 96 #include "intel_lvds.h" 97 + #include "intel_lvds_regs.h" 97 98 #include "intel_modeset_setup.h" 98 99 #include "intel_modeset_verify.h" 99 100 #include "intel_overlay.h"
+1
drivers/gpu/drm/i915/display/intel_lvds.c
··· 49 49 #include "intel_fdi.h" 50 50 #include "intel_gmbus.h" 51 51 #include "intel_lvds.h" 52 + #include "intel_lvds_regs.h" 52 53 #include "intel_panel.h" 53 54 54 55 /* Private structure for the integrated LVDS support */
+65
drivers/gpu/drm/i915/display/intel_lvds_regs.h
··· 1 + /* SPDX-License-Identifier: MIT */ 2 + /* 3 + * Copyright © 2023 Intel Corporation 4 + */ 5 + 6 + #ifndef __INTEL_LVDS_REGS_H__ 7 + #define __INTEL_LVDS_REGS_H__ 8 + 9 + #include "intel_display_reg_defs.h" 10 + 11 + /* LVDS port control */ 12 + #define LVDS _MMIO(0x61180) 13 + /* 14 + * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 15 + * the DPLL semantics change when the LVDS is assigned to that pipe. 16 + */ 17 + #define LVDS_PORT_EN REG_BIT(31) 18 + /* Selects pipe B for LVDS data. Must be set on pre-965. */ 19 + #define LVDS_PIPE_SEL_MASK REG_BIT(30) 20 + #define LVDS_PIPE_SEL(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK, (pipe)) 21 + #define LVDS_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29) 22 + #define LVDS_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK_CPT, (pipe)) 23 + /* LVDS dithering flag on 965/g4x platform */ 24 + #define LVDS_ENABLE_DITHER REG_BIT(25) 25 + /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 26 + #define LVDS_VSYNC_POLARITY REG_BIT(21) 27 + #define LVDS_HSYNC_POLARITY REG_BIT(20) 28 + 29 + /* Enable border for unscaled (or aspect-scaled) display */ 30 + #define LVDS_BORDER_ENABLE REG_BIT(15) 31 + /* 32 + * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 33 + * pixel. 34 + */ 35 + #define LVDS_A0A2_CLKA_POWER_MASK REG_GENMASK(9, 8) 36 + #define LVDS_A0A2_CLKA_POWER_DOWN REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 0) 37 + #define LVDS_A0A2_CLKA_POWER_UP REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 3) 38 + /* 39 + * Controls the A3 data pair, which contains the additional LSBs for 24 bit 40 + * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 41 + * on. 42 + */ 43 + #define LVDS_A3_POWER_MASK REG_GENMASK(7, 6) 44 + #define LVDS_A3_POWER_DOWN REG_FIELD_PREP(LVDS_A3_POWER_MASK, 0) 45 + #define LVDS_A3_POWER_UP REG_FIELD_PREP(LVDS_A3_POWER_MASK, 3) 46 + /* 47 + * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 48 + * is set. 49 + */ 50 + #define LVDS_CLKB_POWER_MASK REG_GENMASK(5, 4) 51 + #define LVDS_CLKB_POWER_DOWN REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 0) 52 + #define LVDS_CLKB_POWER_UP REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 3) 53 + /* 54 + * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 55 + * setting for whether we are in dual-channel mode. The B3 pair will 56 + * additionally only be powered up when LVDS_A3_POWER_UP is set. 57 + */ 58 + #define LVDS_B0B3_POWER_MASK REG_GENMASK(3, 2) 59 + #define LVDS_B0B3_POWER_DOWN REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 0) 60 + #define LVDS_B0B3_POWER_UP REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 3) 61 + 62 + #define PCH_LVDS _MMIO(0xe1180) 63 + #define LVDS_DETECTED REG_BIT(1) 64 + 65 + #endif /* __INTEL_LVDS_REGS_H__ */
+1
drivers/gpu/drm/i915/display/intel_panel.c
··· 39 39 #include "intel_de.h" 40 40 #include "intel_display_types.h" 41 41 #include "intel_drrs.h" 42 + #include "intel_lvds_regs.h" 42 43 #include "intel_panel.h" 43 44 #include "intel_quirks.h" 44 45
+1
drivers/gpu/drm/i915/display/intel_pch_display.c
··· 10 10 #include "intel_display_types.h" 11 11 #include "intel_fdi.h" 12 12 #include "intel_lvds.h" 13 + #include "intel_lvds_regs.h" 13 14 #include "intel_pch_display.h" 14 15 #include "intel_pch_refclk.h" 15 16 #include "intel_pps.h"
+1
drivers/gpu/drm/i915/display/intel_pps.c
··· 13 13 #include "intel_dpio_phy.h" 14 14 #include "intel_dpll.h" 15 15 #include "intel_lvds.h" 16 + #include "intel_lvds_regs.h" 16 17 #include "intel_pps.h" 17 18 #include "intel_quirks.h" 18 19
-54
drivers/gpu/drm/i915/i915_reg.h
··· 2597 2597 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 2598 2598 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 2599 2599 2600 - /* LVDS port control */ 2601 - #define LVDS _MMIO(0x61180) 2602 - /* 2603 - * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 2604 - * the DPLL semantics change when the LVDS is assigned to that pipe. 2605 - */ 2606 - #define LVDS_PORT_EN REG_BIT(31) 2607 - /* Selects pipe B for LVDS data. Must be set on pre-965. */ 2608 - #define LVDS_PIPE_SEL_MASK REG_BIT(30) 2609 - #define LVDS_PIPE_SEL(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK, (pipe)) 2610 - #define LVDS_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29) 2611 - #define LVDS_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK_CPT, (pipe)) 2612 - /* LVDS dithering flag on 965/g4x platform */ 2613 - #define LVDS_ENABLE_DITHER REG_BIT(25) 2614 - /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 2615 - #define LVDS_VSYNC_POLARITY REG_BIT(21) 2616 - #define LVDS_HSYNC_POLARITY REG_BIT(20) 2617 - 2618 - /* Enable border for unscaled (or aspect-scaled) display */ 2619 - #define LVDS_BORDER_ENABLE REG_BIT(15) 2620 - /* 2621 - * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 2622 - * pixel. 2623 - */ 2624 - #define LVDS_A0A2_CLKA_POWER_MASK REG_GENMASK(9, 8) 2625 - #define LVDS_A0A2_CLKA_POWER_DOWN REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 0) 2626 - #define LVDS_A0A2_CLKA_POWER_UP REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 3) 2627 - /* 2628 - * Controls the A3 data pair, which contains the additional LSBs for 24 bit 2629 - * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 2630 - * on. 2631 - */ 2632 - #define LVDS_A3_POWER_MASK REG_GENMASK(7, 6) 2633 - #define LVDS_A3_POWER_DOWN REG_FIELD_PREP(LVDS_A3_POWER_MASK, 0) 2634 - #define LVDS_A3_POWER_UP REG_FIELD_PREP(LVDS_A3_POWER_MASK, 3) 2635 - /* 2636 - * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 2637 - * is set. 2638 - */ 2639 - #define LVDS_CLKB_POWER_MASK REG_GENMASK(5, 4) 2640 - #define LVDS_CLKB_POWER_DOWN REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 0) 2641 - #define LVDS_CLKB_POWER_UP REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 3) 2642 - /* 2643 - * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 2644 - * setting for whether we are in dual-channel mode. The B3 pair will 2645 - * additionally only be powered up when LVDS_A3_POWER_UP is set. 2646 - */ 2647 - #define LVDS_B0B3_POWER_MASK REG_GENMASK(3, 2) 2648 - #define LVDS_B0B3_POWER_DOWN REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 0) 2649 - #define LVDS_B0B3_POWER_UP REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 3) 2650 - 2651 2600 /* Video Data Island Packet control */ 2652 2601 #define VIDEO_DIP_DATA _MMIO(0x61178) 2653 2602 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC ··· 6343 6394 6344 6395 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 6345 6396 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 6346 - 6347 - #define PCH_LVDS _MMIO(0xe1180) 6348 - #define LVDS_DETECTED REG_BIT(1) 6349 6397 6350 6398 #define _PCH_DP_B 0xe4100 6351 6399 #define PCH_DP_B _MMIO(_PCH_DP_B)
+1
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
··· 8 8 #include "display/intel_display_types.h" 9 9 #include "display/intel_dmc_regs.h" 10 10 #include "display/intel_dpio_phy.h" 11 + #include "display/intel_lvds_regs.h" 11 12 #include "display/vlv_dsi_pll_regs.h" 12 13 #include "gt/intel_gt_regs.h" 13 14 #include "gvt/gvt.h"