drivers/net/phy: add the link modes for the 10BASE-T1S Ethernet PHY

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

This patch adds the link modes for the IEEE 802.3cg Clause 147 10BASE-T1S
Ethernet PHY. According to the specifications, the 10BASE-T1S supports
Point-To-Point Full-Duplex, Point-To-Point Half-Duplex and/or
Point-To-Multipoint (AKA Multi-Drop) Half-Duplex operations.

Signed-off-by: Piergiorgio Beruto <piergiorgio.beruto@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Piergiorgio Beruto and committed by

David S. Miller 3 years ago 16178c8e 8580e16c

+48 -2

6 changed files

expand all

drivers

net

phy

phy-core.c

phy_device.c

phylink.c

include

linux

phy.h

uapi

linux

ethtool.h

net

ethtool

common.c

+4 -1

drivers/net/phy/phy-core.c

··· 13 13 */ 14 14 const char *phy_speed_to_str(int speed) 15 15 { 16 - BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 99, 16 + BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 102, 17 17 "Enum ethtool_link_mode_bit_indices and phylib are out of sync. " 18 18 "If a speed or mode has been added please update phy_speed_to_str " 19 19 "and the PHY settings array.\n"); ··· 260 260 PHY_SETTING( 10, FULL, 10baseT_Full ), 261 261 PHY_SETTING( 10, HALF, 10baseT_Half ), 262 262 PHY_SETTING( 10, FULL, 10baseT1L_Full ), 263 + PHY_SETTING( 10, FULL, 10baseT1S_Full ), 264 + PHY_SETTING( 10, HALF, 10baseT1S_Half ), 265 + PHY_SETTING( 10, HALF, 10baseT1S_P2MP_Half ), 263 266 }; 264 267 #undef PHY_SETTING 265 268

+14

drivers/net/phy/phy_device.c

··· 45 45 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init; 46 46 EXPORT_SYMBOL_GPL(phy_basic_t1_features); 47 47 48 + __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init; 49 + EXPORT_SYMBOL_GPL(phy_basic_t1s_p2mp_features); 50 + 48 51 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init; 49 52 EXPORT_SYMBOL_GPL(phy_gbit_features); 50 53 ··· 101 98 }; 102 99 EXPORT_SYMBOL_GPL(phy_basic_t1_features_array); 103 100 101 + const int phy_basic_t1s_p2mp_features_array[2] = { 102 + ETHTOOL_LINK_MODE_TP_BIT, 103 + ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT, 104 + }; 105 + EXPORT_SYMBOL_GPL(phy_basic_t1s_p2mp_features_array); 106 + 104 107 const int phy_gbit_features_array[2] = { 105 108 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 106 109 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, ··· 146 137 linkmode_set_bit_array(phy_basic_t1_features_array, 147 138 ARRAY_SIZE(phy_basic_t1_features_array), 148 139 phy_basic_t1_features); 140 + 141 + /* 10 half, P2MP, TP */ 142 + linkmode_set_bit_array(phy_basic_t1s_p2mp_features_array, 143 + ARRAY_SIZE(phy_basic_t1s_p2mp_features_array), 144 + phy_basic_t1s_p2mp_features); 149 145 150 146 /* 10/100 half/full + 1000 half/full */ 151 147 linkmode_set_bit_array(phy_basic_ports_array,

+5 -1

drivers/net/phy/phylink.c

··· 241 241 if (caps & MAC_ASYM_PAUSE) 242 242 __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, linkmodes); 243 243 244 - if (caps & MAC_10HD) 244 + if (caps & MAC_10HD) { 245 245 __set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, linkmodes); 246 + __set_bit(ETHTOOL_LINK_MODE_10baseT1S_Half_BIT, linkmodes); 247 + __set_bit(ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT, linkmodes); 248 + } 246 249 247 250 if (caps & MAC_10FD) { 248 251 __set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, linkmodes); 249 252 __set_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, linkmodes); 253 + __set_bit(ETHTOOL_LINK_MODE_10baseT1S_Full_BIT, linkmodes); 250 254 } 251 255 252 256 if (caps & MAC_100HD) {

+14

include/linux/phy.h

··· 45 45 46 46 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init; 47 47 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init; 48 + extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init; 48 49 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init; 49 50 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init; 50 51 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init; ··· 55 54 56 55 #define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features) 57 56 #define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features) 57 + #define PHY_BASIC_T1S_P2MP_FEATURES ((unsigned long *)&phy_basic_t1s_p2mp_features) 58 58 #define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features) 59 59 #define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features) 60 60 #define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features) ··· 68 66 extern const int phy_all_ports_features_array[7]; 69 67 extern const int phy_10_100_features_array[4]; 70 68 extern const int phy_basic_t1_features_array[3]; 69 + extern const int phy_basic_t1s_p2mp_features_array[2]; 71 70 extern const int phy_gbit_features_array[2]; 72 71 extern const int phy_10gbit_features_array[1]; 73 72 ··· 1044 1041 int (*get_sqi)(struct phy_device *dev); 1045 1042 /** @get_sqi_max: Get the maximum signal quality indication */ 1046 1043 int (*get_sqi_max)(struct phy_device *dev); 1044 + 1045 + /* PLCA RS interface */ 1046 + /** @get_plca_cfg: Return the current PLCA configuration */ 1047 + int (*get_plca_cfg)(struct phy_device *dev, 1048 + struct phy_plca_cfg *plca_cfg); 1049 + /** @set_plca_cfg: Set the PLCA configuration */ 1050 + int (*set_plca_cfg)(struct phy_device *dev, 1051 + const struct phy_plca_cfg *plca_cfg); 1052 + /** @get_plca_status: Return the current PLCA status info */ 1053 + int (*get_plca_status)(struct phy_device *dev, 1054 + struct phy_plca_status *plca_st); 1047 1055 }; 1048 1056 #define to_phy_driver(d) container_of(to_mdio_common_driver(d), \ 1049 1057 struct phy_driver, mdiodrv)

include/uapi/linux/ethtool.h

··· 1741 1741 ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96, 1742 1742 ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97, 1743 1743 ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98, 1744 + ETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99, 1745 + ETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100, 1746 + ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101, 1744 1747 1745 1748 /* must be last entry */ 1746 1749 __ETHTOOL_LINK_MODE_MASK_NBITS

net/ethtool/common.c

··· 208 208 __DEFINE_LINK_MODE_NAME(800000, DR8_2, Full), 209 209 __DEFINE_LINK_MODE_NAME(800000, SR8, Full), 210 210 __DEFINE_LINK_MODE_NAME(800000, VR8, Full), 211 + __DEFINE_LINK_MODE_NAME(10, T1S, Full), 212 + __DEFINE_LINK_MODE_NAME(10, T1S, Half), 213 + __DEFINE_LINK_MODE_NAME(10, T1S_P2MP, Half), 211 214 }; 212 215 static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS); 213 216 ··· 247 244 #define __LINK_MODE_LANES_X 1 248 245 #define __LINK_MODE_LANES_FX 1 249 246 #define __LINK_MODE_LANES_T1L 1 247 + #define __LINK_MODE_LANES_T1S 1 248 + #define __LINK_MODE_LANES_T1S_P2MP 1 250 249 #define __LINK_MODE_LANES_VR8 8 251 250 #define __LINK_MODE_LANES_DR8_2 8 252 251 ··· 371 366 __DEFINE_LINK_MODE_PARAMS(800000, DR8_2, Full), 372 367 __DEFINE_LINK_MODE_PARAMS(800000, SR8, Full), 373 368 __DEFINE_LINK_MODE_PARAMS(800000, VR8, Full), 369 + __DEFINE_LINK_MODE_PARAMS(10, T1S, Full), 370 + __DEFINE_LINK_MODE_PARAMS(10, T1S, Half), 371 + __DEFINE_LINK_MODE_PARAMS(10, T1S_P2MP, Half), 374 372 }; 375 373 static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS); 376 374