tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branches 'topic/rt5640', 'topic/rt5645' and 'topic/rt5651' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-rl6231
+8699
+25
include/sound/rt5645.h
+25
include/sound/rt5645.h
···
1
+
/*
2
+
* linux/sound/rt5645.h -- Platform data for RT5645
3
+
*
4
+
* Copyright 2013 Realtek Microelectronics
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
11
+
#ifndef __LINUX_SND_RT5645_H
12
+
#define __LINUX_SND_RT5645_H
13
+
14
+
struct rt5645_platform_data {
15
+
/* IN2 can optionally be differential */
16
+
bool in2_diff;
17
+
18
+
bool dmic_en;
19
+
unsigned int dmic1_data_pin;
20
+
/* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */
21
+
unsigned int dmic2_data_pin;
22
+
/* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */
23
+
};
24
+
25
+
#endif
+21
include/sound/rt5651.h
+21
include/sound/rt5651.h
···
1
+
/*
2
+
* linux/sound/rt286.h -- Platform data for RT286
3
+
*
4
+
* Copyright 2013 Realtek Microelectronics
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
11
+
#ifndef __LINUX_SND_RT5651_H
12
+
#define __LINUX_SND_RT5651_H
13
+
14
+
struct rt5651_platform_data {
15
+
/* IN2 can optionally be differential */
16
+
bool in2_diff;
17
+
18
+
bool dmic_en;
19
+
};
20
+
21
+
#endif
+8
sound/soc/codecs/Kconfig
+8
sound/soc/codecs/Kconfig
···
71
71
select SND_SOC_PCM512x_SPI if SPI_MASTER
72
72
select SND_SOC_RT5631 if I2C
73
73
select SND_SOC_RT5640 if I2C
74
+
select SND_SOC_RT5645 if I2C
75
+
select SND_SOC_RT5651 if I2C
74
76
select SND_SOC_SGTL5000 if I2C
75
77
select SND_SOC_SI476X if MFD_SI476X_CORE
76
78
select SND_SOC_SIRF_AUDIO_CODEC
···
396
394
tristate
397
395
398
396
config SND_SOC_RT5640
397
+
tristate
398
+
399
+
config SND_SOC_RT5645
400
+
tristate
401
+
402
+
config SND_SOC_RT5651
399
403
tristate
400
404
401
405
#Freescale sgtl5000 codec
+4
sound/soc/codecs/Makefile
+4
sound/soc/codecs/Makefile
···
60
60
snd-soc-pcm512x-spi-objs := pcm512x-spi.o
61
61
snd-soc-rt5631-objs := rt5631.o
62
62
snd-soc-rt5640-objs := rt5640.o
63
+
snd-soc-rt5645-objs := rt5645.o
64
+
snd-soc-rt5651-objs := rt5651.o
63
65
snd-soc-sgtl5000-objs := sgtl5000.o
64
66
snd-soc-alc5623-objs := alc5623.o
65
67
snd-soc-alc5632-objs := alc5632.o
···
213
211
obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o
214
212
obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
215
213
obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
214
+
obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
215
+
obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
216
216
obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
217
217
obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o
218
218
obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o
+2475
sound/soc/codecs/rt5645.c
+2475
sound/soc/codecs/rt5645.c
···
1
+
/*
2
+
* rt5645.c -- RT5645 ALSA SoC audio codec driver
3
+
*
4
+
* Copyright 2013 Realtek Semiconductor Corp.
5
+
* Author: Bard Liao <bardliao@realtek.com>
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
10
+
*/
11
+
12
+
#include <linux/module.h>
13
+
#include <linux/moduleparam.h>
14
+
#include <linux/init.h>
15
+
#include <linux/delay.h>
16
+
#include <linux/pm.h>
17
+
#include <linux/i2c.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/spi/spi.h>
20
+
#include <sound/core.h>
21
+
#include <sound/pcm.h>
22
+
#include <sound/pcm_params.h>
23
+
#include <sound/jack.h>
24
+
#include <sound/soc.h>
25
+
#include <sound/soc-dapm.h>
26
+
#include <sound/initval.h>
27
+
#include <sound/tlv.h>
28
+
29
+
#include "rt5645.h"
30
+
31
+
#define RT5645_DEVICE_ID 0x6308
32
+
33
+
#define RT5645_PR_RANGE_BASE (0xff + 1)
34
+
#define RT5645_PR_SPACING 0x100
35
+
36
+
#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
37
+
38
+
static const struct regmap_range_cfg rt5645_ranges[] = {
39
+
{
40
+
.name = "PR",
41
+
.range_min = RT5645_PR_BASE,
42
+
.range_max = RT5645_PR_BASE + 0xf8,
43
+
.selector_reg = RT5645_PRIV_INDEX,
44
+
.selector_mask = 0xff,
45
+
.selector_shift = 0x0,
46
+
.window_start = RT5645_PRIV_DATA,
47
+
.window_len = 0x1,
48
+
},
49
+
};
50
+
51
+
static const struct reg_default init_list[] = {
52
+
{RT5645_PR_BASE + 0x3d, 0x3600},
53
+
{RT5645_PR_BASE + 0x1c, 0xfd20},
54
+
{RT5645_PR_BASE + 0x20, 0x611f},
55
+
{RT5645_PR_BASE + 0x21, 0x4040},
56
+
{RT5645_PR_BASE + 0x23, 0x0004},
57
+
};
58
+
#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
59
+
60
+
static const struct reg_default rt5645_reg[] = {
61
+
{ 0x00, 0x0000 },
62
+
{ 0x01, 0xc8c8 },
63
+
{ 0x02, 0xc8c8 },
64
+
{ 0x03, 0xc8c8 },
65
+
{ 0x0a, 0x0002 },
66
+
{ 0x0b, 0x2827 },
67
+
{ 0x0c, 0xe000 },
68
+
{ 0x0d, 0x0000 },
69
+
{ 0x0e, 0x0000 },
70
+
{ 0x0f, 0x0808 },
71
+
{ 0x14, 0x3333 },
72
+
{ 0x16, 0x4b00 },
73
+
{ 0x18, 0x018b },
74
+
{ 0x19, 0xafaf },
75
+
{ 0x1a, 0xafaf },
76
+
{ 0x1b, 0x0001 },
77
+
{ 0x1c, 0x2f2f },
78
+
{ 0x1d, 0x2f2f },
79
+
{ 0x1e, 0x0000 },
80
+
{ 0x20, 0x0000 },
81
+
{ 0x27, 0x7060 },
82
+
{ 0x28, 0x7070 },
83
+
{ 0x29, 0x8080 },
84
+
{ 0x2a, 0x5656 },
85
+
{ 0x2b, 0x5454 },
86
+
{ 0x2c, 0xaaa0 },
87
+
{ 0x2f, 0x1002 },
88
+
{ 0x31, 0x5000 },
89
+
{ 0x32, 0x0000 },
90
+
{ 0x33, 0x0000 },
91
+
{ 0x34, 0x0000 },
92
+
{ 0x35, 0x0000 },
93
+
{ 0x3b, 0x0000 },
94
+
{ 0x3c, 0x007f },
95
+
{ 0x3d, 0x0000 },
96
+
{ 0x3e, 0x007f },
97
+
{ 0x3f, 0x0000 },
98
+
{ 0x40, 0x001f },
99
+
{ 0x41, 0x0000 },
100
+
{ 0x42, 0x001f },
101
+
{ 0x45, 0x6000 },
102
+
{ 0x46, 0x003e },
103
+
{ 0x47, 0x003e },
104
+
{ 0x48, 0xf807 },
105
+
{ 0x4a, 0x0004 },
106
+
{ 0x4d, 0x0000 },
107
+
{ 0x4e, 0x0000 },
108
+
{ 0x4f, 0x01ff },
109
+
{ 0x50, 0x0000 },
110
+
{ 0x51, 0x0000 },
111
+
{ 0x52, 0x01ff },
112
+
{ 0x53, 0xf000 },
113
+
{ 0x56, 0x0111 },
114
+
{ 0x57, 0x0064 },
115
+
{ 0x58, 0xef0e },
116
+
{ 0x59, 0xf0f0 },
117
+
{ 0x5a, 0xef0e },
118
+
{ 0x5b, 0xf0f0 },
119
+
{ 0x5c, 0xef0e },
120
+
{ 0x5d, 0xf0f0 },
121
+
{ 0x5e, 0xf000 },
122
+
{ 0x5f, 0x0000 },
123
+
{ 0x61, 0x0300 },
124
+
{ 0x62, 0x0000 },
125
+
{ 0x63, 0x00c2 },
126
+
{ 0x64, 0x0000 },
127
+
{ 0x65, 0x0000 },
128
+
{ 0x66, 0x0000 },
129
+
{ 0x6a, 0x0000 },
130
+
{ 0x6c, 0x0aaa },
131
+
{ 0x70, 0x8000 },
132
+
{ 0x71, 0x8000 },
133
+
{ 0x72, 0x8000 },
134
+
{ 0x73, 0x7770 },
135
+
{ 0x74, 0x3e00 },
136
+
{ 0x75, 0x2409 },
137
+
{ 0x76, 0x000a },
138
+
{ 0x77, 0x0c00 },
139
+
{ 0x78, 0x0000 },
140
+
{ 0x80, 0x0000 },
141
+
{ 0x81, 0x0000 },
142
+
{ 0x82, 0x0000 },
143
+
{ 0x83, 0x0000 },
144
+
{ 0x84, 0x0000 },
145
+
{ 0x85, 0x0000 },
146
+
{ 0x8a, 0x0000 },
147
+
{ 0x8e, 0x0004 },
148
+
{ 0x8f, 0x1100 },
149
+
{ 0x90, 0x0646 },
150
+
{ 0x91, 0x0c06 },
151
+
{ 0x93, 0x0000 },
152
+
{ 0x94, 0x0200 },
153
+
{ 0x95, 0x0000 },
154
+
{ 0x9a, 0x2184 },
155
+
{ 0x9b, 0x010a },
156
+
{ 0x9c, 0x0aea },
157
+
{ 0x9d, 0x000c },
158
+
{ 0x9e, 0x0400 },
159
+
{ 0xa0, 0xa0a8 },
160
+
{ 0xa1, 0x0059 },
161
+
{ 0xa2, 0x0001 },
162
+
{ 0xae, 0x6000 },
163
+
{ 0xaf, 0x0000 },
164
+
{ 0xb0, 0x6000 },
165
+
{ 0xb1, 0x0000 },
166
+
{ 0xb2, 0x0000 },
167
+
{ 0xb3, 0x001f },
168
+
{ 0xb4, 0x020c },
169
+
{ 0xb5, 0x1f00 },
170
+
{ 0xb6, 0x0000 },
171
+
{ 0xbb, 0x0000 },
172
+
{ 0xbc, 0x0000 },
173
+
{ 0xbd, 0x0000 },
174
+
{ 0xbe, 0x0000 },
175
+
{ 0xbf, 0x3100 },
176
+
{ 0xc0, 0x0000 },
177
+
{ 0xc1, 0x0000 },
178
+
{ 0xc2, 0x0000 },
179
+
{ 0xc3, 0x2000 },
180
+
{ 0xcd, 0x0000 },
181
+
{ 0xce, 0x0000 },
182
+
{ 0xcf, 0x1813 },
183
+
{ 0xd0, 0x0690 },
184
+
{ 0xd1, 0x1c17 },
185
+
{ 0xd3, 0xb320 },
186
+
{ 0xd4, 0x0000 },
187
+
{ 0xd6, 0x0400 },
188
+
{ 0xd9, 0x0809 },
189
+
{ 0xda, 0x0000 },
190
+
{ 0xdb, 0x0003 },
191
+
{ 0xdc, 0x0049 },
192
+
{ 0xdd, 0x001b },
193
+
{ 0xe6, 0x8000 },
194
+
{ 0xe7, 0x0200 },
195
+
{ 0xec, 0xb300 },
196
+
{ 0xed, 0x0000 },
197
+
{ 0xf0, 0x001f },
198
+
{ 0xf1, 0x020c },
199
+
{ 0xf2, 0x1f00 },
200
+
{ 0xf3, 0x0000 },
201
+
{ 0xf4, 0x4000 },
202
+
{ 0xf8, 0x0000 },
203
+
{ 0xf9, 0x0000 },
204
+
{ 0xfa, 0x2060 },
205
+
{ 0xfb, 0x4040 },
206
+
{ 0xfc, 0x0000 },
207
+
{ 0xfd, 0x0002 },
208
+
{ 0xfe, 0x10ec },
209
+
{ 0xff, 0x6308 },
210
+
};
211
+
212
+
static int rt5645_reset(struct snd_soc_codec *codec)
213
+
{
214
+
return snd_soc_write(codec, RT5645_RESET, 0);
215
+
}
216
+
217
+
static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
218
+
{
219
+
int i;
220
+
221
+
for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
222
+
if (reg >= rt5645_ranges[i].range_min &&
223
+
reg <= rt5645_ranges[i].range_max) {
224
+
return true;
225
+
}
226
+
}
227
+
228
+
switch (reg) {
229
+
case RT5645_RESET:
230
+
case RT5645_PRIV_DATA:
231
+
case RT5645_IN1_CTRL1:
232
+
case RT5645_IN1_CTRL2:
233
+
case RT5645_IN1_CTRL3:
234
+
case RT5645_A_JD_CTRL1:
235
+
case RT5645_ADC_EQ_CTRL1:
236
+
case RT5645_EQ_CTRL1:
237
+
case RT5645_ALC_CTRL_1:
238
+
case RT5645_IRQ_CTRL2:
239
+
case RT5645_IRQ_CTRL3:
240
+
case RT5645_INT_IRQ_ST:
241
+
case RT5645_IL_CMD:
242
+
case RT5645_VENDOR_ID:
243
+
case RT5645_VENDOR_ID1:
244
+
case RT5645_VENDOR_ID2:
245
+
return true;
246
+
default:
247
+
return false;
248
+
}
249
+
}
250
+
251
+
static bool rt5645_readable_register(struct device *dev, unsigned int reg)
252
+
{
253
+
int i;
254
+
255
+
for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
256
+
if (reg >= rt5645_ranges[i].range_min &&
257
+
reg <= rt5645_ranges[i].range_max) {
258
+
return true;
259
+
}
260
+
}
261
+
262
+
switch (reg) {
263
+
case RT5645_RESET:
264
+
case RT5645_SPK_VOL:
265
+
case RT5645_HP_VOL:
266
+
case RT5645_LOUT1:
267
+
case RT5645_IN1_CTRL1:
268
+
case RT5645_IN1_CTRL2:
269
+
case RT5645_IN1_CTRL3:
270
+
case RT5645_IN2_CTRL:
271
+
case RT5645_INL1_INR1_VOL:
272
+
case RT5645_SPK_FUNC_LIM:
273
+
case RT5645_ADJ_HPF_CTRL:
274
+
case RT5645_DAC1_DIG_VOL:
275
+
case RT5645_DAC2_DIG_VOL:
276
+
case RT5645_DAC_CTRL:
277
+
case RT5645_STO1_ADC_DIG_VOL:
278
+
case RT5645_MONO_ADC_DIG_VOL:
279
+
case RT5645_ADC_BST_VOL1:
280
+
case RT5645_ADC_BST_VOL2:
281
+
case RT5645_STO1_ADC_MIXER:
282
+
case RT5645_MONO_ADC_MIXER:
283
+
case RT5645_AD_DA_MIXER:
284
+
case RT5645_STO_DAC_MIXER:
285
+
case RT5645_MONO_DAC_MIXER:
286
+
case RT5645_DIG_MIXER:
287
+
case RT5645_DIG_INF1_DATA:
288
+
case RT5645_PDM_OUT_CTRL:
289
+
case RT5645_REC_L1_MIXER:
290
+
case RT5645_REC_L2_MIXER:
291
+
case RT5645_REC_R1_MIXER:
292
+
case RT5645_REC_R2_MIXER:
293
+
case RT5645_HPMIXL_CTRL:
294
+
case RT5645_HPOMIXL_CTRL:
295
+
case RT5645_HPMIXR_CTRL:
296
+
case RT5645_HPOMIXR_CTRL:
297
+
case RT5645_HPO_MIXER:
298
+
case RT5645_SPK_L_MIXER:
299
+
case RT5645_SPK_R_MIXER:
300
+
case RT5645_SPO_MIXER:
301
+
case RT5645_SPO_CLSD_RATIO:
302
+
case RT5645_OUT_L1_MIXER:
303
+
case RT5645_OUT_R1_MIXER:
304
+
case RT5645_OUT_L_GAIN1:
305
+
case RT5645_OUT_L_GAIN2:
306
+
case RT5645_OUT_R_GAIN1:
307
+
case RT5645_OUT_R_GAIN2:
308
+
case RT5645_LOUT_MIXER:
309
+
case RT5645_HAPTIC_CTRL1:
310
+
case RT5645_HAPTIC_CTRL2:
311
+
case RT5645_HAPTIC_CTRL3:
312
+
case RT5645_HAPTIC_CTRL4:
313
+
case RT5645_HAPTIC_CTRL5:
314
+
case RT5645_HAPTIC_CTRL6:
315
+
case RT5645_HAPTIC_CTRL7:
316
+
case RT5645_HAPTIC_CTRL8:
317
+
case RT5645_HAPTIC_CTRL9:
318
+
case RT5645_HAPTIC_CTRL10:
319
+
case RT5645_PWR_DIG1:
320
+
case RT5645_PWR_DIG2:
321
+
case RT5645_PWR_ANLG1:
322
+
case RT5645_PWR_ANLG2:
323
+
case RT5645_PWR_MIXER:
324
+
case RT5645_PWR_VOL:
325
+
case RT5645_PRIV_INDEX:
326
+
case RT5645_PRIV_DATA:
327
+
case RT5645_I2S1_SDP:
328
+
case RT5645_I2S2_SDP:
329
+
case RT5645_ADDA_CLK1:
330
+
case RT5645_ADDA_CLK2:
331
+
case RT5645_DMIC_CTRL1:
332
+
case RT5645_DMIC_CTRL2:
333
+
case RT5645_TDM_CTRL_1:
334
+
case RT5645_TDM_CTRL_2:
335
+
case RT5645_GLB_CLK:
336
+
case RT5645_PLL_CTRL1:
337
+
case RT5645_PLL_CTRL2:
338
+
case RT5645_ASRC_1:
339
+
case RT5645_ASRC_2:
340
+
case RT5645_ASRC_3:
341
+
case RT5645_ASRC_4:
342
+
case RT5645_DEPOP_M1:
343
+
case RT5645_DEPOP_M2:
344
+
case RT5645_DEPOP_M3:
345
+
case RT5645_MICBIAS:
346
+
case RT5645_A_JD_CTRL1:
347
+
case RT5645_VAD_CTRL4:
348
+
case RT5645_CLSD_OUT_CTRL:
349
+
case RT5645_ADC_EQ_CTRL1:
350
+
case RT5645_ADC_EQ_CTRL2:
351
+
case RT5645_EQ_CTRL1:
352
+
case RT5645_EQ_CTRL2:
353
+
case RT5645_ALC_CTRL_1:
354
+
case RT5645_ALC_CTRL_2:
355
+
case RT5645_ALC_CTRL_3:
356
+
case RT5645_ALC_CTRL_4:
357
+
case RT5645_ALC_CTRL_5:
358
+
case RT5645_JD_CTRL:
359
+
case RT5645_IRQ_CTRL1:
360
+
case RT5645_IRQ_CTRL2:
361
+
case RT5645_IRQ_CTRL3:
362
+
case RT5645_INT_IRQ_ST:
363
+
case RT5645_GPIO_CTRL1:
364
+
case RT5645_GPIO_CTRL2:
365
+
case RT5645_GPIO_CTRL3:
366
+
case RT5645_BASS_BACK:
367
+
case RT5645_MP3_PLUS1:
368
+
case RT5645_MP3_PLUS2:
369
+
case RT5645_ADJ_HPF1:
370
+
case RT5645_ADJ_HPF2:
371
+
case RT5645_HP_CALIB_AMP_DET:
372
+
case RT5645_SV_ZCD1:
373
+
case RT5645_SV_ZCD2:
374
+
case RT5645_IL_CMD:
375
+
case RT5645_IL_CMD2:
376
+
case RT5645_IL_CMD3:
377
+
case RT5645_DRC1_HL_CTRL1:
378
+
case RT5645_DRC2_HL_CTRL1:
379
+
case RT5645_ADC_MONO_HP_CTRL1:
380
+
case RT5645_ADC_MONO_HP_CTRL2:
381
+
case RT5645_DRC2_CTRL1:
382
+
case RT5645_DRC2_CTRL2:
383
+
case RT5645_DRC2_CTRL3:
384
+
case RT5645_DRC2_CTRL4:
385
+
case RT5645_DRC2_CTRL5:
386
+
case RT5645_JD_CTRL3:
387
+
case RT5645_JD_CTRL4:
388
+
case RT5645_GEN_CTRL1:
389
+
case RT5645_GEN_CTRL2:
390
+
case RT5645_GEN_CTRL3:
391
+
case RT5645_VENDOR_ID:
392
+
case RT5645_VENDOR_ID1:
393
+
case RT5645_VENDOR_ID2:
394
+
return true;
395
+
default:
396
+
return false;
397
+
}
398
+
}
399
+
400
+
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
401
+
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
402
+
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
403
+
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
404
+
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
405
+
406
+
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
407
+
static unsigned int bst_tlv[] = {
408
+
TLV_DB_RANGE_HEAD(7),
409
+
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
410
+
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
411
+
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
412
+
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
413
+
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
414
+
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
415
+
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
416
+
};
417
+
418
+
static const char * const rt5645_tdm_data_swap_select[] = {
419
+
"L/R", "R/L", "L/L", "R/R"
420
+
};
421
+
422
+
static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
423
+
RT5645_TDM_CTRL_1, 6, rt5645_tdm_data_swap_select);
424
+
425
+
static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
426
+
RT5645_TDM_CTRL_1, 4, rt5645_tdm_data_swap_select);
427
+
428
+
static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
429
+
RT5645_TDM_CTRL_1, 2, rt5645_tdm_data_swap_select);
430
+
431
+
static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot6_7_enum,
432
+
RT5645_TDM_CTRL_1, 0, rt5645_tdm_data_swap_select);
433
+
434
+
static const char * const rt5645_tdm_adc_data_select[] = {
435
+
"1/2/R", "2/1/R", "R/1/2", "R/2/1"
436
+
};
437
+
438
+
static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_sel_enum,
439
+
RT5645_TDM_CTRL_1, 8,
440
+
rt5645_tdm_adc_data_select);
441
+
442
+
static const struct snd_kcontrol_new rt5645_snd_controls[] = {
443
+
/* Speaker Output Volume */
444
+
SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
445
+
RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
446
+
SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
447
+
RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
448
+
449
+
/* Headphone Output Volume */
450
+
SOC_DOUBLE("HP Channel Switch", RT5645_HP_VOL,
451
+
RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
452
+
SOC_DOUBLE_TLV("HP Playback Volume", RT5645_HP_VOL,
453
+
RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
454
+
455
+
/* OUTPUT Control */
456
+
SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
457
+
RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
458
+
SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
459
+
RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
460
+
SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
461
+
RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
462
+
463
+
/* DAC Digital Volume */
464
+
SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
465
+
RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
466
+
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
467
+
RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
468
+
SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
469
+
RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
470
+
471
+
/* IN1/IN2 Control */
472
+
SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
473
+
RT5645_BST_SFT1, 8, 0, bst_tlv),
474
+
SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
475
+
RT5645_BST_SFT2, 8, 0, bst_tlv),
476
+
477
+
/* INL/INR Volume Control */
478
+
SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
479
+
RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
480
+
481
+
/* ADC Digital Volume Control */
482
+
SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
483
+
RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
484
+
SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
485
+
RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
486
+
SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
487
+
RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
488
+
SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
489
+
RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
490
+
491
+
/* ADC Boost Volume Control */
492
+
SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
493
+
RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
494
+
adc_bst_tlv),
495
+
SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1,
496
+
RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0,
497
+
adc_bst_tlv),
498
+
499
+
/* I2S2 function select */
500
+
SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
501
+
1, 1),
502
+
503
+
/* TDM */
504
+
SOC_ENUM("TDM Adc Slot0 1 Data", rt5645_tdm_adc_slot0_1_enum),
505
+
SOC_ENUM("TDM Adc Slot2 3 Data", rt5645_tdm_adc_slot2_3_enum),
506
+
SOC_ENUM("TDM Adc Slot4 5 Data", rt5645_tdm_adc_slot4_5_enum),
507
+
SOC_ENUM("TDM Adc Slot6 7 Data", rt5645_tdm_adc_slot6_7_enum),
508
+
SOC_ENUM("TDM IF1 ADC DATA Sel", rt5645_tdm_adc_sel_enum),
509
+
SOC_SINGLE("TDM IF1_DAC1_L Sel", RT5645_TDM_CTRL_3, 12, 7, 0),
510
+
SOC_SINGLE("TDM IF1_DAC1_R Sel", RT5645_TDM_CTRL_3, 8, 7, 0),
511
+
SOC_SINGLE("TDM IF1_DAC2_L Sel", RT5645_TDM_CTRL_3, 4, 7, 0),
512
+
SOC_SINGLE("TDM IF1_DAC2_R Sel", RT5645_TDM_CTRL_3, 0, 7, 0),
513
+
};
514
+
515
+
/**
516
+
* set_dmic_clk - Set parameter of dmic.
517
+
*
518
+
* @w: DAPM widget.
519
+
* @kcontrol: The kcontrol of this widget.
520
+
* @event: Event id.
521
+
*
522
+
* Choose dmic clock between 1MHz and 3MHz.
523
+
* It is better for clock to approximate 3MHz.
524
+
*/
525
+
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
526
+
struct snd_kcontrol *kcontrol, int event)
527
+
{
528
+
struct snd_soc_codec *codec = w->codec;
529
+
struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
530
+
int div[] = {2, 3, 4, 6, 8, 12};
531
+
int idx = -EINVAL, i;
532
+
int rate, red, bound, temp;
533
+
534
+
rate = rt5645->sysclk;
535
+
red = 3000000 * 12;
536
+
for (i = 0; i < ARRAY_SIZE(div); i++) {
537
+
bound = div[i] * 3000000;
538
+
if (rate > bound)
539
+
continue;
540
+
temp = bound - rate;
541
+
if (temp < red) {
542
+
red = temp;
543
+
idx = i;
544
+
}
545
+
}
546
+
547
+
if (idx < 0)
548
+
dev_err(codec->dev, "Failed to set DMIC clock\n");
549
+
else
550
+
snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
551
+
RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
552
+
return idx;
553
+
}
554
+
555
+
static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
556
+
struct snd_soc_dapm_widget *sink)
557
+
{
558
+
unsigned int val;
559
+
560
+
val = snd_soc_read(source->codec, RT5645_GLB_CLK);
561
+
val &= RT5645_SCLK_SRC_MASK;
562
+
if (val == RT5645_SCLK_SRC_PLL1)
563
+
return 1;
564
+
else
565
+
return 0;
566
+
}
567
+
568
+
/* Digital Mixer */
569
+
static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
570
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
571
+
RT5645_M_ADC_L1_SFT, 1, 1),
572
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
573
+
RT5645_M_ADC_L2_SFT, 1, 1),
574
+
};
575
+
576
+
static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
577
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
578
+
RT5645_M_ADC_R1_SFT, 1, 1),
579
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
580
+
RT5645_M_ADC_R2_SFT, 1, 1),
581
+
};
582
+
583
+
static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
584
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
585
+
RT5645_M_MONO_ADC_L1_SFT, 1, 1),
586
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
587
+
RT5645_M_MONO_ADC_L2_SFT, 1, 1),
588
+
};
589
+
590
+
static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
591
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
592
+
RT5645_M_MONO_ADC_R1_SFT, 1, 1),
593
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
594
+
RT5645_M_MONO_ADC_R2_SFT, 1, 1),
595
+
};
596
+
597
+
static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
598
+
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
599
+
RT5645_M_ADCMIX_L_SFT, 1, 1),
600
+
SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
601
+
RT5645_M_DAC1_L_SFT, 1, 1),
602
+
};
603
+
604
+
static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
605
+
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
606
+
RT5645_M_ADCMIX_R_SFT, 1, 1),
607
+
SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
608
+
RT5645_M_DAC1_R_SFT, 1, 1),
609
+
};
610
+
611
+
static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
612
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
613
+
RT5645_M_DAC_L1_SFT, 1, 1),
614
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
615
+
RT5645_M_DAC_L2_SFT, 1, 1),
616
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
617
+
RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
618
+
};
619
+
620
+
static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
621
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
622
+
RT5645_M_DAC_R1_SFT, 1, 1),
623
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
624
+
RT5645_M_DAC_R2_SFT, 1, 1),
625
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
626
+
RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
627
+
};
628
+
629
+
static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
630
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
631
+
RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
632
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
633
+
RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
634
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
635
+
RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
636
+
};
637
+
638
+
static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
639
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
640
+
RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
641
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
642
+
RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
643
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
644
+
RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
645
+
};
646
+
647
+
static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
648
+
SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
649
+
RT5645_M_STO_L_DAC_L_SFT, 1, 1),
650
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
651
+
RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
652
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
653
+
RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
654
+
};
655
+
656
+
static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
657
+
SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
658
+
RT5645_M_STO_R_DAC_R_SFT, 1, 1),
659
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
660
+
RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
661
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
662
+
RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
663
+
};
664
+
665
+
/* Analog Input Mixer */
666
+
static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
667
+
SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
668
+
RT5645_M_HP_L_RM_L_SFT, 1, 1),
669
+
SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
670
+
RT5645_M_IN_L_RM_L_SFT, 1, 1),
671
+
SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
672
+
RT5645_M_BST2_RM_L_SFT, 1, 1),
673
+
SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
674
+
RT5645_M_BST1_RM_L_SFT, 1, 1),
675
+
SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
676
+
RT5645_M_OM_L_RM_L_SFT, 1, 1),
677
+
};
678
+
679
+
static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
680
+
SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
681
+
RT5645_M_HP_R_RM_R_SFT, 1, 1),
682
+
SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
683
+
RT5645_M_IN_R_RM_R_SFT, 1, 1),
684
+
SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
685
+
RT5645_M_BST2_RM_R_SFT, 1, 1),
686
+
SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
687
+
RT5645_M_BST1_RM_R_SFT, 1, 1),
688
+
SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
689
+
RT5645_M_OM_R_RM_R_SFT, 1, 1),
690
+
};
691
+
692
+
static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
693
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
694
+
RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
695
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
696
+
RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
697
+
SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
698
+
RT5645_M_IN_L_SM_L_SFT, 1, 1),
699
+
SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
700
+
RT5645_M_BST1_L_SM_L_SFT, 1, 1),
701
+
};
702
+
703
+
static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
704
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
705
+
RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
706
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
707
+
RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
708
+
SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
709
+
RT5645_M_IN_R_SM_R_SFT, 1, 1),
710
+
SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
711
+
RT5645_M_BST2_R_SM_R_SFT, 1, 1),
712
+
};
713
+
714
+
static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
715
+
SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
716
+
RT5645_M_BST1_OM_L_SFT, 1, 1),
717
+
SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
718
+
RT5645_M_IN_L_OM_L_SFT, 1, 1),
719
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
720
+
RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
721
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
722
+
RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
723
+
};
724
+
725
+
static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
726
+
SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
727
+
RT5645_M_BST2_OM_R_SFT, 1, 1),
728
+
SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
729
+
RT5645_M_IN_R_OM_R_SFT, 1, 1),
730
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
731
+
RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
732
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
733
+
RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
734
+
};
735
+
736
+
static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
737
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
738
+
RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
739
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
740
+
RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
741
+
SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
742
+
RT5645_M_SV_R_SPM_L_SFT, 1, 1),
743
+
SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
744
+
RT5645_M_SV_L_SPM_L_SFT, 1, 1),
745
+
};
746
+
747
+
static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
748
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
749
+
RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
750
+
SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
751
+
RT5645_M_SV_R_SPM_R_SFT, 1, 1),
752
+
};
753
+
754
+
static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
755
+
SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
756
+
RT5645_M_DAC1_HM_SFT, 1, 1),
757
+
SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
758
+
RT5645_M_HPVOL_HM_SFT, 1, 1),
759
+
};
760
+
761
+
static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
762
+
SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
763
+
RT5645_M_DAC1_HV_SFT, 1, 1),
764
+
SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
765
+
RT5645_M_DAC2_HV_SFT, 1, 1),
766
+
SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
767
+
RT5645_M_IN_HV_SFT, 1, 1),
768
+
SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
769
+
RT5645_M_BST1_HV_SFT, 1, 1),
770
+
};
771
+
772
+
static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
773
+
SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
774
+
RT5645_M_DAC1_HV_SFT, 1, 1),
775
+
SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
776
+
RT5645_M_DAC2_HV_SFT, 1, 1),
777
+
SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
778
+
RT5645_M_IN_HV_SFT, 1, 1),
779
+
SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
780
+
RT5645_M_BST2_HV_SFT, 1, 1),
781
+
};
782
+
783
+
static const struct snd_kcontrol_new rt5645_lout_mix[] = {
784
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
785
+
RT5645_M_DAC_L1_LM_SFT, 1, 1),
786
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
787
+
RT5645_M_DAC_R1_LM_SFT, 1, 1),
788
+
SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
789
+
RT5645_M_OV_L_LM_SFT, 1, 1),
790
+
SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
791
+
RT5645_M_OV_R_LM_SFT, 1, 1),
792
+
};
793
+
794
+
/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
795
+
static const char * const rt5645_dac1_src[] = {
796
+
"IF1 DAC", "IF2 DAC", "IF3 DAC"
797
+
};
798
+
799
+
static SOC_ENUM_SINGLE_DECL(
800
+
rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
801
+
RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
802
+
803
+
static const struct snd_kcontrol_new rt5645_dac1l_mux =
804
+
SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
805
+
806
+
static SOC_ENUM_SINGLE_DECL(
807
+
rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
808
+
RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
809
+
810
+
static const struct snd_kcontrol_new rt5645_dac1r_mux =
811
+
SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
812
+
813
+
/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
814
+
static const char * const rt5645_dac12_src[] = {
815
+
"IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
816
+
};
817
+
818
+
static SOC_ENUM_SINGLE_DECL(
819
+
rt5645_dac2l_enum, RT5645_DAC_CTRL,
820
+
RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
821
+
822
+
static const struct snd_kcontrol_new rt5645_dac_l2_mux =
823
+
SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
824
+
825
+
static const char * const rt5645_dacr2_src[] = {
826
+
"IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
827
+
};
828
+
829
+
static SOC_ENUM_SINGLE_DECL(
830
+
rt5645_dac2r_enum, RT5645_DAC_CTRL,
831
+
RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
832
+
833
+
static const struct snd_kcontrol_new rt5645_dac_r2_mux =
834
+
SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
835
+
836
+
837
+
/* INL/R source */
838
+
static const char * const rt5645_inl_src[] = {
839
+
"IN2P", "MonoP"
840
+
};
841
+
842
+
static SOC_ENUM_SINGLE_DECL(
843
+
rt5645_inl_enum, RT5645_INL1_INR1_VOL,
844
+
RT5645_INL_SEL_SFT, rt5645_inl_src);
845
+
846
+
static const struct snd_kcontrol_new rt5645_inl_mux =
847
+
SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
848
+
849
+
static const char * const rt5645_inr_src[] = {
850
+
"IN2N", "MonoN"
851
+
};
852
+
853
+
static SOC_ENUM_SINGLE_DECL(
854
+
rt5645_inr_enum, RT5645_INL1_INR1_VOL,
855
+
RT5645_INR_SEL_SFT, rt5645_inr_src);
856
+
857
+
static const struct snd_kcontrol_new rt5645_inr_mux =
858
+
SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
859
+
860
+
/* Stereo1 ADC source */
861
+
/* MX-27 [12] */
862
+
static const char * const rt5645_stereo_adc1_src[] = {
863
+
"DAC MIX", "ADC"
864
+
};
865
+
866
+
static SOC_ENUM_SINGLE_DECL(
867
+
rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
868
+
RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
869
+
870
+
static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
871
+
SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
872
+
873
+
/* MX-27 [11] */
874
+
static const char * const rt5645_stereo_adc2_src[] = {
875
+
"DAC MIX", "DMIC"
876
+
};
877
+
878
+
static SOC_ENUM_SINGLE_DECL(
879
+
rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
880
+
RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
881
+
882
+
static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
883
+
SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
884
+
885
+
/* MX-27 [8] */
886
+
static const char * const rt5645_stereo_dmic_src[] = {
887
+
"DMIC1", "DMIC2"
888
+
};
889
+
890
+
static SOC_ENUM_SINGLE_DECL(
891
+
rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
892
+
RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
893
+
894
+
static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
895
+
SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
896
+
897
+
/* Mono ADC source */
898
+
/* MX-28 [12] */
899
+
static const char * const rt5645_mono_adc_l1_src[] = {
900
+
"Mono DAC MIXL", "ADC"
901
+
};
902
+
903
+
static SOC_ENUM_SINGLE_DECL(
904
+
rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
905
+
RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
906
+
907
+
static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
908
+
SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
909
+
/* MX-28 [11] */
910
+
static const char * const rt5645_mono_adc_l2_src[] = {
911
+
"Mono DAC MIXL", "DMIC"
912
+
};
913
+
914
+
static SOC_ENUM_SINGLE_DECL(
915
+
rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
916
+
RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
917
+
918
+
static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
919
+
SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
920
+
921
+
/* MX-28 [8] */
922
+
static const char * const rt5645_mono_dmic_src[] = {
923
+
"DMIC1", "DMIC2"
924
+
};
925
+
926
+
static SOC_ENUM_SINGLE_DECL(
927
+
rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
928
+
RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
929
+
930
+
static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
931
+
SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
932
+
/* MX-28 [1:0] */
933
+
static SOC_ENUM_SINGLE_DECL(
934
+
rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
935
+
RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
936
+
937
+
static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
938
+
SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
939
+
/* MX-28 [4] */
940
+
static const char * const rt5645_mono_adc_r1_src[] = {
941
+
"Mono DAC MIXR", "ADC"
942
+
};
943
+
944
+
static SOC_ENUM_SINGLE_DECL(
945
+
rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
946
+
RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
947
+
948
+
static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
949
+
SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
950
+
/* MX-28 [3] */
951
+
static const char * const rt5645_mono_adc_r2_src[] = {
952
+
"Mono DAC MIXR", "DMIC"
953
+
};
954
+
955
+
static SOC_ENUM_SINGLE_DECL(
956
+
rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
957
+
RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
958
+
959
+
static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
960
+
SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
961
+
962
+
/* MX-77 [9:8] */
963
+
static const char * const rt5645_if1_adc_in_src[] = {
964
+
"IF_ADC1", "IF_ADC2", "VAD_ADC"
965
+
};
966
+
967
+
static SOC_ENUM_SINGLE_DECL(
968
+
rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
969
+
RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
970
+
971
+
static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
972
+
SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
973
+
974
+
/* MX-2F [13:12] */
975
+
static const char * const rt5645_if2_adc_in_src[] = {
976
+
"IF_ADC1", "IF_ADC2", "VAD_ADC"
977
+
};
978
+
979
+
static SOC_ENUM_SINGLE_DECL(
980
+
rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
981
+
RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
982
+
983
+
static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
984
+
SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
985
+
986
+
/* MX-2F [1:0] */
987
+
static const char * const rt5645_if3_adc_in_src[] = {
988
+
"IF_ADC1", "IF_ADC2", "VAD_ADC"
989
+
};
990
+
991
+
static SOC_ENUM_SINGLE_DECL(
992
+
rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
993
+
RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
994
+
995
+
static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
996
+
SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
997
+
998
+
/* MX-31 [15] [13] [11] [9] */
999
+
static const char * const rt5645_pdm_src[] = {
1000
+
"Mono DAC", "Stereo DAC"
1001
+
};
1002
+
1003
+
static SOC_ENUM_SINGLE_DECL(
1004
+
rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1005
+
RT5645_PDM1_L_SFT, rt5645_pdm_src);
1006
+
1007
+
static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1008
+
SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1009
+
1010
+
static SOC_ENUM_SINGLE_DECL(
1011
+
rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1012
+
RT5645_PDM1_R_SFT, rt5645_pdm_src);
1013
+
1014
+
static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1015
+
SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1016
+
1017
+
/* MX-9D [9:8] */
1018
+
static const char * const rt5645_vad_adc_src[] = {
1019
+
"Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1020
+
};
1021
+
1022
+
static SOC_ENUM_SINGLE_DECL(
1023
+
rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1024
+
RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1025
+
1026
+
static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1027
+
SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1028
+
1029
+
static const struct snd_kcontrol_new spk_l_vol_control =
1030
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1031
+
RT5645_L_MUTE_SFT, 1, 1);
1032
+
1033
+
static const struct snd_kcontrol_new spk_r_vol_control =
1034
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1035
+
RT5645_R_MUTE_SFT, 1, 1);
1036
+
1037
+
static const struct snd_kcontrol_new hp_l_vol_control =
1038
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1039
+
RT5645_L_MUTE_SFT, 1, 1);
1040
+
1041
+
static const struct snd_kcontrol_new hp_r_vol_control =
1042
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1043
+
RT5645_R_MUTE_SFT, 1, 1);
1044
+
1045
+
static const struct snd_kcontrol_new pdm1_l_vol_control =
1046
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1047
+
RT5645_M_PDM1_L, 1, 1);
1048
+
1049
+
static const struct snd_kcontrol_new pdm1_r_vol_control =
1050
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1051
+
RT5645_M_PDM1_R, 1, 1);
1052
+
1053
+
static void hp_amp_power(struct snd_soc_codec *codec, int on)
1054
+
{
1055
+
static int hp_amp_power_count;
1056
+
struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1057
+
1058
+
if (on) {
1059
+
if (hp_amp_power_count <= 0) {
1060
+
/* depop parameters */
1061
+
snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1062
+
RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1063
+
snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1064
+
regmap_write(rt5645->regmap, RT5645_PR_BASE +
1065
+
RT5645_HP_DCC_INT1, 0x9f01);
1066
+
mdelay(150);
1067
+
/* headphone amp power on */
1068
+
snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1069
+
RT5645_PWR_FV1 | RT5645_PWR_FV2 , 0);
1070
+
snd_soc_update_bits(codec, RT5645_PWR_VOL,
1071
+
RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1072
+
RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1073
+
snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1074
+
RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1075
+
RT5645_PWR_HA,
1076
+
RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1077
+
RT5645_PWR_HA);
1078
+
mdelay(5);
1079
+
snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1080
+
RT5645_PWR_FV1 | RT5645_PWR_FV2,
1081
+
RT5645_PWR_FV1 | RT5645_PWR_FV2);
1082
+
1083
+
snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1084
+
RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1085
+
RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1086
+
regmap_write(rt5645->regmap, RT5645_PR_BASE +
1087
+
0x14, 0x1aaa);
1088
+
regmap_write(rt5645->regmap, RT5645_PR_BASE +
1089
+
0x24, 0x0430);
1090
+
}
1091
+
hp_amp_power_count++;
1092
+
} else {
1093
+
hp_amp_power_count--;
1094
+
if (hp_amp_power_count <= 0) {
1095
+
snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1096
+
RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1097
+
RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1098
+
RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1099
+
/* headphone amp power down */
1100
+
snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1101
+
snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1102
+
RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1103
+
RT5645_PWR_HA, 0);
1104
+
}
1105
+
}
1106
+
}
1107
+
1108
+
static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1109
+
struct snd_kcontrol *kcontrol, int event)
1110
+
{
1111
+
struct snd_soc_codec *codec = w->codec;
1112
+
struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1113
+
1114
+
switch (event) {
1115
+
case SND_SOC_DAPM_POST_PMU:
1116
+
hp_amp_power(codec, 1);
1117
+
/* headphone unmute sequence */
1118
+
snd_soc_update_bits(codec, RT5645_DEPOP_M3, RT5645_CP_FQ1_MASK |
1119
+
RT5645_CP_FQ2_MASK | RT5645_CP_FQ3_MASK,
1120
+
(RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1121
+
(RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1122
+
(RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1123
+
regmap_write(rt5645->regmap,
1124
+
RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1125
+
snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1126
+
RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1127
+
snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1128
+
RT5645_RSTN_MASK, RT5645_RSTN_EN);
1129
+
snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1130
+
RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1131
+
RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1132
+
RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1133
+
msleep(40);
1134
+
snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1135
+
RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1136
+
RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1137
+
RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1138
+
break;
1139
+
1140
+
case SND_SOC_DAPM_PRE_PMD:
1141
+
/* headphone mute sequence */
1142
+
snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1143
+
RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1144
+
RT5645_CP_FQ3_MASK,
1145
+
(RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1146
+
(RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1147
+
(RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1148
+
regmap_write(rt5645->regmap,
1149
+
RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1150
+
snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1151
+
RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1152
+
snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1153
+
RT5645_RSTP_MASK, RT5645_RSTP_EN);
1154
+
snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1155
+
RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1156
+
RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1157
+
RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1158
+
msleep(30);
1159
+
hp_amp_power(codec, 0);
1160
+
break;
1161
+
1162
+
default:
1163
+
return 0;
1164
+
}
1165
+
1166
+
return 0;
1167
+
}
1168
+
1169
+
static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1170
+
struct snd_kcontrol *kcontrol, int event)
1171
+
{
1172
+
struct snd_soc_codec *codec = w->codec;
1173
+
1174
+
switch (event) {
1175
+
case SND_SOC_DAPM_POST_PMU:
1176
+
snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1177
+
RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1178
+
RT5645_PWR_CLS_D_L,
1179
+
RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1180
+
RT5645_PWR_CLS_D_L);
1181
+
break;
1182
+
1183
+
case SND_SOC_DAPM_PRE_PMD:
1184
+
snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1185
+
RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1186
+
RT5645_PWR_CLS_D_L, 0);
1187
+
break;
1188
+
1189
+
default:
1190
+
return 0;
1191
+
}
1192
+
1193
+
return 0;
1194
+
}
1195
+
1196
+
static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1197
+
struct snd_kcontrol *kcontrol, int event)
1198
+
{
1199
+
struct snd_soc_codec *codec = w->codec;
1200
+
1201
+
switch (event) {
1202
+
case SND_SOC_DAPM_POST_PMU:
1203
+
hp_amp_power(codec, 1);
1204
+
snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1205
+
RT5645_PWR_LM, RT5645_PWR_LM);
1206
+
snd_soc_update_bits(codec, RT5645_LOUT1,
1207
+
RT5645_L_MUTE | RT5645_R_MUTE, 0);
1208
+
break;
1209
+
1210
+
case SND_SOC_DAPM_PRE_PMD:
1211
+
snd_soc_update_bits(codec, RT5645_LOUT1,
1212
+
RT5645_L_MUTE | RT5645_R_MUTE,
1213
+
RT5645_L_MUTE | RT5645_R_MUTE);
1214
+
snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1215
+
RT5645_PWR_LM, 0);
1216
+
hp_amp_power(codec, 0);
1217
+
break;
1218
+
1219
+
default:
1220
+
return 0;
1221
+
}
1222
+
1223
+
return 0;
1224
+
}
1225
+
1226
+
static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1227
+
struct snd_kcontrol *kcontrol, int event)
1228
+
{
1229
+
struct snd_soc_codec *codec = w->codec;
1230
+
1231
+
switch (event) {
1232
+
case SND_SOC_DAPM_POST_PMU:
1233
+
snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1234
+
RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1235
+
break;
1236
+
1237
+
case SND_SOC_DAPM_PRE_PMD:
1238
+
snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1239
+
RT5645_PWR_BST2_P, 0);
1240
+
break;
1241
+
1242
+
default:
1243
+
return 0;
1244
+
}
1245
+
1246
+
return 0;
1247
+
}
1248
+
1249
+
static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1250
+
SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1251
+
RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1252
+
SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1253
+
RT5645_PWR_PLL_BIT, 0, NULL, 0),
1254
+
1255
+
SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1256
+
RT5645_PWR_JD1_BIT, 0, NULL, 0),
1257
+
SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1258
+
RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1259
+
1260
+
/* Input Side */
1261
+
/* micbias */
1262
+
SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1263
+
RT5645_PWR_MB1_BIT, 0),
1264
+
SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1265
+
RT5645_PWR_MB2_BIT, 0),
1266
+
/* Input Lines */
1267
+
SND_SOC_DAPM_INPUT("DMIC L1"),
1268
+
SND_SOC_DAPM_INPUT("DMIC R1"),
1269
+
SND_SOC_DAPM_INPUT("DMIC L2"),
1270
+
SND_SOC_DAPM_INPUT("DMIC R2"),
1271
+
1272
+
SND_SOC_DAPM_INPUT("IN1P"),
1273
+
SND_SOC_DAPM_INPUT("IN1N"),
1274
+
SND_SOC_DAPM_INPUT("IN2P"),
1275
+
SND_SOC_DAPM_INPUT("IN2N"),
1276
+
1277
+
SND_SOC_DAPM_INPUT("Haptic Generator"),
1278
+
1279
+
SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1280
+
SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1281
+
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1282
+
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1283
+
SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1284
+
RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1285
+
SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1286
+
RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1287
+
/* Boost */
1288
+
SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1289
+
RT5645_PWR_BST1_BIT, 0, NULL, 0),
1290
+
SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1291
+
RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1292
+
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1293
+
/* Input Volume */
1294
+
SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1295
+
RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1296
+
SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1297
+
RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1298
+
/* REC Mixer */
1299
+
SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1300
+
0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1301
+
SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1302
+
0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1303
+
/* ADCs */
1304
+
SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1305
+
SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1306
+
1307
+
SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1308
+
RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1309
+
SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1310
+
RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1311
+
1312
+
/* ADC Mux */
1313
+
SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1314
+
&rt5645_sto1_dmic_mux),
1315
+
SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1316
+
&rt5645_sto_adc2_mux),
1317
+
SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1318
+
&rt5645_sto_adc2_mux),
1319
+
SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1320
+
&rt5645_sto_adc1_mux),
1321
+
SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1322
+
&rt5645_sto_adc1_mux),
1323
+
SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1324
+
&rt5645_mono_dmic_l_mux),
1325
+
SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1326
+
&rt5645_mono_dmic_r_mux),
1327
+
SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1328
+
&rt5645_mono_adc_l2_mux),
1329
+
SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1330
+
&rt5645_mono_adc_l1_mux),
1331
+
SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1332
+
&rt5645_mono_adc_r1_mux),
1333
+
SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1334
+
&rt5645_mono_adc_r2_mux),
1335
+
/* ADC Mixer */
1336
+
1337
+
SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1338
+
RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1339
+
SND_SOC_DAPM_SUPPLY_S("adc stereo2 filter", 1, RT5645_PWR_DIG2,
1340
+
RT5645_PWR_ADC_S2F_BIT, 0, NULL, 0),
1341
+
SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1342
+
rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1343
+
NULL, 0),
1344
+
SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1345
+
rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1346
+
NULL, 0),
1347
+
SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1348
+
RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1349
+
SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1350
+
rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1351
+
NULL, 0),
1352
+
SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1353
+
RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1354
+
SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1355
+
rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1356
+
NULL, 0),
1357
+
1358
+
/* ADC PGA */
1359
+
SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1360
+
SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1361
+
SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1362
+
SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1363
+
SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1364
+
SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1365
+
SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1366
+
SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1367
+
SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1368
+
SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1369
+
1370
+
/* IF1 2 Mux */
1371
+
SND_SOC_DAPM_MUX("IF1 ADC Mux", SND_SOC_NOPM,
1372
+
0, 0, &rt5645_if1_adc_in_mux),
1373
+
SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1374
+
0, 0, &rt5645_if2_adc_in_mux),
1375
+
1376
+
/* Digital Interface */
1377
+
SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1378
+
RT5645_PWR_I2S1_BIT, 0, NULL, 0),
1379
+
SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1380
+
SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1381
+
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1382
+
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1383
+
SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1384
+
SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1385
+
SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1386
+
SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1387
+
SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1388
+
SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1389
+
RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1390
+
SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1391
+
SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1392
+
SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1393
+
SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1394
+
1395
+
/* Digital Interface Select */
1396
+
SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1397
+
0, 0, &rt5645_vad_adc_mux),
1398
+
1399
+
/* Audio Interface */
1400
+
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1401
+
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1402
+
SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1403
+
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1404
+
1405
+
/* Output Side */
1406
+
/* DAC mixer before sound effect */
1407
+
SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1408
+
rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1409
+
SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1410
+
rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1411
+
1412
+
/* DAC2 channel Mux */
1413
+
SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1414
+
SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1415
+
SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1416
+
RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1417
+
SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1418
+
RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1419
+
1420
+
SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1421
+
SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1422
+
1423
+
/* DAC Mixer */
1424
+
SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1425
+
RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1426
+
SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1427
+
RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1428
+
SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1429
+
RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1430
+
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1431
+
rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1432
+
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1433
+
rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1434
+
SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1435
+
rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1436
+
SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1437
+
rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1438
+
SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1439
+
rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1440
+
SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1441
+
rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1442
+
1443
+
/* DACs */
1444
+
SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1445
+
0),
1446
+
SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1447
+
0),
1448
+
SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1449
+
0),
1450
+
SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1451
+
0),
1452
+
/* OUT Mixer */
1453
+
SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1454
+
0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1455
+
SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1456
+
0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1457
+
SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1458
+
0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1459
+
SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1460
+
0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1461
+
/* Ouput Volume */
1462
+
SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1463
+
&spk_l_vol_control),
1464
+
SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1465
+
&spk_r_vol_control),
1466
+
SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
1467
+
0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
1468
+
SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
1469
+
0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
1470
+
SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
1471
+
RT5645_PWR_HM_L_BIT, 0, NULL, 0),
1472
+
SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
1473
+
RT5645_PWR_HM_R_BIT, 0, NULL, 0),
1474
+
SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1475
+
SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1476
+
SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1477
+
SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
1478
+
SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
1479
+
1480
+
/* HPO/LOUT/Mono Mixer */
1481
+
SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
1482
+
ARRAY_SIZE(rt5645_spo_l_mix)),
1483
+
SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
1484
+
ARRAY_SIZE(rt5645_spo_r_mix)),
1485
+
SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
1486
+
ARRAY_SIZE(rt5645_hpo_mix)),
1487
+
SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
1488
+
ARRAY_SIZE(rt5645_lout_mix)),
1489
+
1490
+
SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
1491
+
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1492
+
SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
1493
+
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1494
+
SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
1495
+
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1496
+
1497
+
/* PDM */
1498
+
SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
1499
+
0, NULL, 0),
1500
+
SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
1501
+
SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
1502
+
1503
+
SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
1504
+
SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
1505
+
1506
+
/* Output Lines */
1507
+
SND_SOC_DAPM_OUTPUT("HPOL"),
1508
+
SND_SOC_DAPM_OUTPUT("HPOR"),
1509
+
SND_SOC_DAPM_OUTPUT("LOUTL"),
1510
+
SND_SOC_DAPM_OUTPUT("LOUTR"),
1511
+
SND_SOC_DAPM_OUTPUT("PDM1L"),
1512
+
SND_SOC_DAPM_OUTPUT("PDM1R"),
1513
+
SND_SOC_DAPM_OUTPUT("SPOL"),
1514
+
SND_SOC_DAPM_OUTPUT("SPOR"),
1515
+
};
1516
+
1517
+
static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
1518
+
{ "IN1P", NULL, "LDO2" },
1519
+
{ "IN2P", NULL, "LDO2" },
1520
+
1521
+
{ "DMIC1", NULL, "DMIC L1" },
1522
+
{ "DMIC1", NULL, "DMIC R1" },
1523
+
{ "DMIC2", NULL, "DMIC L2" },
1524
+
{ "DMIC2", NULL, "DMIC R2" },
1525
+
1526
+
{ "BST1", NULL, "IN1P" },
1527
+
{ "BST1", NULL, "IN1N" },
1528
+
{ "BST1", NULL, "JD Power" },
1529
+
{ "BST1", NULL, "Mic Det Power" },
1530
+
{ "BST2", NULL, "IN2P" },
1531
+
{ "BST2", NULL, "IN2N" },
1532
+
1533
+
{ "INL VOL", NULL, "IN2P" },
1534
+
{ "INR VOL", NULL, "IN2N" },
1535
+
1536
+
{ "RECMIXL", "HPOL Switch", "HPOL" },
1537
+
{ "RECMIXL", "INL Switch", "INL VOL" },
1538
+
{ "RECMIXL", "BST2 Switch", "BST2" },
1539
+
{ "RECMIXL", "BST1 Switch", "BST1" },
1540
+
{ "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
1541
+
1542
+
{ "RECMIXR", "HPOR Switch", "HPOR" },
1543
+
{ "RECMIXR", "INR Switch", "INR VOL" },
1544
+
{ "RECMIXR", "BST2 Switch", "BST2" },
1545
+
{ "RECMIXR", "BST1 Switch", "BST1" },
1546
+
{ "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
1547
+
1548
+
{ "ADC L", NULL, "RECMIXL" },
1549
+
{ "ADC L", NULL, "ADC L power" },
1550
+
{ "ADC R", NULL, "RECMIXR" },
1551
+
{ "ADC R", NULL, "ADC R power" },
1552
+
1553
+
{"DMIC L1", NULL, "DMIC CLK"},
1554
+
{"DMIC L1", NULL, "DMIC1 Power"},
1555
+
{"DMIC R1", NULL, "DMIC CLK"},
1556
+
{"DMIC R1", NULL, "DMIC1 Power"},
1557
+
{"DMIC L2", NULL, "DMIC CLK"},
1558
+
{"DMIC L2", NULL, "DMIC2 Power"},
1559
+
{"DMIC R2", NULL, "DMIC CLK"},
1560
+
{"DMIC R2", NULL, "DMIC2 Power"},
1561
+
1562
+
{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1563
+
{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
1564
+
1565
+
{ "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1566
+
{ "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
1567
+
1568
+
{ "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1569
+
{ "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
1570
+
1571
+
{ "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1572
+
{ "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1573
+
{ "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
1574
+
{ "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1575
+
1576
+
{ "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
1577
+
{ "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1578
+
{ "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1579
+
{ "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1580
+
1581
+
{ "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1582
+
{ "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1583
+
{ "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1584
+
{ "Mono ADC L1 Mux", "ADC", "ADC L" },
1585
+
1586
+
{ "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1587
+
{ "Mono ADC R1 Mux", "ADC", "ADC R" },
1588
+
{ "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1589
+
{ "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1590
+
1591
+
{ "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1592
+
{ "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1593
+
{ "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1594
+
{ "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1595
+
1596
+
{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1597
+
{ "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
1598
+
{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1599
+
1600
+
{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1601
+
{ "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
1602
+
{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1603
+
1604
+
{ "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1605
+
{ "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1606
+
{ "Mono ADC MIXL", NULL, "adc mono left filter" },
1607
+
{ "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
1608
+
1609
+
{ "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1610
+
{ "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1611
+
{ "Mono ADC MIXR", NULL, "adc mono right filter" },
1612
+
{ "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
1613
+
1614
+
{ "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
1615
+
{ "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
1616
+
{ "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
1617
+
1618
+
{ "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
1619
+
{ "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
1620
+
{ "IF_ADC2", NULL, "Mono ADC MIXL" },
1621
+
{ "IF_ADC2", NULL, "Mono ADC MIXR" },
1622
+
{ "VAD_ADC", NULL, "VAD ADC Mux" },
1623
+
1624
+
{ "IF1 ADC Mux", "IF_ADC1", "IF_ADC1" },
1625
+
{ "IF1 ADC Mux", "IF_ADC2", "IF_ADC2" },
1626
+
{ "IF1 ADC Mux", "VAD_ADC", "VAD_ADC" },
1627
+
1628
+
{ "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
1629
+
{ "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
1630
+
{ "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
1631
+
1632
+
{ "IF1 ADC", NULL, "I2S1" },
1633
+
{ "IF1 ADC", NULL, "IF1 ADC Mux" },
1634
+
{ "IF2 ADC", NULL, "I2S2" },
1635
+
{ "IF2 ADC", NULL, "IF2 ADC Mux" },
1636
+
1637
+
{ "AIF1TX", NULL, "IF1 ADC" },
1638
+
{ "AIF1TX", NULL, "IF2 ADC" },
1639
+
{ "AIF2TX", NULL, "IF2 ADC" },
1640
+
1641
+
{ "IF1 DAC1", NULL, "AIF1RX" },
1642
+
{ "IF1 DAC2", NULL, "AIF1RX" },
1643
+
{ "IF2 DAC", NULL, "AIF2RX" },
1644
+
1645
+
{ "IF1 DAC1", NULL, "I2S1" },
1646
+
{ "IF1 DAC2", NULL, "I2S1" },
1647
+
{ "IF2 DAC", NULL, "I2S2" },
1648
+
1649
+
{ "IF1 DAC2 L", NULL, "IF1 DAC2" },
1650
+
{ "IF1 DAC2 R", NULL, "IF1 DAC2" },
1651
+
{ "IF1 DAC1 L", NULL, "IF1 DAC1" },
1652
+
{ "IF1 DAC1 R", NULL, "IF1 DAC1" },
1653
+
{ "IF2 DAC L", NULL, "IF2 DAC" },
1654
+
{ "IF2 DAC R", NULL, "IF2 DAC" },
1655
+
1656
+
{ "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
1657
+
{ "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1658
+
1659
+
{ "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
1660
+
{ "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
1661
+
1662
+
{ "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
1663
+
{ "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
1664
+
{ "DAC1 MIXL", NULL, "dac stereo1 filter" },
1665
+
{ "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
1666
+
{ "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
1667
+
{ "DAC1 MIXR", NULL, "dac stereo1 filter" },
1668
+
1669
+
{ "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
1670
+
{ "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
1671
+
{ "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
1672
+
{ "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
1673
+
{ "DAC L2 Volume", NULL, "DAC L2 Mux" },
1674
+
{ "DAC L2 Volume", NULL, "dac mono left filter" },
1675
+
1676
+
{ "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
1677
+
{ "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
1678
+
{ "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
1679
+
{ "DAC R2 Mux", "Haptic", "Haptic Generator" },
1680
+
{ "DAC R2 Volume", NULL, "DAC R2 Mux" },
1681
+
{ "DAC R2 Volume", NULL, "dac mono right filter" },
1682
+
1683
+
{ "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1684
+
{ "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
1685
+
{ "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1686
+
{ "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
1687
+
{ "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1688
+
{ "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
1689
+
{ "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1690
+
{ "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
1691
+
1692
+
{ "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1693
+
{ "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1694
+
{ "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1695
+
{ "Mono DAC MIXL", NULL, "dac mono left filter" },
1696
+
{ "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1697
+
{ "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1698
+
{ "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1699
+
{ "Mono DAC MIXR", NULL, "dac mono right filter" },
1700
+
1701
+
{ "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
1702
+
{ "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1703
+
{ "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1704
+
{ "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
1705
+
{ "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1706
+
{ "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1707
+
1708
+
{ "DAC L1", NULL, "Stereo DAC MIXL" },
1709
+
{ "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1710
+
{ "DAC R1", NULL, "Stereo DAC MIXR" },
1711
+
{ "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1712
+
{ "DAC L2", NULL, "Mono DAC MIXL" },
1713
+
{ "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1714
+
{ "DAC R2", NULL, "Mono DAC MIXR" },
1715
+
{ "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
1716
+
1717
+
{ "SPK MIXL", "BST1 Switch", "BST1" },
1718
+
{ "SPK MIXL", "INL Switch", "INL VOL" },
1719
+
{ "SPK MIXL", "DAC L1 Switch", "DAC L1" },
1720
+
{ "SPK MIXL", "DAC L2 Switch", "DAC L2" },
1721
+
{ "SPK MIXR", "BST2 Switch", "BST2" },
1722
+
{ "SPK MIXR", "INR Switch", "INR VOL" },
1723
+
{ "SPK MIXR", "DAC R1 Switch", "DAC R1" },
1724
+
{ "SPK MIXR", "DAC R2 Switch", "DAC R2" },
1725
+
1726
+
{ "OUT MIXL", "BST1 Switch", "BST1" },
1727
+
{ "OUT MIXL", "INL Switch", "INL VOL" },
1728
+
{ "OUT MIXL", "DAC L2 Switch", "DAC L2" },
1729
+
{ "OUT MIXL", "DAC L1 Switch", "DAC L1" },
1730
+
1731
+
{ "OUT MIXR", "BST2 Switch", "BST2" },
1732
+
{ "OUT MIXR", "INR Switch", "INR VOL" },
1733
+
{ "OUT MIXR", "DAC R2 Switch", "DAC R2" },
1734
+
{ "OUT MIXR", "DAC R1 Switch", "DAC R1" },
1735
+
1736
+
{ "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
1737
+
{ "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
1738
+
{ "HPOVOL MIXL", "INL Switch", "INL VOL" },
1739
+
{ "HPOVOL MIXL", "BST1 Switch", "BST1" },
1740
+
{ "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
1741
+
{ "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
1742
+
{ "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
1743
+
{ "HPOVOL MIXR", "INR Switch", "INR VOL" },
1744
+
{ "HPOVOL MIXR", "BST2 Switch", "BST2" },
1745
+
{ "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
1746
+
1747
+
{ "DAC 2", NULL, "DAC L2" },
1748
+
{ "DAC 2", NULL, "DAC R2" },
1749
+
{ "DAC 1", NULL, "DAC L1" },
1750
+
{ "DAC 1", NULL, "DAC R1" },
1751
+
{ "HPOVOL L", "Switch", "HPOVOL MIXL" },
1752
+
{ "HPOVOL R", "Switch", "HPOVOL MIXR" },
1753
+
{ "HPOVOL", NULL, "HPOVOL L" },
1754
+
{ "HPOVOL", NULL, "HPOVOL R" },
1755
+
{ "HPO MIX", "DAC1 Switch", "DAC 1" },
1756
+
{ "HPO MIX", "HPVOL Switch", "HPOVOL" },
1757
+
1758
+
{ "SPKVOL L", "Switch", "SPK MIXL" },
1759
+
{ "SPKVOL R", "Switch", "SPK MIXR" },
1760
+
1761
+
{ "SPOL MIX", "DAC R1 Switch", "DAC R1" },
1762
+
{ "SPOL MIX", "DAC L1 Switch", "DAC L1" },
1763
+
{ "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
1764
+
{ "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
1765
+
{ "SPOR MIX", "DAC R1 Switch", "DAC R1" },
1766
+
{ "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
1767
+
1768
+
{ "LOUT MIX", "DAC L1 Switch", "DAC L1" },
1769
+
{ "LOUT MIX", "DAC R1 Switch", "DAC R1" },
1770
+
{ "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
1771
+
{ "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
1772
+
1773
+
{ "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
1774
+
{ "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
1775
+
{ "PDM1 L Mux", NULL, "PDM1 Power" },
1776
+
{ "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
1777
+
{ "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
1778
+
{ "PDM1 R Mux", NULL, "PDM1 Power" },
1779
+
1780
+
{ "HP amp", NULL, "HPO MIX" },
1781
+
{ "HP amp", NULL, "JD Power" },
1782
+
{ "HP amp", NULL, "Mic Det Power" },
1783
+
{ "HP amp", NULL, "LDO2" },
1784
+
{ "HPOL", NULL, "HP amp" },
1785
+
{ "HPOR", NULL, "HP amp" },
1786
+
1787
+
{ "LOUT amp", NULL, "LOUT MIX" },
1788
+
{ "LOUTL", NULL, "LOUT amp" },
1789
+
{ "LOUTR", NULL, "LOUT amp" },
1790
+
1791
+
{ "PDM1 L", "Switch", "PDM1 L Mux" },
1792
+
{ "PDM1 R", "Switch", "PDM1 R Mux" },
1793
+
1794
+
{ "PDM1L", NULL, "PDM1 L" },
1795
+
{ "PDM1R", NULL, "PDM1 R" },
1796
+
1797
+
{ "SPK amp", NULL, "SPOL MIX" },
1798
+
{ "SPK amp", NULL, "SPOR MIX" },
1799
+
{ "SPOL", NULL, "SPK amp" },
1800
+
{ "SPOR", NULL, "SPK amp" },
1801
+
};
1802
+
1803
+
static int get_clk_info(int sclk, int rate)
1804
+
{
1805
+
int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1806
+
1807
+
if (sclk <= 0 || rate <= 0)
1808
+
return -EINVAL;
1809
+
1810
+
rate = rate << 8;
1811
+
for (i = 0; i < ARRAY_SIZE(pd); i++)
1812
+
if (sclk == rate * pd[i])
1813
+
return i;
1814
+
1815
+
return -EINVAL;
1816
+
}
1817
+
1818
+
static int rt5645_hw_params(struct snd_pcm_substream *substream,
1819
+
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1820
+
{
1821
+
struct snd_soc_codec *codec = dai->codec;
1822
+
struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1823
+
unsigned int val_len = 0, val_clk, mask_clk;
1824
+
int pre_div, bclk_ms, frame_size;
1825
+
1826
+
rt5645->lrck[dai->id] = params_rate(params);
1827
+
pre_div = get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
1828
+
if (pre_div < 0) {
1829
+
dev_err(codec->dev, "Unsupported clock setting\n");
1830
+
return -EINVAL;
1831
+
}
1832
+
frame_size = snd_soc_params_to_frame_size(params);
1833
+
if (frame_size < 0) {
1834
+
dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
1835
+
return -EINVAL;
1836
+
}
1837
+
bclk_ms = frame_size > 32;
1838
+
rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
1839
+
1840
+
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1841
+
rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
1842
+
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1843
+
bclk_ms, pre_div, dai->id);
1844
+
1845
+
switch (params_width(params)) {
1846
+
case 16:
1847
+
break;
1848
+
case 20:
1849
+
val_len |= RT5645_I2S_DL_20;
1850
+
break;
1851
+
case 24:
1852
+
val_len |= RT5645_I2S_DL_24;
1853
+
break;
1854
+
case 8:
1855
+
val_len |= RT5645_I2S_DL_8;
1856
+
break;
1857
+
default:
1858
+
return -EINVAL;
1859
+
}
1860
+
1861
+
switch (dai->id) {
1862
+
case RT5645_AIF1:
1863
+
mask_clk = RT5645_I2S_BCLK_MS1_MASK | RT5645_I2S_PD1_MASK;
1864
+
val_clk = bclk_ms << RT5645_I2S_BCLK_MS1_SFT |
1865
+
pre_div << RT5645_I2S_PD1_SFT;
1866
+
snd_soc_update_bits(codec, RT5645_I2S1_SDP,
1867
+
RT5645_I2S_DL_MASK, val_len);
1868
+
snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
1869
+
break;
1870
+
case RT5645_AIF2:
1871
+
mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
1872
+
val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
1873
+
pre_div << RT5645_I2S_PD2_SFT;
1874
+
snd_soc_update_bits(codec, RT5645_I2S2_SDP,
1875
+
RT5645_I2S_DL_MASK, val_len);
1876
+
snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
1877
+
break;
1878
+
default:
1879
+
dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
1880
+
return -EINVAL;
1881
+
}
1882
+
1883
+
return 0;
1884
+
}
1885
+
1886
+
static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1887
+
{
1888
+
struct snd_soc_codec *codec = dai->codec;
1889
+
struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1890
+
unsigned int reg_val = 0;
1891
+
1892
+
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1893
+
case SND_SOC_DAIFMT_CBM_CFM:
1894
+
rt5645->master[dai->id] = 1;
1895
+
break;
1896
+
case SND_SOC_DAIFMT_CBS_CFS:
1897
+
reg_val |= RT5645_I2S_MS_S;
1898
+
rt5645->master[dai->id] = 0;
1899
+
break;
1900
+
default:
1901
+
return -EINVAL;
1902
+
}
1903
+
1904
+
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1905
+
case SND_SOC_DAIFMT_NB_NF:
1906
+
break;
1907
+
case SND_SOC_DAIFMT_IB_NF:
1908
+
reg_val |= RT5645_I2S_BP_INV;
1909
+
break;
1910
+
default:
1911
+
return -EINVAL;
1912
+
}
1913
+
1914
+
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1915
+
case SND_SOC_DAIFMT_I2S:
1916
+
break;
1917
+
case SND_SOC_DAIFMT_LEFT_J:
1918
+
reg_val |= RT5645_I2S_DF_LEFT;
1919
+
break;
1920
+
case SND_SOC_DAIFMT_DSP_A:
1921
+
reg_val |= RT5645_I2S_DF_PCM_A;
1922
+
break;
1923
+
case SND_SOC_DAIFMT_DSP_B:
1924
+
reg_val |= RT5645_I2S_DF_PCM_B;
1925
+
break;
1926
+
default:
1927
+
return -EINVAL;
1928
+
}
1929
+
switch (dai->id) {
1930
+
case RT5645_AIF1:
1931
+
snd_soc_update_bits(codec, RT5645_I2S1_SDP,
1932
+
RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
1933
+
RT5645_I2S_DF_MASK, reg_val);
1934
+
break;
1935
+
case RT5645_AIF2:
1936
+
snd_soc_update_bits(codec, RT5645_I2S2_SDP,
1937
+
RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
1938
+
RT5645_I2S_DF_MASK, reg_val);
1939
+
break;
1940
+
default:
1941
+
dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
1942
+
return -EINVAL;
1943
+
}
1944
+
return 0;
1945
+
}
1946
+
1947
+
static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
1948
+
int clk_id, unsigned int freq, int dir)
1949
+
{
1950
+
struct snd_soc_codec *codec = dai->codec;
1951
+
struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1952
+
unsigned int reg_val = 0;
1953
+
1954
+
if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
1955
+
return 0;
1956
+
1957
+
switch (clk_id) {
1958
+
case RT5645_SCLK_S_MCLK:
1959
+
reg_val |= RT5645_SCLK_SRC_MCLK;
1960
+
break;
1961
+
case RT5645_SCLK_S_PLL1:
1962
+
reg_val |= RT5645_SCLK_SRC_PLL1;
1963
+
break;
1964
+
case RT5645_SCLK_S_RCCLK:
1965
+
reg_val |= RT5645_SCLK_SRC_RCCLK;
1966
+
break;
1967
+
default:
1968
+
dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
1969
+
return -EINVAL;
1970
+
}
1971
+
snd_soc_update_bits(codec, RT5645_GLB_CLK,
1972
+
RT5645_SCLK_SRC_MASK, reg_val);
1973
+
rt5645->sysclk = freq;
1974
+
rt5645->sysclk_src = clk_id;
1975
+
1976
+
dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1977
+
1978
+
return 0;
1979
+
}
1980
+
1981
+
/**
1982
+
* rt5645_pll_calc - Calcualte PLL M/N/K code.
1983
+
* @freq_in: external clock provided to codec.
1984
+
* @freq_out: target clock which codec works on.
1985
+
* @pll_code: Pointer to structure with M, N, K and bypass flag.
1986
+
*
1987
+
* Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
1988
+
* which make calculation more efficiently.
1989
+
*
1990
+
* Returns 0 for success or negative error code.
1991
+
*/
1992
+
static int rt5645_pll_calc(const unsigned int freq_in,
1993
+
const unsigned int freq_out, struct rt5645_pll_code *pll_code)
1994
+
{
1995
+
int max_n = RT5645_PLL_N_MAX, max_m = RT5645_PLL_M_MAX;
1996
+
int k, n = 0, m = 0, red, n_t, m_t, pll_out, in_t, out_t;
1997
+
int red_t = abs(freq_out - freq_in);
1998
+
bool bypass = false;
1999
+
2000
+
if (RT5645_PLL_INP_MAX < freq_in || RT5645_PLL_INP_MIN > freq_in)
2001
+
return -EINVAL;
2002
+
2003
+
k = 100000000 / freq_out - 2;
2004
+
if (k > RT5645_PLL_K_MAX)
2005
+
k = RT5645_PLL_K_MAX;
2006
+
for (n_t = 0; n_t <= max_n; n_t++) {
2007
+
in_t = freq_in / (k + 2);
2008
+
pll_out = freq_out / (n_t + 2);
2009
+
if (in_t < 0)
2010
+
continue;
2011
+
if (in_t == pll_out) {
2012
+
bypass = true;
2013
+
n = n_t;
2014
+
goto code_find;
2015
+
}
2016
+
red = abs(in_t - pll_out);
2017
+
if (red < red_t) {
2018
+
bypass = true;
2019
+
n = n_t;
2020
+
m = m_t;
2021
+
if (red == 0)
2022
+
goto code_find;
2023
+
red_t = red;
2024
+
}
2025
+
for (m_t = 0; m_t <= max_m; m_t++) {
2026
+
out_t = in_t / (m_t + 2);
2027
+
red = abs(out_t - pll_out);
2028
+
if (red < red_t) {
2029
+
bypass = false;
2030
+
n = n_t;
2031
+
m = m_t;
2032
+
if (red == 0)
2033
+
goto code_find;
2034
+
red_t = red;
2035
+
}
2036
+
}
2037
+
}
2038
+
pr_debug("Only get approximation about PLL\n");
2039
+
2040
+
code_find:
2041
+
2042
+
pll_code->m_bp = bypass;
2043
+
pll_code->m_code = m;
2044
+
pll_code->n_code = n;
2045
+
pll_code->k_code = k;
2046
+
return 0;
2047
+
}
2048
+
2049
+
static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2050
+
unsigned int freq_in, unsigned int freq_out)
2051
+
{
2052
+
struct snd_soc_codec *codec = dai->codec;
2053
+
struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2054
+
struct rt5645_pll_code pll_code;
2055
+
int ret;
2056
+
2057
+
if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2058
+
freq_out == rt5645->pll_out)
2059
+
return 0;
2060
+
2061
+
if (!freq_in || !freq_out) {
2062
+
dev_dbg(codec->dev, "PLL disabled\n");
2063
+
2064
+
rt5645->pll_in = 0;
2065
+
rt5645->pll_out = 0;
2066
+
snd_soc_update_bits(codec, RT5645_GLB_CLK,
2067
+
RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2068
+
return 0;
2069
+
}
2070
+
2071
+
switch (source) {
2072
+
case RT5645_PLL1_S_MCLK:
2073
+
snd_soc_update_bits(codec, RT5645_GLB_CLK,
2074
+
RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2075
+
break;
2076
+
case RT5645_PLL1_S_BCLK1:
2077
+
case RT5645_PLL1_S_BCLK2:
2078
+
switch (dai->id) {
2079
+
case RT5645_AIF1:
2080
+
snd_soc_update_bits(codec, RT5645_GLB_CLK,
2081
+
RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2082
+
break;
2083
+
case RT5645_AIF2:
2084
+
snd_soc_update_bits(codec, RT5645_GLB_CLK,
2085
+
RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2086
+
break;
2087
+
default:
2088
+
dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2089
+
return -EINVAL;
2090
+
}
2091
+
break;
2092
+
default:
2093
+
dev_err(codec->dev, "Unknown PLL source %d\n", source);
2094
+
return -EINVAL;
2095
+
}
2096
+
2097
+
ret = rt5645_pll_calc(freq_in, freq_out, &pll_code);
2098
+
if (ret < 0) {
2099
+
dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2100
+
return ret;
2101
+
}
2102
+
2103
+
dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2104
+
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2105
+
pll_code.n_code, pll_code.k_code);
2106
+
2107
+
snd_soc_write(codec, RT5645_PLL_CTRL1,
2108
+
pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2109
+
snd_soc_write(codec, RT5645_PLL_CTRL2,
2110
+
(pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2111
+
pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2112
+
2113
+
rt5645->pll_in = freq_in;
2114
+
rt5645->pll_out = freq_out;
2115
+
rt5645->pll_src = source;
2116
+
2117
+
return 0;
2118
+
}
2119
+
2120
+
static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2121
+
unsigned int rx_mask, int slots, int slot_width)
2122
+
{
2123
+
struct snd_soc_codec *codec = dai->codec;
2124
+
unsigned int val = 0;
2125
+
2126
+
if (rx_mask || tx_mask)
2127
+
val |= (1 << 14);
2128
+
2129
+
switch (slots) {
2130
+
case 4:
2131
+
val |= (1 << 12);
2132
+
break;
2133
+
case 6:
2134
+
val |= (2 << 12);
2135
+
break;
2136
+
case 8:
2137
+
val |= (3 << 12);
2138
+
break;
2139
+
case 2:
2140
+
default:
2141
+
break;
2142
+
}
2143
+
2144
+
switch (slot_width) {
2145
+
case 20:
2146
+
val |= (1 << 10);
2147
+
break;
2148
+
case 24:
2149
+
val |= (2 << 10);
2150
+
break;
2151
+
case 32:
2152
+
val |= (3 << 10);
2153
+
break;
2154
+
case 16:
2155
+
default:
2156
+
break;
2157
+
}
2158
+
2159
+
snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, 0x7c00, val);
2160
+
2161
+
return 0;
2162
+
}
2163
+
2164
+
static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2165
+
enum snd_soc_bias_level level)
2166
+
{
2167
+
switch (level) {
2168
+
case SND_SOC_BIAS_STANDBY:
2169
+
if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
2170
+
snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2171
+
RT5645_PWR_VREF1 | RT5645_PWR_MB |
2172
+
RT5645_PWR_BG | RT5645_PWR_VREF2,
2173
+
RT5645_PWR_VREF1 | RT5645_PWR_MB |
2174
+
RT5645_PWR_BG | RT5645_PWR_VREF2);
2175
+
mdelay(10);
2176
+
snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2177
+
RT5645_PWR_FV1 | RT5645_PWR_FV2,
2178
+
RT5645_PWR_FV1 | RT5645_PWR_FV2);
2179
+
snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2180
+
RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2181
+
}
2182
+
break;
2183
+
2184
+
case SND_SOC_BIAS_OFF:
2185
+
snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
2186
+
snd_soc_write(codec, RT5645_GEN_CTRL1, 0x0128);
2187
+
snd_soc_write(codec, RT5645_PWR_DIG1, 0x0000);
2188
+
snd_soc_write(codec, RT5645_PWR_DIG2, 0x0000);
2189
+
snd_soc_write(codec, RT5645_PWR_VOL, 0x0000);
2190
+
snd_soc_write(codec, RT5645_PWR_MIXER, 0x0000);
2191
+
snd_soc_write(codec, RT5645_PWR_ANLG1, 0x0000);
2192
+
snd_soc_write(codec, RT5645_PWR_ANLG2, 0x0000);
2193
+
break;
2194
+
2195
+
default:
2196
+
break;
2197
+
}
2198
+
codec->dapm.bias_level = level;
2199
+
2200
+
return 0;
2201
+
}
2202
+
2203
+
static int rt5645_probe(struct snd_soc_codec *codec)
2204
+
{
2205
+
struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2206
+
2207
+
rt5645->codec = codec;
2208
+
2209
+
rt5645_set_bias_level(codec, SND_SOC_BIAS_OFF);
2210
+
2211
+
snd_soc_update_bits(codec, RT5645_CHARGE_PUMP, 0x0300, 0x0200);
2212
+
2213
+
return 0;
2214
+
}
2215
+
2216
+
static int rt5645_remove(struct snd_soc_codec *codec)
2217
+
{
2218
+
rt5645_reset(codec);
2219
+
return 0;
2220
+
}
2221
+
2222
+
#ifdef CONFIG_PM
2223
+
static int rt5645_suspend(struct snd_soc_codec *codec)
2224
+
{
2225
+
struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2226
+
2227
+
regcache_cache_only(rt5645->regmap, true);
2228
+
regcache_mark_dirty(rt5645->regmap);
2229
+
2230
+
return 0;
2231
+
}
2232
+
2233
+
static int rt5645_resume(struct snd_soc_codec *codec)
2234
+
{
2235
+
struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2236
+
2237
+
regcache_cache_only(rt5645->regmap, false);
2238
+
regcache_sync(rt5645->regmap);
2239
+
2240
+
return 0;
2241
+
}
2242
+
#else
2243
+
#define rt5645_suspend NULL
2244
+
#define rt5645_resume NULL
2245
+
#endif
2246
+
2247
+
#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2248
+
#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2249
+
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2250
+
2251
+
static struct snd_soc_dai_ops rt5645_aif_dai_ops = {
2252
+
.hw_params = rt5645_hw_params,
2253
+
.set_fmt = rt5645_set_dai_fmt,
2254
+
.set_sysclk = rt5645_set_dai_sysclk,
2255
+
.set_tdm_slot = rt5645_set_tdm_slot,
2256
+
.set_pll = rt5645_set_dai_pll,
2257
+
};
2258
+
2259
+
static struct snd_soc_dai_driver rt5645_dai[] = {
2260
+
{
2261
+
.name = "rt5645-aif1",
2262
+
.id = RT5645_AIF1,
2263
+
.playback = {
2264
+
.stream_name = "AIF1 Playback",
2265
+
.channels_min = 1,
2266
+
.channels_max = 2,
2267
+
.rates = RT5645_STEREO_RATES,
2268
+
.formats = RT5645_FORMATS,
2269
+
},
2270
+
.capture = {
2271
+
.stream_name = "AIF1 Capture",
2272
+
.channels_min = 1,
2273
+
.channels_max = 2,
2274
+
.rates = RT5645_STEREO_RATES,
2275
+
.formats = RT5645_FORMATS,
2276
+
},
2277
+
.ops = &rt5645_aif_dai_ops,
2278
+
},
2279
+
{
2280
+
.name = "rt5645-aif2",
2281
+
.id = RT5645_AIF2,
2282
+
.playback = {
2283
+
.stream_name = "AIF2 Playback",
2284
+
.channels_min = 1,
2285
+
.channels_max = 2,
2286
+
.rates = RT5645_STEREO_RATES,
2287
+
.formats = RT5645_FORMATS,
2288
+
},
2289
+
.capture = {
2290
+
.stream_name = "AIF2 Capture",
2291
+
.channels_min = 1,
2292
+
.channels_max = 2,
2293
+
.rates = RT5645_STEREO_RATES,
2294
+
.formats = RT5645_FORMATS,
2295
+
},
2296
+
.ops = &rt5645_aif_dai_ops,
2297
+
},
2298
+
};
2299
+
2300
+
static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
2301
+
.probe = rt5645_probe,
2302
+
.remove = rt5645_remove,
2303
+
.suspend = rt5645_suspend,
2304
+
.resume = rt5645_resume,
2305
+
.set_bias_level = rt5645_set_bias_level,
2306
+
.idle_bias_off = true,
2307
+
.controls = rt5645_snd_controls,
2308
+
.num_controls = ARRAY_SIZE(rt5645_snd_controls),
2309
+
.dapm_widgets = rt5645_dapm_widgets,
2310
+
.num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
2311
+
.dapm_routes = rt5645_dapm_routes,
2312
+
.num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
2313
+
};
2314
+
2315
+
static const struct regmap_config rt5645_regmap = {
2316
+
.reg_bits = 8,
2317
+
.val_bits = 16,
2318
+
2319
+
.max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
2320
+
RT5645_PR_SPACING),
2321
+
.volatile_reg = rt5645_volatile_register,
2322
+
.readable_reg = rt5645_readable_register,
2323
+
2324
+
.cache_type = REGCACHE_RBTREE,
2325
+
.reg_defaults = rt5645_reg,
2326
+
.num_reg_defaults = ARRAY_SIZE(rt5645_reg),
2327
+
.ranges = rt5645_ranges,
2328
+
.num_ranges = ARRAY_SIZE(rt5645_ranges),
2329
+
};
2330
+
2331
+
static const struct i2c_device_id rt5645_i2c_id[] = {
2332
+
{ "rt5645", 0 },
2333
+
{ }
2334
+
};
2335
+
MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
2336
+
2337
+
static int rt5645_i2c_probe(struct i2c_client *i2c,
2338
+
const struct i2c_device_id *id)
2339
+
{
2340
+
struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
2341
+
struct rt5645_priv *rt5645;
2342
+
int ret;
2343
+
unsigned int val;
2344
+
2345
+
rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
2346
+
GFP_KERNEL);
2347
+
if (rt5645 == NULL)
2348
+
return -ENOMEM;
2349
+
2350
+
i2c_set_clientdata(i2c, rt5645);
2351
+
2352
+
if (pdata)
2353
+
rt5645->pdata = *pdata;
2354
+
2355
+
rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
2356
+
if (IS_ERR(rt5645->regmap)) {
2357
+
ret = PTR_ERR(rt5645->regmap);
2358
+
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2359
+
ret);
2360
+
return ret;
2361
+
}
2362
+
2363
+
regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
2364
+
if (val != RT5645_DEVICE_ID) {
2365
+
dev_err(&i2c->dev,
2366
+
"Device with ID register %x is not rt5645\n", val);
2367
+
return -ENODEV;
2368
+
}
2369
+
2370
+
regmap_write(rt5645->regmap, RT5645_RESET, 0);
2371
+
2372
+
ret = regmap_register_patch(rt5645->regmap, init_list,
2373
+
ARRAY_SIZE(init_list));
2374
+
if (ret != 0)
2375
+
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2376
+
2377
+
if (rt5645->pdata.in2_diff)
2378
+
regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
2379
+
RT5645_IN_DF2, RT5645_IN_DF2);
2380
+
2381
+
if (rt5645->pdata.dmic_en) {
2382
+
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2383
+
RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
2384
+
2385
+
switch (rt5645->pdata.dmic1_data_pin) {
2386
+
case RT5645_DMIC_DATA_IN2N:
2387
+
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2388
+
RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
2389
+
break;
2390
+
2391
+
case RT5645_DMIC_DATA_GPIO5:
2392
+
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2393
+
RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
2394
+
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2395
+
RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
2396
+
break;
2397
+
2398
+
case RT5645_DMIC_DATA_GPIO11:
2399
+
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2400
+
RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
2401
+
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2402
+
RT5645_GP11_PIN_MASK,
2403
+
RT5645_GP11_PIN_DMIC1_SDA);
2404
+
break;
2405
+
2406
+
default:
2407
+
break;
2408
+
}
2409
+
2410
+
switch (rt5645->pdata.dmic2_data_pin) {
2411
+
case RT5645_DMIC_DATA_IN2P:
2412
+
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2413
+
RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
2414
+
break;
2415
+
2416
+
case RT5645_DMIC_DATA_GPIO6:
2417
+
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2418
+
RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
2419
+
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2420
+
RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
2421
+
break;
2422
+
2423
+
case RT5645_DMIC_DATA_GPIO10:
2424
+
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2425
+
RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
2426
+
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2427
+
RT5645_GP10_PIN_MASK,
2428
+
RT5645_GP10_PIN_DMIC2_SDA);
2429
+
break;
2430
+
2431
+
case RT5645_DMIC_DATA_GPIO12:
2432
+
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2433
+
RT5645_DMIC_1_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
2434
+
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2435
+
RT5645_GP12_PIN_MASK,
2436
+
RT5645_GP12_PIN_DMIC2_SDA);
2437
+
break;
2438
+
2439
+
default:
2440
+
break;
2441
+
}
2442
+
2443
+
}
2444
+
2445
+
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
2446
+
rt5645_dai, ARRAY_SIZE(rt5645_dai));
2447
+
if (ret < 0)
2448
+
goto err;
2449
+
2450
+
return 0;
2451
+
err:
2452
+
return ret;
2453
+
}
2454
+
2455
+
static int rt5645_i2c_remove(struct i2c_client *i2c)
2456
+
{
2457
+
snd_soc_unregister_codec(&i2c->dev);
2458
+
2459
+
return 0;
2460
+
}
2461
+
2462
+
static struct i2c_driver rt5645_i2c_driver = {
2463
+
.driver = {
2464
+
.name = "rt5645",
2465
+
.owner = THIS_MODULE,
2466
+
},
2467
+
.probe = rt5645_i2c_probe,
2468
+
.remove = rt5645_i2c_remove,
2469
+
.id_table = rt5645_i2c_id,
2470
+
};
2471
+
module_i2c_driver(rt5645_i2c_driver);
2472
+
2473
+
MODULE_DESCRIPTION("ASoC RT5645 driver");
2474
+
MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2475
+
MODULE_LICENSE("GPL v2");
+2188
sound/soc/codecs/rt5645.h
+2188
sound/soc/codecs/rt5645.h
···
1
+
/*
2
+
* rt5645.h -- RT5645 ALSA SoC audio driver
3
+
*
4
+
* Copyright 2013 Realtek Microelectronics
5
+
* Author: Bard Liao <bardliao@realtek.com>
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
10
+
*/
11
+
12
+
#ifndef __RT5645_H__
13
+
#define __RT5645_H__
14
+
15
+
#include <sound/rt5645.h>
16
+
17
+
/* Info */
18
+
#define RT5645_RESET 0x00
19
+
#define RT5645_VENDOR_ID 0xfd
20
+
#define RT5645_VENDOR_ID1 0xfe
21
+
#define RT5645_VENDOR_ID2 0xff
22
+
/* I/O - Output */
23
+
#define RT5645_SPK_VOL 0x01
24
+
#define RT5645_HP_VOL 0x02
25
+
#define RT5645_LOUT1 0x03
26
+
#define RT5645_LOUT_CTRL 0x05
27
+
/* I/O - Input */
28
+
#define RT5645_IN1_CTRL1 0x0a
29
+
#define RT5645_IN1_CTRL2 0x0b
30
+
#define RT5645_IN1_CTRL3 0x0c
31
+
#define RT5645_IN2_CTRL 0x0d
32
+
#define RT5645_INL1_INR1_VOL 0x0f
33
+
#define RT5645_SPK_FUNC_LIM 0x14
34
+
#define RT5645_ADJ_HPF_CTRL 0x16
35
+
/* I/O - ADC/DAC/DMIC */
36
+
#define RT5645_DAC1_DIG_VOL 0x19
37
+
#define RT5645_DAC2_DIG_VOL 0x1a
38
+
#define RT5645_DAC_CTRL 0x1b
39
+
#define RT5645_STO1_ADC_DIG_VOL 0x1c
40
+
#define RT5645_MONO_ADC_DIG_VOL 0x1d
41
+
#define RT5645_ADC_BST_VOL1 0x1e
42
+
/* Mixer - D-D */
43
+
#define RT5645_ADC_BST_VOL2 0x20
44
+
#define RT5645_STO1_ADC_MIXER 0x27
45
+
#define RT5645_MONO_ADC_MIXER 0x28
46
+
#define RT5645_AD_DA_MIXER 0x29
47
+
#define RT5645_STO_DAC_MIXER 0x2a
48
+
#define RT5645_MONO_DAC_MIXER 0x2b
49
+
#define RT5645_DIG_MIXER 0x2c
50
+
#define RT5645_DIG_INF1_DATA 0x2f
51
+
/* Mixer - PDM */
52
+
#define RT5645_PDM_OUT_CTRL 0x31
53
+
/* Mixer - ADC */
54
+
#define RT5645_REC_L1_MIXER 0x3b
55
+
#define RT5645_REC_L2_MIXER 0x3c
56
+
#define RT5645_REC_R1_MIXER 0x3d
57
+
#define RT5645_REC_R2_MIXER 0x3e
58
+
/* Mixer - DAC */
59
+
#define RT5645_HPMIXL_CTRL 0x3f
60
+
#define RT5645_HPOMIXL_CTRL 0x40
61
+
#define RT5645_HPMIXR_CTRL 0x41
62
+
#define RT5645_HPOMIXR_CTRL 0x42
63
+
#define RT5645_HPO_MIXER 0x45
64
+
#define RT5645_SPK_L_MIXER 0x46
65
+
#define RT5645_SPK_R_MIXER 0x47
66
+
#define RT5645_SPO_MIXER 0x48
67
+
#define RT5645_SPO_CLSD_RATIO 0x4a
68
+
#define RT5645_OUT_L_GAIN1 0x4d
69
+
#define RT5645_OUT_L_GAIN2 0x4e
70
+
#define RT5645_OUT_L1_MIXER 0x4f
71
+
#define RT5645_OUT_R_GAIN1 0x50
72
+
#define RT5645_OUT_R_GAIN2 0x51
73
+
#define RT5645_OUT_R1_MIXER 0x52
74
+
#define RT5645_LOUT_MIXER 0x53
75
+
/* Haptic */
76
+
#define RT5645_HAPTIC_CTRL1 0x56
77
+
#define RT5645_HAPTIC_CTRL2 0x57
78
+
#define RT5645_HAPTIC_CTRL3 0x58
79
+
#define RT5645_HAPTIC_CTRL4 0x59
80
+
#define RT5645_HAPTIC_CTRL5 0x5a
81
+
#define RT5645_HAPTIC_CTRL6 0x5b
82
+
#define RT5645_HAPTIC_CTRL7 0x5c
83
+
#define RT5645_HAPTIC_CTRL8 0x5d
84
+
#define RT5645_HAPTIC_CTRL9 0x5e
85
+
#define RT5645_HAPTIC_CTRL10 0x5f
86
+
/* Power */
87
+
#define RT5645_PWR_DIG1 0x61
88
+
#define RT5645_PWR_DIG2 0x62
89
+
#define RT5645_PWR_ANLG1 0x63
90
+
#define RT5645_PWR_ANLG2 0x64
91
+
#define RT5645_PWR_MIXER 0x65
92
+
#define RT5645_PWR_VOL 0x66
93
+
/* Private Register Control */
94
+
#define RT5645_PRIV_INDEX 0x6a
95
+
#define RT5645_PRIV_DATA 0x6c
96
+
/* Format - ADC/DAC */
97
+
#define RT5645_I2S1_SDP 0x70
98
+
#define RT5645_I2S2_SDP 0x71
99
+
#define RT5645_ADDA_CLK1 0x73
100
+
#define RT5645_ADDA_CLK2 0x74
101
+
#define RT5645_DMIC_CTRL1 0x75
102
+
#define RT5645_DMIC_CTRL2 0x76
103
+
/* Format - TDM Control */
104
+
#define RT5645_TDM_CTRL_1 0x77
105
+
#define RT5645_TDM_CTRL_2 0x78
106
+
#define RT5645_TDM_CTRL_3 0x79
107
+
108
+
/* Function - Analog */
109
+
#define RT5645_GLB_CLK 0x80
110
+
#define RT5645_PLL_CTRL1 0x81
111
+
#define RT5645_PLL_CTRL2 0x82
112
+
#define RT5645_ASRC_1 0x83
113
+
#define RT5645_ASRC_2 0x84
114
+
#define RT5645_ASRC_3 0x85
115
+
#define RT5645_ASRC_4 0x8a
116
+
#define RT5645_DEPOP_M1 0x8e
117
+
#define RT5645_DEPOP_M2 0x8f
118
+
#define RT5645_DEPOP_M3 0x90
119
+
#define RT5645_CHARGE_PUMP 0x91
120
+
#define RT5645_MICBIAS 0x93
121
+
#define RT5645_A_JD_CTRL1 0x94
122
+
#define RT5645_VAD_CTRL4 0x9d
123
+
#define RT5645_CLSD_OUT_CTRL 0xa0
124
+
/* Function - Digital */
125
+
#define RT5645_ADC_EQ_CTRL1 0xae
126
+
#define RT5645_ADC_EQ_CTRL2 0xaf
127
+
#define RT5645_EQ_CTRL1 0xb0
128
+
#define RT5645_EQ_CTRL2 0xb1
129
+
#define RT5645_ALC_CTRL_1 0xb3
130
+
#define RT5645_ALC_CTRL_2 0xb4
131
+
#define RT5645_ALC_CTRL_3 0xb5
132
+
#define RT5645_ALC_CTRL_4 0xb6
133
+
#define RT5645_ALC_CTRL_5 0xb7
134
+
#define RT5645_JD_CTRL 0xbb
135
+
#define RT5645_IRQ_CTRL1 0xbc
136
+
#define RT5645_IRQ_CTRL2 0xbd
137
+
#define RT5645_IRQ_CTRL3 0xbe
138
+
#define RT5645_INT_IRQ_ST 0xbf
139
+
#define RT5645_GPIO_CTRL1 0xc0
140
+
#define RT5645_GPIO_CTRL2 0xc1
141
+
#define RT5645_GPIO_CTRL3 0xc2
142
+
#define RT5645_BASS_BACK 0xcf
143
+
#define RT5645_MP3_PLUS1 0xd0
144
+
#define RT5645_MP3_PLUS2 0xd1
145
+
#define RT5645_ADJ_HPF1 0xd3
146
+
#define RT5645_ADJ_HPF2 0xd4
147
+
#define RT5645_HP_CALIB_AMP_DET 0xd6
148
+
#define RT5645_SV_ZCD1 0xd9
149
+
#define RT5645_SV_ZCD2 0xda
150
+
#define RT5645_IL_CMD 0xdb
151
+
#define RT5645_IL_CMD2 0xdc
152
+
#define RT5645_IL_CMD3 0xdd
153
+
#define RT5645_DRC1_HL_CTRL1 0xe7
154
+
#define RT5645_DRC2_HL_CTRL1 0xe9
155
+
#define RT5645_MUTI_DRC_CTRL1 0xea
156
+
#define RT5645_ADC_MONO_HP_CTRL1 0xec
157
+
#define RT5645_ADC_MONO_HP_CTRL2 0xed
158
+
#define RT5645_DRC2_CTRL1 0xf0
159
+
#define RT5645_DRC2_CTRL2 0xf1
160
+
#define RT5645_DRC2_CTRL3 0xf2
161
+
#define RT5645_DRC2_CTRL4 0xf3
162
+
#define RT5645_DRC2_CTRL5 0xf4
163
+
#define RT5645_JD_CTRL3 0xf8
164
+
#define RT5645_JD_CTRL4 0xf9
165
+
/* General Control */
166
+
#define RT5645_GEN_CTRL1 0xfa
167
+
#define RT5645_GEN_CTRL2 0xfb
168
+
#define RT5645_GEN_CTRL3 0xfc
169
+
170
+
171
+
/* Index of Codec Private Register definition */
172
+
#define RT5645_DIG_VOL 0x00
173
+
#define RT5645_PR_ALC_CTRL_1 0x01
174
+
#define RT5645_PR_ALC_CTRL_2 0x02
175
+
#define RT5645_PR_ALC_CTRL_3 0x03
176
+
#define RT5645_PR_ALC_CTRL_4 0x04
177
+
#define RT5645_PR_ALC_CTRL_5 0x05
178
+
#define RT5645_PR_ALC_CTRL_6 0x06
179
+
#define RT5645_BIAS_CUR1 0x12
180
+
#define RT5645_BIAS_CUR3 0x14
181
+
#define RT5645_CLSD_INT_REG1 0x1c
182
+
#define RT5645_MAMP_INT_REG2 0x37
183
+
#define RT5645_CHOP_DAC_ADC 0x3d
184
+
#define RT5645_MIXER_INT_REG 0x3f
185
+
#define RT5645_3D_SPK 0x63
186
+
#define RT5645_WND_1 0x6c
187
+
#define RT5645_WND_2 0x6d
188
+
#define RT5645_WND_3 0x6e
189
+
#define RT5645_WND_4 0x6f
190
+
#define RT5645_WND_5 0x70
191
+
#define RT5645_WND_8 0x73
192
+
#define RT5645_DIP_SPK_INF 0x75
193
+
#define RT5645_HP_DCC_INT1 0x77
194
+
#define RT5645_EQ_BW_LOP 0xa0
195
+
#define RT5645_EQ_GN_LOP 0xa1
196
+
#define RT5645_EQ_FC_BP1 0xa2
197
+
#define RT5645_EQ_BW_BP1 0xa3
198
+
#define RT5645_EQ_GN_BP1 0xa4
199
+
#define RT5645_EQ_FC_BP2 0xa5
200
+
#define RT5645_EQ_BW_BP2 0xa6
201
+
#define RT5645_EQ_GN_BP2 0xa7
202
+
#define RT5645_EQ_FC_BP3 0xa8
203
+
#define RT5645_EQ_BW_BP3 0xa9
204
+
#define RT5645_EQ_GN_BP3 0xaa
205
+
#define RT5645_EQ_FC_BP4 0xab
206
+
#define RT5645_EQ_BW_BP4 0xac
207
+
#define RT5645_EQ_GN_BP4 0xad
208
+
#define RT5645_EQ_FC_HIP1 0xae
209
+
#define RT5645_EQ_GN_HIP1 0xaf
210
+
#define RT5645_EQ_FC_HIP2 0xb0
211
+
#define RT5645_EQ_BW_HIP2 0xb1
212
+
#define RT5645_EQ_GN_HIP2 0xb2
213
+
#define RT5645_EQ_PRE_VOL 0xb3
214
+
#define RT5645_EQ_PST_VOL 0xb4
215
+
216
+
217
+
/* global definition */
218
+
#define RT5645_L_MUTE (0x1 << 15)
219
+
#define RT5645_L_MUTE_SFT 15
220
+
#define RT5645_VOL_L_MUTE (0x1 << 14)
221
+
#define RT5645_VOL_L_SFT 14
222
+
#define RT5645_R_MUTE (0x1 << 7)
223
+
#define RT5645_R_MUTE_SFT 7
224
+
#define RT5645_VOL_R_MUTE (0x1 << 6)
225
+
#define RT5645_VOL_R_SFT 6
226
+
#define RT5645_L_VOL_MASK (0x3f << 8)
227
+
#define RT5645_L_VOL_SFT 8
228
+
#define RT5645_R_VOL_MASK (0x3f)
229
+
#define RT5645_R_VOL_SFT 0
230
+
231
+
/* IN1 Control 1 (0x0a) */
232
+
#define RT5645_CBJ_BST1_MASK (0xf << 12)
233
+
#define RT5645_CBJ_BST1_SFT (12)
234
+
#define RT5645_CBJ_JD_HP_EN (0x1 << 9)
235
+
#define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
236
+
#define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7)
237
+
#define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
238
+
#define RT5645_CBJ_MIC_SEL_L (0x1 << 5)
239
+
#define RT5645_CBJ_MIC_SW (0x1 << 4)
240
+
#define RT5645_CBJ_BST1_EN (0x1 << 2)
241
+
242
+
/* IN1 Control 2 (0x0b) */
243
+
#define RT5645_CBJ_MN_JD (0x1 << 12)
244
+
#define RT5645_CAPLESS_EN (0x1 << 11)
245
+
#define RT5645_CBJ_DET_MODE (0x1 << 7)
246
+
247
+
/* IN1 Control 3 (0x0c) */
248
+
#define RT5645_CBJ_TIE_G_L (0x1 << 15)
249
+
#define RT5645_CBJ_TIE_G_R (0x1 << 14)
250
+
251
+
/* IN2 Control (0x0d) */
252
+
#define RT5645_BST_MASK1 (0xf<<12)
253
+
#define RT5645_BST_SFT1 12
254
+
#define RT5645_BST_MASK2 (0xf<<8)
255
+
#define RT5645_BST_SFT2 8
256
+
#define RT5645_IN_DF2 (0x1 << 6)
257
+
#define RT5645_IN_SFT2 6
258
+
259
+
/* INL and INR Volume Control (0x0f) */
260
+
#define RT5645_INL_SEL_MASK (0x1 << 15)
261
+
#define RT5645_INL_SEL_SFT 15
262
+
#define RT5645_INL_SEL_IN4P (0x0 << 15)
263
+
#define RT5645_INL_SEL_MONOP (0x1 << 15)
264
+
#define RT5645_INL_VOL_MASK (0x1f << 8)
265
+
#define RT5645_INL_VOL_SFT 8
266
+
#define RT5645_INR_SEL_MASK (0x1 << 7)
267
+
#define RT5645_INR_SEL_SFT 7
268
+
#define RT5645_INR_SEL_IN4N (0x0 << 7)
269
+
#define RT5645_INR_SEL_MONON (0x1 << 7)
270
+
#define RT5645_INR_VOL_MASK (0x1f)
271
+
#define RT5645_INR_VOL_SFT 0
272
+
273
+
/* DAC1 Digital Volume (0x19) */
274
+
#define RT5645_DAC_L1_VOL_MASK (0xff << 8)
275
+
#define RT5645_DAC_L1_VOL_SFT 8
276
+
#define RT5645_DAC_R1_VOL_MASK (0xff)
277
+
#define RT5645_DAC_R1_VOL_SFT 0
278
+
279
+
/* DAC2 Digital Volume (0x1a) */
280
+
#define RT5645_DAC_L2_VOL_MASK (0xff << 8)
281
+
#define RT5645_DAC_L2_VOL_SFT 8
282
+
#define RT5645_DAC_R2_VOL_MASK (0xff)
283
+
#define RT5645_DAC_R2_VOL_SFT 0
284
+
285
+
/* DAC2 Control (0x1b) */
286
+
#define RT5645_M_DAC_L2_VOL (0x1 << 13)
287
+
#define RT5645_M_DAC_L2_VOL_SFT 13
288
+
#define RT5645_M_DAC_R2_VOL (0x1 << 12)
289
+
#define RT5645_M_DAC_R2_VOL_SFT 12
290
+
#define RT5645_DAC2_L_SEL_MASK (0x7 << 4)
291
+
#define RT5645_DAC2_L_SEL_SFT 4
292
+
#define RT5645_DAC2_R_SEL_MASK (0x7 << 0)
293
+
#define RT5645_DAC2_R_SEL_SFT 0
294
+
295
+
/* ADC Digital Volume Control (0x1c) */
296
+
#define RT5645_ADC_L_VOL_MASK (0x7f << 8)
297
+
#define RT5645_ADC_L_VOL_SFT 8
298
+
#define RT5645_ADC_R_VOL_MASK (0x7f)
299
+
#define RT5645_ADC_R_VOL_SFT 0
300
+
301
+
/* Mono ADC Digital Volume Control (0x1d) */
302
+
#define RT5645_MONO_ADC_L_VOL_MASK (0x7f << 8)
303
+
#define RT5645_MONO_ADC_L_VOL_SFT 8
304
+
#define RT5645_MONO_ADC_R_VOL_MASK (0x7f)
305
+
#define RT5645_MONO_ADC_R_VOL_SFT 0
306
+
307
+
/* ADC Boost Volume Control (0x1e) */
308
+
#define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14)
309
+
#define RT5645_STO1_ADC_L_BST_SFT 14
310
+
#define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12)
311
+
#define RT5645_STO1_ADC_R_BST_SFT 12
312
+
#define RT5645_STO1_ADC_COMP_MASK (0x3 << 10)
313
+
#define RT5645_STO1_ADC_COMP_SFT 10
314
+
#define RT5645_STO2_ADC_L_BST_MASK (0x3 << 8)
315
+
#define RT5645_STO2_ADC_L_BST_SFT 8
316
+
#define RT5645_STO2_ADC_R_BST_MASK (0x3 << 6)
317
+
#define RT5645_STO2_ADC_R_BST_SFT 6
318
+
#define RT5645_STO2_ADC_COMP_MASK (0x3 << 4)
319
+
#define RT5645_STO2_ADC_COMP_SFT 4
320
+
321
+
/* Stereo2 ADC Mixer Control (0x26) */
322
+
#define RT5645_STO2_ADC_SRC_MASK (0x1 << 15)
323
+
#define RT5645_STO2_ADC_SRC_SFT 15
324
+
325
+
/* Stereo ADC Mixer Control (0x27) */
326
+
#define RT5645_M_ADC_L1 (0x1 << 14)
327
+
#define RT5645_M_ADC_L1_SFT 14
328
+
#define RT5645_M_ADC_L2 (0x1 << 13)
329
+
#define RT5645_M_ADC_L2_SFT 13
330
+
#define RT5645_ADC_1_SRC_MASK (0x1 << 12)
331
+
#define RT5645_ADC_1_SRC_SFT 12
332
+
#define RT5645_ADC_1_SRC_ADC (0x1 << 12)
333
+
#define RT5645_ADC_1_SRC_DACMIX (0x0 << 12)
334
+
#define RT5645_ADC_2_SRC_MASK (0x1 << 11)
335
+
#define RT5645_ADC_2_SRC_SFT 11
336
+
#define RT5645_DMIC_SRC_MASK (0x1 << 8)
337
+
#define RT5645_DMIC_SRC_SFT 8
338
+
#define RT5645_M_ADC_R1 (0x1 << 6)
339
+
#define RT5645_M_ADC_R1_SFT 6
340
+
#define RT5645_M_ADC_R2 (0x1 << 5)
341
+
#define RT5645_M_ADC_R2_SFT 5
342
+
#define RT5645_DMIC3_SRC_MASK (0x1 << 1)
343
+
#define RT5645_DMIC3_SRC_SFT 0
344
+
345
+
/* Mono ADC Mixer Control (0x28) */
346
+
#define RT5645_M_MONO_ADC_L1 (0x1 << 14)
347
+
#define RT5645_M_MONO_ADC_L1_SFT 14
348
+
#define RT5645_M_MONO_ADC_L2 (0x1 << 13)
349
+
#define RT5645_M_MONO_ADC_L2_SFT 13
350
+
#define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12)
351
+
#define RT5645_MONO_ADC_L1_SRC_SFT 12
352
+
#define RT5645_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
353
+
#define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
354
+
#define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11)
355
+
#define RT5645_MONO_ADC_L2_SRC_SFT 11
356
+
#define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8)
357
+
#define RT5645_MONO_DMIC_L_SRC_SFT 8
358
+
#define RT5645_M_MONO_ADC_R1 (0x1 << 6)
359
+
#define RT5645_M_MONO_ADC_R1_SFT 6
360
+
#define RT5645_M_MONO_ADC_R2 (0x1 << 5)
361
+
#define RT5645_M_MONO_ADC_R2_SFT 5
362
+
#define RT5645_MONO_ADC_R1_SRC_MASK (0x1 << 4)
363
+
#define RT5645_MONO_ADC_R1_SRC_SFT 4
364
+
#define RT5645_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
365
+
#define RT5645_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
366
+
#define RT5645_MONO_ADC_R2_SRC_MASK (0x1 << 3)
367
+
#define RT5645_MONO_ADC_R2_SRC_SFT 3
368
+
#define RT5645_MONO_DMIC_R_SRC_MASK (0x3)
369
+
#define RT5645_MONO_DMIC_R_SRC_SFT 0
370
+
371
+
/* ADC Mixer to DAC Mixer Control (0x29) */
372
+
#define RT5645_M_ADCMIX_L (0x1 << 15)
373
+
#define RT5645_M_ADCMIX_L_SFT 15
374
+
#define RT5645_M_DAC1_L (0x1 << 14)
375
+
#define RT5645_M_DAC1_L_SFT 14
376
+
#define RT5645_DAC1_R_SEL_MASK (0x3 << 10)
377
+
#define RT5645_DAC1_R_SEL_SFT 10
378
+
#define RT5645_DAC1_R_SEL_IF1 (0x0 << 10)
379
+
#define RT5645_DAC1_R_SEL_IF2 (0x1 << 10)
380
+
#define RT5645_DAC1_R_SEL_IF3 (0x2 << 10)
381
+
#define RT5645_DAC1_R_SEL_IF4 (0x3 << 10)
382
+
#define RT5645_DAC1_L_SEL_MASK (0x3 << 8)
383
+
#define RT5645_DAC1_L_SEL_SFT 8
384
+
#define RT5645_DAC1_L_SEL_IF1 (0x0 << 8)
385
+
#define RT5645_DAC1_L_SEL_IF2 (0x1 << 8)
386
+
#define RT5645_DAC1_L_SEL_IF3 (0x2 << 8)
387
+
#define RT5645_DAC1_L_SEL_IF4 (0x3 << 8)
388
+
#define RT5645_M_ADCMIX_R (0x1 << 7)
389
+
#define RT5645_M_ADCMIX_R_SFT 7
390
+
#define RT5645_M_DAC1_R (0x1 << 6)
391
+
#define RT5645_M_DAC1_R_SFT 6
392
+
393
+
/* Stereo DAC Mixer Control (0x2a) */
394
+
#define RT5645_M_DAC_L1 (0x1 << 14)
395
+
#define RT5645_M_DAC_L1_SFT 14
396
+
#define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
397
+
#define RT5645_DAC_L1_STO_L_VOL_SFT 13
398
+
#define RT5645_M_DAC_L2 (0x1 << 12)
399
+
#define RT5645_M_DAC_L2_SFT 12
400
+
#define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
401
+
#define RT5645_DAC_L2_STO_L_VOL_SFT 11
402
+
#define RT5645_M_ANC_DAC_L (0x1 << 10)
403
+
#define RT5645_M_ANC_DAC_L_SFT 10
404
+
#define RT5645_M_DAC_R1_STO_L (0x1 << 9)
405
+
#define RT5645_M_DAC_R1_STO_L_SFT 9
406
+
#define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
407
+
#define RT5645_DAC_R1_STO_L_VOL_SFT 8
408
+
#define RT5645_M_DAC_R1 (0x1 << 6)
409
+
#define RT5645_M_DAC_R1_SFT 6
410
+
#define RT5645_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
411
+
#define RT5645_DAC_R1_STO_R_VOL_SFT 5
412
+
#define RT5645_M_DAC_R2 (0x1 << 4)
413
+
#define RT5645_M_DAC_R2_SFT 4
414
+
#define RT5645_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
415
+
#define RT5645_DAC_R2_STO_R_VOL_SFT 3
416
+
#define RT5645_M_ANC_DAC_R (0x1 << 2)
417
+
#define RT5645_M_ANC_DAC_R_SFT 2
418
+
#define RT5645_M_DAC_L1_STO_R (0x1 << 1)
419
+
#define RT5645_M_DAC_L1_STO_R_SFT 1
420
+
#define RT5645_DAC_L1_STO_R_VOL_MASK (0x1)
421
+
#define RT5645_DAC_L1_STO_R_VOL_SFT 0
422
+
423
+
/* Mono DAC Mixer Control (0x2b) */
424
+
#define RT5645_M_DAC_L1_MONO_L (0x1 << 14)
425
+
#define RT5645_M_DAC_L1_MONO_L_SFT 14
426
+
#define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
427
+
#define RT5645_DAC_L1_MONO_L_VOL_SFT 13
428
+
#define RT5645_M_DAC_L2_MONO_L (0x1 << 12)
429
+
#define RT5645_M_DAC_L2_MONO_L_SFT 12
430
+
#define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
431
+
#define RT5645_DAC_L2_MONO_L_VOL_SFT 11
432
+
#define RT5645_M_DAC_R2_MONO_L (0x1 << 10)
433
+
#define RT5645_M_DAC_R2_MONO_L_SFT 10
434
+
#define RT5645_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
435
+
#define RT5645_DAC_R2_MONO_L_VOL_SFT 9
436
+
#define RT5645_M_DAC_R1_MONO_R (0x1 << 6)
437
+
#define RT5645_M_DAC_R1_MONO_R_SFT 6
438
+
#define RT5645_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
439
+
#define RT5645_DAC_R1_MONO_R_VOL_SFT 5
440
+
#define RT5645_M_DAC_R2_MONO_R (0x1 << 4)
441
+
#define RT5645_M_DAC_R2_MONO_R_SFT 4
442
+
#define RT5645_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
443
+
#define RT5645_DAC_R2_MONO_R_VOL_SFT 3
444
+
#define RT5645_M_DAC_L2_MONO_R (0x1 << 2)
445
+
#define RT5645_M_DAC_L2_MONO_R_SFT 2
446
+
#define RT5645_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
447
+
#define RT5645_DAC_L2_MONO_R_VOL_SFT 1
448
+
449
+
/* Digital Mixer Control (0x2c) */
450
+
#define RT5645_M_STO_L_DAC_L (0x1 << 15)
451
+
#define RT5645_M_STO_L_DAC_L_SFT 15
452
+
#define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14)
453
+
#define RT5645_STO_L_DAC_L_VOL_SFT 14
454
+
#define RT5645_M_DAC_L2_DAC_L (0x1 << 13)
455
+
#define RT5645_M_DAC_L2_DAC_L_SFT 13
456
+
#define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
457
+
#define RT5645_DAC_L2_DAC_L_VOL_SFT 12
458
+
#define RT5645_M_STO_R_DAC_R (0x1 << 11)
459
+
#define RT5645_M_STO_R_DAC_R_SFT 11
460
+
#define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10)
461
+
#define RT5645_STO_R_DAC_R_VOL_SFT 10
462
+
#define RT5645_M_DAC_R2_DAC_R (0x1 << 9)
463
+
#define RT5645_M_DAC_R2_DAC_R_SFT 9
464
+
#define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
465
+
#define RT5645_DAC_R2_DAC_R_VOL_SFT 8
466
+
#define RT5645_M_DAC_R2_DAC_L (0x1 << 7)
467
+
#define RT5645_M_DAC_R2_DAC_L_SFT 7
468
+
#define RT5645_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
469
+
#define RT5645_DAC_R2_DAC_L_VOL_SFT 6
470
+
#define RT5645_M_DAC_L2_DAC_R (0x1 << 5)
471
+
#define RT5645_M_DAC_L2_DAC_R_SFT 5
472
+
#define RT5645_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
473
+
#define RT5645_DAC_L2_DAC_R_VOL_SFT 4
474
+
475
+
/* Digital Interface Data Control (0x2f) */
476
+
#define RT5645_IF1_ADC2_IN_SEL (0x1 << 15)
477
+
#define RT5645_IF1_ADC2_IN_SFT 15
478
+
#define RT5645_IF2_ADC_IN_MASK (0x7 << 12)
479
+
#define RT5645_IF2_ADC_IN_SFT 12
480
+
#define RT5645_IF2_DAC_SEL_MASK (0x3 << 10)
481
+
#define RT5645_IF2_DAC_SEL_SFT 10
482
+
#define RT5645_IF2_ADC_SEL_MASK (0x3 << 8)
483
+
#define RT5645_IF2_ADC_SEL_SFT 8
484
+
#define RT5645_IF3_DAC_SEL_MASK (0x3 << 6)
485
+
#define RT5645_IF3_DAC_SEL_SFT 6
486
+
#define RT5645_IF3_ADC_SEL_MASK (0x3 << 4)
487
+
#define RT5645_IF3_ADC_SEL_SFT 4
488
+
#define RT5645_IF3_ADC_IN_MASK (0x7)
489
+
#define RT5645_IF3_ADC_IN_SFT 0
490
+
491
+
/* PDM Output Control (0x31) */
492
+
#define RT5645_PDM1_L_MASK (0x1 << 15)
493
+
#define RT5645_PDM1_L_SFT 15
494
+
#define RT5645_M_PDM1_L (0x1 << 14)
495
+
#define RT5645_M_PDM1_L_SFT 14
496
+
#define RT5645_PDM1_R_MASK (0x1 << 13)
497
+
#define RT5645_PDM1_R_SFT 13
498
+
#define RT5645_M_PDM1_R (0x1 << 12)
499
+
#define RT5645_M_PDM1_R_SFT 12
500
+
#define RT5645_PDM2_L_MASK (0x1 << 11)
501
+
#define RT5645_PDM2_L_SFT 11
502
+
#define RT5645_M_PDM2_L (0x1 << 10)
503
+
#define RT5645_M_PDM2_L_SFT 10
504
+
#define RT5645_PDM2_R_MASK (0x1 << 9)
505
+
#define RT5645_PDM2_R_SFT 9
506
+
#define RT5645_M_PDM2_R (0x1 << 8)
507
+
#define RT5645_M_PDM2_R_SFT 8
508
+
#define RT5645_PDM2_BUSY (0x1 << 7)
509
+
#define RT5645_PDM1_BUSY (0x1 << 6)
510
+
#define RT5645_PDM_PATTERN (0x1 << 5)
511
+
#define RT5645_PDM_GAIN (0x1 << 4)
512
+
#define RT5645_PDM_DIV_MASK (0x3)
513
+
514
+
/* REC Left Mixer Control 1 (0x3b) */
515
+
#define RT5645_G_HP_L_RM_L_MASK (0x7 << 13)
516
+
#define RT5645_G_HP_L_RM_L_SFT 13
517
+
#define RT5645_G_IN_L_RM_L_MASK (0x7 << 10)
518
+
#define RT5645_G_IN_L_RM_L_SFT 10
519
+
#define RT5645_G_BST4_RM_L_MASK (0x7 << 7)
520
+
#define RT5645_G_BST4_RM_L_SFT 7
521
+
#define RT5645_G_BST3_RM_L_MASK (0x7 << 4)
522
+
#define RT5645_G_BST3_RM_L_SFT 4
523
+
#define RT5645_G_BST2_RM_L_MASK (0x7 << 1)
524
+
#define RT5645_G_BST2_RM_L_SFT 1
525
+
526
+
/* REC Left Mixer Control 2 (0x3c) */
527
+
#define RT5645_G_BST1_RM_L_MASK (0x7 << 13)
528
+
#define RT5645_G_BST1_RM_L_SFT 13
529
+
#define RT5645_G_OM_L_RM_L_MASK (0x7 << 10)
530
+
#define RT5645_G_OM_L_RM_L_SFT 10
531
+
#define RT5645_M_MM_L_RM_L (0x1 << 6)
532
+
#define RT5645_M_MM_L_RM_L_SFT 6
533
+
#define RT5645_M_IN_L_RM_L (0x1 << 5)
534
+
#define RT5645_M_IN_L_RM_L_SFT 5
535
+
#define RT5645_M_HP_L_RM_L (0x1 << 4)
536
+
#define RT5645_M_HP_L_RM_L_SFT 4
537
+
#define RT5645_M_BST3_RM_L (0x1 << 3)
538
+
#define RT5645_M_BST3_RM_L_SFT 3
539
+
#define RT5645_M_BST2_RM_L (0x1 << 2)
540
+
#define RT5645_M_BST2_RM_L_SFT 2
541
+
#define RT5645_M_BST1_RM_L (0x1 << 1)
542
+
#define RT5645_M_BST1_RM_L_SFT 1
543
+
#define RT5645_M_OM_L_RM_L (0x1)
544
+
#define RT5645_M_OM_L_RM_L_SFT 0
545
+
546
+
/* REC Right Mixer Control 1 (0x3d) */
547
+
#define RT5645_G_HP_R_RM_R_MASK (0x7 << 13)
548
+
#define RT5645_G_HP_R_RM_R_SFT 13
549
+
#define RT5645_G_IN_R_RM_R_MASK (0x7 << 10)
550
+
#define RT5645_G_IN_R_RM_R_SFT 10
551
+
#define RT5645_G_BST4_RM_R_MASK (0x7 << 7)
552
+
#define RT5645_G_BST4_RM_R_SFT 7
553
+
#define RT5645_G_BST3_RM_R_MASK (0x7 << 4)
554
+
#define RT5645_G_BST3_RM_R_SFT 4
555
+
#define RT5645_G_BST2_RM_R_MASK (0x7 << 1)
556
+
#define RT5645_G_BST2_RM_R_SFT 1
557
+
558
+
/* REC Right Mixer Control 2 (0x3e) */
559
+
#define RT5645_G_BST1_RM_R_MASK (0x7 << 13)
560
+
#define RT5645_G_BST1_RM_R_SFT 13
561
+
#define RT5645_G_OM_R_RM_R_MASK (0x7 << 10)
562
+
#define RT5645_G_OM_R_RM_R_SFT 10
563
+
#define RT5645_M_MM_R_RM_R (0x1 << 6)
564
+
#define RT5645_M_MM_R_RM_R_SFT 6
565
+
#define RT5645_M_IN_R_RM_R (0x1 << 5)
566
+
#define RT5645_M_IN_R_RM_R_SFT 5
567
+
#define RT5645_M_HP_R_RM_R (0x1 << 4)
568
+
#define RT5645_M_HP_R_RM_R_SFT 4
569
+
#define RT5645_M_BST3_RM_R (0x1 << 3)
570
+
#define RT5645_M_BST3_RM_R_SFT 3
571
+
#define RT5645_M_BST2_RM_R (0x1 << 2)
572
+
#define RT5645_M_BST2_RM_R_SFT 2
573
+
#define RT5645_M_BST1_RM_R (0x1 << 1)
574
+
#define RT5645_M_BST1_RM_R_SFT 1
575
+
#define RT5645_M_OM_R_RM_R (0x1)
576
+
#define RT5645_M_OM_R_RM_R_SFT 0
577
+
578
+
/* HPOMIX Control (0x40) (0x42) */
579
+
#define RT5645_M_BST1_HV (0x1 << 4)
580
+
#define RT5645_M_BST1_HV_SFT 4
581
+
#define RT5645_M_BST2_HV (0x1 << 4)
582
+
#define RT5645_M_BST2_HV_SFT 4
583
+
#define RT5645_M_BST3_HV (0x1 << 3)
584
+
#define RT5645_M_BST3_HV_SFT 3
585
+
#define RT5645_M_IN_HV (0x1 << 2)
586
+
#define RT5645_M_IN_HV_SFT 2
587
+
#define RT5645_M_DAC2_HV (0x1 << 1)
588
+
#define RT5645_M_DAC2_HV_SFT 1
589
+
#define RT5645_M_DAC1_HV (0x1 << 0)
590
+
#define RT5645_M_DAC1_HV_SFT 0
591
+
592
+
/* HPMIX Control (0x45) */
593
+
#define RT5645_M_DAC1_HM (0x1 << 14)
594
+
#define RT5645_M_DAC1_HM_SFT 14
595
+
#define RT5645_M_HPVOL_HM (0x1 << 13)
596
+
#define RT5645_M_HPVOL_HM_SFT 13
597
+
598
+
/* SPK Left Mixer Control (0x46) */
599
+
#define RT5645_G_RM_L_SM_L_MASK (0x3 << 14)
600
+
#define RT5645_G_RM_L_SM_L_SFT 14
601
+
#define RT5645_G_IN_L_SM_L_MASK (0x3 << 12)
602
+
#define RT5645_G_IN_L_SM_L_SFT 12
603
+
#define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10)
604
+
#define RT5645_G_DAC_L1_SM_L_SFT 10
605
+
#define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8)
606
+
#define RT5645_G_DAC_L2_SM_L_SFT 8
607
+
#define RT5645_G_OM_L_SM_L_MASK (0x3 << 6)
608
+
#define RT5645_G_OM_L_SM_L_SFT 6
609
+
#define RT5645_M_BST1_L_SM_L (0x1 << 5)
610
+
#define RT5645_M_BST1_L_SM_L_SFT 5
611
+
#define RT5645_M_IN_L_SM_L (0x1 << 3)
612
+
#define RT5645_M_IN_L_SM_L_SFT 3
613
+
#define RT5645_M_DAC_L1_SM_L (0x1 << 1)
614
+
#define RT5645_M_DAC_L1_SM_L_SFT 1
615
+
#define RT5645_M_DAC_L2_SM_L (0x1 << 2)
616
+
#define RT5645_M_DAC_L2_SM_L_SFT 2
617
+
#define RT5645_M_BST3_L_SM_L (0x1 << 4)
618
+
#define RT5645_M_BST3_L_SM_L_SFT 4
619
+
620
+
/* SPK Right Mixer Control (0x47) */
621
+
#define RT5645_G_RM_R_SM_R_MASK (0x3 << 14)
622
+
#define RT5645_G_RM_R_SM_R_SFT 14
623
+
#define RT5645_G_IN_R_SM_R_MASK (0x3 << 12)
624
+
#define RT5645_G_IN_R_SM_R_SFT 12
625
+
#define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10)
626
+
#define RT5645_G_DAC_R1_SM_R_SFT 10
627
+
#define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8)
628
+
#define RT5645_G_DAC_R2_SM_R_SFT 8
629
+
#define RT5645_G_OM_R_SM_R_MASK (0x3 << 6)
630
+
#define RT5645_G_OM_R_SM_R_SFT 6
631
+
#define RT5645_M_BST2_R_SM_R (0x1 << 5)
632
+
#define RT5645_M_BST2_R_SM_R_SFT 5
633
+
#define RT5645_M_IN_R_SM_R (0x1 << 3)
634
+
#define RT5645_M_IN_R_SM_R_SFT 3
635
+
#define RT5645_M_DAC_R1_SM_R (0x1 << 1)
636
+
#define RT5645_M_DAC_R1_SM_R_SFT 1
637
+
#define RT5645_M_DAC_R2_SM_R (0x1 << 2)
638
+
#define RT5645_M_DAC_R2_SM_R_SFT 2
639
+
#define RT5645_M_BST3_R_SM_R (0x1 << 4)
640
+
#define RT5645_M_BST3_R_SM_R_SFT 4
641
+
642
+
/* SPOLMIX Control (0x48) */
643
+
#define RT5645_M_DAC_L1_SPM_L (0x1 << 15)
644
+
#define RT5645_M_DAC_L1_SPM_L_SFT 15
645
+
#define RT5645_M_DAC_R1_SPM_L (0x1 << 14)
646
+
#define RT5645_M_DAC_R1_SPM_L_SFT 14
647
+
#define RT5645_M_SV_L_SPM_L (0x1 << 13)
648
+
#define RT5645_M_SV_L_SPM_L_SFT 13
649
+
#define RT5645_M_SV_R_SPM_L (0x1 << 12)
650
+
#define RT5645_M_SV_R_SPM_L_SFT 12
651
+
#define RT5645_M_BST3_SPM_L (0x1 << 11)
652
+
#define RT5645_M_BST3_SPM_L_SFT 11
653
+
#define RT5645_M_DAC_R1_SPM_R (0x1 << 2)
654
+
#define RT5645_M_DAC_R1_SPM_R_SFT 2
655
+
#define RT5645_M_BST3_SPM_R (0x1 << 1)
656
+
#define RT5645_M_BST3_SPM_R_SFT 1
657
+
#define RT5645_M_SV_R_SPM_R (0x1 << 0)
658
+
#define RT5645_M_SV_R_SPM_R_SFT 0
659
+
660
+
/* Mono Output Mixer Control (0x4c) */
661
+
#define RT5645_M_OV_L_MM (0x1 << 9)
662
+
#define RT5645_M_OV_L_MM_SFT 9
663
+
#define RT5645_M_DAC_L2_MA (0x1 << 8)
664
+
#define RT5645_M_DAC_L2_MA_SFT 8
665
+
#define RT5645_G_MONOMIX_MASK (0x1 << 10)
666
+
#define RT5645_G_MONOMIX_SFT 10
667
+
#define RT5645_M_BST2_MM (0x1 << 4)
668
+
#define RT5645_M_BST2_MM_SFT 4
669
+
#define RT5645_M_DAC_R1_MM (0x1 << 3)
670
+
#define RT5645_M_DAC_R1_MM_SFT 3
671
+
#define RT5645_M_DAC_R2_MM (0x1 << 2)
672
+
#define RT5645_M_DAC_R2_MM_SFT 2
673
+
#define RT5645_M_DAC_L2_MM (0x1 << 1)
674
+
#define RT5645_M_DAC_L2_MM_SFT 1
675
+
#define RT5645_M_BST3_MM (0x1 << 0)
676
+
#define RT5645_M_BST3_MM_SFT 0
677
+
678
+
/* Output Left Mixer Control 1 (0x4d) */
679
+
#define RT5645_G_BST3_OM_L_MASK (0x7 << 13)
680
+
#define RT5645_G_BST3_OM_L_SFT 13
681
+
#define RT5645_G_BST2_OM_L_MASK (0x7 << 10)
682
+
#define RT5645_G_BST2_OM_L_SFT 10
683
+
#define RT5645_G_BST1_OM_L_MASK (0x7 << 7)
684
+
#define RT5645_G_BST1_OM_L_SFT 7
685
+
#define RT5645_G_IN_L_OM_L_MASK (0x7 << 4)
686
+
#define RT5645_G_IN_L_OM_L_SFT 4
687
+
#define RT5645_G_RM_L_OM_L_MASK (0x7 << 1)
688
+
#define RT5645_G_RM_L_OM_L_SFT 1
689
+
690
+
/* Output Left Mixer Control 2 (0x4e) */
691
+
#define RT5645_G_DAC_R2_OM_L_MASK (0x7 << 13)
692
+
#define RT5645_G_DAC_R2_OM_L_SFT 13
693
+
#define RT5645_G_DAC_L2_OM_L_MASK (0x7 << 10)
694
+
#define RT5645_G_DAC_L2_OM_L_SFT 10
695
+
#define RT5645_G_DAC_L1_OM_L_MASK (0x7 << 7)
696
+
#define RT5645_G_DAC_L1_OM_L_SFT 7
697
+
698
+
/* Output Left Mixer Control 3 (0x4f) */
699
+
#define RT5645_M_BST3_OM_L (0x1 << 4)
700
+
#define RT5645_M_BST3_OM_L_SFT 4
701
+
#define RT5645_M_BST1_OM_L (0x1 << 3)
702
+
#define RT5645_M_BST1_OM_L_SFT 3
703
+
#define RT5645_M_IN_L_OM_L (0x1 << 2)
704
+
#define RT5645_M_IN_L_OM_L_SFT 2
705
+
#define RT5645_M_DAC_L2_OM_L (0x1 << 1)
706
+
#define RT5645_M_DAC_L2_OM_L_SFT 1
707
+
#define RT5645_M_DAC_L1_OM_L (0x1)
708
+
#define RT5645_M_DAC_L1_OM_L_SFT 0
709
+
710
+
/* Output Right Mixer Control 1 (0x50) */
711
+
#define RT5645_G_BST4_OM_R_MASK (0x7 << 13)
712
+
#define RT5645_G_BST4_OM_R_SFT 13
713
+
#define RT5645_G_BST2_OM_R_MASK (0x7 << 10)
714
+
#define RT5645_G_BST2_OM_R_SFT 10
715
+
#define RT5645_G_BST1_OM_R_MASK (0x7 << 7)
716
+
#define RT5645_G_BST1_OM_R_SFT 7
717
+
#define RT5645_G_IN_R_OM_R_MASK (0x7 << 4)
718
+
#define RT5645_G_IN_R_OM_R_SFT 4
719
+
#define RT5645_G_RM_R_OM_R_MASK (0x7 << 1)
720
+
#define RT5645_G_RM_R_OM_R_SFT 1
721
+
722
+
/* Output Right Mixer Control 2 (0x51) */
723
+
#define RT5645_G_DAC_L2_OM_R_MASK (0x7 << 13)
724
+
#define RT5645_G_DAC_L2_OM_R_SFT 13
725
+
#define RT5645_G_DAC_R2_OM_R_MASK (0x7 << 10)
726
+
#define RT5645_G_DAC_R2_OM_R_SFT 10
727
+
#define RT5645_G_DAC_R1_OM_R_MASK (0x7 << 7)
728
+
#define RT5645_G_DAC_R1_OM_R_SFT 7
729
+
730
+
/* Output Right Mixer Control 3 (0x52) */
731
+
#define RT5645_M_BST3_OM_R (0x1 << 4)
732
+
#define RT5645_M_BST3_OM_R_SFT 4
733
+
#define RT5645_M_BST2_OM_R (0x1 << 3)
734
+
#define RT5645_M_BST2_OM_R_SFT 3
735
+
#define RT5645_M_IN_R_OM_R (0x1 << 2)
736
+
#define RT5645_M_IN_R_OM_R_SFT 2
737
+
#define RT5645_M_DAC_R2_OM_R (0x1 << 1)
738
+
#define RT5645_M_DAC_R2_OM_R_SFT 1
739
+
#define RT5645_M_DAC_R1_OM_R (0x1)
740
+
#define RT5645_M_DAC_R1_OM_R_SFT 0
741
+
742
+
/* LOUT Mixer Control (0x53) */
743
+
#define RT5645_M_DAC_L1_LM (0x1 << 15)
744
+
#define RT5645_M_DAC_L1_LM_SFT 15
745
+
#define RT5645_M_DAC_R1_LM (0x1 << 14)
746
+
#define RT5645_M_DAC_R1_LM_SFT 14
747
+
#define RT5645_M_OV_L_LM (0x1 << 13)
748
+
#define RT5645_M_OV_L_LM_SFT 13
749
+
#define RT5645_M_OV_R_LM (0x1 << 12)
750
+
#define RT5645_M_OV_R_LM_SFT 12
751
+
#define RT5645_G_LOUTMIX_MASK (0x1 << 11)
752
+
#define RT5645_G_LOUTMIX_SFT 11
753
+
754
+
/* Power Management for Digital 1 (0x61) */
755
+
#define RT5645_PWR_I2S1 (0x1 << 15)
756
+
#define RT5645_PWR_I2S1_BIT 15
757
+
#define RT5645_PWR_I2S2 (0x1 << 14)
758
+
#define RT5645_PWR_I2S2_BIT 14
759
+
#define RT5645_PWR_I2S3 (0x1 << 13)
760
+
#define RT5645_PWR_I2S3_BIT 13
761
+
#define RT5645_PWR_DAC_L1 (0x1 << 12)
762
+
#define RT5645_PWR_DAC_L1_BIT 12
763
+
#define RT5645_PWR_DAC_R1 (0x1 << 11)
764
+
#define RT5645_PWR_DAC_R1_BIT 11
765
+
#define RT5645_PWR_CLS_D_R (0x1 << 9)
766
+
#define RT5645_PWR_CLS_D_R_BIT 9
767
+
#define RT5645_PWR_CLS_D_L (0x1 << 8)
768
+
#define RT5645_PWR_CLS_D_L_BIT 8
769
+
#define RT5645_PWR_ADC_R (0x1 << 1)
770
+
#define RT5645_PWR_ADC_R_BIT 1
771
+
#define RT5645_PWR_DAC_L2 (0x1 << 7)
772
+
#define RT5645_PWR_DAC_L2_BIT 7
773
+
#define RT5645_PWR_DAC_R2 (0x1 << 6)
774
+
#define RT5645_PWR_DAC_R2_BIT 6
775
+
#define RT5645_PWR_ADC_L (0x1 << 2)
776
+
#define RT5645_PWR_ADC_L_BIT 2
777
+
#define RT5645_PWR_ADC_R (0x1 << 1)
778
+
#define RT5645_PWR_ADC_R_BIT 1
779
+
#define RT5645_PWR_CLS_D (0x1)
780
+
#define RT5645_PWR_CLS_D_BIT 0
781
+
782
+
/* Power Management for Digital 2 (0x62) */
783
+
#define RT5645_PWR_ADC_S1F (0x1 << 15)
784
+
#define RT5645_PWR_ADC_S1F_BIT 15
785
+
#define RT5645_PWR_ADC_MF_L (0x1 << 14)
786
+
#define RT5645_PWR_ADC_MF_L_BIT 14
787
+
#define RT5645_PWR_ADC_MF_R (0x1 << 13)
788
+
#define RT5645_PWR_ADC_MF_R_BIT 13
789
+
#define RT5645_PWR_I2S_DSP (0x1 << 12)
790
+
#define RT5645_PWR_I2S_DSP_BIT 12
791
+
#define RT5645_PWR_DAC_S1F (0x1 << 11)
792
+
#define RT5645_PWR_DAC_S1F_BIT 11
793
+
#define RT5645_PWR_DAC_MF_L (0x1 << 10)
794
+
#define RT5645_PWR_DAC_MF_L_BIT 10
795
+
#define RT5645_PWR_DAC_MF_R (0x1 << 9)
796
+
#define RT5645_PWR_DAC_MF_R_BIT 9
797
+
#define RT5645_PWR_ADC_S2F (0x1 << 8)
798
+
#define RT5645_PWR_ADC_S2F_BIT 8
799
+
#define RT5645_PWR_PDM1 (0x1 << 7)
800
+
#define RT5645_PWR_PDM1_BIT 7
801
+
#define RT5645_PWR_PDM2 (0x1 << 6)
802
+
#define RT5645_PWR_PDM2_BIT 6
803
+
#define RT5645_PWR_IPTV (0x1 << 1)
804
+
#define RT5645_PWR_IPTV_BIT 1
805
+
#define RT5645_PWR_PAD (0x1)
806
+
#define RT5645_PWR_PAD_BIT 0
807
+
808
+
/* Power Management for Analog 1 (0x63) */
809
+
#define RT5645_PWR_VREF1 (0x1 << 15)
810
+
#define RT5645_PWR_VREF1_BIT 15
811
+
#define RT5645_PWR_FV1 (0x1 << 14)
812
+
#define RT5645_PWR_FV1_BIT 14
813
+
#define RT5645_PWR_MB (0x1 << 13)
814
+
#define RT5645_PWR_MB_BIT 13
815
+
#define RT5645_PWR_LM (0x1 << 12)
816
+
#define RT5645_PWR_LM_BIT 12
817
+
#define RT5645_PWR_BG (0x1 << 11)
818
+
#define RT5645_PWR_BG_BIT 11
819
+
#define RT5645_PWR_MA (0x1 << 10)
820
+
#define RT5645_PWR_MA_BIT 10
821
+
#define RT5645_PWR_HP_L (0x1 << 7)
822
+
#define RT5645_PWR_HP_L_BIT 7
823
+
#define RT5645_PWR_HP_R (0x1 << 6)
824
+
#define RT5645_PWR_HP_R_BIT 6
825
+
#define RT5645_PWR_HA (0x1 << 5)
826
+
#define RT5645_PWR_HA_BIT 5
827
+
#define RT5645_PWR_VREF2 (0x1 << 4)
828
+
#define RT5645_PWR_VREF2_BIT 4
829
+
#define RT5645_PWR_FV2 (0x1 << 3)
830
+
#define RT5645_PWR_FV2_BIT 3
831
+
#define RT5645_LDO_SEL_MASK (0x3)
832
+
#define RT5645_LDO_SEL_SFT 0
833
+
834
+
/* Power Management for Analog 2 (0x64) */
835
+
#define RT5645_PWR_BST1 (0x1 << 15)
836
+
#define RT5645_PWR_BST1_BIT 15
837
+
#define RT5645_PWR_BST2 (0x1 << 14)
838
+
#define RT5645_PWR_BST2_BIT 14
839
+
#define RT5645_PWR_BST3 (0x1 << 13)
840
+
#define RT5645_PWR_BST3_BIT 13
841
+
#define RT5645_PWR_BST4 (0x1 << 12)
842
+
#define RT5645_PWR_BST4_BIT 12
843
+
#define RT5645_PWR_MB1 (0x1 << 11)
844
+
#define RT5645_PWR_MB1_BIT 11
845
+
#define RT5645_PWR_MB2 (0x1 << 10)
846
+
#define RT5645_PWR_MB2_BIT 10
847
+
#define RT5645_PWR_PLL (0x1 << 9)
848
+
#define RT5645_PWR_PLL_BIT 9
849
+
#define RT5645_PWR_BST2_P (0x1 << 5)
850
+
#define RT5645_PWR_BST2_P_BIT 5
851
+
#define RT5645_PWR_BST3_P (0x1 << 4)
852
+
#define RT5645_PWR_BST3_P_BIT 4
853
+
#define RT5645_PWR_BST4_P (0x1 << 3)
854
+
#define RT5645_PWR_BST4_P_BIT 3
855
+
#define RT5645_PWR_JD1 (0x1 << 2)
856
+
#define RT5645_PWR_JD1_BIT 2
857
+
#define RT5645_PWR_JD (0x1 << 1)
858
+
#define RT5645_PWR_JD_BIT 1
859
+
860
+
/* Power Management for Mixer (0x65) */
861
+
#define RT5645_PWR_OM_L (0x1 << 15)
862
+
#define RT5645_PWR_OM_L_BIT 15
863
+
#define RT5645_PWR_OM_R (0x1 << 14)
864
+
#define RT5645_PWR_OM_R_BIT 14
865
+
#define RT5645_PWR_SM_L (0x1 << 13)
866
+
#define RT5645_PWR_SM_L_BIT 13
867
+
#define RT5645_PWR_SM_R (0x1 << 12)
868
+
#define RT5645_PWR_SM_R_BIT 12
869
+
#define RT5645_PWR_RM_L (0x1 << 11)
870
+
#define RT5645_PWR_RM_L_BIT 11
871
+
#define RT5645_PWR_RM_R (0x1 << 10)
872
+
#define RT5645_PWR_RM_R_BIT 10
873
+
#define RT5645_PWR_MM (0x1 << 8)
874
+
#define RT5645_PWR_MM_BIT 8
875
+
#define RT5645_PWR_HM_L (0x1 << 7)
876
+
#define RT5645_PWR_HM_L_BIT 7
877
+
#define RT5645_PWR_HM_R (0x1 << 6)
878
+
#define RT5645_PWR_HM_R_BIT 6
879
+
#define RT5645_PWR_LDO2 (0x1 << 1)
880
+
#define RT5645_PWR_LDO2_BIT 1
881
+
882
+
/* Power Management for Volume (0x66) */
883
+
#define RT5645_PWR_SV_L (0x1 << 15)
884
+
#define RT5645_PWR_SV_L_BIT 15
885
+
#define RT5645_PWR_SV_R (0x1 << 14)
886
+
#define RT5645_PWR_SV_R_BIT 14
887
+
#define RT5645_PWR_HV_L (0x1 << 11)
888
+
#define RT5645_PWR_HV_L_BIT 11
889
+
#define RT5645_PWR_HV_R (0x1 << 10)
890
+
#define RT5645_PWR_HV_R_BIT 10
891
+
#define RT5645_PWR_IN_L (0x1 << 9)
892
+
#define RT5645_PWR_IN_L_BIT 9
893
+
#define RT5645_PWR_IN_R (0x1 << 8)
894
+
#define RT5645_PWR_IN_R_BIT 8
895
+
#define RT5645_PWR_MIC_DET (0x1 << 5)
896
+
#define RT5645_PWR_MIC_DET_BIT 5
897
+
898
+
/* I2S1/2 Audio Serial Data Port Control (0x70 0x71) */
899
+
#define RT5645_I2S_MS_MASK (0x1 << 15)
900
+
#define RT5645_I2S_MS_SFT 15
901
+
#define RT5645_I2S_MS_M (0x0 << 15)
902
+
#define RT5645_I2S_MS_S (0x1 << 15)
903
+
#define RT5645_I2S_O_CP_MASK (0x3 << 10)
904
+
#define RT5645_I2S_O_CP_SFT 10
905
+
#define RT5645_I2S_O_CP_OFF (0x0 << 10)
906
+
#define RT5645_I2S_O_CP_U_LAW (0x1 << 10)
907
+
#define RT5645_I2S_O_CP_A_LAW (0x2 << 10)
908
+
#define RT5645_I2S_I_CP_MASK (0x3 << 8)
909
+
#define RT5645_I2S_I_CP_SFT 8
910
+
#define RT5645_I2S_I_CP_OFF (0x0 << 8)
911
+
#define RT5645_I2S_I_CP_U_LAW (0x1 << 8)
912
+
#define RT5645_I2S_I_CP_A_LAW (0x2 << 8)
913
+
#define RT5645_I2S_BP_MASK (0x1 << 7)
914
+
#define RT5645_I2S_BP_SFT 7
915
+
#define RT5645_I2S_BP_NOR (0x0 << 7)
916
+
#define RT5645_I2S_BP_INV (0x1 << 7)
917
+
#define RT5645_I2S_DL_MASK (0x3 << 2)
918
+
#define RT5645_I2S_DL_SFT 2
919
+
#define RT5645_I2S_DL_16 (0x0 << 2)
920
+
#define RT5645_I2S_DL_20 (0x1 << 2)
921
+
#define RT5645_I2S_DL_24 (0x2 << 2)
922
+
#define RT5645_I2S_DL_8 (0x3 << 2)
923
+
#define RT5645_I2S_DF_MASK (0x3)
924
+
#define RT5645_I2S_DF_SFT 0
925
+
#define RT5645_I2S_DF_I2S (0x0)
926
+
#define RT5645_I2S_DF_LEFT (0x1)
927
+
#define RT5645_I2S_DF_PCM_A (0x2)
928
+
#define RT5645_I2S_DF_PCM_B (0x3)
929
+
930
+
/* I2S2 Audio Serial Data Port Control (0x71) */
931
+
#define RT5645_I2S2_SDI_MASK (0x1 << 6)
932
+
#define RT5645_I2S2_SDI_SFT 6
933
+
#define RT5645_I2S2_SDI_I2S1 (0x0 << 6)
934
+
#define RT5645_I2S2_SDI_I2S2 (0x1 << 6)
935
+
936
+
/* ADC/DAC Clock Control 1 (0x73) */
937
+
#define RT5645_I2S_BCLK_MS1_MASK (0x1 << 15)
938
+
#define RT5645_I2S_BCLK_MS1_SFT 15
939
+
#define RT5645_I2S_BCLK_MS1_32 (0x0 << 15)
940
+
#define RT5645_I2S_BCLK_MS1_64 (0x1 << 15)
941
+
#define RT5645_I2S_PD1_MASK (0x7 << 12)
942
+
#define RT5645_I2S_PD1_SFT 12
943
+
#define RT5645_I2S_PD1_1 (0x0 << 12)
944
+
#define RT5645_I2S_PD1_2 (0x1 << 12)
945
+
#define RT5645_I2S_PD1_3 (0x2 << 12)
946
+
#define RT5645_I2S_PD1_4 (0x3 << 12)
947
+
#define RT5645_I2S_PD1_6 (0x4 << 12)
948
+
#define RT5645_I2S_PD1_8 (0x5 << 12)
949
+
#define RT5645_I2S_PD1_12 (0x6 << 12)
950
+
#define RT5645_I2S_PD1_16 (0x7 << 12)
951
+
#define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11)
952
+
#define RT5645_I2S_BCLK_MS2_SFT 11
953
+
#define RT5645_I2S_BCLK_MS2_32 (0x0 << 11)
954
+
#define RT5645_I2S_BCLK_MS2_64 (0x1 << 11)
955
+
#define RT5645_I2S_PD2_MASK (0x7 << 8)
956
+
#define RT5645_I2S_PD2_SFT 8
957
+
#define RT5645_I2S_PD2_1 (0x0 << 8)
958
+
#define RT5645_I2S_PD2_2 (0x1 << 8)
959
+
#define RT5645_I2S_PD2_3 (0x2 << 8)
960
+
#define RT5645_I2S_PD2_4 (0x3 << 8)
961
+
#define RT5645_I2S_PD2_6 (0x4 << 8)
962
+
#define RT5645_I2S_PD2_8 (0x5 << 8)
963
+
#define RT5645_I2S_PD2_12 (0x6 << 8)
964
+
#define RT5645_I2S_PD2_16 (0x7 << 8)
965
+
#define RT5645_I2S_BCLK_MS3_MASK (0x1 << 7)
966
+
#define RT5645_I2S_BCLK_MS3_SFT 7
967
+
#define RT5645_I2S_BCLK_MS3_32 (0x0 << 7)
968
+
#define RT5645_I2S_BCLK_MS3_64 (0x1 << 7)
969
+
#define RT5645_I2S_PD3_MASK (0x7 << 4)
970
+
#define RT5645_I2S_PD3_SFT 4
971
+
#define RT5645_I2S_PD3_1 (0x0 << 4)
972
+
#define RT5645_I2S_PD3_2 (0x1 << 4)
973
+
#define RT5645_I2S_PD3_3 (0x2 << 4)
974
+
#define RT5645_I2S_PD3_4 (0x3 << 4)
975
+
#define RT5645_I2S_PD3_6 (0x4 << 4)
976
+
#define RT5645_I2S_PD3_8 (0x5 << 4)
977
+
#define RT5645_I2S_PD3_12 (0x6 << 4)
978
+
#define RT5645_I2S_PD3_16 (0x7 << 4)
979
+
#define RT5645_DAC_OSR_MASK (0x3 << 2)
980
+
#define RT5645_DAC_OSR_SFT 2
981
+
#define RT5645_DAC_OSR_128 (0x0 << 2)
982
+
#define RT5645_DAC_OSR_64 (0x1 << 2)
983
+
#define RT5645_DAC_OSR_32 (0x2 << 2)
984
+
#define RT5645_DAC_OSR_16 (0x3 << 2)
985
+
#define RT5645_ADC_OSR_MASK (0x3)
986
+
#define RT5645_ADC_OSR_SFT 0
987
+
#define RT5645_ADC_OSR_128 (0x0)
988
+
#define RT5645_ADC_OSR_64 (0x1)
989
+
#define RT5645_ADC_OSR_32 (0x2)
990
+
#define RT5645_ADC_OSR_16 (0x3)
991
+
992
+
/* ADC/DAC Clock Control 2 (0x74) */
993
+
#define RT5645_DAC_L_OSR_MASK (0x3 << 14)
994
+
#define RT5645_DAC_L_OSR_SFT 14
995
+
#define RT5645_DAC_L_OSR_128 (0x0 << 14)
996
+
#define RT5645_DAC_L_OSR_64 (0x1 << 14)
997
+
#define RT5645_DAC_L_OSR_32 (0x2 << 14)
998
+
#define RT5645_DAC_L_OSR_16 (0x3 << 14)
999
+
#define RT5645_ADC_R_OSR_MASK (0x3 << 12)
1000
+
#define RT5645_ADC_R_OSR_SFT 12
1001
+
#define RT5645_ADC_R_OSR_128 (0x0 << 12)
1002
+
#define RT5645_ADC_R_OSR_64 (0x1 << 12)
1003
+
#define RT5645_ADC_R_OSR_32 (0x2 << 12)
1004
+
#define RT5645_ADC_R_OSR_16 (0x3 << 12)
1005
+
#define RT5645_DAHPF_EN (0x1 << 11)
1006
+
#define RT5645_DAHPF_EN_SFT 11
1007
+
#define RT5645_ADHPF_EN (0x1 << 10)
1008
+
#define RT5645_ADHPF_EN_SFT 10
1009
+
1010
+
/* Digital Microphone Control (0x75) */
1011
+
#define RT5645_DMIC_1_EN_MASK (0x1 << 15)
1012
+
#define RT5645_DMIC_1_EN_SFT 15
1013
+
#define RT5645_DMIC_1_DIS (0x0 << 15)
1014
+
#define RT5645_DMIC_1_EN (0x1 << 15)
1015
+
#define RT5645_DMIC_2_EN_MASK (0x1 << 14)
1016
+
#define RT5645_DMIC_2_EN_SFT 14
1017
+
#define RT5645_DMIC_2_DIS (0x0 << 14)
1018
+
#define RT5645_DMIC_2_EN (0x1 << 14)
1019
+
#define RT5645_DMIC_1L_LH_MASK (0x1 << 13)
1020
+
#define RT5645_DMIC_1L_LH_SFT 13
1021
+
#define RT5645_DMIC_1L_LH_FALLING (0x0 << 13)
1022
+
#define RT5645_DMIC_1L_LH_RISING (0x1 << 13)
1023
+
#define RT5645_DMIC_1R_LH_MASK (0x1 << 12)
1024
+
#define RT5645_DMIC_1R_LH_SFT 12
1025
+
#define RT5645_DMIC_1R_LH_FALLING (0x0 << 12)
1026
+
#define RT5645_DMIC_1R_LH_RISING (0x1 << 12)
1027
+
#define RT5645_DMIC_2_DP_MASK (0x3 << 10)
1028
+
#define RT5645_DMIC_2_DP_SFT 10
1029
+
#define RT5645_DMIC_2_DP_GPIO6 (0x0 << 10)
1030
+
#define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10)
1031
+
#define RT5645_DMIC_2_DP_GPIO12 (0x2 << 10)
1032
+
#define RT5645_DMIC_2_DP_IN2P (0x3 << 10)
1033
+
#define RT5645_DMIC_2L_LH_MASK (0x1 << 9)
1034
+
#define RT5645_DMIC_2L_LH_SFT 9
1035
+
#define RT5645_DMIC_2L_LH_FALLING (0x0 << 9)
1036
+
#define RT5645_DMIC_2L_LH_RISING (0x1 << 9)
1037
+
#define RT5645_DMIC_2R_LH_MASK (0x1 << 8)
1038
+
#define RT5645_DMIC_2R_LH_SFT 8
1039
+
#define RT5645_DMIC_2R_LH_FALLING (0x0 << 8)
1040
+
#define RT5645_DMIC_2R_LH_RISING (0x1 << 8)
1041
+
#define RT5645_DMIC_CLK_MASK (0x7 << 5)
1042
+
#define RT5645_DMIC_CLK_SFT 5
1043
+
#define RT5645_DMIC_3_EN_MASK (0x1 << 4)
1044
+
#define RT5645_DMIC_3_EN_SFT 4
1045
+
#define RT5645_DMIC_3_DIS (0x0 << 4)
1046
+
#define RT5645_DMIC_3_EN (0x1 << 4)
1047
+
#define RT5645_DMIC_1_DP_MASK (0x3 << 0)
1048
+
#define RT5645_DMIC_1_DP_SFT 0
1049
+
#define RT5645_DMIC_1_DP_GPIO5 (0x0 << 0)
1050
+
#define RT5645_DMIC_1_DP_IN2N (0x1 << 0)
1051
+
#define RT5645_DMIC_1_DP_GPIO11 (0x2 << 0)
1052
+
1053
+
/* TDM Control 1 (0x77) */
1054
+
#define RT5645_IF1_ADC_IN_MASK (0x3 << 8)
1055
+
#define RT5645_IF1_ADC_IN_SFT 8
1056
+
1057
+
/* Global Clock Control (0x80) */
1058
+
#define RT5645_SCLK_SRC_MASK (0x3 << 14)
1059
+
#define RT5645_SCLK_SRC_SFT 14
1060
+
#define RT5645_SCLK_SRC_MCLK (0x0 << 14)
1061
+
#define RT5645_SCLK_SRC_PLL1 (0x1 << 14)
1062
+
#define RT5645_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
1063
+
#define RT5645_PLL1_SRC_MASK (0x3 << 12)
1064
+
#define RT5645_PLL1_SRC_SFT 12
1065
+
#define RT5645_PLL1_SRC_MCLK (0x0 << 12)
1066
+
#define RT5645_PLL1_SRC_BCLK1 (0x1 << 12)
1067
+
#define RT5645_PLL1_SRC_BCLK2 (0x2 << 12)
1068
+
#define RT5645_PLL1_SRC_BCLK3 (0x3 << 12)
1069
+
#define RT5645_PLL1_PD_MASK (0x1 << 3)
1070
+
#define RT5645_PLL1_PD_SFT 3
1071
+
#define RT5645_PLL1_PD_1 (0x0 << 3)
1072
+
#define RT5645_PLL1_PD_2 (0x1 << 3)
1073
+
1074
+
#define RT5645_PLL_INP_MAX 40000000
1075
+
#define RT5645_PLL_INP_MIN 256000
1076
+
/* PLL M/N/K Code Control 1 (0x81) */
1077
+
#define RT5645_PLL_N_MAX 0x1ff
1078
+
#define RT5645_PLL_N_MASK (RT5645_PLL_N_MAX << 7)
1079
+
#define RT5645_PLL_N_SFT 7
1080
+
#define RT5645_PLL_K_MAX 0x1f
1081
+
#define RT5645_PLL_K_MASK (RT5645_PLL_K_MAX)
1082
+
#define RT5645_PLL_K_SFT 0
1083
+
1084
+
/* PLL M/N/K Code Control 2 (0x82) */
1085
+
#define RT5645_PLL_M_MAX 0xf
1086
+
#define RT5645_PLL_M_MASK (RT5645_PLL_M_MAX << 12)
1087
+
#define RT5645_PLL_M_SFT 12
1088
+
#define RT5645_PLL_M_BP (0x1 << 11)
1089
+
#define RT5645_PLL_M_BP_SFT 11
1090
+
1091
+
/* ASRC Control 1 (0x83) */
1092
+
#define RT5645_STO_T_MASK (0x1 << 15)
1093
+
#define RT5645_STO_T_SFT 15
1094
+
#define RT5645_STO_T_SCLK (0x0 << 15)
1095
+
#define RT5645_STO_T_LRCK1 (0x1 << 15)
1096
+
#define RT5645_M1_T_MASK (0x1 << 14)
1097
+
#define RT5645_M1_T_SFT 14
1098
+
#define RT5645_M1_T_I2S2 (0x0 << 14)
1099
+
#define RT5645_M1_T_I2S2_D3 (0x1 << 14)
1100
+
#define RT5645_I2S2_F_MASK (0x1 << 12)
1101
+
#define RT5645_I2S2_F_SFT 12
1102
+
#define RT5645_I2S2_F_I2S2_D2 (0x0 << 12)
1103
+
#define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12)
1104
+
#define RT5645_DMIC_1_M_MASK (0x1 << 9)
1105
+
#define RT5645_DMIC_1_M_SFT 9
1106
+
#define RT5645_DMIC_1_M_NOR (0x0 << 9)
1107
+
#define RT5645_DMIC_1_M_ASYN (0x1 << 9)
1108
+
#define RT5645_DMIC_2_M_MASK (0x1 << 8)
1109
+
#define RT5645_DMIC_2_M_SFT 8
1110
+
#define RT5645_DMIC_2_M_NOR (0x0 << 8)
1111
+
#define RT5645_DMIC_2_M_ASYN (0x1 << 8)
1112
+
1113
+
/* ASRC Control 2 (0x84) */
1114
+
#define RT5645_MDA_L_M_MASK (0x1 << 15)
1115
+
#define RT5645_MDA_L_M_SFT 15
1116
+
#define RT5645_MDA_L_M_NOR (0x0 << 15)
1117
+
#define RT5645_MDA_L_M_ASYN (0x1 << 15)
1118
+
#define RT5645_MDA_R_M_MASK (0x1 << 14)
1119
+
#define RT5645_MDA_R_M_SFT 14
1120
+
#define RT5645_MDA_R_M_NOR (0x0 << 14)
1121
+
#define RT5645_MDA_R_M_ASYN (0x1 << 14)
1122
+
#define RT5645_MAD_L_M_MASK (0x1 << 13)
1123
+
#define RT5645_MAD_L_M_SFT 13
1124
+
#define RT5645_MAD_L_M_NOR (0x0 << 13)
1125
+
#define RT5645_MAD_L_M_ASYN (0x1 << 13)
1126
+
#define RT5645_MAD_R_M_MASK (0x1 << 12)
1127
+
#define RT5645_MAD_R_M_SFT 12
1128
+
#define RT5645_MAD_R_M_NOR (0x0 << 12)
1129
+
#define RT5645_MAD_R_M_ASYN (0x1 << 12)
1130
+
#define RT5645_ADC_M_MASK (0x1 << 11)
1131
+
#define RT5645_ADC_M_SFT 11
1132
+
#define RT5645_ADC_M_NOR (0x0 << 11)
1133
+
#define RT5645_ADC_M_ASYN (0x1 << 11)
1134
+
#define RT5645_STO_DAC_M_MASK (0x1 << 5)
1135
+
#define RT5645_STO_DAC_M_SFT 5
1136
+
#define RT5645_STO_DAC_M_NOR (0x0 << 5)
1137
+
#define RT5645_STO_DAC_M_ASYN (0x1 << 5)
1138
+
#define RT5645_I2S1_R_D_MASK (0x1 << 4)
1139
+
#define RT5645_I2S1_R_D_SFT 4
1140
+
#define RT5645_I2S1_R_D_DIS (0x0 << 4)
1141
+
#define RT5645_I2S1_R_D_EN (0x1 << 4)
1142
+
#define RT5645_I2S2_R_D_MASK (0x1 << 3)
1143
+
#define RT5645_I2S2_R_D_SFT 3
1144
+
#define RT5645_I2S2_R_D_DIS (0x0 << 3)
1145
+
#define RT5645_I2S2_R_D_EN (0x1 << 3)
1146
+
#define RT5645_PRE_SCLK_MASK (0x3)
1147
+
#define RT5645_PRE_SCLK_SFT 0
1148
+
#define RT5645_PRE_SCLK_512 (0x0)
1149
+
#define RT5645_PRE_SCLK_1024 (0x1)
1150
+
#define RT5645_PRE_SCLK_2048 (0x2)
1151
+
1152
+
/* ASRC Control 3 (0x85) */
1153
+
#define RT5645_I2S1_RATE_MASK (0xf << 12)
1154
+
#define RT5645_I2S1_RATE_SFT 12
1155
+
#define RT5645_I2S2_RATE_MASK (0xf << 8)
1156
+
#define RT5645_I2S2_RATE_SFT 8
1157
+
1158
+
/* ASRC Control 4 (0x89) */
1159
+
#define RT5645_I2S1_PD_MASK (0x7 << 12)
1160
+
#define RT5645_I2S1_PD_SFT 12
1161
+
#define RT5645_I2S2_PD_MASK (0x7 << 8)
1162
+
#define RT5645_I2S2_PD_SFT 8
1163
+
1164
+
/* HPOUT Over Current Detection (0x8b) */
1165
+
#define RT5645_HP_OVCD_MASK (0x1 << 10)
1166
+
#define RT5645_HP_OVCD_SFT 10
1167
+
#define RT5645_HP_OVCD_DIS (0x0 << 10)
1168
+
#define RT5645_HP_OVCD_EN (0x1 << 10)
1169
+
#define RT5645_HP_OC_TH_MASK (0x3 << 8)
1170
+
#define RT5645_HP_OC_TH_SFT 8
1171
+
#define RT5645_HP_OC_TH_90 (0x0 << 8)
1172
+
#define RT5645_HP_OC_TH_105 (0x1 << 8)
1173
+
#define RT5645_HP_OC_TH_120 (0x2 << 8)
1174
+
#define RT5645_HP_OC_TH_135 (0x3 << 8)
1175
+
1176
+
/* Class D Over Current Control (0x8c) */
1177
+
#define RT5645_CLSD_OC_MASK (0x1 << 9)
1178
+
#define RT5645_CLSD_OC_SFT 9
1179
+
#define RT5645_CLSD_OC_PU (0x0 << 9)
1180
+
#define RT5645_CLSD_OC_PD (0x1 << 9)
1181
+
#define RT5645_AUTO_PD_MASK (0x1 << 8)
1182
+
#define RT5645_AUTO_PD_SFT 8
1183
+
#define RT5645_AUTO_PD_DIS (0x0 << 8)
1184
+
#define RT5645_AUTO_PD_EN (0x1 << 8)
1185
+
#define RT5645_CLSD_OC_TH_MASK (0x3f)
1186
+
#define RT5645_CLSD_OC_TH_SFT 0
1187
+
1188
+
/* Class D Output Control (0x8d) */
1189
+
#define RT5645_CLSD_RATIO_MASK (0xf << 12)
1190
+
#define RT5645_CLSD_RATIO_SFT 12
1191
+
#define RT5645_CLSD_OM_MASK (0x1 << 11)
1192
+
#define RT5645_CLSD_OM_SFT 11
1193
+
#define RT5645_CLSD_OM_MONO (0x0 << 11)
1194
+
#define RT5645_CLSD_OM_STO (0x1 << 11)
1195
+
#define RT5645_CLSD_SCH_MASK (0x1 << 10)
1196
+
#define RT5645_CLSD_SCH_SFT 10
1197
+
#define RT5645_CLSD_SCH_L (0x0 << 10)
1198
+
#define RT5645_CLSD_SCH_S (0x1 << 10)
1199
+
1200
+
/* Depop Mode Control 1 (0x8e) */
1201
+
#define RT5645_SMT_TRIG_MASK (0x1 << 15)
1202
+
#define RT5645_SMT_TRIG_SFT 15
1203
+
#define RT5645_SMT_TRIG_DIS (0x0 << 15)
1204
+
#define RT5645_SMT_TRIG_EN (0x1 << 15)
1205
+
#define RT5645_HP_L_SMT_MASK (0x1 << 9)
1206
+
#define RT5645_HP_L_SMT_SFT 9
1207
+
#define RT5645_HP_L_SMT_DIS (0x0 << 9)
1208
+
#define RT5645_HP_L_SMT_EN (0x1 << 9)
1209
+
#define RT5645_HP_R_SMT_MASK (0x1 << 8)
1210
+
#define RT5645_HP_R_SMT_SFT 8
1211
+
#define RT5645_HP_R_SMT_DIS (0x0 << 8)
1212
+
#define RT5645_HP_R_SMT_EN (0x1 << 8)
1213
+
#define RT5645_HP_CD_PD_MASK (0x1 << 7)
1214
+
#define RT5645_HP_CD_PD_SFT 7
1215
+
#define RT5645_HP_CD_PD_DIS (0x0 << 7)
1216
+
#define RT5645_HP_CD_PD_EN (0x1 << 7)
1217
+
#define RT5645_RSTN_MASK (0x1 << 6)
1218
+
#define RT5645_RSTN_SFT 6
1219
+
#define RT5645_RSTN_DIS (0x0 << 6)
1220
+
#define RT5645_RSTN_EN (0x1 << 6)
1221
+
#define RT5645_RSTP_MASK (0x1 << 5)
1222
+
#define RT5645_RSTP_SFT 5
1223
+
#define RT5645_RSTP_DIS (0x0 << 5)
1224
+
#define RT5645_RSTP_EN (0x1 << 5)
1225
+
#define RT5645_HP_CO_MASK (0x1 << 4)
1226
+
#define RT5645_HP_CO_SFT 4
1227
+
#define RT5645_HP_CO_DIS (0x0 << 4)
1228
+
#define RT5645_HP_CO_EN (0x1 << 4)
1229
+
#define RT5645_HP_CP_MASK (0x1 << 3)
1230
+
#define RT5645_HP_CP_SFT 3
1231
+
#define RT5645_HP_CP_PD (0x0 << 3)
1232
+
#define RT5645_HP_CP_PU (0x1 << 3)
1233
+
#define RT5645_HP_SG_MASK (0x1 << 2)
1234
+
#define RT5645_HP_SG_SFT 2
1235
+
#define RT5645_HP_SG_DIS (0x0 << 2)
1236
+
#define RT5645_HP_SG_EN (0x1 << 2)
1237
+
#define RT5645_HP_DP_MASK (0x1 << 1)
1238
+
#define RT5645_HP_DP_SFT 1
1239
+
#define RT5645_HP_DP_PD (0x0 << 1)
1240
+
#define RT5645_HP_DP_PU (0x1 << 1)
1241
+
#define RT5645_HP_CB_MASK (0x1)
1242
+
#define RT5645_HP_CB_SFT 0
1243
+
#define RT5645_HP_CB_PD (0x0)
1244
+
#define RT5645_HP_CB_PU (0x1)
1245
+
1246
+
/* Depop Mode Control 2 (0x8f) */
1247
+
#define RT5645_DEPOP_MASK (0x1 << 13)
1248
+
#define RT5645_DEPOP_SFT 13
1249
+
#define RT5645_DEPOP_AUTO (0x0 << 13)
1250
+
#define RT5645_DEPOP_MAN (0x1 << 13)
1251
+
#define RT5645_RAMP_MASK (0x1 << 12)
1252
+
#define RT5645_RAMP_SFT 12
1253
+
#define RT5645_RAMP_DIS (0x0 << 12)
1254
+
#define RT5645_RAMP_EN (0x1 << 12)
1255
+
#define RT5645_BPS_MASK (0x1 << 11)
1256
+
#define RT5645_BPS_SFT 11
1257
+
#define RT5645_BPS_DIS (0x0 << 11)
1258
+
#define RT5645_BPS_EN (0x1 << 11)
1259
+
#define RT5645_FAST_UPDN_MASK (0x1 << 10)
1260
+
#define RT5645_FAST_UPDN_SFT 10
1261
+
#define RT5645_FAST_UPDN_DIS (0x0 << 10)
1262
+
#define RT5645_FAST_UPDN_EN (0x1 << 10)
1263
+
#define RT5645_MRES_MASK (0x3 << 8)
1264
+
#define RT5645_MRES_SFT 8
1265
+
#define RT5645_MRES_15MO (0x0 << 8)
1266
+
#define RT5645_MRES_25MO (0x1 << 8)
1267
+
#define RT5645_MRES_35MO (0x2 << 8)
1268
+
#define RT5645_MRES_45MO (0x3 << 8)
1269
+
#define RT5645_VLO_MASK (0x1 << 7)
1270
+
#define RT5645_VLO_SFT 7
1271
+
#define RT5645_VLO_3V (0x0 << 7)
1272
+
#define RT5645_VLO_32V (0x1 << 7)
1273
+
#define RT5645_DIG_DP_MASK (0x1 << 6)
1274
+
#define RT5645_DIG_DP_SFT 6
1275
+
#define RT5645_DIG_DP_DIS (0x0 << 6)
1276
+
#define RT5645_DIG_DP_EN (0x1 << 6)
1277
+
#define RT5645_DP_TH_MASK (0x3 << 4)
1278
+
#define RT5645_DP_TH_SFT 4
1279
+
1280
+
/* Depop Mode Control 3 (0x90) */
1281
+
#define RT5645_CP_SYS_MASK (0x7 << 12)
1282
+
#define RT5645_CP_SYS_SFT 12
1283
+
#define RT5645_CP_FQ1_MASK (0x7 << 8)
1284
+
#define RT5645_CP_FQ1_SFT 8
1285
+
#define RT5645_CP_FQ2_MASK (0x7 << 4)
1286
+
#define RT5645_CP_FQ2_SFT 4
1287
+
#define RT5645_CP_FQ3_MASK (0x7)
1288
+
#define RT5645_CP_FQ3_SFT 0
1289
+
#define RT5645_CP_FQ_1_5_KHZ 0
1290
+
#define RT5645_CP_FQ_3_KHZ 1
1291
+
#define RT5645_CP_FQ_6_KHZ 2
1292
+
#define RT5645_CP_FQ_12_KHZ 3
1293
+
#define RT5645_CP_FQ_24_KHZ 4
1294
+
#define RT5645_CP_FQ_48_KHZ 5
1295
+
#define RT5645_CP_FQ_96_KHZ 6
1296
+
#define RT5645_CP_FQ_192_KHZ 7
1297
+
1298
+
/* PV detection and SPK gain control (0x92) */
1299
+
#define RT5645_PVDD_DET_MASK (0x1 << 15)
1300
+
#define RT5645_PVDD_DET_SFT 15
1301
+
#define RT5645_PVDD_DET_DIS (0x0 << 15)
1302
+
#define RT5645_PVDD_DET_EN (0x1 << 15)
1303
+
#define RT5645_SPK_AG_MASK (0x1 << 14)
1304
+
#define RT5645_SPK_AG_SFT 14
1305
+
#define RT5645_SPK_AG_DIS (0x0 << 14)
1306
+
#define RT5645_SPK_AG_EN (0x1 << 14)
1307
+
1308
+
/* Micbias Control (0x93) */
1309
+
#define RT5645_MIC1_BS_MASK (0x1 << 15)
1310
+
#define RT5645_MIC1_BS_SFT 15
1311
+
#define RT5645_MIC1_BS_9AV (0x0 << 15)
1312
+
#define RT5645_MIC1_BS_75AV (0x1 << 15)
1313
+
#define RT5645_MIC2_BS_MASK (0x1 << 14)
1314
+
#define RT5645_MIC2_BS_SFT 14
1315
+
#define RT5645_MIC2_BS_9AV (0x0 << 14)
1316
+
#define RT5645_MIC2_BS_75AV (0x1 << 14)
1317
+
#define RT5645_MIC1_CLK_MASK (0x1 << 13)
1318
+
#define RT5645_MIC1_CLK_SFT 13
1319
+
#define RT5645_MIC1_CLK_DIS (0x0 << 13)
1320
+
#define RT5645_MIC1_CLK_EN (0x1 << 13)
1321
+
#define RT5645_MIC2_CLK_MASK (0x1 << 12)
1322
+
#define RT5645_MIC2_CLK_SFT 12
1323
+
#define RT5645_MIC2_CLK_DIS (0x0 << 12)
1324
+
#define RT5645_MIC2_CLK_EN (0x1 << 12)
1325
+
#define RT5645_MIC1_OVCD_MASK (0x1 << 11)
1326
+
#define RT5645_MIC1_OVCD_SFT 11
1327
+
#define RT5645_MIC1_OVCD_DIS (0x0 << 11)
1328
+
#define RT5645_MIC1_OVCD_EN (0x1 << 11)
1329
+
#define RT5645_MIC1_OVTH_MASK (0x3 << 9)
1330
+
#define RT5645_MIC1_OVTH_SFT 9
1331
+
#define RT5645_MIC1_OVTH_600UA (0x0 << 9)
1332
+
#define RT5645_MIC1_OVTH_1500UA (0x1 << 9)
1333
+
#define RT5645_MIC1_OVTH_2000UA (0x2 << 9)
1334
+
#define RT5645_MIC2_OVCD_MASK (0x1 << 8)
1335
+
#define RT5645_MIC2_OVCD_SFT 8
1336
+
#define RT5645_MIC2_OVCD_DIS (0x0 << 8)
1337
+
#define RT5645_MIC2_OVCD_EN (0x1 << 8)
1338
+
#define RT5645_MIC2_OVTH_MASK (0x3 << 6)
1339
+
#define RT5645_MIC2_OVTH_SFT 6
1340
+
#define RT5645_MIC2_OVTH_600UA (0x0 << 6)
1341
+
#define RT5645_MIC2_OVTH_1500UA (0x1 << 6)
1342
+
#define RT5645_MIC2_OVTH_2000UA (0x2 << 6)
1343
+
#define RT5645_PWR_MB_MASK (0x1 << 5)
1344
+
#define RT5645_PWR_MB_SFT 5
1345
+
#define RT5645_PWR_MB_PD (0x0 << 5)
1346
+
#define RT5645_PWR_MB_PU (0x1 << 5)
1347
+
#define RT5645_PWR_CLK25M_MASK (0x1 << 4)
1348
+
#define RT5645_PWR_CLK25M_SFT 4
1349
+
#define RT5645_PWR_CLK25M_PD (0x0 << 4)
1350
+
#define RT5645_PWR_CLK25M_PU (0x1 << 4)
1351
+
1352
+
/* VAD Control 4 (0x9d) */
1353
+
#define RT5645_VAD_SEL_MASK (0x3 << 8)
1354
+
#define RT5645_VAD_SEL_SFT 8
1355
+
1356
+
/* EQ Control 1 (0xb0) */
1357
+
#define RT5645_EQ_SRC_MASK (0x1 << 15)
1358
+
#define RT5645_EQ_SRC_SFT 15
1359
+
#define RT5645_EQ_SRC_DAC (0x0 << 15)
1360
+
#define RT5645_EQ_SRC_ADC (0x1 << 15)
1361
+
#define RT5645_EQ_UPD (0x1 << 14)
1362
+
#define RT5645_EQ_UPD_BIT 14
1363
+
#define RT5645_EQ_CD_MASK (0x1 << 13)
1364
+
#define RT5645_EQ_CD_SFT 13
1365
+
#define RT5645_EQ_CD_DIS (0x0 << 13)
1366
+
#define RT5645_EQ_CD_EN (0x1 << 13)
1367
+
#define RT5645_EQ_DITH_MASK (0x3 << 8)
1368
+
#define RT5645_EQ_DITH_SFT 8
1369
+
#define RT5645_EQ_DITH_NOR (0x0 << 8)
1370
+
#define RT5645_EQ_DITH_LSB (0x1 << 8)
1371
+
#define RT5645_EQ_DITH_LSB_1 (0x2 << 8)
1372
+
#define RT5645_EQ_DITH_LSB_2 (0x3 << 8)
1373
+
1374
+
/* EQ Control 2 (0xb1) */
1375
+
#define RT5645_EQ_HPF1_M_MASK (0x1 << 8)
1376
+
#define RT5645_EQ_HPF1_M_SFT 8
1377
+
#define RT5645_EQ_HPF1_M_HI (0x0 << 8)
1378
+
#define RT5645_EQ_HPF1_M_1ST (0x1 << 8)
1379
+
#define RT5645_EQ_LPF1_M_MASK (0x1 << 7)
1380
+
#define RT5645_EQ_LPF1_M_SFT 7
1381
+
#define RT5645_EQ_LPF1_M_LO (0x0 << 7)
1382
+
#define RT5645_EQ_LPF1_M_1ST (0x1 << 7)
1383
+
#define RT5645_EQ_HPF2_MASK (0x1 << 6)
1384
+
#define RT5645_EQ_HPF2_SFT 6
1385
+
#define RT5645_EQ_HPF2_DIS (0x0 << 6)
1386
+
#define RT5645_EQ_HPF2_EN (0x1 << 6)
1387
+
#define RT5645_EQ_HPF1_MASK (0x1 << 5)
1388
+
#define RT5645_EQ_HPF1_SFT 5
1389
+
#define RT5645_EQ_HPF1_DIS (0x0 << 5)
1390
+
#define RT5645_EQ_HPF1_EN (0x1 << 5)
1391
+
#define RT5645_EQ_BPF4_MASK (0x1 << 4)
1392
+
#define RT5645_EQ_BPF4_SFT 4
1393
+
#define RT5645_EQ_BPF4_DIS (0x0 << 4)
1394
+
#define RT5645_EQ_BPF4_EN (0x1 << 4)
1395
+
#define RT5645_EQ_BPF3_MASK (0x1 << 3)
1396
+
#define RT5645_EQ_BPF3_SFT 3
1397
+
#define RT5645_EQ_BPF3_DIS (0x0 << 3)
1398
+
#define RT5645_EQ_BPF3_EN (0x1 << 3)
1399
+
#define RT5645_EQ_BPF2_MASK (0x1 << 2)
1400
+
#define RT5645_EQ_BPF2_SFT 2
1401
+
#define RT5645_EQ_BPF2_DIS (0x0 << 2)
1402
+
#define RT5645_EQ_BPF2_EN (0x1 << 2)
1403
+
#define RT5645_EQ_BPF1_MASK (0x1 << 1)
1404
+
#define RT5645_EQ_BPF1_SFT 1
1405
+
#define RT5645_EQ_BPF1_DIS (0x0 << 1)
1406
+
#define RT5645_EQ_BPF1_EN (0x1 << 1)
1407
+
#define RT5645_EQ_LPF_MASK (0x1)
1408
+
#define RT5645_EQ_LPF_SFT 0
1409
+
#define RT5645_EQ_LPF_DIS (0x0)
1410
+
#define RT5645_EQ_LPF_EN (0x1)
1411
+
#define RT5645_EQ_CTRL_MASK (0x7f)
1412
+
1413
+
/* Memory Test (0xb2) */
1414
+
#define RT5645_MT_MASK (0x1 << 15)
1415
+
#define RT5645_MT_SFT 15
1416
+
#define RT5645_MT_DIS (0x0 << 15)
1417
+
#define RT5645_MT_EN (0x1 << 15)
1418
+
1419
+
/* DRC/AGC Control 1 (0xb4) */
1420
+
#define RT5645_DRC_AGC_P_MASK (0x1 << 15)
1421
+
#define RT5645_DRC_AGC_P_SFT 15
1422
+
#define RT5645_DRC_AGC_P_DAC (0x0 << 15)
1423
+
#define RT5645_DRC_AGC_P_ADC (0x1 << 15)
1424
+
#define RT5645_DRC_AGC_MASK (0x1 << 14)
1425
+
#define RT5645_DRC_AGC_SFT 14
1426
+
#define RT5645_DRC_AGC_DIS (0x0 << 14)
1427
+
#define RT5645_DRC_AGC_EN (0x1 << 14)
1428
+
#define RT5645_DRC_AGC_UPD (0x1 << 13)
1429
+
#define RT5645_DRC_AGC_UPD_BIT 13
1430
+
#define RT5645_DRC_AGC_AR_MASK (0x1f << 8)
1431
+
#define RT5645_DRC_AGC_AR_SFT 8
1432
+
#define RT5645_DRC_AGC_R_MASK (0x7 << 5)
1433
+
#define RT5645_DRC_AGC_R_SFT 5
1434
+
#define RT5645_DRC_AGC_R_48K (0x1 << 5)
1435
+
#define RT5645_DRC_AGC_R_96K (0x2 << 5)
1436
+
#define RT5645_DRC_AGC_R_192K (0x3 << 5)
1437
+
#define RT5645_DRC_AGC_R_441K (0x5 << 5)
1438
+
#define RT5645_DRC_AGC_R_882K (0x6 << 5)
1439
+
#define RT5645_DRC_AGC_R_1764K (0x7 << 5)
1440
+
#define RT5645_DRC_AGC_RC_MASK (0x1f)
1441
+
#define RT5645_DRC_AGC_RC_SFT 0
1442
+
1443
+
/* DRC/AGC Control 2 (0xb5) */
1444
+
#define RT5645_DRC_AGC_POB_MASK (0x3f << 8)
1445
+
#define RT5645_DRC_AGC_POB_SFT 8
1446
+
#define RT5645_DRC_AGC_CP_MASK (0x1 << 7)
1447
+
#define RT5645_DRC_AGC_CP_SFT 7
1448
+
#define RT5645_DRC_AGC_CP_DIS (0x0 << 7)
1449
+
#define RT5645_DRC_AGC_CP_EN (0x1 << 7)
1450
+
#define RT5645_DRC_AGC_CPR_MASK (0x3 << 5)
1451
+
#define RT5645_DRC_AGC_CPR_SFT 5
1452
+
#define RT5645_DRC_AGC_CPR_1_1 (0x0 << 5)
1453
+
#define RT5645_DRC_AGC_CPR_1_2 (0x1 << 5)
1454
+
#define RT5645_DRC_AGC_CPR_1_3 (0x2 << 5)
1455
+
#define RT5645_DRC_AGC_CPR_1_4 (0x3 << 5)
1456
+
#define RT5645_DRC_AGC_PRB_MASK (0x1f)
1457
+
#define RT5645_DRC_AGC_PRB_SFT 0
1458
+
1459
+
/* DRC/AGC Control 3 (0xb6) */
1460
+
#define RT5645_DRC_AGC_NGB_MASK (0xf << 12)
1461
+
#define RT5645_DRC_AGC_NGB_SFT 12
1462
+
#define RT5645_DRC_AGC_TAR_MASK (0x1f << 7)
1463
+
#define RT5645_DRC_AGC_TAR_SFT 7
1464
+
#define RT5645_DRC_AGC_NG_MASK (0x1 << 6)
1465
+
#define RT5645_DRC_AGC_NG_SFT 6
1466
+
#define RT5645_DRC_AGC_NG_DIS (0x0 << 6)
1467
+
#define RT5645_DRC_AGC_NG_EN (0x1 << 6)
1468
+
#define RT5645_DRC_AGC_NGH_MASK (0x1 << 5)
1469
+
#define RT5645_DRC_AGC_NGH_SFT 5
1470
+
#define RT5645_DRC_AGC_NGH_DIS (0x0 << 5)
1471
+
#define RT5645_DRC_AGC_NGH_EN (0x1 << 5)
1472
+
#define RT5645_DRC_AGC_NGT_MASK (0x1f)
1473
+
#define RT5645_DRC_AGC_NGT_SFT 0
1474
+
1475
+
/* ANC Control 1 (0xb8) */
1476
+
#define RT5645_ANC_M_MASK (0x1 << 15)
1477
+
#define RT5645_ANC_M_SFT 15
1478
+
#define RT5645_ANC_M_NOR (0x0 << 15)
1479
+
#define RT5645_ANC_M_REV (0x1 << 15)
1480
+
#define RT5645_ANC_MASK (0x1 << 14)
1481
+
#define RT5645_ANC_SFT 14
1482
+
#define RT5645_ANC_DIS (0x0 << 14)
1483
+
#define RT5645_ANC_EN (0x1 << 14)
1484
+
#define RT5645_ANC_MD_MASK (0x3 << 12)
1485
+
#define RT5645_ANC_MD_SFT 12
1486
+
#define RT5645_ANC_MD_DIS (0x0 << 12)
1487
+
#define RT5645_ANC_MD_67MS (0x1 << 12)
1488
+
#define RT5645_ANC_MD_267MS (0x2 << 12)
1489
+
#define RT5645_ANC_MD_1067MS (0x3 << 12)
1490
+
#define RT5645_ANC_SN_MASK (0x1 << 11)
1491
+
#define RT5645_ANC_SN_SFT 11
1492
+
#define RT5645_ANC_SN_DIS (0x0 << 11)
1493
+
#define RT5645_ANC_SN_EN (0x1 << 11)
1494
+
#define RT5645_ANC_CLK_MASK (0x1 << 10)
1495
+
#define RT5645_ANC_CLK_SFT 10
1496
+
#define RT5645_ANC_CLK_ANC (0x0 << 10)
1497
+
#define RT5645_ANC_CLK_REG (0x1 << 10)
1498
+
#define RT5645_ANC_ZCD_MASK (0x3 << 8)
1499
+
#define RT5645_ANC_ZCD_SFT 8
1500
+
#define RT5645_ANC_ZCD_DIS (0x0 << 8)
1501
+
#define RT5645_ANC_ZCD_T1 (0x1 << 8)
1502
+
#define RT5645_ANC_ZCD_T2 (0x2 << 8)
1503
+
#define RT5645_ANC_ZCD_WT (0x3 << 8)
1504
+
#define RT5645_ANC_CS_MASK (0x1 << 7)
1505
+
#define RT5645_ANC_CS_SFT 7
1506
+
#define RT5645_ANC_CS_DIS (0x0 << 7)
1507
+
#define RT5645_ANC_CS_EN (0x1 << 7)
1508
+
#define RT5645_ANC_SW_MASK (0x1 << 6)
1509
+
#define RT5645_ANC_SW_SFT 6
1510
+
#define RT5645_ANC_SW_NOR (0x0 << 6)
1511
+
#define RT5645_ANC_SW_AUTO (0x1 << 6)
1512
+
#define RT5645_ANC_CO_L_MASK (0x3f)
1513
+
#define RT5645_ANC_CO_L_SFT 0
1514
+
1515
+
/* ANC Control 2 (0xb6) */
1516
+
#define RT5645_ANC_FG_R_MASK (0xf << 12)
1517
+
#define RT5645_ANC_FG_R_SFT 12
1518
+
#define RT5645_ANC_FG_L_MASK (0xf << 8)
1519
+
#define RT5645_ANC_FG_L_SFT 8
1520
+
#define RT5645_ANC_CG_R_MASK (0xf << 4)
1521
+
#define RT5645_ANC_CG_R_SFT 4
1522
+
#define RT5645_ANC_CG_L_MASK (0xf)
1523
+
#define RT5645_ANC_CG_L_SFT 0
1524
+
1525
+
/* ANC Control 3 (0xb6) */
1526
+
#define RT5645_ANC_CD_MASK (0x1 << 6)
1527
+
#define RT5645_ANC_CD_SFT 6
1528
+
#define RT5645_ANC_CD_BOTH (0x0 << 6)
1529
+
#define RT5645_ANC_CD_IND (0x1 << 6)
1530
+
#define RT5645_ANC_CO_R_MASK (0x3f)
1531
+
#define RT5645_ANC_CO_R_SFT 0
1532
+
1533
+
/* Jack Detect Control (0xbb) */
1534
+
#define RT5645_JD_MASK (0x7 << 13)
1535
+
#define RT5645_JD_SFT 13
1536
+
#define RT5645_JD_DIS (0x0 << 13)
1537
+
#define RT5645_JD_GPIO1 (0x1 << 13)
1538
+
#define RT5645_JD_JD1_IN4P (0x2 << 13)
1539
+
#define RT5645_JD_JD2_IN4N (0x3 << 13)
1540
+
#define RT5645_JD_GPIO2 (0x4 << 13)
1541
+
#define RT5645_JD_GPIO3 (0x5 << 13)
1542
+
#define RT5645_JD_GPIO4 (0x6 << 13)
1543
+
#define RT5645_JD_HP_MASK (0x1 << 11)
1544
+
#define RT5645_JD_HP_SFT 11
1545
+
#define RT5645_JD_HP_DIS (0x0 << 11)
1546
+
#define RT5645_JD_HP_EN (0x1 << 11)
1547
+
#define RT5645_JD_HP_TRG_MASK (0x1 << 10)
1548
+
#define RT5645_JD_HP_TRG_SFT 10
1549
+
#define RT5645_JD_HP_TRG_LO (0x0 << 10)
1550
+
#define RT5645_JD_HP_TRG_HI (0x1 << 10)
1551
+
#define RT5645_JD_SPL_MASK (0x1 << 9)
1552
+
#define RT5645_JD_SPL_SFT 9
1553
+
#define RT5645_JD_SPL_DIS (0x0 << 9)
1554
+
#define RT5645_JD_SPL_EN (0x1 << 9)
1555
+
#define RT5645_JD_SPL_TRG_MASK (0x1 << 8)
1556
+
#define RT5645_JD_SPL_TRG_SFT 8
1557
+
#define RT5645_JD_SPL_TRG_LO (0x0 << 8)
1558
+
#define RT5645_JD_SPL_TRG_HI (0x1 << 8)
1559
+
#define RT5645_JD_SPR_MASK (0x1 << 7)
1560
+
#define RT5645_JD_SPR_SFT 7
1561
+
#define RT5645_JD_SPR_DIS (0x0 << 7)
1562
+
#define RT5645_JD_SPR_EN (0x1 << 7)
1563
+
#define RT5645_JD_SPR_TRG_MASK (0x1 << 6)
1564
+
#define RT5645_JD_SPR_TRG_SFT 6
1565
+
#define RT5645_JD_SPR_TRG_LO (0x0 << 6)
1566
+
#define RT5645_JD_SPR_TRG_HI (0x1 << 6)
1567
+
#define RT5645_JD_MO_MASK (0x1 << 5)
1568
+
#define RT5645_JD_MO_SFT 5
1569
+
#define RT5645_JD_MO_DIS (0x0 << 5)
1570
+
#define RT5645_JD_MO_EN (0x1 << 5)
1571
+
#define RT5645_JD_MO_TRG_MASK (0x1 << 4)
1572
+
#define RT5645_JD_MO_TRG_SFT 4
1573
+
#define RT5645_JD_MO_TRG_LO (0x0 << 4)
1574
+
#define RT5645_JD_MO_TRG_HI (0x1 << 4)
1575
+
#define RT5645_JD_LO_MASK (0x1 << 3)
1576
+
#define RT5645_JD_LO_SFT 3
1577
+
#define RT5645_JD_LO_DIS (0x0 << 3)
1578
+
#define RT5645_JD_LO_EN (0x1 << 3)
1579
+
#define RT5645_JD_LO_TRG_MASK (0x1 << 2)
1580
+
#define RT5645_JD_LO_TRG_SFT 2
1581
+
#define RT5645_JD_LO_TRG_LO (0x0 << 2)
1582
+
#define RT5645_JD_LO_TRG_HI (0x1 << 2)
1583
+
#define RT5645_JD1_IN4P_MASK (0x1 << 1)
1584
+
#define RT5645_JD1_IN4P_SFT 1
1585
+
#define RT5645_JD1_IN4P_DIS (0x0 << 1)
1586
+
#define RT5645_JD1_IN4P_EN (0x1 << 1)
1587
+
#define RT5645_JD2_IN4N_MASK (0x1)
1588
+
#define RT5645_JD2_IN4N_SFT 0
1589
+
#define RT5645_JD2_IN4N_DIS (0x0)
1590
+
#define RT5645_JD2_IN4N_EN (0x1)
1591
+
1592
+
/* Jack detect for ANC (0xbc) */
1593
+
#define RT5645_ANC_DET_MASK (0x3 << 4)
1594
+
#define RT5645_ANC_DET_SFT 4
1595
+
#define RT5645_ANC_DET_DIS (0x0 << 4)
1596
+
#define RT5645_ANC_DET_MB1 (0x1 << 4)
1597
+
#define RT5645_ANC_DET_MB2 (0x2 << 4)
1598
+
#define RT5645_ANC_DET_JD (0x3 << 4)
1599
+
#define RT5645_AD_TRG_MASK (0x1 << 3)
1600
+
#define RT5645_AD_TRG_SFT 3
1601
+
#define RT5645_AD_TRG_LO (0x0 << 3)
1602
+
#define RT5645_AD_TRG_HI (0x1 << 3)
1603
+
#define RT5645_ANCM_DET_MASK (0x3 << 4)
1604
+
#define RT5645_ANCM_DET_SFT 4
1605
+
#define RT5645_ANCM_DET_DIS (0x0 << 4)
1606
+
#define RT5645_ANCM_DET_MB1 (0x1 << 4)
1607
+
#define RT5645_ANCM_DET_MB2 (0x2 << 4)
1608
+
#define RT5645_ANCM_DET_JD (0x3 << 4)
1609
+
#define RT5645_AMD_TRG_MASK (0x1 << 3)
1610
+
#define RT5645_AMD_TRG_SFT 3
1611
+
#define RT5645_AMD_TRG_LO (0x0 << 3)
1612
+
#define RT5645_AMD_TRG_HI (0x1 << 3)
1613
+
1614
+
/* IRQ Control 1 (0xbd) */
1615
+
#define RT5645_IRQ_JD_MASK (0x1 << 15)
1616
+
#define RT5645_IRQ_JD_SFT 15
1617
+
#define RT5645_IRQ_JD_BP (0x0 << 15)
1618
+
#define RT5645_IRQ_JD_NOR (0x1 << 15)
1619
+
#define RT5645_IRQ_OT_MASK (0x1 << 14)
1620
+
#define RT5645_IRQ_OT_SFT 14
1621
+
#define RT5645_IRQ_OT_BP (0x0 << 14)
1622
+
#define RT5645_IRQ_OT_NOR (0x1 << 14)
1623
+
#define RT5645_JD_STKY_MASK (0x1 << 13)
1624
+
#define RT5645_JD_STKY_SFT 13
1625
+
#define RT5645_JD_STKY_DIS (0x0 << 13)
1626
+
#define RT5645_JD_STKY_EN (0x1 << 13)
1627
+
#define RT5645_OT_STKY_MASK (0x1 << 12)
1628
+
#define RT5645_OT_STKY_SFT 12
1629
+
#define RT5645_OT_STKY_DIS (0x0 << 12)
1630
+
#define RT5645_OT_STKY_EN (0x1 << 12)
1631
+
#define RT5645_JD_P_MASK (0x1 << 11)
1632
+
#define RT5645_JD_P_SFT 11
1633
+
#define RT5645_JD_P_NOR (0x0 << 11)
1634
+
#define RT5645_JD_P_INV (0x1 << 11)
1635
+
#define RT5645_OT_P_MASK (0x1 << 10)
1636
+
#define RT5645_OT_P_SFT 10
1637
+
#define RT5645_OT_P_NOR (0x0 << 10)
1638
+
#define RT5645_OT_P_INV (0x1 << 10)
1639
+
1640
+
/* IRQ Control 2 (0xbe) */
1641
+
#define RT5645_IRQ_MB1_OC_MASK (0x1 << 15)
1642
+
#define RT5645_IRQ_MB1_OC_SFT 15
1643
+
#define RT5645_IRQ_MB1_OC_BP (0x0 << 15)
1644
+
#define RT5645_IRQ_MB1_OC_NOR (0x1 << 15)
1645
+
#define RT5645_IRQ_MB2_OC_MASK (0x1 << 14)
1646
+
#define RT5645_IRQ_MB2_OC_SFT 14
1647
+
#define RT5645_IRQ_MB2_OC_BP (0x0 << 14)
1648
+
#define RT5645_IRQ_MB2_OC_NOR (0x1 << 14)
1649
+
#define RT5645_MB1_OC_STKY_MASK (0x1 << 13)
1650
+
#define RT5645_MB1_OC_STKY_SFT 13
1651
+
#define RT5645_MB1_OC_STKY_DIS (0x0 << 13)
1652
+
#define RT5645_MB1_OC_STKY_EN (0x1 << 13)
1653
+
#define RT5645_MB2_OC_STKY_MASK (0x1 << 12)
1654
+
#define RT5645_MB2_OC_STKY_SFT 12
1655
+
#define RT5645_MB2_OC_STKY_DIS (0x0 << 12)
1656
+
#define RT5645_MB2_OC_STKY_EN (0x1 << 12)
1657
+
#define RT5645_MB1_OC_P_MASK (0x1 << 7)
1658
+
#define RT5645_MB1_OC_P_SFT 7
1659
+
#define RT5645_MB1_OC_P_NOR (0x0 << 7)
1660
+
#define RT5645_MB1_OC_P_INV (0x1 << 7)
1661
+
#define RT5645_MB2_OC_P_MASK (0x1 << 6)
1662
+
#define RT5645_MB2_OC_P_SFT 6
1663
+
#define RT5645_MB2_OC_P_NOR (0x0 << 6)
1664
+
#define RT5645_MB2_OC_P_INV (0x1 << 6)
1665
+
#define RT5645_MB1_OC_CLR (0x1 << 3)
1666
+
#define RT5645_MB1_OC_CLR_SFT 3
1667
+
#define RT5645_MB2_OC_CLR (0x1 << 2)
1668
+
#define RT5645_MB2_OC_CLR_SFT 2
1669
+
1670
+
/* GPIO Control 1 (0xc0) */
1671
+
#define RT5645_GP1_PIN_MASK (0x1 << 15)
1672
+
#define RT5645_GP1_PIN_SFT 15
1673
+
#define RT5645_GP1_PIN_GPIO1 (0x0 << 15)
1674
+
#define RT5645_GP1_PIN_IRQ (0x1 << 15)
1675
+
#define RT5645_GP2_PIN_MASK (0x1 << 14)
1676
+
#define RT5645_GP2_PIN_SFT 14
1677
+
#define RT5645_GP2_PIN_GPIO2 (0x0 << 14)
1678
+
#define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14)
1679
+
#define RT5645_GP3_PIN_MASK (0x3 << 12)
1680
+
#define RT5645_GP3_PIN_SFT 12
1681
+
#define RT5645_GP3_PIN_GPIO3 (0x0 << 12)
1682
+
#define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12)
1683
+
#define RT5645_GP3_PIN_IRQ (0x2 << 12)
1684
+
#define RT5645_GP4_PIN_MASK (0x1 << 11)
1685
+
#define RT5645_GP4_PIN_SFT 11
1686
+
#define RT5645_GP4_PIN_GPIO4 (0x0 << 11)
1687
+
#define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11)
1688
+
#define RT5645_DP_SIG_MASK (0x1 << 10)
1689
+
#define RT5645_DP_SIG_SFT 10
1690
+
#define RT5645_DP_SIG_TEST (0x0 << 10)
1691
+
#define RT5645_DP_SIG_AP (0x1 << 10)
1692
+
#define RT5645_GPIO_M_MASK (0x1 << 9)
1693
+
#define RT5645_GPIO_M_SFT 9
1694
+
#define RT5645_GPIO_M_FLT (0x0 << 9)
1695
+
#define RT5645_GPIO_M_PH (0x1 << 9)
1696
+
#define RT5645_I2S2_SEL (0x1 << 8)
1697
+
#define RT5645_I2S2_SEL_SFT 8
1698
+
#define RT5645_GP5_PIN_MASK (0x1 << 7)
1699
+
#define RT5645_GP5_PIN_SFT 7
1700
+
#define RT5645_GP5_PIN_GPIO5 (0x0 << 7)
1701
+
#define RT5645_GP5_PIN_DMIC1_SDA (0x1 << 7)
1702
+
#define RT5645_GP6_PIN_MASK (0x1 << 6)
1703
+
#define RT5645_GP6_PIN_SFT 6
1704
+
#define RT5645_GP6_PIN_GPIO6 (0x0 << 6)
1705
+
#define RT5645_GP6_PIN_DMIC2_SDA (0x1 << 6)
1706
+
#define RT5645_GP8_PIN_MASK (0x1 << 3)
1707
+
#define RT5645_GP8_PIN_SFT 3
1708
+
#define RT5645_GP8_PIN_GPIO8 (0x0 << 3)
1709
+
#define RT5645_GP8_PIN_DMIC2_SDA (0x1 << 3)
1710
+
#define RT5645_GP12_PIN_MASK (0x1 << 2)
1711
+
#define RT5645_GP12_PIN_SFT 2
1712
+
#define RT5645_GP12_PIN_GPIO12 (0x0 << 2)
1713
+
#define RT5645_GP12_PIN_DMIC2_SDA (0x1 << 2)
1714
+
#define RT5645_GP11_PIN_MASK (0x1 << 1)
1715
+
#define RT5645_GP11_PIN_SFT 1
1716
+
#define RT5645_GP11_PIN_GPIO11 (0x0 << 1)
1717
+
#define RT5645_GP11_PIN_DMIC1_SDA (0x1 << 1)
1718
+
#define RT5645_GP10_PIN_MASK (0x1)
1719
+
#define RT5645_GP10_PIN_SFT 0
1720
+
#define RT5645_GP10_PIN_GPIO10 (0x0)
1721
+
#define RT5645_GP10_PIN_DMIC2_SDA (0x1)
1722
+
1723
+
/* GPIO Control 3 (0xc2) */
1724
+
#define RT5645_GP4_PF_MASK (0x1 << 11)
1725
+
#define RT5645_GP4_PF_SFT 11
1726
+
#define RT5645_GP4_PF_IN (0x0 << 11)
1727
+
#define RT5645_GP4_PF_OUT (0x1 << 11)
1728
+
#define RT5645_GP4_OUT_MASK (0x1 << 10)
1729
+
#define RT5645_GP4_OUT_SFT 10
1730
+
#define RT5645_GP4_OUT_LO (0x0 << 10)
1731
+
#define RT5645_GP4_OUT_HI (0x1 << 10)
1732
+
#define RT5645_GP4_P_MASK (0x1 << 9)
1733
+
#define RT5645_GP4_P_SFT 9
1734
+
#define RT5645_GP4_P_NOR (0x0 << 9)
1735
+
#define RT5645_GP4_P_INV (0x1 << 9)
1736
+
#define RT5645_GP3_PF_MASK (0x1 << 8)
1737
+
#define RT5645_GP3_PF_SFT 8
1738
+
#define RT5645_GP3_PF_IN (0x0 << 8)
1739
+
#define RT5645_GP3_PF_OUT (0x1 << 8)
1740
+
#define RT5645_GP3_OUT_MASK (0x1 << 7)
1741
+
#define RT5645_GP3_OUT_SFT 7
1742
+
#define RT5645_GP3_OUT_LO (0x0 << 7)
1743
+
#define RT5645_GP3_OUT_HI (0x1 << 7)
1744
+
#define RT5645_GP3_P_MASK (0x1 << 6)
1745
+
#define RT5645_GP3_P_SFT 6
1746
+
#define RT5645_GP3_P_NOR (0x0 << 6)
1747
+
#define RT5645_GP3_P_INV (0x1 << 6)
1748
+
#define RT5645_GP2_PF_MASK (0x1 << 5)
1749
+
#define RT5645_GP2_PF_SFT 5
1750
+
#define RT5645_GP2_PF_IN (0x0 << 5)
1751
+
#define RT5645_GP2_PF_OUT (0x1 << 5)
1752
+
#define RT5645_GP2_OUT_MASK (0x1 << 4)
1753
+
#define RT5645_GP2_OUT_SFT 4
1754
+
#define RT5645_GP2_OUT_LO (0x0 << 4)
1755
+
#define RT5645_GP2_OUT_HI (0x1 << 4)
1756
+
#define RT5645_GP2_P_MASK (0x1 << 3)
1757
+
#define RT5645_GP2_P_SFT 3
1758
+
#define RT5645_GP2_P_NOR (0x0 << 3)
1759
+
#define RT5645_GP2_P_INV (0x1 << 3)
1760
+
#define RT5645_GP1_PF_MASK (0x1 << 2)
1761
+
#define RT5645_GP1_PF_SFT 2
1762
+
#define RT5645_GP1_PF_IN (0x0 << 2)
1763
+
#define RT5645_GP1_PF_OUT (0x1 << 2)
1764
+
#define RT5645_GP1_OUT_MASK (0x1 << 1)
1765
+
#define RT5645_GP1_OUT_SFT 1
1766
+
#define RT5645_GP1_OUT_LO (0x0 << 1)
1767
+
#define RT5645_GP1_OUT_HI (0x1 << 1)
1768
+
#define RT5645_GP1_P_MASK (0x1)
1769
+
#define RT5645_GP1_P_SFT 0
1770
+
#define RT5645_GP1_P_NOR (0x0)
1771
+
#define RT5645_GP1_P_INV (0x1)
1772
+
1773
+
/* Programmable Register Array Control 1 (0xc8) */
1774
+
#define RT5645_REG_SEQ_MASK (0xf << 12)
1775
+
#define RT5645_REG_SEQ_SFT 12
1776
+
#define RT5645_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1777
+
#define RT5645_SEQ1_ST_SFT 11
1778
+
#define RT5645_SEQ1_ST_RUN (0x0 << 11)
1779
+
#define RT5645_SEQ1_ST_FIN (0x1 << 11)
1780
+
#define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1781
+
#define RT5645_SEQ2_ST_SFT 10
1782
+
#define RT5645_SEQ2_ST_RUN (0x0 << 10)
1783
+
#define RT5645_SEQ2_ST_FIN (0x1 << 10)
1784
+
#define RT5645_REG_LV_MASK (0x1 << 9)
1785
+
#define RT5645_REG_LV_SFT 9
1786
+
#define RT5645_REG_LV_MX (0x0 << 9)
1787
+
#define RT5645_REG_LV_PR (0x1 << 9)
1788
+
#define RT5645_SEQ_2_PT_MASK (0x1 << 8)
1789
+
#define RT5645_SEQ_2_PT_BIT 8
1790
+
#define RT5645_REG_IDX_MASK (0xff)
1791
+
#define RT5645_REG_IDX_SFT 0
1792
+
1793
+
/* Programmable Register Array Control 2 (0xc9) */
1794
+
#define RT5645_REG_DAT_MASK (0xffff)
1795
+
#define RT5645_REG_DAT_SFT 0
1796
+
1797
+
/* Programmable Register Array Control 3 (0xca) */
1798
+
#define RT5645_SEQ_DLY_MASK (0xff << 8)
1799
+
#define RT5645_SEQ_DLY_SFT 8
1800
+
#define RT5645_PROG_MASK (0x1 << 7)
1801
+
#define RT5645_PROG_SFT 7
1802
+
#define RT5645_PROG_DIS (0x0 << 7)
1803
+
#define RT5645_PROG_EN (0x1 << 7)
1804
+
#define RT5645_SEQ1_PT_RUN (0x1 << 6)
1805
+
#define RT5645_SEQ1_PT_RUN_BIT 6
1806
+
#define RT5645_SEQ2_PT_RUN (0x1 << 5)
1807
+
#define RT5645_SEQ2_PT_RUN_BIT 5
1808
+
1809
+
/* Programmable Register Array Control 4 (0xcb) */
1810
+
#define RT5645_SEQ1_START_MASK (0xf << 8)
1811
+
#define RT5645_SEQ1_START_SFT 8
1812
+
#define RT5645_SEQ1_END_MASK (0xf)
1813
+
#define RT5645_SEQ1_END_SFT 0
1814
+
1815
+
/* Programmable Register Array Control 5 (0xcc) */
1816
+
#define RT5645_SEQ2_START_MASK (0xf << 8)
1817
+
#define RT5645_SEQ2_START_SFT 8
1818
+
#define RT5645_SEQ2_END_MASK (0xf)
1819
+
#define RT5645_SEQ2_END_SFT 0
1820
+
1821
+
/* Scramble Function (0xcd) */
1822
+
#define RT5645_SCB_KEY_MASK (0xff)
1823
+
#define RT5645_SCB_KEY_SFT 0
1824
+
1825
+
/* Scramble Control (0xce) */
1826
+
#define RT5645_SCB_SWAP_MASK (0x1 << 15)
1827
+
#define RT5645_SCB_SWAP_SFT 15
1828
+
#define RT5645_SCB_SWAP_DIS (0x0 << 15)
1829
+
#define RT5645_SCB_SWAP_EN (0x1 << 15)
1830
+
#define RT5645_SCB_MASK (0x1 << 14)
1831
+
#define RT5645_SCB_SFT 14
1832
+
#define RT5645_SCB_DIS (0x0 << 14)
1833
+
#define RT5645_SCB_EN (0x1 << 14)
1834
+
1835
+
/* Baseback Control (0xcf) */
1836
+
#define RT5645_BB_MASK (0x1 << 15)
1837
+
#define RT5645_BB_SFT 15
1838
+
#define RT5645_BB_DIS (0x0 << 15)
1839
+
#define RT5645_BB_EN (0x1 << 15)
1840
+
#define RT5645_BB_CT_MASK (0x7 << 12)
1841
+
#define RT5645_BB_CT_SFT 12
1842
+
#define RT5645_BB_CT_A (0x0 << 12)
1843
+
#define RT5645_BB_CT_B (0x1 << 12)
1844
+
#define RT5645_BB_CT_C (0x2 << 12)
1845
+
#define RT5645_BB_CT_D (0x3 << 12)
1846
+
#define RT5645_M_BB_L_MASK (0x1 << 9)
1847
+
#define RT5645_M_BB_L_SFT 9
1848
+
#define RT5645_M_BB_R_MASK (0x1 << 8)
1849
+
#define RT5645_M_BB_R_SFT 8
1850
+
#define RT5645_M_BB_HPF_L_MASK (0x1 << 7)
1851
+
#define RT5645_M_BB_HPF_L_SFT 7
1852
+
#define RT5645_M_BB_HPF_R_MASK (0x1 << 6)
1853
+
#define RT5645_M_BB_HPF_R_SFT 6
1854
+
#define RT5645_G_BB_BST_MASK (0x3f)
1855
+
#define RT5645_G_BB_BST_SFT 0
1856
+
1857
+
/* MP3 Plus Control 1 (0xd0) */
1858
+
#define RT5645_M_MP3_L_MASK (0x1 << 15)
1859
+
#define RT5645_M_MP3_L_SFT 15
1860
+
#define RT5645_M_MP3_R_MASK (0x1 << 14)
1861
+
#define RT5645_M_MP3_R_SFT 14
1862
+
#define RT5645_M_MP3_MASK (0x1 << 13)
1863
+
#define RT5645_M_MP3_SFT 13
1864
+
#define RT5645_M_MP3_DIS (0x0 << 13)
1865
+
#define RT5645_M_MP3_EN (0x1 << 13)
1866
+
#define RT5645_EG_MP3_MASK (0x1f << 8)
1867
+
#define RT5645_EG_MP3_SFT 8
1868
+
#define RT5645_MP3_HLP_MASK (0x1 << 7)
1869
+
#define RT5645_MP3_HLP_SFT 7
1870
+
#define RT5645_MP3_HLP_DIS (0x0 << 7)
1871
+
#define RT5645_MP3_HLP_EN (0x1 << 7)
1872
+
#define RT5645_M_MP3_ORG_L_MASK (0x1 << 6)
1873
+
#define RT5645_M_MP3_ORG_L_SFT 6
1874
+
#define RT5645_M_MP3_ORG_R_MASK (0x1 << 5)
1875
+
#define RT5645_M_MP3_ORG_R_SFT 5
1876
+
1877
+
/* MP3 Plus Control 2 (0xd1) */
1878
+
#define RT5645_MP3_WT_MASK (0x1 << 13)
1879
+
#define RT5645_MP3_WT_SFT 13
1880
+
#define RT5645_MP3_WT_1_4 (0x0 << 13)
1881
+
#define RT5645_MP3_WT_1_2 (0x1 << 13)
1882
+
#define RT5645_OG_MP3_MASK (0x1f << 8)
1883
+
#define RT5645_OG_MP3_SFT 8
1884
+
#define RT5645_HG_MP3_MASK (0x3f)
1885
+
#define RT5645_HG_MP3_SFT 0
1886
+
1887
+
/* 3D HP Control 1 (0xd2) */
1888
+
#define RT5645_3D_CF_MASK (0x1 << 15)
1889
+
#define RT5645_3D_CF_SFT 15
1890
+
#define RT5645_3D_CF_DIS (0x0 << 15)
1891
+
#define RT5645_3D_CF_EN (0x1 << 15)
1892
+
#define RT5645_3D_HP_MASK (0x1 << 14)
1893
+
#define RT5645_3D_HP_SFT 14
1894
+
#define RT5645_3D_HP_DIS (0x0 << 14)
1895
+
#define RT5645_3D_HP_EN (0x1 << 14)
1896
+
#define RT5645_3D_BT_MASK (0x1 << 13)
1897
+
#define RT5645_3D_BT_SFT 13
1898
+
#define RT5645_3D_BT_DIS (0x0 << 13)
1899
+
#define RT5645_3D_BT_EN (0x1 << 13)
1900
+
#define RT5645_3D_1F_MIX_MASK (0x3 << 11)
1901
+
#define RT5645_3D_1F_MIX_SFT 11
1902
+
#define RT5645_3D_HP_M_MASK (0x1 << 10)
1903
+
#define RT5645_3D_HP_M_SFT 10
1904
+
#define RT5645_3D_HP_M_SUR (0x0 << 10)
1905
+
#define RT5645_3D_HP_M_FRO (0x1 << 10)
1906
+
#define RT5645_M_3D_HRTF_MASK (0x1 << 9)
1907
+
#define RT5645_M_3D_HRTF_SFT 9
1908
+
#define RT5645_M_3D_D2H_MASK (0x1 << 8)
1909
+
#define RT5645_M_3D_D2H_SFT 8
1910
+
#define RT5645_M_3D_D2R_MASK (0x1 << 7)
1911
+
#define RT5645_M_3D_D2R_SFT 7
1912
+
#define RT5645_M_3D_REVB_MASK (0x1 << 6)
1913
+
#define RT5645_M_3D_REVB_SFT 6
1914
+
1915
+
/* Adjustable high pass filter control 1 (0xd3) */
1916
+
#define RT5645_2ND_HPF_MASK (0x1 << 15)
1917
+
#define RT5645_2ND_HPF_SFT 15
1918
+
#define RT5645_2ND_HPF_DIS (0x0 << 15)
1919
+
#define RT5645_2ND_HPF_EN (0x1 << 15)
1920
+
#define RT5645_HPF_CF_L_MASK (0x7 << 12)
1921
+
#define RT5645_HPF_CF_L_SFT 12
1922
+
#define RT5645_1ST_HPF_MASK (0x1 << 11)
1923
+
#define RT5645_1ST_HPF_SFT 11
1924
+
#define RT5645_1ST_HPF_DIS (0x0 << 11)
1925
+
#define RT5645_1ST_HPF_EN (0x1 << 11)
1926
+
#define RT5645_HPF_CF_R_MASK (0x7 << 8)
1927
+
#define RT5645_HPF_CF_R_SFT 8
1928
+
#define RT5645_ZD_T_MASK (0x3 << 6)
1929
+
#define RT5645_ZD_T_SFT 6
1930
+
#define RT5645_ZD_F_MASK (0x3 << 4)
1931
+
#define RT5645_ZD_F_SFT 4
1932
+
#define RT5645_ZD_F_IM (0x0 << 4)
1933
+
#define RT5645_ZD_F_ZC_IM (0x1 << 4)
1934
+
#define RT5645_ZD_F_ZC_IOD (0x2 << 4)
1935
+
#define RT5645_ZD_F_UN (0x3 << 4)
1936
+
1937
+
/* HP calibration control and Amp detection (0xd6) */
1938
+
#define RT5645_SI_DAC_MASK (0x1 << 11)
1939
+
#define RT5645_SI_DAC_SFT 11
1940
+
#define RT5645_SI_DAC_AUTO (0x0 << 11)
1941
+
#define RT5645_SI_DAC_TEST (0x1 << 11)
1942
+
#define RT5645_DC_CAL_M_MASK (0x1 << 10)
1943
+
#define RT5645_DC_CAL_M_SFT 10
1944
+
#define RT5645_DC_CAL_M_CAL (0x0 << 10)
1945
+
#define RT5645_DC_CAL_M_NOR (0x1 << 10)
1946
+
#define RT5645_DC_CAL_MASK (0x1 << 9)
1947
+
#define RT5645_DC_CAL_SFT 9
1948
+
#define RT5645_DC_CAL_DIS (0x0 << 9)
1949
+
#define RT5645_DC_CAL_EN (0x1 << 9)
1950
+
#define RT5645_HPD_RCV_MASK (0x7 << 6)
1951
+
#define RT5645_HPD_RCV_SFT 6
1952
+
#define RT5645_HPD_PS_MASK (0x1 << 5)
1953
+
#define RT5645_HPD_PS_SFT 5
1954
+
#define RT5645_HPD_PS_DIS (0x0 << 5)
1955
+
#define RT5645_HPD_PS_EN (0x1 << 5)
1956
+
#define RT5645_CAL_M_MASK (0x1 << 4)
1957
+
#define RT5645_CAL_M_SFT 4
1958
+
#define RT5645_CAL_M_DEP (0x0 << 4)
1959
+
#define RT5645_CAL_M_CAL (0x1 << 4)
1960
+
#define RT5645_CAL_MASK (0x1 << 3)
1961
+
#define RT5645_CAL_SFT 3
1962
+
#define RT5645_CAL_DIS (0x0 << 3)
1963
+
#define RT5645_CAL_EN (0x1 << 3)
1964
+
#define RT5645_CAL_TEST_MASK (0x1 << 2)
1965
+
#define RT5645_CAL_TEST_SFT 2
1966
+
#define RT5645_CAL_TEST_DIS (0x0 << 2)
1967
+
#define RT5645_CAL_TEST_EN (0x1 << 2)
1968
+
#define RT5645_CAL_P_MASK (0x3)
1969
+
#define RT5645_CAL_P_SFT 0
1970
+
#define RT5645_CAL_P_NONE (0x0)
1971
+
#define RT5645_CAL_P_CAL (0x1)
1972
+
#define RT5645_CAL_P_DAC_CAL (0x2)
1973
+
1974
+
/* Soft volume and zero cross control 1 (0xd9) */
1975
+
#define RT5645_SV_MASK (0x1 << 15)
1976
+
#define RT5645_SV_SFT 15
1977
+
#define RT5645_SV_DIS (0x0 << 15)
1978
+
#define RT5645_SV_EN (0x1 << 15)
1979
+
#define RT5645_SPO_SV_MASK (0x1 << 14)
1980
+
#define RT5645_SPO_SV_SFT 14
1981
+
#define RT5645_SPO_SV_DIS (0x0 << 14)
1982
+
#define RT5645_SPO_SV_EN (0x1 << 14)
1983
+
#define RT5645_OUT_SV_MASK (0x1 << 13)
1984
+
#define RT5645_OUT_SV_SFT 13
1985
+
#define RT5645_OUT_SV_DIS (0x0 << 13)
1986
+
#define RT5645_OUT_SV_EN (0x1 << 13)
1987
+
#define RT5645_HP_SV_MASK (0x1 << 12)
1988
+
#define RT5645_HP_SV_SFT 12
1989
+
#define RT5645_HP_SV_DIS (0x0 << 12)
1990
+
#define RT5645_HP_SV_EN (0x1 << 12)
1991
+
#define RT5645_ZCD_DIG_MASK (0x1 << 11)
1992
+
#define RT5645_ZCD_DIG_SFT 11
1993
+
#define RT5645_ZCD_DIG_DIS (0x0 << 11)
1994
+
#define RT5645_ZCD_DIG_EN (0x1 << 11)
1995
+
#define RT5645_ZCD_MASK (0x1 << 10)
1996
+
#define RT5645_ZCD_SFT 10
1997
+
#define RT5645_ZCD_PD (0x0 << 10)
1998
+
#define RT5645_ZCD_PU (0x1 << 10)
1999
+
#define RT5645_M_ZCD_MASK (0x3f << 4)
2000
+
#define RT5645_M_ZCD_SFT 4
2001
+
#define RT5645_M_ZCD_RM_L (0x1 << 9)
2002
+
#define RT5645_M_ZCD_RM_R (0x1 << 8)
2003
+
#define RT5645_M_ZCD_SM_L (0x1 << 7)
2004
+
#define RT5645_M_ZCD_SM_R (0x1 << 6)
2005
+
#define RT5645_M_ZCD_OM_L (0x1 << 5)
2006
+
#define RT5645_M_ZCD_OM_R (0x1 << 4)
2007
+
#define RT5645_SV_DLY_MASK (0xf)
2008
+
#define RT5645_SV_DLY_SFT 0
2009
+
2010
+
/* Soft volume and zero cross control 2 (0xda) */
2011
+
#define RT5645_ZCD_HP_MASK (0x1 << 15)
2012
+
#define RT5645_ZCD_HP_SFT 15
2013
+
#define RT5645_ZCD_HP_DIS (0x0 << 15)
2014
+
#define RT5645_ZCD_HP_EN (0x1 << 15)
2015
+
2016
+
2017
+
/* Codec Private Register definition */
2018
+
/* 3D Speaker Control (0x63) */
2019
+
#define RT5645_3D_SPK_MASK (0x1 << 15)
2020
+
#define RT5645_3D_SPK_SFT 15
2021
+
#define RT5645_3D_SPK_DIS (0x0 << 15)
2022
+
#define RT5645_3D_SPK_EN (0x1 << 15)
2023
+
#define RT5645_3D_SPK_M_MASK (0x3 << 13)
2024
+
#define RT5645_3D_SPK_M_SFT 13
2025
+
#define RT5645_3D_SPK_CG_MASK (0x1f << 8)
2026
+
#define RT5645_3D_SPK_CG_SFT 8
2027
+
#define RT5645_3D_SPK_SG_MASK (0x1f)
2028
+
#define RT5645_3D_SPK_SG_SFT 0
2029
+
2030
+
/* Wind Noise Detection Control 1 (0x6c) */
2031
+
#define RT5645_WND_MASK (0x1 << 15)
2032
+
#define RT5645_WND_SFT 15
2033
+
#define RT5645_WND_DIS (0x0 << 15)
2034
+
#define RT5645_WND_EN (0x1 << 15)
2035
+
2036
+
/* Wind Noise Detection Control 2 (0x6d) */
2037
+
#define RT5645_WND_FC_NW_MASK (0x3f << 10)
2038
+
#define RT5645_WND_FC_NW_SFT 10
2039
+
#define RT5645_WND_FC_WK_MASK (0x3f << 4)
2040
+
#define RT5645_WND_FC_WK_SFT 4
2041
+
2042
+
/* Wind Noise Detection Control 3 (0x6e) */
2043
+
#define RT5645_HPF_FC_MASK (0x3f << 6)
2044
+
#define RT5645_HPF_FC_SFT 6
2045
+
#define RT5645_WND_FC_ST_MASK (0x3f)
2046
+
#define RT5645_WND_FC_ST_SFT 0
2047
+
2048
+
/* Wind Noise Detection Control 4 (0x6f) */
2049
+
#define RT5645_WND_TH_LO_MASK (0x3ff)
2050
+
#define RT5645_WND_TH_LO_SFT 0
2051
+
2052
+
/* Wind Noise Detection Control 5 (0x70) */
2053
+
#define RT5645_WND_TH_HI_MASK (0x3ff)
2054
+
#define RT5645_WND_TH_HI_SFT 0
2055
+
2056
+
/* Wind Noise Detection Control 8 (0x73) */
2057
+
#define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2058
+
#define RT5645_WND_WIND_SFT 13
2059
+
#define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2060
+
#define RT5645_WND_STRONG_SFT 12
2061
+
enum {
2062
+
RT5645_NO_WIND,
2063
+
RT5645_BREEZE,
2064
+
RT5645_STORM,
2065
+
};
2066
+
2067
+
/* Dipole Speaker Interface (0x75) */
2068
+
#define RT5645_DP_ATT_MASK (0x3 << 14)
2069
+
#define RT5645_DP_ATT_SFT 14
2070
+
#define RT5645_DP_SPK_MASK (0x1 << 10)
2071
+
#define RT5645_DP_SPK_SFT 10
2072
+
#define RT5645_DP_SPK_DIS (0x0 << 10)
2073
+
#define RT5645_DP_SPK_EN (0x1 << 10)
2074
+
2075
+
/* EQ Pre Volume Control (0xb3) */
2076
+
#define RT5645_EQ_PRE_VOL_MASK (0xffff)
2077
+
#define RT5645_EQ_PRE_VOL_SFT 0
2078
+
2079
+
/* EQ Post Volume Control (0xb4) */
2080
+
#define RT5645_EQ_PST_VOL_MASK (0xffff)
2081
+
#define RT5645_EQ_PST_VOL_SFT 0
2082
+
2083
+
/* Jack Detect Control 3 (0xf8) */
2084
+
#define RT5645_CMP_MIC_IN_DET_MASK (0x7 << 12)
2085
+
#define RT5645_JD_CBJ_EN (0x1 << 7)
2086
+
#define RT5645_JD_CBJ_POL (0x1 << 6)
2087
+
#define RT5645_JD_TRI_CBJ_SEL_MASK (0x7 << 3)
2088
+
#define RT5645_JD_TRI_CBJ_SEL_SFT (3)
2089
+
#define RT5645_JD_TRI_HPO_SEL_MASK (0x7)
2090
+
#define RT5645_JD_TRI_HPO_SEL_SFT (0)
2091
+
#define RT5645_JD_F_GPIO_JD1 (0x0)
2092
+
#define RT5645_JD_F_JD1_1 (0x1)
2093
+
#define RT5645_JD_F_JD1_2 (0x2)
2094
+
#define RT5645_JD_F_JD2 (0x3)
2095
+
#define RT5645_JD_F_JD3 (0x4)
2096
+
#define RT5645_JD_F_GPIO_JD2 (0x5)
2097
+
#define RT5645_JD_F_MX0B_12 (0x6)
2098
+
2099
+
/* Digital Misc Control (0xfa) */
2100
+
#define RT5645_RST_DSP (0x1 << 13)
2101
+
#define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12)
2102
+
#define RT5645_IF1_ADC1_IN1_SFT 12
2103
+
#define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11)
2104
+
#define RT5645_IF1_ADC1_IN2_SFT 11
2105
+
#define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10)
2106
+
#define RT5645_IF1_ADC2_IN1_SFT 10
2107
+
#define RT5645_DIG_GATE_CTRL 0x1
2108
+
2109
+
/* General Control2 (0xfb) */
2110
+
#define RT5645_RXDC_SRC_MASK (0x1 << 7)
2111
+
#define RT5645_RXDC_SRC_STO (0x0 << 7)
2112
+
#define RT5645_RXDC_SRC_MONO (0x1 << 7)
2113
+
#define RT5645_RXDC_SRC_SFT (7)
2114
+
#define RT5645_RXDP2_SEL_MASK (0x1 << 3)
2115
+
#define RT5645_RXDP2_SEL_IF2 (0x0 << 3)
2116
+
#define RT5645_RXDP2_SEL_ADC (0x1 << 3)
2117
+
#define RT5645_RXDP2_SEL_SFT (3)
2118
+
2119
+
2120
+
/* Vendor ID (0xfd) */
2121
+
#define RT5645_VER_C 0x2
2122
+
#define RT5645_VER_D 0x3
2123
+
2124
+
2125
+
/* Volume Rescale */
2126
+
#define RT5645_VOL_RSCL_MAX 0x27
2127
+
#define RT5645_VOL_RSCL_RANGE 0x1F
2128
+
/* Debug String Length */
2129
+
#define RT5645_REG_DISP_LEN 23
2130
+
2131
+
2132
+
/* System Clock Source */
2133
+
enum {
2134
+
RT5645_SCLK_S_MCLK,
2135
+
RT5645_SCLK_S_PLL1,
2136
+
RT5645_SCLK_S_RCCLK,
2137
+
};
2138
+
2139
+
/* PLL1 Source */
2140
+
enum {
2141
+
RT5645_PLL1_S_MCLK,
2142
+
RT5645_PLL1_S_BCLK1,
2143
+
RT5645_PLL1_S_BCLK2,
2144
+
};
2145
+
2146
+
enum {
2147
+
RT5645_AIF1,
2148
+
RT5645_AIF2,
2149
+
RT5645_AIFS,
2150
+
};
2151
+
2152
+
enum {
2153
+
RT5645_DMIC_DATA_IN2P,
2154
+
RT5645_DMIC_DATA_GPIO6,
2155
+
RT5645_DMIC_DATA_GPIO10,
2156
+
RT5645_DMIC_DATA_GPIO12,
2157
+
};
2158
+
2159
+
enum {
2160
+
RT5645_DMIC_DATA_IN2N,
2161
+
RT5645_DMIC_DATA_GPIO5,
2162
+
RT5645_DMIC_DATA_GPIO11,
2163
+
};
2164
+
2165
+
struct rt5645_pll_code {
2166
+
bool m_bp; /* Indicates bypass m code or not. */
2167
+
int m_code;
2168
+
int n_code;
2169
+
int k_code;
2170
+
};
2171
+
2172
+
struct rt5645_priv {
2173
+
struct snd_soc_codec *codec;
2174
+
struct rt5645_platform_data pdata;
2175
+
struct regmap *regmap;
2176
+
2177
+
int sysclk;
2178
+
int sysclk_src;
2179
+
int lrck[RT5645_AIFS];
2180
+
int bclk[RT5645_AIFS];
2181
+
int master[RT5645_AIFS];
2182
+
2183
+
int pll_src;
2184
+
int pll_in;
2185
+
int pll_out;
2186
+
};
2187
+
2188
+
#endif /* __RT5645_H__ */
+1897
sound/soc/codecs/rt5651.c
+1897
sound/soc/codecs/rt5651.c
···
1
+
/*
2
+
* rt5651.c -- RT5651 ALSA SoC audio codec driver
3
+
*
4
+
* Copyright 2014 Realtek Semiconductor Corp.
5
+
* Author: Bard Liao <bardliao@realtek.com>
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
10
+
*/
11
+
12
+
#include <linux/module.h>
13
+
#include <linux/moduleparam.h>
14
+
#include <linux/init.h>
15
+
#include <linux/delay.h>
16
+
#include <linux/pm.h>
17
+
#include <linux/i2c.h>
18
+
#include <linux/regmap.h>
19
+
#include <linux/platform_device.h>
20
+
#include <linux/spi/spi.h>
21
+
#include <sound/core.h>
22
+
#include <sound/pcm.h>
23
+
#include <sound/pcm_params.h>
24
+
#include <sound/soc.h>
25
+
#include <sound/soc-dapm.h>
26
+
#include <sound/initval.h>
27
+
#include <sound/tlv.h>
28
+
29
+
#include "rt5651.h"
30
+
31
+
#define RT5651_DEVICE_ID_VALUE 0x6281
32
+
33
+
#define RT5651_PR_RANGE_BASE (0xff + 1)
34
+
#define RT5651_PR_SPACING 0x100
35
+
36
+
#define RT5651_PR_BASE (RT5651_PR_RANGE_BASE + (0 * RT5651_PR_SPACING))
37
+
38
+
static const struct regmap_range_cfg rt5651_ranges[] = {
39
+
{ .name = "PR", .range_min = RT5651_PR_BASE,
40
+
.range_max = RT5651_PR_BASE + 0xb4,
41
+
.selector_reg = RT5651_PRIV_INDEX,
42
+
.selector_mask = 0xff,
43
+
.selector_shift = 0x0,
44
+
.window_start = RT5651_PRIV_DATA,
45
+
.window_len = 0x1, },
46
+
};
47
+
48
+
static struct reg_default init_list[] = {
49
+
{RT5651_PR_BASE + 0x3d, 0x3e00},
50
+
};
51
+
52
+
static const struct reg_default rt5651_reg[] = {
53
+
{ 0x00, 0x0000 },
54
+
{ 0x02, 0xc8c8 },
55
+
{ 0x03, 0xc8c8 },
56
+
{ 0x05, 0x0000 },
57
+
{ 0x0d, 0x0000 },
58
+
{ 0x0e, 0x0000 },
59
+
{ 0x0f, 0x0808 },
60
+
{ 0x10, 0x0808 },
61
+
{ 0x19, 0xafaf },
62
+
{ 0x1a, 0xafaf },
63
+
{ 0x1b, 0x0c00 },
64
+
{ 0x1c, 0x2f2f },
65
+
{ 0x1d, 0x2f2f },
66
+
{ 0x1e, 0x0000 },
67
+
{ 0x27, 0x7860 },
68
+
{ 0x28, 0x7070 },
69
+
{ 0x29, 0x8080 },
70
+
{ 0x2a, 0x5252 },
71
+
{ 0x2b, 0x5454 },
72
+
{ 0x2f, 0x0000 },
73
+
{ 0x30, 0x5000 },
74
+
{ 0x3b, 0x0000 },
75
+
{ 0x3c, 0x006f },
76
+
{ 0x3d, 0x0000 },
77
+
{ 0x3e, 0x006f },
78
+
{ 0x45, 0x6000 },
79
+
{ 0x4d, 0x0000 },
80
+
{ 0x4e, 0x0000 },
81
+
{ 0x4f, 0x0279 },
82
+
{ 0x50, 0x0000 },
83
+
{ 0x51, 0x0000 },
84
+
{ 0x52, 0x0279 },
85
+
{ 0x53, 0xf000 },
86
+
{ 0x61, 0x0000 },
87
+
{ 0x62, 0x0000 },
88
+
{ 0x63, 0x00c0 },
89
+
{ 0x64, 0x0000 },
90
+
{ 0x65, 0x0000 },
91
+
{ 0x66, 0x0000 },
92
+
{ 0x70, 0x8000 },
93
+
{ 0x71, 0x8000 },
94
+
{ 0x73, 0x1104 },
95
+
{ 0x74, 0x0c00 },
96
+
{ 0x75, 0x1400 },
97
+
{ 0x77, 0x0c00 },
98
+
{ 0x78, 0x4000 },
99
+
{ 0x79, 0x0123 },
100
+
{ 0x80, 0x0000 },
101
+
{ 0x81, 0x0000 },
102
+
{ 0x82, 0x0000 },
103
+
{ 0x83, 0x0800 },
104
+
{ 0x84, 0x0000 },
105
+
{ 0x85, 0x0008 },
106
+
{ 0x89, 0x0000 },
107
+
{ 0x8e, 0x0004 },
108
+
{ 0x8f, 0x1100 },
109
+
{ 0x90, 0x0000 },
110
+
{ 0x93, 0x2000 },
111
+
{ 0x94, 0x0200 },
112
+
{ 0xb0, 0x2080 },
113
+
{ 0xb1, 0x0000 },
114
+
{ 0xb4, 0x2206 },
115
+
{ 0xb5, 0x1f00 },
116
+
{ 0xb6, 0x0000 },
117
+
{ 0xbb, 0x0000 },
118
+
{ 0xbc, 0x0000 },
119
+
{ 0xbd, 0x0000 },
120
+
{ 0xbe, 0x0000 },
121
+
{ 0xbf, 0x0000 },
122
+
{ 0xc0, 0x0400 },
123
+
{ 0xc1, 0x0000 },
124
+
{ 0xc2, 0x0000 },
125
+
{ 0xcf, 0x0013 },
126
+
{ 0xd0, 0x0680 },
127
+
{ 0xd1, 0x1c17 },
128
+
{ 0xd3, 0xb320 },
129
+
{ 0xd9, 0x0809 },
130
+
{ 0xfa, 0x0010 },
131
+
{ 0xfe, 0x10ec },
132
+
{ 0xff, 0x6281 },
133
+
};
134
+
135
+
static bool rt5651_volatile_register(struct device *dev, unsigned int reg)
136
+
{
137
+
int i;
138
+
139
+
for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
140
+
if ((reg >= rt5651_ranges[i].window_start &&
141
+
reg <= rt5651_ranges[i].window_start +
142
+
rt5651_ranges[i].window_len) ||
143
+
(reg >= rt5651_ranges[i].range_min &&
144
+
reg <= rt5651_ranges[i].range_max)) {
145
+
return true;
146
+
}
147
+
}
148
+
149
+
switch (reg) {
150
+
case RT5651_RESET:
151
+
case RT5651_PRIV_DATA:
152
+
case RT5651_EQ_CTRL1:
153
+
case RT5651_ALC_1:
154
+
case RT5651_IRQ_CTRL2:
155
+
case RT5651_INT_IRQ_ST:
156
+
case RT5651_PGM_REG_ARR1:
157
+
case RT5651_PGM_REG_ARR3:
158
+
case RT5651_VENDOR_ID:
159
+
case RT5651_DEVICE_ID:
160
+
return true;
161
+
default:
162
+
return false;
163
+
}
164
+
}
165
+
166
+
static bool rt5651_readable_register(struct device *dev, unsigned int reg)
167
+
{
168
+
int i;
169
+
170
+
for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
171
+
if ((reg >= rt5651_ranges[i].window_start &&
172
+
reg <= rt5651_ranges[i].window_start +
173
+
rt5651_ranges[i].window_len) ||
174
+
(reg >= rt5651_ranges[i].range_min &&
175
+
reg <= rt5651_ranges[i].range_max)) {
176
+
return true;
177
+
}
178
+
}
179
+
180
+
switch (reg) {
181
+
case RT5651_RESET:
182
+
case RT5651_VERSION_ID:
183
+
case RT5651_VENDOR_ID:
184
+
case RT5651_DEVICE_ID:
185
+
case RT5651_HP_VOL:
186
+
case RT5651_LOUT_CTRL1:
187
+
case RT5651_LOUT_CTRL2:
188
+
case RT5651_IN1_IN2:
189
+
case RT5651_IN3:
190
+
case RT5651_INL1_INR1_VOL:
191
+
case RT5651_INL2_INR2_VOL:
192
+
case RT5651_DAC1_DIG_VOL:
193
+
case RT5651_DAC2_DIG_VOL:
194
+
case RT5651_DAC2_CTRL:
195
+
case RT5651_ADC_DIG_VOL:
196
+
case RT5651_ADC_DATA:
197
+
case RT5651_ADC_BST_VOL:
198
+
case RT5651_STO1_ADC_MIXER:
199
+
case RT5651_STO2_ADC_MIXER:
200
+
case RT5651_AD_DA_MIXER:
201
+
case RT5651_STO_DAC_MIXER:
202
+
case RT5651_DD_MIXER:
203
+
case RT5651_DIG_INF_DATA:
204
+
case RT5651_PDM_CTL:
205
+
case RT5651_REC_L1_MIXER:
206
+
case RT5651_REC_L2_MIXER:
207
+
case RT5651_REC_R1_MIXER:
208
+
case RT5651_REC_R2_MIXER:
209
+
case RT5651_HPO_MIXER:
210
+
case RT5651_OUT_L1_MIXER:
211
+
case RT5651_OUT_L2_MIXER:
212
+
case RT5651_OUT_L3_MIXER:
213
+
case RT5651_OUT_R1_MIXER:
214
+
case RT5651_OUT_R2_MIXER:
215
+
case RT5651_OUT_R3_MIXER:
216
+
case RT5651_LOUT_MIXER:
217
+
case RT5651_PWR_DIG1:
218
+
case RT5651_PWR_DIG2:
219
+
case RT5651_PWR_ANLG1:
220
+
case RT5651_PWR_ANLG2:
221
+
case RT5651_PWR_MIXER:
222
+
case RT5651_PWR_VOL:
223
+
case RT5651_PRIV_INDEX:
224
+
case RT5651_PRIV_DATA:
225
+
case RT5651_I2S1_SDP:
226
+
case RT5651_I2S2_SDP:
227
+
case RT5651_ADDA_CLK1:
228
+
case RT5651_ADDA_CLK2:
229
+
case RT5651_DMIC:
230
+
case RT5651_TDM_CTL_1:
231
+
case RT5651_TDM_CTL_2:
232
+
case RT5651_TDM_CTL_3:
233
+
case RT5651_GLB_CLK:
234
+
case RT5651_PLL_CTRL1:
235
+
case RT5651_PLL_CTRL2:
236
+
case RT5651_PLL_MODE_1:
237
+
case RT5651_PLL_MODE_2:
238
+
case RT5651_PLL_MODE_3:
239
+
case RT5651_PLL_MODE_4:
240
+
case RT5651_PLL_MODE_5:
241
+
case RT5651_PLL_MODE_6:
242
+
case RT5651_PLL_MODE_7:
243
+
case RT5651_DEPOP_M1:
244
+
case RT5651_DEPOP_M2:
245
+
case RT5651_DEPOP_M3:
246
+
case RT5651_CHARGE_PUMP:
247
+
case RT5651_MICBIAS:
248
+
case RT5651_A_JD_CTL1:
249
+
case RT5651_EQ_CTRL1:
250
+
case RT5651_EQ_CTRL2:
251
+
case RT5651_ALC_1:
252
+
case RT5651_ALC_2:
253
+
case RT5651_ALC_3:
254
+
case RT5651_JD_CTRL1:
255
+
case RT5651_JD_CTRL2:
256
+
case RT5651_IRQ_CTRL1:
257
+
case RT5651_IRQ_CTRL2:
258
+
case RT5651_INT_IRQ_ST:
259
+
case RT5651_GPIO_CTRL1:
260
+
case RT5651_GPIO_CTRL2:
261
+
case RT5651_GPIO_CTRL3:
262
+
case RT5651_PGM_REG_ARR1:
263
+
case RT5651_PGM_REG_ARR2:
264
+
case RT5651_PGM_REG_ARR3:
265
+
case RT5651_PGM_REG_ARR4:
266
+
case RT5651_PGM_REG_ARR5:
267
+
case RT5651_SCB_FUNC:
268
+
case RT5651_SCB_CTRL:
269
+
case RT5651_BASE_BACK:
270
+
case RT5651_MP3_PLUS1:
271
+
case RT5651_MP3_PLUS2:
272
+
case RT5651_ADJ_HPF_CTRL1:
273
+
case RT5651_ADJ_HPF_CTRL2:
274
+
case RT5651_HP_CALIB_AMP_DET:
275
+
case RT5651_HP_CALIB2:
276
+
case RT5651_SV_ZCD1:
277
+
case RT5651_SV_ZCD2:
278
+
case RT5651_D_MISC:
279
+
case RT5651_DUMMY2:
280
+
case RT5651_DUMMY3:
281
+
return true;
282
+
default:
283
+
return false;
284
+
}
285
+
}
286
+
287
+
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
288
+
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
289
+
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
290
+
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
291
+
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
292
+
293
+
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
294
+
static unsigned int bst_tlv[] = {
295
+
TLV_DB_RANGE_HEAD(7),
296
+
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
297
+
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
298
+
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
299
+
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
300
+
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
301
+
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
302
+
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
303
+
};
304
+
305
+
/* Interface data select */
306
+
static const char * const rt5651_data_select[] = {
307
+
"Normal", "Swap", "left copy to right", "right copy to left"};
308
+
309
+
static SOC_ENUM_SINGLE_DECL(rt5651_if2_dac_enum, RT5651_DIG_INF_DATA,
310
+
RT5651_IF2_DAC_SEL_SFT, rt5651_data_select);
311
+
312
+
static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_enum, RT5651_DIG_INF_DATA,
313
+
RT5651_IF2_ADC_SEL_SFT, rt5651_data_select);
314
+
315
+
static const struct snd_kcontrol_new rt5651_snd_controls[] = {
316
+
/* Headphone Output Volume */
317
+
SOC_DOUBLE_TLV("HP Playback Volume", RT5651_HP_VOL,
318
+
RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
319
+
/* OUTPUT Control */
320
+
SOC_DOUBLE_TLV("OUT Playback Volume", RT5651_LOUT_CTRL1,
321
+
RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
322
+
323
+
/* DAC Digital Volume */
324
+
SOC_DOUBLE("DAC2 Playback Switch", RT5651_DAC2_CTRL,
325
+
RT5651_M_DAC_L2_VOL_SFT, RT5651_M_DAC_R2_VOL_SFT, 1, 1),
326
+
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5651_DAC1_DIG_VOL,
327
+
RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
328
+
175, 0, dac_vol_tlv),
329
+
SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5651_DAC2_DIG_VOL,
330
+
RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
331
+
175, 0, dac_vol_tlv),
332
+
/* IN1/IN2 Control */
333
+
SOC_SINGLE_TLV("IN1 Boost", RT5651_IN1_IN2,
334
+
RT5651_BST_SFT1, 8, 0, bst_tlv),
335
+
SOC_SINGLE_TLV("IN2 Boost", RT5651_IN1_IN2,
336
+
RT5651_BST_SFT2, 8, 0, bst_tlv),
337
+
/* INL/INR Volume Control */
338
+
SOC_DOUBLE_TLV("IN Capture Volume", RT5651_INL1_INR1_VOL,
339
+
RT5651_INL_VOL_SFT, RT5651_INR_VOL_SFT,
340
+
31, 1, in_vol_tlv),
341
+
/* ADC Digital Volume Control */
342
+
SOC_DOUBLE("ADC Capture Switch", RT5651_ADC_DIG_VOL,
343
+
RT5651_L_MUTE_SFT, RT5651_R_MUTE_SFT, 1, 1),
344
+
SOC_DOUBLE_TLV("ADC Capture Volume", RT5651_ADC_DIG_VOL,
345
+
RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
346
+
127, 0, adc_vol_tlv),
347
+
SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5651_ADC_DATA,
348
+
RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
349
+
127, 0, adc_vol_tlv),
350
+
/* ADC Boost Volume Control */
351
+
SOC_DOUBLE_TLV("ADC Boost Gain", RT5651_ADC_BST_VOL,
352
+
RT5651_ADC_L_BST_SFT, RT5651_ADC_R_BST_SFT,
353
+
3, 0, adc_bst_tlv),
354
+
355
+
/* ASRC */
356
+
SOC_SINGLE("IF1 ASRC Switch", RT5651_PLL_MODE_1,
357
+
RT5651_STO1_T_SFT, 1, 0),
358
+
SOC_SINGLE("IF2 ASRC Switch", RT5651_PLL_MODE_1,
359
+
RT5651_STO2_T_SFT, 1, 0),
360
+
SOC_SINGLE("DMIC ASRC Switch", RT5651_PLL_MODE_1,
361
+
RT5651_DMIC_1_M_SFT, 1, 0),
362
+
363
+
SOC_ENUM("ADC IF2 Data Switch", rt5651_if2_adc_enum),
364
+
SOC_ENUM("DAC IF2 Data Switch", rt5651_if2_dac_enum),
365
+
};
366
+
367
+
/**
368
+
* set_dmic_clk - Set parameter of dmic.
369
+
*
370
+
* @w: DAPM widget.
371
+
* @kcontrol: The kcontrol of this widget.
372
+
* @event: Event id.
373
+
*
374
+
* Choose dmic clock between 1MHz and 3MHz.
375
+
* It is better for clock to approximate 3MHz.
376
+
*/
377
+
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
378
+
struct snd_kcontrol *kcontrol, int event)
379
+
{
380
+
struct snd_soc_codec *codec = w->codec;
381
+
struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
382
+
int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL;
383
+
int i, rate, red, bound, temp;
384
+
385
+
rate = rt5651->sysclk;
386
+
red = 3000000 * 12;
387
+
for (i = 0; i < ARRAY_SIZE(div); i++) {
388
+
bound = div[i] * 3000000;
389
+
if (rate > bound)
390
+
continue;
391
+
temp = bound - rate;
392
+
if (temp < red) {
393
+
red = temp;
394
+
idx = i;
395
+
}
396
+
}
397
+
if (idx < 0)
398
+
dev_err(codec->dev, "Failed to set DMIC clock\n");
399
+
else
400
+
snd_soc_update_bits(codec, RT5651_DMIC, RT5651_DMIC_CLK_MASK,
401
+
idx << RT5651_DMIC_CLK_SFT);
402
+
403
+
return idx;
404
+
}
405
+
406
+
static int is_sysclk_from_pll(struct snd_soc_dapm_widget *source,
407
+
struct snd_soc_dapm_widget *sink)
408
+
{
409
+
unsigned int val;
410
+
411
+
val = snd_soc_read(source->codec, RT5651_GLB_CLK);
412
+
val &= RT5651_SCLK_SRC_MASK;
413
+
if (val == RT5651_SCLK_SRC_PLL1)
414
+
return 1;
415
+
else
416
+
return 0;
417
+
}
418
+
419
+
/* Digital Mixer */
420
+
static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = {
421
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
422
+
RT5651_M_STO1_ADC_L1_SFT, 1, 1),
423
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
424
+
RT5651_M_STO1_ADC_L2_SFT, 1, 1),
425
+
};
426
+
427
+
static const struct snd_kcontrol_new rt5651_sto1_adc_r_mix[] = {
428
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
429
+
RT5651_M_STO1_ADC_R1_SFT, 1, 1),
430
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
431
+
RT5651_M_STO1_ADC_R2_SFT, 1, 1),
432
+
};
433
+
434
+
static const struct snd_kcontrol_new rt5651_sto2_adc_l_mix[] = {
435
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
436
+
RT5651_M_STO2_ADC_L1_SFT, 1, 1),
437
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
438
+
RT5651_M_STO2_ADC_L2_SFT, 1, 1),
439
+
};
440
+
441
+
static const struct snd_kcontrol_new rt5651_sto2_adc_r_mix[] = {
442
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
443
+
RT5651_M_STO2_ADC_R1_SFT, 1, 1),
444
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
445
+
RT5651_M_STO2_ADC_R2_SFT, 1, 1),
446
+
};
447
+
448
+
static const struct snd_kcontrol_new rt5651_dac_l_mix[] = {
449
+
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
450
+
RT5651_M_ADCMIX_L_SFT, 1, 1),
451
+
SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
452
+
RT5651_M_IF1_DAC_L_SFT, 1, 1),
453
+
};
454
+
455
+
static const struct snd_kcontrol_new rt5651_dac_r_mix[] = {
456
+
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
457
+
RT5651_M_ADCMIX_R_SFT, 1, 1),
458
+
SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
459
+
RT5651_M_IF1_DAC_R_SFT, 1, 1),
460
+
};
461
+
462
+
static const struct snd_kcontrol_new rt5651_sto_dac_l_mix[] = {
463
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
464
+
RT5651_M_DAC_L1_MIXL_SFT, 1, 1),
465
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER,
466
+
RT5651_M_DAC_L2_MIXL_SFT, 1, 1),
467
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
468
+
RT5651_M_DAC_R1_MIXL_SFT, 1, 1),
469
+
};
470
+
471
+
static const struct snd_kcontrol_new rt5651_sto_dac_r_mix[] = {
472
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
473
+
RT5651_M_DAC_R1_MIXR_SFT, 1, 1),
474
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER,
475
+
RT5651_M_DAC_R2_MIXR_SFT, 1, 1),
476
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
477
+
RT5651_M_DAC_L1_MIXR_SFT, 1, 1),
478
+
};
479
+
480
+
static const struct snd_kcontrol_new rt5651_dd_dac_l_mix[] = {
481
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_DD_MIXER,
482
+
RT5651_M_STO_DD_L1_SFT, 1, 1),
483
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
484
+
RT5651_M_STO_DD_L2_SFT, 1, 1),
485
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
486
+
RT5651_M_STO_DD_R2_L_SFT, 1, 1),
487
+
};
488
+
489
+
static const struct snd_kcontrol_new rt5651_dd_dac_r_mix[] = {
490
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER,
491
+
RT5651_M_STO_DD_R1_SFT, 1, 1),
492
+
SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
493
+
RT5651_M_STO_DD_R2_SFT, 1, 1),
494
+
SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
495
+
RT5651_M_STO_DD_L2_R_SFT, 1, 1),
496
+
};
497
+
498
+
/* Analog Input Mixer */
499
+
static const struct snd_kcontrol_new rt5651_rec_l_mix[] = {
500
+
SOC_DAPM_SINGLE("INL1 Switch", RT5651_REC_L2_MIXER,
501
+
RT5651_M_IN1_L_RM_L_SFT, 1, 1),
502
+
SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_L2_MIXER,
503
+
RT5651_M_BST3_RM_L_SFT, 1, 1),
504
+
SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_L2_MIXER,
505
+
RT5651_M_BST2_RM_L_SFT, 1, 1),
506
+
SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_L2_MIXER,
507
+
RT5651_M_BST1_RM_L_SFT, 1, 1),
508
+
};
509
+
510
+
static const struct snd_kcontrol_new rt5651_rec_r_mix[] = {
511
+
SOC_DAPM_SINGLE("INR1 Switch", RT5651_REC_R2_MIXER,
512
+
RT5651_M_IN1_R_RM_R_SFT, 1, 1),
513
+
SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_R2_MIXER,
514
+
RT5651_M_BST3_RM_R_SFT, 1, 1),
515
+
SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_R2_MIXER,
516
+
RT5651_M_BST2_RM_R_SFT, 1, 1),
517
+
SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_R2_MIXER,
518
+
RT5651_M_BST1_RM_R_SFT, 1, 1),
519
+
};
520
+
521
+
/* Analog Output Mixer */
522
+
523
+
static const struct snd_kcontrol_new rt5651_out_l_mix[] = {
524
+
SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_L3_MIXER,
525
+
RT5651_M_BST1_OM_L_SFT, 1, 1),
526
+
SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_L3_MIXER,
527
+
RT5651_M_BST2_OM_L_SFT, 1, 1),
528
+
SOC_DAPM_SINGLE("INL1 Switch", RT5651_OUT_L3_MIXER,
529
+
RT5651_M_IN1_L_OM_L_SFT, 1, 1),
530
+
SOC_DAPM_SINGLE("REC MIXL Switch", RT5651_OUT_L3_MIXER,
531
+
RT5651_M_RM_L_OM_L_SFT, 1, 1),
532
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_OUT_L3_MIXER,
533
+
RT5651_M_DAC_L1_OM_L_SFT, 1, 1),
534
+
};
535
+
536
+
static const struct snd_kcontrol_new rt5651_out_r_mix[] = {
537
+
SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_R3_MIXER,
538
+
RT5651_M_BST2_OM_R_SFT, 1, 1),
539
+
SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_R3_MIXER,
540
+
RT5651_M_BST1_OM_R_SFT, 1, 1),
541
+
SOC_DAPM_SINGLE("INR1 Switch", RT5651_OUT_R3_MIXER,
542
+
RT5651_M_IN1_R_OM_R_SFT, 1, 1),
543
+
SOC_DAPM_SINGLE("REC MIXR Switch", RT5651_OUT_R3_MIXER,
544
+
RT5651_M_RM_R_OM_R_SFT, 1, 1),
545
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER,
546
+
RT5651_M_DAC_R1_OM_R_SFT, 1, 1),
547
+
};
548
+
549
+
static const struct snd_kcontrol_new rt5651_hpo_mix[] = {
550
+
SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5651_HPO_MIXER,
551
+
RT5651_M_DAC1_HM_SFT, 1, 1),
552
+
SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5651_HPO_MIXER,
553
+
RT5651_M_HPVOL_HM_SFT, 1, 1),
554
+
};
555
+
556
+
static const struct snd_kcontrol_new rt5651_lout_mix[] = {
557
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_LOUT_MIXER,
558
+
RT5651_M_DAC_L1_LM_SFT, 1, 1),
559
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER,
560
+
RT5651_M_DAC_R1_LM_SFT, 1, 1),
561
+
SOC_DAPM_SINGLE("OUTVOL L Switch", RT5651_LOUT_MIXER,
562
+
RT5651_M_OV_L_LM_SFT, 1, 1),
563
+
SOC_DAPM_SINGLE("OUTVOL R Switch", RT5651_LOUT_MIXER,
564
+
RT5651_M_OV_R_LM_SFT, 1, 1),
565
+
};
566
+
567
+
static const struct snd_kcontrol_new outvol_l_control =
568
+
SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
569
+
RT5651_VOL_L_SFT, 1, 1);
570
+
571
+
static const struct snd_kcontrol_new outvol_r_control =
572
+
SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
573
+
RT5651_VOL_R_SFT, 1, 1);
574
+
575
+
static const struct snd_kcontrol_new lout_l_mute_control =
576
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
577
+
RT5651_L_MUTE_SFT, 1, 1);
578
+
579
+
static const struct snd_kcontrol_new lout_r_mute_control =
580
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
581
+
RT5651_R_MUTE_SFT, 1, 1);
582
+
583
+
static const struct snd_kcontrol_new hpovol_l_control =
584
+
SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
585
+
RT5651_VOL_L_SFT, 1, 1);
586
+
587
+
static const struct snd_kcontrol_new hpovol_r_control =
588
+
SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
589
+
RT5651_VOL_R_SFT, 1, 1);
590
+
591
+
static const struct snd_kcontrol_new hpo_l_mute_control =
592
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
593
+
RT5651_L_MUTE_SFT, 1, 1);
594
+
595
+
static const struct snd_kcontrol_new hpo_r_mute_control =
596
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
597
+
RT5651_R_MUTE_SFT, 1, 1);
598
+
599
+
/* INL/R source */
600
+
static const char * const rt5651_inl_src[] = {"IN2P", "HPOVOLLP"};
601
+
602
+
static SOC_ENUM_SINGLE_DECL(
603
+
rt5651_inl_enum, RT5651_INL1_INR1_VOL,
604
+
RT5651_INL_SEL_SFT, rt5651_inl_src);
605
+
606
+
static const struct snd_kcontrol_new rt5651_inl1_mux =
607
+
SOC_DAPM_ENUM("INL1 source", rt5651_inl_enum);
608
+
609
+
static const char * const rt5651_inr1_src[] = {"IN2N", "HPOVOLRP"};
610
+
611
+
static SOC_ENUM_SINGLE_DECL(
612
+
rt5651_inr1_enum, RT5651_INL1_INR1_VOL,
613
+
RT5651_INR_SEL_SFT, rt5651_inr1_src);
614
+
615
+
static const struct snd_kcontrol_new rt5651_inr1_mux =
616
+
SOC_DAPM_ENUM("INR1 source", rt5651_inr1_enum);
617
+
618
+
static const char * const rt5651_inl2_src[] = {"IN3P", "OUTVOLLP"};
619
+
620
+
static SOC_ENUM_SINGLE_DECL(
621
+
rt5651_inl2_enum, RT5651_INL2_INR2_VOL,
622
+
RT5651_INL_SEL_SFT, rt5651_inl2_src);
623
+
624
+
static const struct snd_kcontrol_new rt5651_inl2_mux =
625
+
SOC_DAPM_ENUM("INL2 source", rt5651_inl2_enum);
626
+
627
+
static const char * const rt5651_inr2_src[] = {"IN3N", "OUTVOLRP"};
628
+
629
+
static SOC_ENUM_SINGLE_DECL(
630
+
rt5651_inr2_enum, RT5651_INL2_INR2_VOL,
631
+
RT5651_INR_SEL_SFT, rt5651_inr2_src);
632
+
633
+
static const struct snd_kcontrol_new rt5651_inr2_mux =
634
+
SOC_DAPM_ENUM("INR2 source", rt5651_inr2_enum);
635
+
636
+
637
+
/* Stereo ADC source */
638
+
static const char * const rt5651_stereo1_adc1_src[] = {"DD MIX", "ADC"};
639
+
640
+
static SOC_ENUM_SINGLE_DECL(
641
+
rt5651_stereo1_adc1_enum, RT5651_STO1_ADC_MIXER,
642
+
RT5651_STO1_ADC_1_SRC_SFT, rt5651_stereo1_adc1_src);
643
+
644
+
static const struct snd_kcontrol_new rt5651_sto1_adc_l1_mux =
645
+
SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5651_stereo1_adc1_enum);
646
+
647
+
static const struct snd_kcontrol_new rt5651_sto1_adc_r1_mux =
648
+
SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum);
649
+
650
+
static const char * const rt5651_stereo1_adc2_src[] = {"DMIC", "DD MIX"};
651
+
652
+
static SOC_ENUM_SINGLE_DECL(
653
+
rt5651_stereo1_adc2_enum, RT5651_STO1_ADC_MIXER,
654
+
RT5651_STO1_ADC_2_SRC_SFT, rt5651_stereo1_adc2_src);
655
+
656
+
static const struct snd_kcontrol_new rt5651_sto1_adc_l2_mux =
657
+
SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum);
658
+
659
+
static const struct snd_kcontrol_new rt5651_sto1_adc_r2_mux =
660
+
SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum);
661
+
662
+
/* Mono ADC source */
663
+
static const char * const rt5651_sto2_adc_l1_src[] = {"DD MIXL", "ADCL"};
664
+
665
+
static SOC_ENUM_SINGLE_DECL(
666
+
rt5651_sto2_adc_l1_enum, RT5651_STO1_ADC_MIXER,
667
+
RT5651_STO2_ADC_L1_SRC_SFT, rt5651_sto2_adc_l1_src);
668
+
669
+
static const struct snd_kcontrol_new rt5651_sto2_adc_l1_mux =
670
+
SOC_DAPM_ENUM("Stereo2 ADC1 left source", rt5651_sto2_adc_l1_enum);
671
+
672
+
static const char * const rt5651_sto2_adc_l2_src[] = {"DMIC L", "DD MIXL"};
673
+
674
+
static SOC_ENUM_SINGLE_DECL(
675
+
rt5651_sto2_adc_l2_enum, RT5651_STO1_ADC_MIXER,
676
+
RT5651_STO2_ADC_L2_SRC_SFT, rt5651_sto2_adc_l2_src);
677
+
678
+
static const struct snd_kcontrol_new rt5651_sto2_adc_l2_mux =
679
+
SOC_DAPM_ENUM("Stereo2 ADC2 left source", rt5651_sto2_adc_l2_enum);
680
+
681
+
static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"};
682
+
683
+
static SOC_ENUM_SINGLE_DECL(
684
+
rt5651_sto2_adc_r1_enum, RT5651_STO1_ADC_MIXER,
685
+
RT5651_STO2_ADC_R1_SRC_SFT, rt5651_sto2_adc_r1_src);
686
+
687
+
static const struct snd_kcontrol_new rt5651_sto2_adc_r1_mux =
688
+
SOC_DAPM_ENUM("Stereo2 ADC1 right source", rt5651_sto2_adc_r1_enum);
689
+
690
+
static const char * const rt5651_sto2_adc_r2_src[] = {"DMIC R", "DD MIXR"};
691
+
692
+
static SOC_ENUM_SINGLE_DECL(
693
+
rt5651_sto2_adc_r2_enum, RT5651_STO1_ADC_MIXER,
694
+
RT5651_STO2_ADC_R2_SRC_SFT, rt5651_sto2_adc_r2_src);
695
+
696
+
static const struct snd_kcontrol_new rt5651_sto2_adc_r2_mux =
697
+
SOC_DAPM_ENUM("Stereo2 ADC2 right source", rt5651_sto2_adc_r2_enum);
698
+
699
+
/* DAC2 channel source */
700
+
701
+
static const char * const rt5651_dac_src[] = {"IF1", "IF2"};
702
+
703
+
static SOC_ENUM_SINGLE_DECL(rt5651_dac_l2_enum, RT5651_DAC2_CTRL,
704
+
RT5651_SEL_DAC_L2_SFT, rt5651_dac_src);
705
+
706
+
static const struct snd_kcontrol_new rt5651_dac_l2_mux =
707
+
SOC_DAPM_ENUM("DAC2 left channel source", rt5651_dac_l2_enum);
708
+
709
+
static SOC_ENUM_SINGLE_DECL(
710
+
rt5651_dac_r2_enum, RT5651_DAC2_CTRL,
711
+
RT5651_SEL_DAC_R2_SFT, rt5651_dac_src);
712
+
713
+
static const struct snd_kcontrol_new rt5651_dac_r2_mux =
714
+
SOC_DAPM_ENUM("DAC2 right channel source", rt5651_dac_r2_enum);
715
+
716
+
/* IF2_ADC channel source */
717
+
718
+
static const char * const rt5651_adc_src[] = {"IF1 ADC1", "IF1 ADC2"};
719
+
720
+
static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_src_enum, RT5651_DIG_INF_DATA,
721
+
RT5651_IF2_ADC_SRC_SFT, rt5651_adc_src);
722
+
723
+
static const struct snd_kcontrol_new rt5651_if2_adc_src_mux =
724
+
SOC_DAPM_ENUM("IF2 ADC channel source", rt5651_if2_adc_src_enum);
725
+
726
+
/* PDM select */
727
+
static const char * const rt5651_pdm_sel[] = {"DD MIX", "Stereo DAC MIX"};
728
+
729
+
static SOC_ENUM_SINGLE_DECL(
730
+
rt5651_pdm_l_sel_enum, RT5651_PDM_CTL,
731
+
RT5651_PDM_L_SEL_SFT, rt5651_pdm_sel);
732
+
733
+
static SOC_ENUM_SINGLE_DECL(
734
+
rt5651_pdm_r_sel_enum, RT5651_PDM_CTL,
735
+
RT5651_PDM_R_SEL_SFT, rt5651_pdm_sel);
736
+
737
+
static const struct snd_kcontrol_new rt5651_pdm_l_mux =
738
+
SOC_DAPM_ENUM("PDM L select", rt5651_pdm_l_sel_enum);
739
+
740
+
static const struct snd_kcontrol_new rt5651_pdm_r_mux =
741
+
SOC_DAPM_ENUM("PDM R select", rt5651_pdm_r_sel_enum);
742
+
743
+
static int rt5651_amp_power_event(struct snd_soc_dapm_widget *w,
744
+
struct snd_kcontrol *kcontrol, int event)
745
+
{
746
+
struct snd_soc_codec *codec = w->codec;
747
+
struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
748
+
749
+
switch (event) {
750
+
case SND_SOC_DAPM_POST_PMU:
751
+
/* depop parameters */
752
+
regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
753
+
RT5651_CHPUMP_INT_REG1, 0x0700, 0x0200);
754
+
regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
755
+
RT5651_DEPOP_MASK, RT5651_DEPOP_MAN);
756
+
regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
757
+
RT5651_HP_CP_MASK | RT5651_HP_SG_MASK |
758
+
RT5651_HP_CB_MASK, RT5651_HP_CP_PU |
759
+
RT5651_HP_SG_DIS | RT5651_HP_CB_PU);
760
+
regmap_write(rt5651->regmap, RT5651_PR_BASE +
761
+
RT5651_HP_DCC_INT1, 0x9f00);
762
+
/* headphone amp power on */
763
+
regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
764
+
RT5651_PWR_FV1 | RT5651_PWR_FV2, 0);
765
+
regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
766
+
RT5651_PWR_HA,
767
+
RT5651_PWR_HA);
768
+
usleep_range(10000, 15000);
769
+
regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
770
+
RT5651_PWR_FV1 | RT5651_PWR_FV2 ,
771
+
RT5651_PWR_FV1 | RT5651_PWR_FV2);
772
+
break;
773
+
774
+
default:
775
+
return 0;
776
+
}
777
+
778
+
return 0;
779
+
}
780
+
781
+
static int rt5651_hp_event(struct snd_soc_dapm_widget *w,
782
+
struct snd_kcontrol *kcontrol, int event)
783
+
{
784
+
struct snd_soc_codec *codec = w->codec;
785
+
struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
786
+
787
+
switch (event) {
788
+
case SND_SOC_DAPM_POST_PMU:
789
+
/* headphone unmute sequence */
790
+
regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
791
+
RT5651_DEPOP_MASK | RT5651_DIG_DP_MASK,
792
+
RT5651_DEPOP_AUTO | RT5651_DIG_DP_EN);
793
+
regmap_update_bits(rt5651->regmap, RT5651_CHARGE_PUMP,
794
+
RT5651_PM_HP_MASK, RT5651_PM_HP_HV);
795
+
796
+
regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M3,
797
+
RT5651_CP_FQ1_MASK | RT5651_CP_FQ2_MASK |
798
+
RT5651_CP_FQ3_MASK,
799
+
(RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ1_SFT) |
800
+
(RT5651_CP_FQ_12_KHZ << RT5651_CP_FQ2_SFT) |
801
+
(RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ3_SFT));
802
+
803
+
regmap_write(rt5651->regmap, RT5651_PR_BASE +
804
+
RT5651_MAMP_INT_REG2, 0x1c00);
805
+
regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
806
+
RT5651_HP_CP_MASK | RT5651_HP_SG_MASK,
807
+
RT5651_HP_CP_PD | RT5651_HP_SG_EN);
808
+
regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
809
+
RT5651_CHPUMP_INT_REG1, 0x0700, 0x0400);
810
+
rt5651->hp_mute = 0;
811
+
break;
812
+
813
+
case SND_SOC_DAPM_PRE_PMD:
814
+
rt5651->hp_mute = 1;
815
+
usleep_range(70000, 75000);
816
+
break;
817
+
818
+
default:
819
+
return 0;
820
+
}
821
+
822
+
return 0;
823
+
}
824
+
825
+
static int rt5651_hp_post_event(struct snd_soc_dapm_widget *w,
826
+
struct snd_kcontrol *kcontrol, int event)
827
+
{
828
+
struct snd_soc_codec *codec = w->codec;
829
+
struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
830
+
831
+
switch (event) {
832
+
case SND_SOC_DAPM_POST_PMU:
833
+
if (!rt5651->hp_mute)
834
+
usleep_range(80000, 85000);
835
+
836
+
break;
837
+
838
+
default:
839
+
return 0;
840
+
}
841
+
842
+
return 0;
843
+
}
844
+
845
+
static int rt5651_bst1_event(struct snd_soc_dapm_widget *w,
846
+
struct snd_kcontrol *kcontrol, int event)
847
+
{
848
+
struct snd_soc_codec *codec = w->codec;
849
+
850
+
switch (event) {
851
+
case SND_SOC_DAPM_POST_PMU:
852
+
snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
853
+
RT5651_PWR_BST1_OP2, RT5651_PWR_BST1_OP2);
854
+
break;
855
+
856
+
case SND_SOC_DAPM_PRE_PMD:
857
+
snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
858
+
RT5651_PWR_BST1_OP2, 0);
859
+
break;
860
+
861
+
default:
862
+
return 0;
863
+
}
864
+
865
+
return 0;
866
+
}
867
+
868
+
static int rt5651_bst2_event(struct snd_soc_dapm_widget *w,
869
+
struct snd_kcontrol *kcontrol, int event)
870
+
{
871
+
struct snd_soc_codec *codec = w->codec;
872
+
873
+
switch (event) {
874
+
case SND_SOC_DAPM_POST_PMU:
875
+
snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
876
+
RT5651_PWR_BST2_OP2, RT5651_PWR_BST2_OP2);
877
+
break;
878
+
879
+
case SND_SOC_DAPM_PRE_PMD:
880
+
snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
881
+
RT5651_PWR_BST2_OP2, 0);
882
+
break;
883
+
884
+
default:
885
+
return 0;
886
+
}
887
+
888
+
return 0;
889
+
}
890
+
891
+
static int rt5651_bst3_event(struct snd_soc_dapm_widget *w,
892
+
struct snd_kcontrol *kcontrol, int event)
893
+
{
894
+
struct snd_soc_codec *codec = w->codec;
895
+
896
+
switch (event) {
897
+
case SND_SOC_DAPM_POST_PMU:
898
+
snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
899
+
RT5651_PWR_BST3_OP2, RT5651_PWR_BST3_OP2);
900
+
break;
901
+
902
+
case SND_SOC_DAPM_PRE_PMD:
903
+
snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
904
+
RT5651_PWR_BST3_OP2, 0);
905
+
break;
906
+
907
+
default:
908
+
return 0;
909
+
}
910
+
911
+
return 0;
912
+
}
913
+
914
+
static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = {
915
+
/* ASRC */
916
+
SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5651_PLL_MODE_2,
917
+
15, 0, NULL, 0),
918
+
SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5651_PLL_MODE_2,
919
+
14, 0, NULL, 0),
920
+
SND_SOC_DAPM_SUPPLY_S("STO1 DAC ASRC", 1, RT5651_PLL_MODE_2,
921
+
13, 0, NULL, 0),
922
+
SND_SOC_DAPM_SUPPLY_S("STO2 DAC ASRC", 1, RT5651_PLL_MODE_2,
923
+
12, 0, NULL, 0),
924
+
SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2,
925
+
11, 0, NULL, 0),
926
+
927
+
SND_SOC_DAPM_SUPPLY("PLL1", RT5651_PWR_ANLG2,
928
+
RT5651_PWR_PLL_BIT, 0, NULL, 0),
929
+
/* Input Side */
930
+
/* micbias */
931
+
SND_SOC_DAPM_SUPPLY("LDO", RT5651_PWR_ANLG1,
932
+
RT5651_PWR_LDO_BIT, 0, NULL, 0),
933
+
SND_SOC_DAPM_MICBIAS("micbias1", RT5651_PWR_ANLG2,
934
+
RT5651_PWR_MB1_BIT, 0),
935
+
/* Input Lines */
936
+
SND_SOC_DAPM_INPUT("MIC1"),
937
+
SND_SOC_DAPM_INPUT("MIC2"),
938
+
SND_SOC_DAPM_INPUT("MIC3"),
939
+
940
+
SND_SOC_DAPM_INPUT("IN1P"),
941
+
SND_SOC_DAPM_INPUT("IN2P"),
942
+
SND_SOC_DAPM_INPUT("IN2N"),
943
+
SND_SOC_DAPM_INPUT("IN3P"),
944
+
SND_SOC_DAPM_INPUT("DMIC L1"),
945
+
SND_SOC_DAPM_INPUT("DMIC R1"),
946
+
SND_SOC_DAPM_SUPPLY("DMIC CLK", RT5651_DMIC, RT5651_DMIC_1_EN_SFT,
947
+
0, set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
948
+
/* Boost */
949
+
SND_SOC_DAPM_PGA_E("BST1", RT5651_PWR_ANLG2,
950
+
RT5651_PWR_BST1_BIT, 0, NULL, 0, rt5651_bst1_event,
951
+
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
952
+
SND_SOC_DAPM_PGA_E("BST2", RT5651_PWR_ANLG2,
953
+
RT5651_PWR_BST2_BIT, 0, NULL, 0, rt5651_bst2_event,
954
+
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
955
+
SND_SOC_DAPM_PGA_E("BST3", RT5651_PWR_ANLG2,
956
+
RT5651_PWR_BST3_BIT, 0, NULL, 0, rt5651_bst3_event,
957
+
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
958
+
/* Input Volume */
959
+
SND_SOC_DAPM_PGA("INL1 VOL", RT5651_PWR_VOL,
960
+
RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
961
+
SND_SOC_DAPM_PGA("INR1 VOL", RT5651_PWR_VOL,
962
+
RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
963
+
SND_SOC_DAPM_PGA("INL2 VOL", RT5651_PWR_VOL,
964
+
RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
965
+
SND_SOC_DAPM_PGA("INR2 VOL", RT5651_PWR_VOL,
966
+
RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
967
+
/* IN Mux */
968
+
SND_SOC_DAPM_MUX("INL1 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inl1_mux),
969
+
SND_SOC_DAPM_MUX("INR1 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inr1_mux),
970
+
SND_SOC_DAPM_MUX("INL2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inl2_mux),
971
+
SND_SOC_DAPM_MUX("INR2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inr2_mux),
972
+
/* REC Mixer */
973
+
SND_SOC_DAPM_MIXER("RECMIXL", RT5651_PWR_MIXER, RT5651_PWR_RM_L_BIT, 0,
974
+
rt5651_rec_l_mix, ARRAY_SIZE(rt5651_rec_l_mix)),
975
+
SND_SOC_DAPM_MIXER("RECMIXR", RT5651_PWR_MIXER, RT5651_PWR_RM_R_BIT, 0,
976
+
rt5651_rec_r_mix, ARRAY_SIZE(rt5651_rec_r_mix)),
977
+
/* ADCs */
978
+
SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
979
+
SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
980
+
SND_SOC_DAPM_SUPPLY("ADC L Power", RT5651_PWR_DIG1,
981
+
RT5651_PWR_ADC_L_BIT, 0, NULL, 0),
982
+
SND_SOC_DAPM_SUPPLY("ADC R Power", RT5651_PWR_DIG1,
983
+
RT5651_PWR_ADC_R_BIT, 0, NULL, 0),
984
+
/* ADC Mux */
985
+
SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
986
+
&rt5651_sto1_adc_l2_mux),
987
+
SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
988
+
&rt5651_sto1_adc_r2_mux),
989
+
SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
990
+
&rt5651_sto1_adc_l1_mux),
991
+
SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
992
+
&rt5651_sto1_adc_r1_mux),
993
+
SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
994
+
&rt5651_sto2_adc_l2_mux),
995
+
SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
996
+
&rt5651_sto2_adc_l1_mux),
997
+
SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
998
+
&rt5651_sto2_adc_r1_mux),
999
+
SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1000
+
&rt5651_sto2_adc_r2_mux),
1001
+
/* ADC Mixer */
1002
+
SND_SOC_DAPM_SUPPLY("Stereo1 Filter", RT5651_PWR_DIG2,
1003
+
RT5651_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
1004
+
SND_SOC_DAPM_SUPPLY("Stereo2 Filter", RT5651_PWR_DIG2,
1005
+
RT5651_PWR_ADC_STO2_F_BIT, 0, NULL, 0),
1006
+
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1007
+
rt5651_sto1_adc_l_mix,
1008
+
ARRAY_SIZE(rt5651_sto1_adc_l_mix)),
1009
+
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1010
+
rt5651_sto1_adc_r_mix,
1011
+
ARRAY_SIZE(rt5651_sto1_adc_r_mix)),
1012
+
SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1013
+
rt5651_sto2_adc_l_mix,
1014
+
ARRAY_SIZE(rt5651_sto2_adc_l_mix)),
1015
+
SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1016
+
rt5651_sto2_adc_r_mix,
1017
+
ARRAY_SIZE(rt5651_sto2_adc_r_mix)),
1018
+
1019
+
/* Digital Interface */
1020
+
SND_SOC_DAPM_SUPPLY("I2S1", RT5651_PWR_DIG1,
1021
+
RT5651_PWR_I2S1_BIT, 0, NULL, 0),
1022
+
SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1023
+
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1024
+
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1025
+
SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1026
+
SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1027
+
SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1028
+
SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1029
+
SND_SOC_DAPM_SUPPLY("I2S2", RT5651_PWR_DIG1,
1030
+
RT5651_PWR_I2S2_BIT, 0, NULL, 0),
1031
+
SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1032
+
SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1033
+
SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1034
+
SND_SOC_DAPM_MUX("IF2 ADC", SND_SOC_NOPM, 0, 0,
1035
+
&rt5651_if2_adc_src_mux),
1036
+
1037
+
/* Digital Interface Select */
1038
+
1039
+
SND_SOC_DAPM_MUX("PDM L Mux", RT5651_PDM_CTL,
1040
+
RT5651_M_PDM_L_SFT, 1, &rt5651_pdm_l_mux),
1041
+
SND_SOC_DAPM_MUX("PDM R Mux", RT5651_PDM_CTL,
1042
+
RT5651_M_PDM_R_SFT, 1, &rt5651_pdm_r_mux),
1043
+
/* Audio Interface */
1044
+
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1045
+
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1046
+
SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1047
+
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1048
+
1049
+
/* Audio DSP */
1050
+
SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1051
+
1052
+
/* Output Side */
1053
+
/* DAC mixer before sound effect */
1054
+
SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1055
+
rt5651_dac_l_mix, ARRAY_SIZE(rt5651_dac_l_mix)),
1056
+
SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1057
+
rt5651_dac_r_mix, ARRAY_SIZE(rt5651_dac_r_mix)),
1058
+
1059
+
/* DAC2 channel Mux */
1060
+
SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux),
1061
+
SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux),
1062
+
SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1063
+
SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1064
+
1065
+
SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5651_PWR_DIG2,
1066
+
RT5651_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
1067
+
SND_SOC_DAPM_SUPPLY("Stero2 DAC Power", RT5651_PWR_DIG2,
1068
+
RT5651_PWR_DAC_STO2_F_BIT, 0, NULL, 0),
1069
+
/* DAC Mixer */
1070
+
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1071
+
rt5651_sto_dac_l_mix,
1072
+
ARRAY_SIZE(rt5651_sto_dac_l_mix)),
1073
+
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1074
+
rt5651_sto_dac_r_mix,
1075
+
ARRAY_SIZE(rt5651_sto_dac_r_mix)),
1076
+
SND_SOC_DAPM_MIXER("DD MIXL", SND_SOC_NOPM, 0, 0,
1077
+
rt5651_dd_dac_l_mix,
1078
+
ARRAY_SIZE(rt5651_dd_dac_l_mix)),
1079
+
SND_SOC_DAPM_MIXER("DD MIXR", SND_SOC_NOPM, 0, 0,
1080
+
rt5651_dd_dac_r_mix,
1081
+
ARRAY_SIZE(rt5651_dd_dac_r_mix)),
1082
+
1083
+
/* DACs */
1084
+
SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
1085
+
SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1086
+
SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5651_PWR_DIG1,
1087
+
RT5651_PWR_DAC_L1_BIT, 0, NULL, 0),
1088
+
SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1,
1089
+
RT5651_PWR_DAC_R1_BIT, 0, NULL, 0),
1090
+
/* OUT Mixer */
1091
+
SND_SOC_DAPM_MIXER("OUT MIXL", RT5651_PWR_MIXER, RT5651_PWR_OM_L_BIT,
1092
+
0, rt5651_out_l_mix, ARRAY_SIZE(rt5651_out_l_mix)),
1093
+
SND_SOC_DAPM_MIXER("OUT MIXR", RT5651_PWR_MIXER, RT5651_PWR_OM_R_BIT,
1094
+
0, rt5651_out_r_mix, ARRAY_SIZE(rt5651_out_r_mix)),
1095
+
/* Ouput Volume */
1096
+
SND_SOC_DAPM_SWITCH("OUTVOL L", RT5651_PWR_VOL,
1097
+
RT5651_PWR_OV_L_BIT, 0, &outvol_l_control),
1098
+
SND_SOC_DAPM_SWITCH("OUTVOL R", RT5651_PWR_VOL,
1099
+
RT5651_PWR_OV_R_BIT, 0, &outvol_r_control),
1100
+
SND_SOC_DAPM_SWITCH("HPOVOL L", RT5651_PWR_VOL,
1101
+
RT5651_PWR_HV_L_BIT, 0, &hpovol_l_control),
1102
+
SND_SOC_DAPM_SWITCH("HPOVOL R", RT5651_PWR_VOL,
1103
+
RT5651_PWR_HV_R_BIT, 0, &hpovol_r_control),
1104
+
SND_SOC_DAPM_PGA("INL1", RT5651_PWR_VOL,
1105
+
RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
1106
+
SND_SOC_DAPM_PGA("INR1", RT5651_PWR_VOL,
1107
+
RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
1108
+
SND_SOC_DAPM_PGA("INL2", RT5651_PWR_VOL,
1109
+
RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
1110
+
SND_SOC_DAPM_PGA("INR2", RT5651_PWR_VOL,
1111
+
RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
1112
+
/* HPO/LOUT/Mono Mixer */
1113
+
SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
1114
+
rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1115
+
SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
1116
+
rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1117
+
SND_SOC_DAPM_SUPPLY("HP L Amp", RT5651_PWR_ANLG1,
1118
+
RT5651_PWR_HP_L_BIT, 0, NULL, 0),
1119
+
SND_SOC_DAPM_SUPPLY("HP R Amp", RT5651_PWR_ANLG1,
1120
+
RT5651_PWR_HP_R_BIT, 0, NULL, 0),
1121
+
SND_SOC_DAPM_MIXER("LOUT MIX", RT5651_PWR_ANLG1, RT5651_PWR_LM_BIT, 0,
1122
+
rt5651_lout_mix, ARRAY_SIZE(rt5651_lout_mix)),
1123
+
1124
+
SND_SOC_DAPM_SUPPLY("Amp Power", RT5651_PWR_ANLG1,
1125
+
RT5651_PWR_HA_BIT, 0, rt5651_amp_power_event,
1126
+
SND_SOC_DAPM_POST_PMU),
1127
+
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5651_hp_event,
1128
+
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1129
+
SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
1130
+
&hpo_l_mute_control),
1131
+
SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
1132
+
&hpo_r_mute_control),
1133
+
SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
1134
+
&lout_l_mute_control),
1135
+
SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
1136
+
&lout_r_mute_control),
1137
+
SND_SOC_DAPM_POST("HP Post", rt5651_hp_post_event),
1138
+
1139
+
/* Output Lines */
1140
+
SND_SOC_DAPM_OUTPUT("HPOL"),
1141
+
SND_SOC_DAPM_OUTPUT("HPOR"),
1142
+
SND_SOC_DAPM_OUTPUT("LOUTL"),
1143
+
SND_SOC_DAPM_OUTPUT("LOUTR"),
1144
+
SND_SOC_DAPM_OUTPUT("PDML"),
1145
+
SND_SOC_DAPM_OUTPUT("PDMR"),
1146
+
};
1147
+
1148
+
static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
1149
+
{"Stero1 DAC Power", NULL, "STO1 DAC ASRC"},
1150
+
{"Stero2 DAC Power", NULL, "STO2 DAC ASRC"},
1151
+
{"I2S1", NULL, "I2S1 ASRC"},
1152
+
{"I2S2", NULL, "I2S2 ASRC"},
1153
+
1154
+
{"IN1P", NULL, "LDO"},
1155
+
{"IN2P", NULL, "LDO"},
1156
+
{"IN3P", NULL, "LDO"},
1157
+
1158
+
{"IN1P", NULL, "MIC1"},
1159
+
{"IN2P", NULL, "MIC2"},
1160
+
{"IN2N", NULL, "MIC2"},
1161
+
{"IN3P", NULL, "MIC3"},
1162
+
1163
+
{"BST1", NULL, "IN1P"},
1164
+
{"BST2", NULL, "IN2P"},
1165
+
{"BST2", NULL, "IN2N"},
1166
+
{"BST3", NULL, "IN3P"},
1167
+
1168
+
{"INL1 VOL", NULL, "IN2P"},
1169
+
{"INR1 VOL", NULL, "IN2N"},
1170
+
1171
+
{"RECMIXL", "INL1 Switch", "INL1 VOL"},
1172
+
{"RECMIXL", "BST3 Switch", "BST3"},
1173
+
{"RECMIXL", "BST2 Switch", "BST2"},
1174
+
{"RECMIXL", "BST1 Switch", "BST1"},
1175
+
1176
+
{"RECMIXR", "INR1 Switch", "INR1 VOL"},
1177
+
{"RECMIXR", "BST3 Switch", "BST3"},
1178
+
{"RECMIXR", "BST2 Switch", "BST2"},
1179
+
{"RECMIXR", "BST1 Switch", "BST1"},
1180
+
1181
+
{"ADC L", NULL, "RECMIXL"},
1182
+
{"ADC L", NULL, "ADC L Power"},
1183
+
{"ADC R", NULL, "RECMIXR"},
1184
+
{"ADC R", NULL, "ADC R Power"},
1185
+
1186
+
{"DMIC L1", NULL, "DMIC CLK"},
1187
+
{"DMIC R1", NULL, "DMIC CLK"},
1188
+
1189
+
{"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1190
+
{"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"},
1191
+
{"Stereo1 ADC L1 Mux", "ADC", "ADC L"},
1192
+
{"Stereo1 ADC L1 Mux", "DD MIX", "DD MIXL"},
1193
+
1194
+
{"Stereo1 ADC R1 Mux", "ADC", "ADC R"},
1195
+
{"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"},
1196
+
{"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1197
+
{"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"},
1198
+
1199
+
{"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"},
1200
+
{"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"},
1201
+
{"Stereo2 ADC L1 Mux", "DD MIXL", "DD MIXL"},
1202
+
{"Stereo2 ADC L1 Mux", "ADCL", "ADC L"},
1203
+
1204
+
{"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"},
1205
+
{"Stereo2 ADC R1 Mux", "ADCR", "ADC R"},
1206
+
{"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"},
1207
+
{"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"},
1208
+
1209
+
{"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1210
+
{"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1211
+
{"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"},
1212
+
{"Stereo1 Filter", NULL, "PLL1", is_sysclk_from_pll},
1213
+
{"Stereo1 Filter", NULL, "ADC ASRC"},
1214
+
1215
+
{"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1216
+
{"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1217
+
{"Stereo1 ADC MIXR", NULL, "Stereo1 Filter"},
1218
+
1219
+
{"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
1220
+
{"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
1221
+
{"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"},
1222
+
{"Stereo2 Filter", NULL, "PLL1", is_sysclk_from_pll},
1223
+
{"Stereo2 Filter", NULL, "ADC ASRC"},
1224
+
1225
+
{"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
1226
+
{"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
1227
+
{"Stereo2 ADC MIXR", NULL, "Stereo2 Filter"},
1228
+
1229
+
{"IF1 ADC2", NULL, "Stereo2 ADC MIXL"},
1230
+
{"IF1 ADC2", NULL, "Stereo2 ADC MIXR"},
1231
+
{"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
1232
+
{"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
1233
+
1234
+
{"IF1 ADC1", NULL, "I2S1"},
1235
+
1236
+
{"IF2 ADC", "IF1 ADC1", "IF1 ADC1"},
1237
+
{"IF2 ADC", "IF1 ADC2", "IF1 ADC2"},
1238
+
{"IF2 ADC", NULL, "I2S2"},
1239
+
1240
+
{"AIF1TX", NULL, "IF1 ADC1"},
1241
+
{"AIF1TX", NULL, "IF1 ADC2"},
1242
+
{"AIF2TX", NULL, "IF2 ADC"},
1243
+
1244
+
{"IF1 DAC", NULL, "AIF1RX"},
1245
+
{"IF1 DAC", NULL, "I2S1"},
1246
+
{"IF2 DAC", NULL, "AIF2RX"},
1247
+
{"IF2 DAC", NULL, "I2S2"},
1248
+
1249
+
{"IF1 DAC1 L", NULL, "IF1 DAC"},
1250
+
{"IF1 DAC1 R", NULL, "IF1 DAC"},
1251
+
{"IF1 DAC2 L", NULL, "IF1 DAC"},
1252
+
{"IF1 DAC2 R", NULL, "IF1 DAC"},
1253
+
{"IF2 DAC L", NULL, "IF2 DAC"},
1254
+
{"IF2 DAC R", NULL, "IF2 DAC"},
1255
+
1256
+
{"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1257
+
{"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
1258
+
{"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1259
+
{"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
1260
+
1261
+
{"Audio DSP", NULL, "DAC MIXL"},
1262
+
{"Audio DSP", NULL, "DAC MIXR"},
1263
+
1264
+
{"DAC L2 Mux", "IF1", "IF1 DAC2 L"},
1265
+
{"DAC L2 Mux", "IF2", "IF2 DAC L"},
1266
+
{"DAC L2 Volume", NULL, "DAC L2 Mux"},
1267
+
1268
+
{"DAC R2 Mux", "IF1", "IF1 DAC2 R"},
1269
+
{"DAC R2 Mux", "IF2", "IF2 DAC R"},
1270
+
{"DAC R2 Volume", NULL, "DAC R2 Mux"},
1271
+
1272
+
{"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
1273
+
{"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1274
+
{"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
1275
+
{"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
1276
+
{"Stereo DAC MIXL", NULL, "Stero2 DAC Power"},
1277
+
{"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
1278
+
{"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1279
+
{"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
1280
+
{"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
1281
+
{"Stereo DAC MIXR", NULL, "Stero2 DAC Power"},
1282
+
1283
+
{"PDM L Mux", "Stereo DAC MIX", "Stereo DAC MIXL"},
1284
+
{"PDM L Mux", "DD MIX", "DAC MIXL"},
1285
+
{"PDM R Mux", "Stereo DAC MIX", "Stereo DAC MIXR"},
1286
+
{"PDM R Mux", "DD MIX", "DAC MIXR"},
1287
+
1288
+
{"DAC L1", NULL, "Stereo DAC MIXL"},
1289
+
{"DAC L1", NULL, "PLL1", is_sysclk_from_pll},
1290
+
{"DAC L1", NULL, "DAC L1 Power"},
1291
+
{"DAC R1", NULL, "Stereo DAC MIXR"},
1292
+
{"DAC R1", NULL, "PLL1", is_sysclk_from_pll},
1293
+
{"DAC R1", NULL, "DAC R1 Power"},
1294
+
1295
+
{"DD MIXL", "DAC L1 Switch", "DAC MIXL"},
1296
+
{"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1297
+
{"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"},
1298
+
{"DD MIXL", NULL, "Stero2 DAC Power"},
1299
+
1300
+
{"DD MIXR", "DAC R1 Switch", "DAC MIXR"},
1301
+
{"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1302
+
{"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"},
1303
+
{"DD MIXR", NULL, "Stero2 DAC Power"},
1304
+
1305
+
{"OUT MIXL", "BST1 Switch", "BST1"},
1306
+
{"OUT MIXL", "BST2 Switch", "BST2"},
1307
+
{"OUT MIXL", "INL1 Switch", "INL1 VOL"},
1308
+
{"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
1309
+
{"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1310
+
1311
+
{"OUT MIXR", "BST2 Switch", "BST2"},
1312
+
{"OUT MIXR", "BST1 Switch", "BST1"},
1313
+
{"OUT MIXR", "INR1 Switch", "INR1 VOL"},
1314
+
{"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
1315
+
{"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1316
+
1317
+
{"HPOVOL L", "Switch", "OUT MIXL"},
1318
+
{"HPOVOL R", "Switch", "OUT MIXR"},
1319
+
{"OUTVOL L", "Switch", "OUT MIXL"},
1320
+
{"OUTVOL R", "Switch", "OUT MIXR"},
1321
+
1322
+
{"HPOL MIX", "HPO MIX DAC1 Switch", "DAC L1"},
1323
+
{"HPOL MIX", "HPO MIX HPVOL Switch", "HPOVOL L"},
1324
+
{"HPOL MIX", NULL, "HP L Amp"},
1325
+
{"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"},
1326
+
{"HPOR MIX", "HPO MIX HPVOL Switch", "HPOVOL R"},
1327
+
{"HPOR MIX", NULL, "HP R Amp"},
1328
+
1329
+
{"LOUT MIX", "DAC L1 Switch", "DAC L1"},
1330
+
{"LOUT MIX", "DAC R1 Switch", "DAC R1"},
1331
+
{"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1332
+
{"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1333
+
1334
+
{"HP Amp", NULL, "HPOL MIX"},
1335
+
{"HP Amp", NULL, "HPOR MIX"},
1336
+
{"HP Amp", NULL, "Amp Power"},
1337
+
{"HPO L Playback", "Switch", "HP Amp"},
1338
+
{"HPO R Playback", "Switch", "HP Amp"},
1339
+
{"HPOL", NULL, "HPO L Playback"},
1340
+
{"HPOR", NULL, "HPO R Playback"},
1341
+
1342
+
{"LOUT L Playback", "Switch", "LOUT MIX"},
1343
+
{"LOUT R Playback", "Switch", "LOUT MIX"},
1344
+
{"LOUTL", NULL, "LOUT L Playback"},
1345
+
{"LOUTL", NULL, "Amp Power"},
1346
+
{"LOUTR", NULL, "LOUT R Playback"},
1347
+
{"LOUTR", NULL, "Amp Power"},
1348
+
1349
+
{"PDML", NULL, "PDM L Mux"},
1350
+
{"PDMR", NULL, "PDM R Mux"},
1351
+
};
1352
+
1353
+
static int get_clk_info(int sclk, int rate)
1354
+
{
1355
+
int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1356
+
1357
+
if (sclk <= 0 || rate <= 0)
1358
+
return -EINVAL;
1359
+
1360
+
rate = rate << 8;
1361
+
for (i = 0; i < ARRAY_SIZE(pd); i++)
1362
+
if (sclk == rate * pd[i])
1363
+
return i;
1364
+
1365
+
return -EINVAL;
1366
+
}
1367
+
1368
+
static int rt5651_hw_params(struct snd_pcm_substream *substream,
1369
+
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1370
+
{
1371
+
struct snd_soc_codec *codec = dai->codec;
1372
+
struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1373
+
unsigned int val_len = 0, val_clk, mask_clk;
1374
+
int pre_div, bclk_ms, frame_size;
1375
+
1376
+
rt5651->lrck[dai->id] = params_rate(params);
1377
+
pre_div = get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]);
1378
+
1379
+
if (pre_div < 0) {
1380
+
dev_err(codec->dev, "Unsupported clock setting\n");
1381
+
return -EINVAL;
1382
+
}
1383
+
frame_size = snd_soc_params_to_frame_size(params);
1384
+
if (frame_size < 0) {
1385
+
dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
1386
+
return -EINVAL;
1387
+
}
1388
+
bclk_ms = frame_size > 32 ? 1 : 0;
1389
+
rt5651->bclk[dai->id] = rt5651->lrck[dai->id] * (32 << bclk_ms);
1390
+
1391
+
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1392
+
rt5651->bclk[dai->id], rt5651->lrck[dai->id]);
1393
+
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1394
+
bclk_ms, pre_div, dai->id);
1395
+
1396
+
switch (params_format(params)) {
1397
+
case SNDRV_PCM_FORMAT_S16_LE:
1398
+
break;
1399
+
case SNDRV_PCM_FORMAT_S20_3LE:
1400
+
val_len |= RT5651_I2S_DL_20;
1401
+
break;
1402
+
case SNDRV_PCM_FORMAT_S24_LE:
1403
+
val_len |= RT5651_I2S_DL_24;
1404
+
break;
1405
+
case SNDRV_PCM_FORMAT_S8:
1406
+
val_len |= RT5651_I2S_DL_8;
1407
+
break;
1408
+
default:
1409
+
return -EINVAL;
1410
+
}
1411
+
1412
+
switch (dai->id) {
1413
+
case RT5651_AIF1:
1414
+
mask_clk = RT5651_I2S_PD1_MASK;
1415
+
val_clk = pre_div << RT5651_I2S_PD1_SFT;
1416
+
snd_soc_update_bits(codec, RT5651_I2S1_SDP,
1417
+
RT5651_I2S_DL_MASK, val_len);
1418
+
snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk);
1419
+
break;
1420
+
case RT5651_AIF2:
1421
+
mask_clk = RT5651_I2S_BCLK_MS2_MASK | RT5651_I2S_PD2_MASK;
1422
+
val_clk = pre_div << RT5651_I2S_PD2_SFT;
1423
+
snd_soc_update_bits(codec, RT5651_I2S2_SDP,
1424
+
RT5651_I2S_DL_MASK, val_len);
1425
+
snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk);
1426
+
break;
1427
+
default:
1428
+
dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id);
1429
+
return -EINVAL;
1430
+
}
1431
+
1432
+
return 0;
1433
+
}
1434
+
1435
+
static int rt5651_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1436
+
{
1437
+
struct snd_soc_codec *codec = dai->codec;
1438
+
struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1439
+
unsigned int reg_val = 0;
1440
+
1441
+
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1442
+
case SND_SOC_DAIFMT_CBM_CFM:
1443
+
rt5651->master[dai->id] = 1;
1444
+
break;
1445
+
case SND_SOC_DAIFMT_CBS_CFS:
1446
+
reg_val |= RT5651_I2S_MS_S;
1447
+
rt5651->master[dai->id] = 0;
1448
+
break;
1449
+
default:
1450
+
return -EINVAL;
1451
+
}
1452
+
1453
+
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1454
+
case SND_SOC_DAIFMT_NB_NF:
1455
+
break;
1456
+
case SND_SOC_DAIFMT_IB_NF:
1457
+
reg_val |= RT5651_I2S_BP_INV;
1458
+
break;
1459
+
default:
1460
+
return -EINVAL;
1461
+
}
1462
+
1463
+
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1464
+
case SND_SOC_DAIFMT_I2S:
1465
+
break;
1466
+
case SND_SOC_DAIFMT_LEFT_J:
1467
+
reg_val |= RT5651_I2S_DF_LEFT;
1468
+
break;
1469
+
case SND_SOC_DAIFMT_DSP_A:
1470
+
reg_val |= RT5651_I2S_DF_PCM_A;
1471
+
break;
1472
+
case SND_SOC_DAIFMT_DSP_B:
1473
+
reg_val |= RT5651_I2S_DF_PCM_B;
1474
+
break;
1475
+
default:
1476
+
return -EINVAL;
1477
+
}
1478
+
1479
+
switch (dai->id) {
1480
+
case RT5651_AIF1:
1481
+
snd_soc_update_bits(codec, RT5651_I2S1_SDP,
1482
+
RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1483
+
RT5651_I2S_DF_MASK, reg_val);
1484
+
break;
1485
+
case RT5651_AIF2:
1486
+
snd_soc_update_bits(codec, RT5651_I2S2_SDP,
1487
+
RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1488
+
RT5651_I2S_DF_MASK, reg_val);
1489
+
break;
1490
+
default:
1491
+
dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id);
1492
+
return -EINVAL;
1493
+
}
1494
+
return 0;
1495
+
}
1496
+
1497
+
static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
1498
+
int clk_id, unsigned int freq, int dir)
1499
+
{
1500
+
struct snd_soc_codec *codec = dai->codec;
1501
+
struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1502
+
unsigned int reg_val = 0;
1503
+
1504
+
if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src)
1505
+
return 0;
1506
+
1507
+
switch (clk_id) {
1508
+
case RT5651_SCLK_S_MCLK:
1509
+
reg_val |= RT5651_SCLK_SRC_MCLK;
1510
+
break;
1511
+
case RT5651_SCLK_S_PLL1:
1512
+
reg_val |= RT5651_SCLK_SRC_PLL1;
1513
+
break;
1514
+
case RT5651_SCLK_S_RCCLK:
1515
+
reg_val |= RT5651_SCLK_SRC_RCCLK;
1516
+
break;
1517
+
default:
1518
+
dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
1519
+
return -EINVAL;
1520
+
}
1521
+
snd_soc_update_bits(codec, RT5651_GLB_CLK,
1522
+
RT5651_SCLK_SRC_MASK, reg_val);
1523
+
rt5651->sysclk = freq;
1524
+
rt5651->sysclk_src = clk_id;
1525
+
1526
+
dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1527
+
1528
+
return 0;
1529
+
}
1530
+
1531
+
/**
1532
+
* rt5651_pll_calc - Calcualte PLL M/N/K code.
1533
+
* @freq_in: external clock provided to codec.
1534
+
* @freq_out: target clock which codec works on.
1535
+
* @pll_code: Pointer to structure with M, N, K and bypass flag.
1536
+
*
1537
+
* Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
1538
+
* which make calculation more efficiently.
1539
+
*
1540
+
* Returns 0 for success or negative error code.
1541
+
*/
1542
+
static int rt5651_pll_calc(const unsigned int freq_in,
1543
+
const unsigned int freq_out, struct rt5651_pll_code *pll_code)
1544
+
{
1545
+
int max_n = RT5651_PLL_N_MAX, max_m = RT5651_PLL_M_MAX;
1546
+
int n = 0, m = 0, red, n_t, m_t, in_t, out_t;
1547
+
int red_t = abs(freq_out - freq_in);
1548
+
bool bypass = false;
1549
+
1550
+
if (RT5651_PLL_INP_MAX < freq_in || RT5651_PLL_INP_MIN > freq_in)
1551
+
return -EINVAL;
1552
+
1553
+
for (n_t = 0; n_t <= max_n; n_t++) {
1554
+
in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
1555
+
if (in_t < 0)
1556
+
continue;
1557
+
if (in_t == freq_out) {
1558
+
bypass = true;
1559
+
n = n_t;
1560
+
goto code_find;
1561
+
}
1562
+
for (m_t = 0; m_t <= max_m; m_t++) {
1563
+
out_t = in_t / (m_t + 2);
1564
+
red = abs(out_t - freq_out);
1565
+
if (red < red_t) {
1566
+
n = n_t;
1567
+
m = m_t;
1568
+
if (red == 0)
1569
+
goto code_find;
1570
+
red_t = red;
1571
+
}
1572
+
}
1573
+
}
1574
+
pr_debug("Only get approximation about PLL\n");
1575
+
1576
+
code_find:
1577
+
pll_code->m_bp = bypass;
1578
+
pll_code->m_code = m;
1579
+
pll_code->n_code = n;
1580
+
pll_code->k_code = 2;
1581
+
return 0;
1582
+
}
1583
+
1584
+
static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1585
+
unsigned int freq_in, unsigned int freq_out)
1586
+
{
1587
+
struct snd_soc_codec *codec = dai->codec;
1588
+
struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1589
+
struct rt5651_pll_code *pll_code = &rt5651->pll_code;
1590
+
int ret;
1591
+
1592
+
if (source == rt5651->pll_src && freq_in == rt5651->pll_in &&
1593
+
freq_out == rt5651->pll_out)
1594
+
return 0;
1595
+
1596
+
if (!freq_in || !freq_out) {
1597
+
dev_dbg(codec->dev, "PLL disabled\n");
1598
+
1599
+
rt5651->pll_in = 0;
1600
+
rt5651->pll_out = 0;
1601
+
snd_soc_update_bits(codec, RT5651_GLB_CLK,
1602
+
RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_MCLK);
1603
+
return 0;
1604
+
}
1605
+
1606
+
switch (source) {
1607
+
case RT5651_PLL1_S_MCLK:
1608
+
snd_soc_update_bits(codec, RT5651_GLB_CLK,
1609
+
RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_MCLK);
1610
+
break;
1611
+
case RT5651_PLL1_S_BCLK1:
1612
+
snd_soc_update_bits(codec, RT5651_GLB_CLK,
1613
+
RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK1);
1614
+
break;
1615
+
case RT5651_PLL1_S_BCLK2:
1616
+
snd_soc_update_bits(codec, RT5651_GLB_CLK,
1617
+
RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK2);
1618
+
break;
1619
+
default:
1620
+
dev_err(codec->dev, "Unknown PLL source %d\n", source);
1621
+
return -EINVAL;
1622
+
}
1623
+
1624
+
ret = rt5651_pll_calc(freq_in, freq_out, pll_code);
1625
+
if (ret < 0) {
1626
+
dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
1627
+
return ret;
1628
+
}
1629
+
1630
+
dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code->m_bp,
1631
+
(pll_code->m_bp ? 0 : pll_code->m_code), pll_code->n_code);
1632
+
1633
+
snd_soc_write(codec, RT5651_PLL_CTRL1,
1634
+
pll_code->n_code << RT5651_PLL_N_SFT | pll_code->k_code);
1635
+
snd_soc_write(codec, RT5651_PLL_CTRL2,
1636
+
(pll_code->m_bp ? 0 : pll_code->m_code) << RT5651_PLL_M_SFT |
1637
+
pll_code->m_bp << RT5651_PLL_M_BP_SFT);
1638
+
1639
+
rt5651->pll_in = freq_in;
1640
+
rt5651->pll_out = freq_out;
1641
+
rt5651->pll_src = source;
1642
+
1643
+
return 0;
1644
+
}
1645
+
1646
+
static int rt5651_set_bias_level(struct snd_soc_codec *codec,
1647
+
enum snd_soc_bias_level level)
1648
+
{
1649
+
switch (level) {
1650
+
case SND_SOC_BIAS_PREPARE:
1651
+
if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
1652
+
snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1653
+
RT5651_PWR_VREF1 | RT5651_PWR_MB |
1654
+
RT5651_PWR_BG | RT5651_PWR_VREF2,
1655
+
RT5651_PWR_VREF1 | RT5651_PWR_MB |
1656
+
RT5651_PWR_BG | RT5651_PWR_VREF2);
1657
+
usleep_range(10000, 15000);
1658
+
snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1659
+
RT5651_PWR_FV1 | RT5651_PWR_FV2,
1660
+
RT5651_PWR_FV1 | RT5651_PWR_FV2);
1661
+
snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1662
+
RT5651_PWR_LDO_DVO_MASK,
1663
+
RT5651_PWR_LDO_DVO_1_2V);
1664
+
snd_soc_update_bits(codec, RT5651_D_MISC, 0x1, 0x1);
1665
+
if (snd_soc_read(codec, RT5651_PLL_MODE_1) & 0x9200)
1666
+
snd_soc_update_bits(codec, RT5651_D_MISC,
1667
+
0xc00, 0xc00);
1668
+
}
1669
+
break;
1670
+
1671
+
case SND_SOC_BIAS_STANDBY:
1672
+
snd_soc_write(codec, RT5651_D_MISC, 0x0010);
1673
+
snd_soc_write(codec, RT5651_PWR_DIG1, 0x0000);
1674
+
snd_soc_write(codec, RT5651_PWR_DIG2, 0x0000);
1675
+
snd_soc_write(codec, RT5651_PWR_VOL, 0x0000);
1676
+
snd_soc_write(codec, RT5651_PWR_MIXER, 0x0000);
1677
+
snd_soc_write(codec, RT5651_PWR_ANLG1, 0x0000);
1678
+
snd_soc_write(codec, RT5651_PWR_ANLG2, 0x0000);
1679
+
break;
1680
+
1681
+
default:
1682
+
break;
1683
+
}
1684
+
codec->dapm.bias_level = level;
1685
+
1686
+
return 0;
1687
+
}
1688
+
1689
+
static int rt5651_probe(struct snd_soc_codec *codec)
1690
+
{
1691
+
struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1692
+
1693
+
rt5651->codec = codec;
1694
+
1695
+
snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1696
+
RT5651_PWR_VREF1 | RT5651_PWR_MB |
1697
+
RT5651_PWR_BG | RT5651_PWR_VREF2,
1698
+
RT5651_PWR_VREF1 | RT5651_PWR_MB |
1699
+
RT5651_PWR_BG | RT5651_PWR_VREF2);
1700
+
usleep_range(10000, 15000);
1701
+
snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1702
+
RT5651_PWR_FV1 | RT5651_PWR_FV2,
1703
+
RT5651_PWR_FV1 | RT5651_PWR_FV2);
1704
+
1705
+
rt5651_set_bias_level(codec, SND_SOC_BIAS_OFF);
1706
+
1707
+
return 0;
1708
+
}
1709
+
1710
+
#ifdef CONFIG_PM
1711
+
static int rt5651_suspend(struct snd_soc_codec *codec)
1712
+
{
1713
+
struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1714
+
1715
+
regcache_cache_only(rt5651->regmap, true);
1716
+
regcache_mark_dirty(rt5651->regmap);
1717
+
return 0;
1718
+
}
1719
+
1720
+
static int rt5651_resume(struct snd_soc_codec *codec)
1721
+
{
1722
+
struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1723
+
1724
+
regcache_cache_only(rt5651->regmap, false);
1725
+
snd_soc_cache_sync(codec);
1726
+
1727
+
return 0;
1728
+
}
1729
+
#else
1730
+
#define rt5651_suspend NULL
1731
+
#define rt5651_resume NULL
1732
+
#endif
1733
+
1734
+
#define RT5651_STEREO_RATES SNDRV_PCM_RATE_8000_96000
1735
+
#define RT5651_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1736
+
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1737
+
1738
+
static const struct snd_soc_dai_ops rt5651_aif_dai_ops = {
1739
+
.hw_params = rt5651_hw_params,
1740
+
.set_fmt = rt5651_set_dai_fmt,
1741
+
.set_sysclk = rt5651_set_dai_sysclk,
1742
+
.set_pll = rt5651_set_dai_pll,
1743
+
};
1744
+
1745
+
static struct snd_soc_dai_driver rt5651_dai[] = {
1746
+
{
1747
+
.name = "rt5651-aif1",
1748
+
.id = RT5651_AIF1,
1749
+
.playback = {
1750
+
.stream_name = "AIF1 Playback",
1751
+
.channels_min = 1,
1752
+
.channels_max = 2,
1753
+
.rates = RT5651_STEREO_RATES,
1754
+
.formats = RT5651_FORMATS,
1755
+
},
1756
+
.capture = {
1757
+
.stream_name = "AIF1 Capture",
1758
+
.channels_min = 1,
1759
+
.channels_max = 2,
1760
+
.rates = RT5651_STEREO_RATES,
1761
+
.formats = RT5651_FORMATS,
1762
+
},
1763
+
.ops = &rt5651_aif_dai_ops,
1764
+
},
1765
+
{
1766
+
.name = "rt5651-aif2",
1767
+
.id = RT5651_AIF2,
1768
+
.playback = {
1769
+
.stream_name = "AIF2 Playback",
1770
+
.channels_min = 1,
1771
+
.channels_max = 2,
1772
+
.rates = RT5651_STEREO_RATES,
1773
+
.formats = RT5651_FORMATS,
1774
+
},
1775
+
.capture = {
1776
+
.stream_name = "AIF2 Capture",
1777
+
.channels_min = 1,
1778
+
.channels_max = 2,
1779
+
.rates = RT5651_STEREO_RATES,
1780
+
.formats = RT5651_FORMATS,
1781
+
},
1782
+
.ops = &rt5651_aif_dai_ops,
1783
+
},
1784
+
};
1785
+
1786
+
static struct snd_soc_codec_driver soc_codec_dev_rt5651 = {
1787
+
.probe = rt5651_probe,
1788
+
.suspend = rt5651_suspend,
1789
+
.resume = rt5651_resume,
1790
+
.set_bias_level = rt5651_set_bias_level,
1791
+
.idle_bias_off = true,
1792
+
.controls = rt5651_snd_controls,
1793
+
.num_controls = ARRAY_SIZE(rt5651_snd_controls),
1794
+
.dapm_widgets = rt5651_dapm_widgets,
1795
+
.num_dapm_widgets = ARRAY_SIZE(rt5651_dapm_widgets),
1796
+
.dapm_routes = rt5651_dapm_routes,
1797
+
.num_dapm_routes = ARRAY_SIZE(rt5651_dapm_routes),
1798
+
};
1799
+
1800
+
static const struct regmap_config rt5651_regmap = {
1801
+
.reg_bits = 8,
1802
+
.val_bits = 16,
1803
+
1804
+
.max_register = RT5651_DEVICE_ID + 1 + (ARRAY_SIZE(rt5651_ranges) *
1805
+
RT5651_PR_SPACING),
1806
+
.volatile_reg = rt5651_volatile_register,
1807
+
.readable_reg = rt5651_readable_register,
1808
+
1809
+
.cache_type = REGCACHE_RBTREE,
1810
+
.reg_defaults = rt5651_reg,
1811
+
.num_reg_defaults = ARRAY_SIZE(rt5651_reg),
1812
+
.ranges = rt5651_ranges,
1813
+
.num_ranges = ARRAY_SIZE(rt5651_ranges),
1814
+
};
1815
+
1816
+
static const struct i2c_device_id rt5651_i2c_id[] = {
1817
+
{ "rt5651", 0 },
1818
+
{ }
1819
+
};
1820
+
MODULE_DEVICE_TABLE(i2c, rt5651_i2c_id);
1821
+
1822
+
static int rt5651_i2c_probe(struct i2c_client *i2c,
1823
+
const struct i2c_device_id *id)
1824
+
{
1825
+
struct rt5651_platform_data *pdata = dev_get_platdata(&i2c->dev);
1826
+
struct rt5651_priv *rt5651;
1827
+
int ret;
1828
+
1829
+
rt5651 = devm_kzalloc(&i2c->dev, sizeof(*rt5651),
1830
+
GFP_KERNEL);
1831
+
if (NULL == rt5651)
1832
+
return -ENOMEM;
1833
+
1834
+
i2c_set_clientdata(i2c, rt5651);
1835
+
1836
+
if (pdata)
1837
+
rt5651->pdata = *pdata;
1838
+
1839
+
rt5651->regmap = devm_regmap_init_i2c(i2c, &rt5651_regmap);
1840
+
if (IS_ERR(rt5651->regmap)) {
1841
+
ret = PTR_ERR(rt5651->regmap);
1842
+
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1843
+
ret);
1844
+
return ret;
1845
+
}
1846
+
1847
+
regmap_read(rt5651->regmap, RT5651_DEVICE_ID, &ret);
1848
+
if (ret != RT5651_DEVICE_ID_VALUE) {
1849
+
dev_err(&i2c->dev,
1850
+
"Device with ID register %x is not rt5651\n", ret);
1851
+
return -ENODEV;
1852
+
}
1853
+
1854
+
regmap_write(rt5651->regmap, RT5651_RESET, 0);
1855
+
1856
+
ret = regmap_register_patch(rt5651->regmap, init_list,
1857
+
ARRAY_SIZE(init_list));
1858
+
if (ret != 0)
1859
+
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1860
+
1861
+
if (rt5651->pdata.in2_diff)
1862
+
regmap_update_bits(rt5651->regmap, RT5651_IN1_IN2,
1863
+
RT5651_IN_DF2, RT5651_IN_DF2);
1864
+
1865
+
if (rt5651->pdata.dmic_en)
1866
+
regmap_update_bits(rt5651->regmap, RT5651_GPIO_CTRL1,
1867
+
RT5651_GP2_PIN_MASK, RT5651_GP2_PIN_DMIC1_SCL);
1868
+
1869
+
rt5651->hp_mute = 1;
1870
+
1871
+
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5651,
1872
+
rt5651_dai, ARRAY_SIZE(rt5651_dai));
1873
+
1874
+
return ret;
1875
+
}
1876
+
1877
+
static int rt5651_i2c_remove(struct i2c_client *i2c)
1878
+
{
1879
+
snd_soc_unregister_codec(&i2c->dev);
1880
+
1881
+
return 0;
1882
+
}
1883
+
1884
+
static struct i2c_driver rt5651_i2c_driver = {
1885
+
.driver = {
1886
+
.name = "rt5651",
1887
+
.owner = THIS_MODULE,
1888
+
},
1889
+
.probe = rt5651_i2c_probe,
1890
+
.remove = rt5651_i2c_remove,
1891
+
.id_table = rt5651_i2c_id,
1892
+
};
1893
+
module_i2c_driver(rt5651_i2c_driver);
1894
+
1895
+
MODULE_DESCRIPTION("ASoC RT5651 driver");
1896
+
MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1897
+
MODULE_LICENSE("GPL v2");
+2081
sound/soc/codecs/rt5651.h
+2081
sound/soc/codecs/rt5651.h
···
1
+
/*
2
+
* rt5651.h -- RT5651 ALSA SoC audio driver
3
+
*
4
+
* Copyright 2011 Realtek Microelectronics
5
+
* Author: Johnny Hsu <johnnyhsu@realtek.com>
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
10
+
*/
11
+
12
+
#ifndef __RT5651_H__
13
+
#define __RT5651_H__
14
+
15
+
#include <sound/rt5651.h>
16
+
17
+
/* Info */
18
+
#define RT5651_RESET 0x00
19
+
#define RT5651_VERSION_ID 0xfd
20
+
#define RT5651_VENDOR_ID 0xfe
21
+
#define RT5651_DEVICE_ID 0xff
22
+
/* I/O - Output */
23
+
#define RT5651_HP_VOL 0x02
24
+
#define RT5651_LOUT_CTRL1 0x03
25
+
#define RT5651_LOUT_CTRL2 0x05
26
+
/* I/O - Input */
27
+
#define RT5651_IN1_IN2 0x0d
28
+
#define RT5651_IN3 0x0e
29
+
#define RT5651_INL1_INR1_VOL 0x0f
30
+
#define RT5651_INL2_INR2_VOL 0x10
31
+
/* I/O - ADC/DAC/DMIC */
32
+
#define RT5651_DAC1_DIG_VOL 0x19
33
+
#define RT5651_DAC2_DIG_VOL 0x1a
34
+
#define RT5651_DAC2_CTRL 0x1b
35
+
#define RT5651_ADC_DIG_VOL 0x1c
36
+
#define RT5651_ADC_DATA 0x1d
37
+
#define RT5651_ADC_BST_VOL 0x1e
38
+
/* Mixer - D-D */
39
+
#define RT5651_STO1_ADC_MIXER 0x27
40
+
#define RT5651_STO2_ADC_MIXER 0x28
41
+
#define RT5651_AD_DA_MIXER 0x29
42
+
#define RT5651_STO_DAC_MIXER 0x2a
43
+
#define RT5651_DD_MIXER 0x2b
44
+
#define RT5651_DIG_INF_DATA 0x2f
45
+
/* PDM */
46
+
#define RT5651_PDM_CTL 0x30
47
+
#define RT5651_PDM_I2C_CTL1 0x31
48
+
#define RT5651_PDM_I2C_CTL2 0x32
49
+
#define RT5651_PDM_I2C_DATA_W 0x33
50
+
#define RT5651_PDM_I2C_DATA_R 0x34
51
+
/* Mixer - ADC */
52
+
#define RT5651_REC_L1_MIXER 0x3b
53
+
#define RT5651_REC_L2_MIXER 0x3c
54
+
#define RT5651_REC_R1_MIXER 0x3d
55
+
#define RT5651_REC_R2_MIXER 0x3e
56
+
/* Mixer - DAC */
57
+
#define RT5651_HPO_MIXER 0x45
58
+
#define RT5651_OUT_L1_MIXER 0x4d
59
+
#define RT5651_OUT_L2_MIXER 0x4e
60
+
#define RT5651_OUT_L3_MIXER 0x4f
61
+
#define RT5651_OUT_R1_MIXER 0x50
62
+
#define RT5651_OUT_R2_MIXER 0x51
63
+
#define RT5651_OUT_R3_MIXER 0x52
64
+
#define RT5651_LOUT_MIXER 0x53
65
+
/* Power */
66
+
#define RT5651_PWR_DIG1 0x61
67
+
#define RT5651_PWR_DIG2 0x62
68
+
#define RT5651_PWR_ANLG1 0x63
69
+
#define RT5651_PWR_ANLG2 0x64
70
+
#define RT5651_PWR_MIXER 0x65
71
+
#define RT5651_PWR_VOL 0x66
72
+
/* Private Register Control */
73
+
#define RT5651_PRIV_INDEX 0x6a
74
+
#define RT5651_PRIV_DATA 0x6c
75
+
/* Format - ADC/DAC */
76
+
#define RT5651_I2S1_SDP 0x70
77
+
#define RT5651_I2S2_SDP 0x71
78
+
#define RT5651_ADDA_CLK1 0x73
79
+
#define RT5651_ADDA_CLK2 0x74
80
+
#define RT5651_DMIC 0x75
81
+
/* TDM Control */
82
+
#define RT5651_TDM_CTL_1 0x77
83
+
#define RT5651_TDM_CTL_2 0x78
84
+
#define RT5651_TDM_CTL_3 0x79
85
+
/* Function - Analog */
86
+
#define RT5651_GLB_CLK 0x80
87
+
#define RT5651_PLL_CTRL1 0x81
88
+
#define RT5651_PLL_CTRL2 0x82
89
+
#define RT5651_PLL_MODE_1 0x83
90
+
#define RT5651_PLL_MODE_2 0x84
91
+
#define RT5651_PLL_MODE_3 0x85
92
+
#define RT5651_PLL_MODE_4 0x86
93
+
#define RT5651_PLL_MODE_5 0x87
94
+
#define RT5651_PLL_MODE_6 0x89
95
+
#define RT5651_PLL_MODE_7 0x8a
96
+
#define RT5651_DEPOP_M1 0x8e
97
+
#define RT5651_DEPOP_M2 0x8f
98
+
#define RT5651_DEPOP_M3 0x90
99
+
#define RT5651_CHARGE_PUMP 0x91
100
+
#define RT5651_MICBIAS 0x93
101
+
#define RT5651_A_JD_CTL1 0x94
102
+
/* Function - Digital */
103
+
#define RT5651_EQ_CTRL1 0xb0
104
+
#define RT5651_EQ_CTRL2 0xb1
105
+
#define RT5651_ALC_1 0xb4
106
+
#define RT5651_ALC_2 0xb5
107
+
#define RT5651_ALC_3 0xb6
108
+
#define RT5651_JD_CTRL1 0xbb
109
+
#define RT5651_JD_CTRL2 0xbc
110
+
#define RT5651_IRQ_CTRL1 0xbd
111
+
#define RT5651_IRQ_CTRL2 0xbe
112
+
#define RT5651_INT_IRQ_ST 0xbf
113
+
#define RT5651_GPIO_CTRL1 0xc0
114
+
#define RT5651_GPIO_CTRL2 0xc1
115
+
#define RT5651_GPIO_CTRL3 0xc2
116
+
#define RT5651_PGM_REG_ARR1 0xc8
117
+
#define RT5651_PGM_REG_ARR2 0xc9
118
+
#define RT5651_PGM_REG_ARR3 0xca
119
+
#define RT5651_PGM_REG_ARR4 0xcb
120
+
#define RT5651_PGM_REG_ARR5 0xcc
121
+
#define RT5651_SCB_FUNC 0xcd
122
+
#define RT5651_SCB_CTRL 0xce
123
+
#define RT5651_BASE_BACK 0xcf
124
+
#define RT5651_MP3_PLUS1 0xd0
125
+
#define RT5651_MP3_PLUS2 0xd1
126
+
#define RT5651_ADJ_HPF_CTRL1 0xd3
127
+
#define RT5651_ADJ_HPF_CTRL2 0xd4
128
+
#define RT5651_HP_CALIB_AMP_DET 0xd6
129
+
#define RT5651_HP_CALIB2 0xd7
130
+
#define RT5651_SV_ZCD1 0xd9
131
+
#define RT5651_SV_ZCD2 0xda
132
+
#define RT5651_D_MISC 0xfa
133
+
/* Dummy Register */
134
+
#define RT5651_DUMMY2 0xfb
135
+
#define RT5651_DUMMY3 0xfc
136
+
137
+
138
+
/* Index of Codec Private Register definition */
139
+
#define RT5651_BIAS_CUR1 0x12
140
+
#define RT5651_BIAS_CUR3 0x14
141
+
#define RT5651_CLSD_INT_REG1 0x1c
142
+
#define RT5651_CHPUMP_INT_REG1 0x24
143
+
#define RT5651_MAMP_INT_REG2 0x37
144
+
#define RT5651_CHOP_DAC_ADC 0x3d
145
+
#define RT5651_3D_SPK 0x63
146
+
#define RT5651_WND_1 0x6c
147
+
#define RT5651_WND_2 0x6d
148
+
#define RT5651_WND_3 0x6e
149
+
#define RT5651_WND_4 0x6f
150
+
#define RT5651_WND_5 0x70
151
+
#define RT5651_WND_8 0x73
152
+
#define RT5651_DIP_SPK_INF 0x75
153
+
#define RT5651_HP_DCC_INT1 0x77
154
+
#define RT5651_EQ_BW_LOP 0xa0
155
+
#define RT5651_EQ_GN_LOP 0xa1
156
+
#define RT5651_EQ_FC_BP1 0xa2
157
+
#define RT5651_EQ_BW_BP1 0xa3
158
+
#define RT5651_EQ_GN_BP1 0xa4
159
+
#define RT5651_EQ_FC_BP2 0xa5
160
+
#define RT5651_EQ_BW_BP2 0xa6
161
+
#define RT5651_EQ_GN_BP2 0xa7
162
+
#define RT5651_EQ_FC_BP3 0xa8
163
+
#define RT5651_EQ_BW_BP3 0xa9
164
+
#define RT5651_EQ_GN_BP3 0xaa
165
+
#define RT5651_EQ_FC_BP4 0xab
166
+
#define RT5651_EQ_BW_BP4 0xac
167
+
#define RT5651_EQ_GN_BP4 0xad
168
+
#define RT5651_EQ_FC_HIP1 0xae
169
+
#define RT5651_EQ_GN_HIP1 0xaf
170
+
#define RT5651_EQ_FC_HIP2 0xb0
171
+
#define RT5651_EQ_BW_HIP2 0xb1
172
+
#define RT5651_EQ_GN_HIP2 0xb2
173
+
#define RT5651_EQ_PRE_VOL 0xb3
174
+
#define RT5651_EQ_PST_VOL 0xb4
175
+
176
+
177
+
/* global definition */
178
+
#define RT5651_L_MUTE (0x1 << 15)
179
+
#define RT5651_L_MUTE_SFT 15
180
+
#define RT5651_VOL_L_MUTE (0x1 << 14)
181
+
#define RT5651_VOL_L_SFT 14
182
+
#define RT5651_R_MUTE (0x1 << 7)
183
+
#define RT5651_R_MUTE_SFT 7
184
+
#define RT5651_VOL_R_MUTE (0x1 << 6)
185
+
#define RT5651_VOL_R_SFT 6
186
+
#define RT5651_L_VOL_MASK (0x3f << 8)
187
+
#define RT5651_L_VOL_SFT 8
188
+
#define RT5651_R_VOL_MASK (0x3f)
189
+
#define RT5651_R_VOL_SFT 0
190
+
191
+
/* LOUT Control 2(0x05) */
192
+
#define RT5651_EN_DFO (0x1 << 15)
193
+
194
+
/* IN1 and IN2 Control (0x0d) */
195
+
/* IN3 and IN4 Control (0x0e) */
196
+
#define RT5651_BST_MASK1 (0xf<<12)
197
+
#define RT5651_BST_SFT1 12
198
+
#define RT5651_BST_MASK2 (0xf<<8)
199
+
#define RT5651_BST_SFT2 8
200
+
#define RT5651_IN_DF1 (0x1 << 7)
201
+
#define RT5651_IN_SFT1 7
202
+
#define RT5651_IN_DF2 (0x1 << 6)
203
+
#define RT5651_IN_SFT2 6
204
+
205
+
/* INL1 and INR1 Volume Control (0x0f) */
206
+
/* INL2 and INR2 Volume Control (0x10) */
207
+
#define RT5651_INL_SEL_MASK (0x1 << 15)
208
+
#define RT5651_INL_SEL_SFT 15
209
+
#define RT5651_INL_SEL_IN4P (0x0 << 15)
210
+
#define RT5651_INL_SEL_MONOP (0x1 << 15)
211
+
#define RT5651_INL_VOL_MASK (0x1f << 8)
212
+
#define RT5651_INL_VOL_SFT 8
213
+
#define RT5651_INR_SEL_MASK (0x1 << 7)
214
+
#define RT5651_INR_SEL_SFT 7
215
+
#define RT5651_INR_SEL_IN4N (0x0 << 7)
216
+
#define RT5651_INR_SEL_MONON (0x1 << 7)
217
+
#define RT5651_INR_VOL_MASK (0x1f)
218
+
#define RT5651_INR_VOL_SFT 0
219
+
220
+
/* DAC1 Digital Volume (0x19) */
221
+
#define RT5651_DAC_L1_VOL_MASK (0xff << 8)
222
+
#define RT5651_DAC_L1_VOL_SFT 8
223
+
#define RT5651_DAC_R1_VOL_MASK (0xff)
224
+
#define RT5651_DAC_R1_VOL_SFT 0
225
+
226
+
/* DAC2 Digital Volume (0x1a) */
227
+
#define RT5651_DAC_L2_VOL_MASK (0xff << 8)
228
+
#define RT5651_DAC_L2_VOL_SFT 8
229
+
#define RT5651_DAC_R2_VOL_MASK (0xff)
230
+
#define RT5651_DAC_R2_VOL_SFT 0
231
+
232
+
/* DAC2 Control (0x1b) */
233
+
#define RT5651_M_DAC_L2_VOL (0x1 << 13)
234
+
#define RT5651_M_DAC_L2_VOL_SFT 13
235
+
#define RT5651_M_DAC_R2_VOL (0x1 << 12)
236
+
#define RT5651_M_DAC_R2_VOL_SFT 12
237
+
#define RT5651_SEL_DAC_L2 (0x1 << 11)
238
+
#define RT5651_IF2_DAC_L2 (0x1 << 11)
239
+
#define RT5651_IF1_DAC_L2 (0x0 << 11)
240
+
#define RT5651_SEL_DAC_L2_SFT 11
241
+
#define RT5651_SEL_DAC_R2 (0x1 << 10)
242
+
#define RT5651_IF2_DAC_R2 (0x1 << 11)
243
+
#define RT5651_IF1_DAC_R2 (0x0 << 11)
244
+
#define RT5651_SEL_DAC_R2_SFT 10
245
+
246
+
/* ADC Digital Volume Control (0x1c) */
247
+
#define RT5651_ADC_L_VOL_MASK (0x7f << 8)
248
+
#define RT5651_ADC_L_VOL_SFT 8
249
+
#define RT5651_ADC_R_VOL_MASK (0x7f)
250
+
#define RT5651_ADC_R_VOL_SFT 0
251
+
252
+
/* Mono ADC Digital Volume Control (0x1d) */
253
+
#define RT5651_M_MONO_ADC_L (0x1 << 15)
254
+
#define RT5651_M_MONO_ADC_L_SFT 15
255
+
#define RT5651_MONO_ADC_L_VOL_MASK (0x7f << 8)
256
+
#define RT5651_MONO_ADC_L_VOL_SFT 8
257
+
#define RT5651_M_MONO_ADC_R (0x1 << 7)
258
+
#define RT5651_M_MONO_ADC_R_SFT 7
259
+
#define RT5651_MONO_ADC_R_VOL_MASK (0x7f)
260
+
#define RT5651_MONO_ADC_R_VOL_SFT 0
261
+
262
+
/* ADC Boost Volume Control (0x1e) */
263
+
#define RT5651_ADC_L_BST_MASK (0x3 << 14)
264
+
#define RT5651_ADC_L_BST_SFT 14
265
+
#define RT5651_ADC_R_BST_MASK (0x3 << 12)
266
+
#define RT5651_ADC_R_BST_SFT 12
267
+
#define RT5651_ADC_COMP_MASK (0x3 << 10)
268
+
#define RT5651_ADC_COMP_SFT 10
269
+
270
+
/* Stereo ADC1 Mixer Control (0x27) */
271
+
#define RT5651_M_STO1_ADC_L1 (0x1 << 14)
272
+
#define RT5651_M_STO1_ADC_L1_SFT 14
273
+
#define RT5651_M_STO1_ADC_L2 (0x1 << 13)
274
+
#define RT5651_M_STO1_ADC_L2_SFT 13
275
+
#define RT5651_STO1_ADC_1_SRC_MASK (0x1 << 12)
276
+
#define RT5651_STO1_ADC_1_SRC_SFT 12
277
+
#define RT5651_STO1_ADC_1_SRC_ADC (0x1 << 12)
278
+
#define RT5651_STO1_ADC_1_SRC_DACMIX (0x0 << 12)
279
+
#define RT5651_STO1_ADC_2_SRC_MASK (0x1 << 11)
280
+
#define RT5651_STO1_ADC_2_SRC_SFT 11
281
+
#define RT5651_STO1_ADC_2_SRC_DMIC (0x0 << 11)
282
+
#define RT5651_STO1_ADC_2_SRC_DACMIXR (0x1 << 11)
283
+
#define RT5651_M_STO1_ADC_R1 (0x1 << 6)
284
+
#define RT5651_M_STO1_ADC_R1_SFT 6
285
+
#define RT5651_M_STO1_ADC_R2 (0x1 << 5)
286
+
#define RT5651_M_STO1_ADC_R2_SFT 5
287
+
288
+
/* Stereo ADC2 Mixer Control (0x28) */
289
+
#define RT5651_M_STO2_ADC_L1 (0x1 << 14)
290
+
#define RT5651_M_STO2_ADC_L1_SFT 14
291
+
#define RT5651_M_STO2_ADC_L2 (0x1 << 13)
292
+
#define RT5651_M_STO2_ADC_L2_SFT 13
293
+
#define RT5651_STO2_ADC_L1_SRC_MASK (0x1 << 12)
294
+
#define RT5651_STO2_ADC_L1_SRC_SFT 12
295
+
#define RT5651_STO2_ADC_L1_SRC_DACMIXL (0x0 << 12)
296
+
#define RT5651_STO2_ADC_L1_SRC_ADCL (0x1 << 12)
297
+
#define RT5651_STO2_ADC_L2_SRC_MASK (0x1 << 11)
298
+
#define RT5651_STO2_ADC_L2_SRC_SFT 11
299
+
#define RT5651_STO2_ADC_L2_SRC_DMIC (0x0 << 11)
300
+
#define RT5651_STO2_ADC_L2_SRC_DACMIXR (0x1 << 11)
301
+
#define RT5651_M_STO2_ADC_R1 (0x1 << 6)
302
+
#define RT5651_M_STO2_ADC_R1_SFT 6
303
+
#define RT5651_M_STO2_ADC_R2 (0x1 << 5)
304
+
#define RT5651_M_STO2_ADC_R2_SFT 5
305
+
#define RT5651_STO2_ADC_R1_SRC_MASK (0x1 << 4)
306
+
#define RT5651_STO2_ADC_R1_SRC_SFT 4
307
+
#define RT5651_STO2_ADC_R1_SRC_ADCR (0x1 << 4)
308
+
#define RT5651_STO2_ADC_R1_SRC_DACMIXR (0x0 << 4)
309
+
#define RT5651_STO2_ADC_R2_SRC_MASK (0x1 << 3)
310
+
#define RT5651_STO2_ADC_R2_SRC_SFT 3
311
+
#define RT5651_STO2_ADC_R2_SRC_DMIC (0x0 << 3)
312
+
#define RT5651_STO2_ADC_R2_SRC_DACMIXR (0x1 << 3)
313
+
314
+
/* ADC Mixer to DAC Mixer Control (0x29) */
315
+
#define RT5651_M_ADCMIX_L (0x1 << 15)
316
+
#define RT5651_M_ADCMIX_L_SFT 15
317
+
#define RT5651_M_IF1_DAC_L (0x1 << 14)
318
+
#define RT5651_M_IF1_DAC_L_SFT 14
319
+
#define RT5651_M_ADCMIX_R (0x1 << 7)
320
+
#define RT5651_M_ADCMIX_R_SFT 7
321
+
#define RT5651_M_IF1_DAC_R (0x1 << 6)
322
+
#define RT5651_M_IF1_DAC_R_SFT 6
323
+
324
+
/* Stereo DAC Mixer Control (0x2a) */
325
+
#define RT5651_M_DAC_L1_MIXL (0x1 << 14)
326
+
#define RT5651_M_DAC_L1_MIXL_SFT 14
327
+
#define RT5651_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
328
+
#define RT5651_DAC_L1_STO_L_VOL_SFT 13
329
+
#define RT5651_M_DAC_L2_MIXL (0x1 << 12)
330
+
#define RT5651_M_DAC_L2_MIXL_SFT 12
331
+
#define RT5651_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
332
+
#define RT5651_DAC_L2_STO_L_VOL_SFT 11
333
+
#define RT5651_M_DAC_R1_MIXL (0x1 << 9)
334
+
#define RT5651_M_DAC_R1_MIXL_SFT 9
335
+
#define RT5651_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
336
+
#define RT5651_DAC_R1_STO_L_VOL_SFT 8
337
+
#define RT5651_M_DAC_R1_MIXR (0x1 << 6)
338
+
#define RT5651_M_DAC_R1_MIXR_SFT 6
339
+
#define RT5651_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
340
+
#define RT5651_DAC_R1_STO_R_VOL_SFT 5
341
+
#define RT5651_M_DAC_R2_MIXR (0x1 << 4)
342
+
#define RT5651_M_DAC_R2_MIXR_SFT 4
343
+
#define RT5651_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
344
+
#define RT5651_DAC_R2_STO_R_VOL_SFT 3
345
+
#define RT5651_M_DAC_L1_MIXR (0x1 << 1)
346
+
#define RT5651_M_DAC_L1_MIXR_SFT 1
347
+
#define RT5651_DAC_L1_STO_R_VOL_MASK (0x1)
348
+
#define RT5651_DAC_L1_STO_R_VOL_SFT 0
349
+
350
+
/* DD Mixer Control (0x2b) */
351
+
#define RT5651_M_STO_DD_L1 (0x1 << 14)
352
+
#define RT5651_M_STO_DD_L1_SFT 14
353
+
#define RT5651_STO_DD_L1_VOL_MASK (0x1 << 13)
354
+
#define RT5651_DAC_DD_L1_VOL_SFT 13
355
+
#define RT5651_M_STO_DD_L2 (0x1 << 12)
356
+
#define RT5651_M_STO_DD_L2_SFT 12
357
+
#define RT5651_STO_DD_L2_VOL_MASK (0x1 << 11)
358
+
#define RT5651_STO_DD_L2_VOL_SFT 11
359
+
#define RT5651_M_STO_DD_R2_L (0x1 << 10)
360
+
#define RT5651_M_STO_DD_R2_L_SFT 10
361
+
#define RT5651_STO_DD_R2_L_VOL_MASK (0x1 << 9)
362
+
#define RT5651_STO_DD_R2_L_VOL_SFT 9
363
+
#define RT5651_M_STO_DD_R1 (0x1 << 6)
364
+
#define RT5651_M_STO_DD_R1_SFT 6
365
+
#define RT5651_STO_DD_R1_VOL_MASK (0x1 << 5)
366
+
#define RT5651_STO_DD_R1_VOL_SFT 5
367
+
#define RT5651_M_STO_DD_R2 (0x1 << 4)
368
+
#define RT5651_M_STO_DD_R2_SFT 4
369
+
#define RT5651_STO_DD_R2_VOL_MASK (0x1 << 3)
370
+
#define RT5651_STO_DD_R2_VOL_SFT 3
371
+
#define RT5651_M_STO_DD_L2_R (0x1 << 2)
372
+
#define RT5651_M_STO_DD_L2_R_SFT 2
373
+
#define RT5651_STO_DD_L2_R_VOL_MASK (0x1 << 1)
374
+
#define RT5651_STO_DD_L2_R_VOL_SFT 1
375
+
376
+
/* Digital Mixer Control (0x2c) */
377
+
#define RT5651_M_STO_L_DAC_L (0x1 << 15)
378
+
#define RT5651_M_STO_L_DAC_L_SFT 15
379
+
#define RT5651_STO_L_DAC_L_VOL_MASK (0x1 << 14)
380
+
#define RT5651_STO_L_DAC_L_VOL_SFT 14
381
+
#define RT5651_M_DAC_L2_DAC_L (0x1 << 13)
382
+
#define RT5651_M_DAC_L2_DAC_L_SFT 13
383
+
#define RT5651_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
384
+
#define RT5651_DAC_L2_DAC_L_VOL_SFT 12
385
+
#define RT5651_M_STO_R_DAC_R (0x1 << 11)
386
+
#define RT5651_M_STO_R_DAC_R_SFT 11
387
+
#define RT5651_STO_R_DAC_R_VOL_MASK (0x1 << 10)
388
+
#define RT5651_STO_R_DAC_R_VOL_SFT 10
389
+
#define RT5651_M_DAC_R2_DAC_R (0x1 << 9)
390
+
#define RT5651_M_DAC_R2_DAC_R_SFT 9
391
+
#define RT5651_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
392
+
#define RT5651_DAC_R2_DAC_R_VOL_SFT 8
393
+
394
+
/* DSP Path Control 1 (0x2d) */
395
+
#define RT5651_RXDP_SRC_MASK (0x1 << 15)
396
+
#define RT5651_RXDP_SRC_SFT 15
397
+
#define RT5651_RXDP_SRC_NOR (0x0 << 15)
398
+
#define RT5651_RXDP_SRC_DIV3 (0x1 << 15)
399
+
#define RT5651_TXDP_SRC_MASK (0x1 << 14)
400
+
#define RT5651_TXDP_SRC_SFT 14
401
+
#define RT5651_TXDP_SRC_NOR (0x0 << 14)
402
+
#define RT5651_TXDP_SRC_DIV3 (0x1 << 14)
403
+
404
+
/* DSP Path Control 2 (0x2e) */
405
+
#define RT5651_DAC_L2_SEL_MASK (0x3 << 14)
406
+
#define RT5651_DAC_L2_SEL_SFT 14
407
+
#define RT5651_DAC_L2_SEL_IF2 (0x0 << 14)
408
+
#define RT5651_DAC_L2_SEL_IF3 (0x1 << 14)
409
+
#define RT5651_DAC_L2_SEL_TXDC (0x2 << 14)
410
+
#define RT5651_DAC_L2_SEL_BASS (0x3 << 14)
411
+
#define RT5651_DAC_R2_SEL_MASK (0x3 << 12)
412
+
#define RT5651_DAC_R2_SEL_SFT 12
413
+
#define RT5651_DAC_R2_SEL_IF2 (0x0 << 12)
414
+
#define RT5651_DAC_R2_SEL_IF3 (0x1 << 12)
415
+
#define RT5651_DAC_R2_SEL_TXDC (0x2 << 12)
416
+
#define RT5651_IF2_ADC_L_SEL_MASK (0x1 << 11)
417
+
#define RT5651_IF2_ADC_L_SEL_SFT 11
418
+
#define RT5651_IF2_ADC_L_SEL_TXDP (0x0 << 11)
419
+
#define RT5651_IF2_ADC_L_SEL_PASS (0x1 << 11)
420
+
#define RT5651_IF2_ADC_R_SEL_MASK (0x1 << 10)
421
+
#define RT5651_IF2_ADC_R_SEL_SFT 10
422
+
#define RT5651_IF2_ADC_R_SEL_TXDP (0x0 << 10)
423
+
#define RT5651_IF2_ADC_R_SEL_PASS (0x1 << 10)
424
+
#define RT5651_RXDC_SEL_MASK (0x3 << 8)
425
+
#define RT5651_RXDC_SEL_SFT 8
426
+
#define RT5651_RXDC_SEL_NOR (0x0 << 8)
427
+
#define RT5651_RXDC_SEL_L2R (0x1 << 8)
428
+
#define RT5651_RXDC_SEL_R2L (0x2 << 8)
429
+
#define RT5651_RXDC_SEL_SWAP (0x3 << 8)
430
+
#define RT5651_RXDP_SEL_MASK (0x3 << 6)
431
+
#define RT5651_RXDP_SEL_SFT 6
432
+
#define RT5651_RXDP_SEL_NOR (0x0 << 6)
433
+
#define RT5651_RXDP_SEL_L2R (0x1 << 6)
434
+
#define RT5651_RXDP_SEL_R2L (0x2 << 6)
435
+
#define RT5651_RXDP_SEL_SWAP (0x3 << 6)
436
+
#define RT5651_TXDC_SEL_MASK (0x3 << 4)
437
+
#define RT5651_TXDC_SEL_SFT 4
438
+
#define RT5651_TXDC_SEL_NOR (0x0 << 4)
439
+
#define RT5651_TXDC_SEL_L2R (0x1 << 4)
440
+
#define RT5651_TXDC_SEL_R2L (0x2 << 4)
441
+
#define RT5651_TXDC_SEL_SWAP (0x3 << 4)
442
+
#define RT5651_TXDP_SEL_MASK (0x3 << 2)
443
+
#define RT5651_TXDP_SEL_SFT 2
444
+
#define RT5651_TXDP_SEL_NOR (0x0 << 2)
445
+
#define RT5651_TXDP_SEL_L2R (0x1 << 2)
446
+
#define RT5651_TXDP_SEL_R2L (0x2 << 2)
447
+
#define RT5651_TRXDP_SEL_SWAP (0x3 << 2)
448
+
449
+
/* Digital Interface Data Control (0x2f) */
450
+
#define RT5651_IF2_DAC_SEL_MASK (0x3 << 10)
451
+
#define RT5651_IF2_DAC_SEL_SFT 10
452
+
#define RT5651_IF2_DAC_SEL_NOR (0x0 << 10)
453
+
#define RT5651_IF2_DAC_SEL_SWAP (0x1 << 10)
454
+
#define RT5651_IF2_DAC_SEL_L2R (0x2 << 10)
455
+
#define RT5651_IF2_DAC_SEL_R2L (0x3 << 10)
456
+
#define RT5651_IF2_ADC_SEL_MASK (0x3 << 8)
457
+
#define RT5651_IF2_ADC_SEL_SFT 8
458
+
#define RT5651_IF2_ADC_SEL_NOR (0x0 << 8)
459
+
#define RT5651_IF2_ADC_SEL_SWAP (0x1 << 8)
460
+
#define RT5651_IF2_ADC_SEL_L2R (0x2 << 8)
461
+
#define RT5651_IF2_ADC_SEL_R2L (0x3 << 8)
462
+
#define RT5651_IF2_ADC_SRC_MASK (0x1 << 7)
463
+
#define RT5651_IF2_ADC_SRC_SFT 7
464
+
#define RT5651_IF1_ADC1 (0x0 << 7)
465
+
#define RT5651_IF1_ADC2 (0x1 << 7)
466
+
467
+
/* PDM Output Control (0x30) */
468
+
#define RT5651_PDM_L_SEL_MASK (0x1 << 15)
469
+
#define RT5651_PDM_L_SEL_SFT 15
470
+
#define RT5651_PDM_L_SEL_DD_L (0x0 << 15)
471
+
#define RT5651_PDM_L_SEL_STO_L (0x1 << 15)
472
+
#define RT5651_M_PDM_L (0x1 << 14)
473
+
#define RT5651_M_PDM_L_SFT 14
474
+
#define RT5651_PDM_R_SEL_MASK (0x1 << 13)
475
+
#define RT5651_PDM_R_SEL_SFT 13
476
+
#define RT5651_PDM_R_SEL_DD_L (0x0 << 13)
477
+
#define RT5651_PDM_R_SEL_STO_L (0x1 << 13)
478
+
#define RT5651_M_PDM_R (0x1 << 12)
479
+
#define RT5651_M_PDM_R_SFT 12
480
+
#define RT5651_PDM_BUSY (0x1 << 6)
481
+
#define RT5651_PDM_BUSY_SFT 6
482
+
#define RT5651_PDM_PATTERN_SEL_MASK (0x1 << 5)
483
+
#define RT5651_PDM_PATTERN_SEL_64 (0x0 << 5)
484
+
#define RT5651_PDM_PATTERN_SEL_128 (0x1 << 5)
485
+
#define RT5651_PDM_VOL_MASK (0x1 << 4)
486
+
#define RT5651_PDM_VOL_SFT 4
487
+
#define RT5651_PDM_DIV_MASK (0x3)
488
+
#define RT5651_PDM_DIV_SFT 0
489
+
#define RT5651_PDM_DIV_1 0
490
+
#define RT5651_PDM_DIV_2 1
491
+
#define RT5651_PDM_DIV_3 2
492
+
#define RT5651_PDM_DIV_4 3
493
+
494
+
/* PDM I2C/Data Control 1 (0x31) */
495
+
#define RT5651_PDM_I2C_ID_MASK (0xf << 12)
496
+
#define PT5631_PDM_CMD_EXE (0x1 << 11)
497
+
#define RT5651_PDM_I2C_CMD_MASK (0x1 << 10)
498
+
#define RT5651_PDM_I2C_CMD_R (0x0 << 10)
499
+
#define RT5651_PDM_I2C_CMD_W (0x1 << 10)
500
+
#define RT5651_PDM_I2C_CMD_EXE (0x1 << 9)
501
+
#define RT5651_PDM_I2C_NORMAL (0x0 << 8)
502
+
#define RT5651_PDM_I2C_BUSY (0x1 << 8)
503
+
504
+
/* PDM I2C/Data Control 2 (0x32) */
505
+
#define RT5651_PDM_I2C_ADDR (0xff << 8)
506
+
#define RT5651_PDM_I2C_CMD_PATTERN (0xff)
507
+
508
+
509
+
/* REC Left Mixer Control 1 (0x3b) */
510
+
#define RT5651_G_LN_L2_RM_L_MASK (0x7 << 13)
511
+
#define RT5651_G_IN_L2_RM_L_SFT 13
512
+
#define RT5651_G_LN_L1_RM_L_MASK (0x7 << 10)
513
+
#define RT5651_G_IN_L1_RM_L_SFT 10
514
+
#define RT5651_G_BST3_RM_L_MASK (0x7 << 4)
515
+
#define RT5651_G_BST3_RM_L_SFT 4
516
+
#define RT5651_G_BST2_RM_L_MASK (0x7 << 1)
517
+
#define RT5651_G_BST2_RM_L_SFT 1
518
+
519
+
/* REC Left Mixer Control 2 (0x3c) */
520
+
#define RT5651_G_BST1_RM_L_MASK (0x7 << 13)
521
+
#define RT5651_G_BST1_RM_L_SFT 13
522
+
#define RT5651_G_OM_L_RM_L_MASK (0x7 << 10)
523
+
#define RT5651_G_OM_L_RM_L_SFT 10
524
+
#define RT5651_M_IN2_L_RM_L (0x1 << 6)
525
+
#define RT5651_M_IN2_L_RM_L_SFT 6
526
+
#define RT5651_M_IN1_L_RM_L (0x1 << 5)
527
+
#define RT5651_M_IN1_L_RM_L_SFT 5
528
+
#define RT5651_M_BST3_RM_L (0x1 << 3)
529
+
#define RT5651_M_BST3_RM_L_SFT 3
530
+
#define RT5651_M_BST2_RM_L (0x1 << 2)
531
+
#define RT5651_M_BST2_RM_L_SFT 2
532
+
#define RT5651_M_BST1_RM_L (0x1 << 1)
533
+
#define RT5651_M_BST1_RM_L_SFT 1
534
+
#define RT5651_M_OM_L_RM_L (0x1)
535
+
#define RT5651_M_OM_L_RM_L_SFT 0
536
+
537
+
/* REC Right Mixer Control 1 (0x3d) */
538
+
#define RT5651_G_IN2_R_RM_R_MASK (0x7 << 13)
539
+
#define RT5651_G_IN2_R_RM_R_SFT 13
540
+
#define RT5651_G_IN1_R_RM_R_MASK (0x7 << 10)
541
+
#define RT5651_G_IN1_R_RM_R_SFT 10
542
+
#define RT5651_G_BST3_RM_R_MASK (0x7 << 4)
543
+
#define RT5651_G_BST3_RM_R_SFT 4
544
+
#define RT5651_G_BST2_RM_R_MASK (0x7 << 1)
545
+
#define RT5651_G_BST2_RM_R_SFT 1
546
+
547
+
/* REC Right Mixer Control 2 (0x3e) */
548
+
#define RT5651_G_BST1_RM_R_MASK (0x7 << 13)
549
+
#define RT5651_G_BST1_RM_R_SFT 13
550
+
#define RT5651_G_OM_R_RM_R_MASK (0x7 << 10)
551
+
#define RT5651_G_OM_R_RM_R_SFT 10
552
+
#define RT5651_M_IN2_R_RM_R (0x1 << 6)
553
+
#define RT5651_M_IN2_R_RM_R_SFT 6
554
+
#define RT5651_M_IN1_R_RM_R (0x1 << 5)
555
+
#define RT5651_M_IN1_R_RM_R_SFT 5
556
+
#define RT5651_M_BST3_RM_R (0x1 << 3)
557
+
#define RT5651_M_BST3_RM_R_SFT 3
558
+
#define RT5651_M_BST2_RM_R (0x1 << 2)
559
+
#define RT5651_M_BST2_RM_R_SFT 2
560
+
#define RT5651_M_BST1_RM_R (0x1 << 1)
561
+
#define RT5651_M_BST1_RM_R_SFT 1
562
+
#define RT5651_M_OM_R_RM_R (0x1)
563
+
#define RT5651_M_OM_R_RM_R_SFT 0
564
+
565
+
/* HPMIX Control (0x45) */
566
+
#define RT5651_M_DAC1_HM (0x1 << 14)
567
+
#define RT5651_M_DAC1_HM_SFT 14
568
+
#define RT5651_M_HPVOL_HM (0x1 << 13)
569
+
#define RT5651_M_HPVOL_HM_SFT 13
570
+
#define RT5651_G_HPOMIX_MASK (0x1 << 12)
571
+
#define RT5651_G_HPOMIX_SFT 12
572
+
573
+
/* SPK Left Mixer Control (0x46) */
574
+
#define RT5651_G_RM_L_SM_L_MASK (0x3 << 14)
575
+
#define RT5651_G_RM_L_SM_L_SFT 14
576
+
#define RT5651_G_IN_L_SM_L_MASK (0x3 << 12)
577
+
#define RT5651_G_IN_L_SM_L_SFT 12
578
+
#define RT5651_G_DAC_L1_SM_L_MASK (0x3 << 10)
579
+
#define RT5651_G_DAC_L1_SM_L_SFT 10
580
+
#define RT5651_G_DAC_L2_SM_L_MASK (0x3 << 8)
581
+
#define RT5651_G_DAC_L2_SM_L_SFT 8
582
+
#define RT5651_G_OM_L_SM_L_MASK (0x3 << 6)
583
+
#define RT5651_G_OM_L_SM_L_SFT 6
584
+
#define RT5651_M_RM_L_SM_L (0x1 << 5)
585
+
#define RT5651_M_RM_L_SM_L_SFT 5
586
+
#define RT5651_M_IN_L_SM_L (0x1 << 4)
587
+
#define RT5651_M_IN_L_SM_L_SFT 4
588
+
#define RT5651_M_DAC_L1_SM_L (0x1 << 3)
589
+
#define RT5651_M_DAC_L1_SM_L_SFT 3
590
+
#define RT5651_M_DAC_L2_SM_L (0x1 << 2)
591
+
#define RT5651_M_DAC_L2_SM_L_SFT 2
592
+
#define RT5651_M_OM_L_SM_L (0x1 << 1)
593
+
#define RT5651_M_OM_L_SM_L_SFT 1
594
+
595
+
/* SPK Right Mixer Control (0x47) */
596
+
#define RT5651_G_RM_R_SM_R_MASK (0x3 << 14)
597
+
#define RT5651_G_RM_R_SM_R_SFT 14
598
+
#define RT5651_G_IN_R_SM_R_MASK (0x3 << 12)
599
+
#define RT5651_G_IN_R_SM_R_SFT 12
600
+
#define RT5651_G_DAC_R1_SM_R_MASK (0x3 << 10)
601
+
#define RT5651_G_DAC_R1_SM_R_SFT 10
602
+
#define RT5651_G_DAC_R2_SM_R_MASK (0x3 << 8)
603
+
#define RT5651_G_DAC_R2_SM_R_SFT 8
604
+
#define RT5651_G_OM_R_SM_R_MASK (0x3 << 6)
605
+
#define RT5651_G_OM_R_SM_R_SFT 6
606
+
#define RT5651_M_RM_R_SM_R (0x1 << 5)
607
+
#define RT5651_M_RM_R_SM_R_SFT 5
608
+
#define RT5651_M_IN_R_SM_R (0x1 << 4)
609
+
#define RT5651_M_IN_R_SM_R_SFT 4
610
+
#define RT5651_M_DAC_R1_SM_R (0x1 << 3)
611
+
#define RT5651_M_DAC_R1_SM_R_SFT 3
612
+
#define RT5651_M_DAC_R2_SM_R (0x1 << 2)
613
+
#define RT5651_M_DAC_R2_SM_R_SFT 2
614
+
#define RT5651_M_OM_R_SM_R (0x1 << 1)
615
+
#define RT5651_M_OM_R_SM_R_SFT 1
616
+
617
+
/* SPOLMIX Control (0x48) */
618
+
#define RT5651_M_DAC_R1_SPM_L (0x1 << 15)
619
+
#define RT5651_M_DAC_R1_SPM_L_SFT 15
620
+
#define RT5651_M_DAC_L1_SPM_L (0x1 << 14)
621
+
#define RT5651_M_DAC_L1_SPM_L_SFT 14
622
+
#define RT5651_M_SV_R_SPM_L (0x1 << 13)
623
+
#define RT5651_M_SV_R_SPM_L_SFT 13
624
+
#define RT5651_M_SV_L_SPM_L (0x1 << 12)
625
+
#define RT5651_M_SV_L_SPM_L_SFT 12
626
+
#define RT5651_M_BST1_SPM_L (0x1 << 11)
627
+
#define RT5651_M_BST1_SPM_L_SFT 11
628
+
629
+
/* SPORMIX Control (0x49) */
630
+
#define RT5651_M_DAC_R1_SPM_R (0x1 << 13)
631
+
#define RT5651_M_DAC_R1_SPM_R_SFT 13
632
+
#define RT5651_M_SV_R_SPM_R (0x1 << 12)
633
+
#define RT5651_M_SV_R_SPM_R_SFT 12
634
+
#define RT5651_M_BST1_SPM_R (0x1 << 11)
635
+
#define RT5651_M_BST1_SPM_R_SFT 11
636
+
637
+
/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
638
+
#define RT5651_SPO_CLSD_RATIO_MASK (0x7)
639
+
#define RT5651_SPO_CLSD_RATIO_SFT 0
640
+
641
+
/* Mono Output Mixer Control (0x4c) */
642
+
#define RT5651_M_DAC_R2_MM (0x1 << 15)
643
+
#define RT5651_M_DAC_R2_MM_SFT 15
644
+
#define RT5651_M_DAC_L2_MM (0x1 << 14)
645
+
#define RT5651_M_DAC_L2_MM_SFT 14
646
+
#define RT5651_M_OV_R_MM (0x1 << 13)
647
+
#define RT5651_M_OV_R_MM_SFT 13
648
+
#define RT5651_M_OV_L_MM (0x1 << 12)
649
+
#define RT5651_M_OV_L_MM_SFT 12
650
+
#define RT5651_M_BST1_MM (0x1 << 11)
651
+
#define RT5651_M_BST1_MM_SFT 11
652
+
#define RT5651_G_MONOMIX_MASK (0x1 << 10)
653
+
#define RT5651_G_MONOMIX_SFT 10
654
+
655
+
/* Output Left Mixer Control 1 (0x4d) */
656
+
#define RT5651_G_BST2_OM_L_MASK (0x7 << 10)
657
+
#define RT5651_G_BST2_OM_L_SFT 10
658
+
#define RT5651_G_BST1_OM_L_MASK (0x7 << 7)
659
+
#define RT5651_G_BST1_OM_L_SFT 7
660
+
#define RT5651_G_IN1_L_OM_L_MASK (0x7 << 4)
661
+
#define RT5651_G_IN1_L_OM_L_SFT 4
662
+
#define RT5651_G_RM_L_OM_L_MASK (0x7 << 1)
663
+
#define RT5651_G_RM_L_OM_L_SFT 1
664
+
665
+
/* Output Left Mixer Control 2 (0x4e) */
666
+
#define RT5651_G_DAC_L1_OM_L_MASK (0x7 << 7)
667
+
#define RT5651_G_DAC_L1_OM_L_SFT 7
668
+
#define RT5651_G_IN2_L_OM_L_MASK (0x7 << 4)
669
+
#define RT5651_G_IN2_L_OM_L_SFT 4
670
+
671
+
/* Output Left Mixer Control 3 (0x4f) */
672
+
#define RT5651_M_IN2_L_OM_L (0x1 << 9)
673
+
#define RT5651_M_IN2_L_OM_L_SFT 9
674
+
#define RT5651_M_BST2_OM_L (0x1 << 6)
675
+
#define RT5651_M_BST2_OM_L_SFT 6
676
+
#define RT5651_M_BST1_OM_L (0x1 << 5)
677
+
#define RT5651_M_BST1_OM_L_SFT 5
678
+
#define RT5651_M_IN1_L_OM_L (0x1 << 4)
679
+
#define RT5651_M_IN1_L_OM_L_SFT 4
680
+
#define RT5651_M_RM_L_OM_L (0x1 << 3)
681
+
#define RT5651_M_RM_L_OM_L_SFT 3
682
+
#define RT5651_M_DAC_L1_OM_L (0x1)
683
+
#define RT5651_M_DAC_L1_OM_L_SFT 0
684
+
685
+
/* Output Right Mixer Control 1 (0x50) */
686
+
#define RT5651_G_BST2_OM_R_MASK (0x7 << 10)
687
+
#define RT5651_G_BST2_OM_R_SFT 10
688
+
#define RT5651_G_BST1_OM_R_MASK (0x7 << 7)
689
+
#define RT5651_G_BST1_OM_R_SFT 7
690
+
#define RT5651_G_IN1_R_OM_R_MASK (0x7 << 4)
691
+
#define RT5651_G_IN1_R_OM_R_SFT 4
692
+
#define RT5651_G_RM_R_OM_R_MASK (0x7 << 1)
693
+
#define RT5651_G_RM_R_OM_R_SFT 1
694
+
695
+
/* Output Right Mixer Control 2 (0x51) */
696
+
#define RT5651_G_DAC_R1_OM_R_MASK (0x7 << 7)
697
+
#define RT5651_G_DAC_R1_OM_R_SFT 7
698
+
#define RT5651_G_IN2_R_OM_R_MASK (0x7 << 4)
699
+
#define RT5651_G_IN2_R_OM_R_SFT 4
700
+
701
+
/* Output Right Mixer Control 3 (0x52) */
702
+
#define RT5651_M_IN2_R_OM_R (0x1 << 9)
703
+
#define RT5651_M_IN2_R_OM_R_SFT 9
704
+
#define RT5651_M_BST2_OM_R (0x1 << 6)
705
+
#define RT5651_M_BST2_OM_R_SFT 6
706
+
#define RT5651_M_BST1_OM_R (0x1 << 5)
707
+
#define RT5651_M_BST1_OM_R_SFT 5
708
+
#define RT5651_M_IN1_R_OM_R (0x1 << 4)
709
+
#define RT5651_M_IN1_R_OM_R_SFT 4
710
+
#define RT5651_M_RM_R_OM_R (0x1 << 3)
711
+
#define RT5651_M_RM_R_OM_R_SFT 3
712
+
#define RT5651_M_DAC_R1_OM_R (0x1)
713
+
#define RT5651_M_DAC_R1_OM_R_SFT 0
714
+
715
+
/* LOUT Mixer Control (0x53) */
716
+
#define RT5651_M_DAC_L1_LM (0x1 << 15)
717
+
#define RT5651_M_DAC_L1_LM_SFT 15
718
+
#define RT5651_M_DAC_R1_LM (0x1 << 14)
719
+
#define RT5651_M_DAC_R1_LM_SFT 14
720
+
#define RT5651_M_OV_L_LM (0x1 << 13)
721
+
#define RT5651_M_OV_L_LM_SFT 13
722
+
#define RT5651_M_OV_R_LM (0x1 << 12)
723
+
#define RT5651_M_OV_R_LM_SFT 12
724
+
#define RT5651_G_LOUTMIX_MASK (0x1 << 11)
725
+
#define RT5651_G_LOUTMIX_SFT 11
726
+
727
+
/* Power Management for Digital 1 (0x61) */
728
+
#define RT5651_PWR_I2S1 (0x1 << 15)
729
+
#define RT5651_PWR_I2S1_BIT 15
730
+
#define RT5651_PWR_I2S2 (0x1 << 14)
731
+
#define RT5651_PWR_I2S2_BIT 14
732
+
#define RT5651_PWR_DAC_L1 (0x1 << 12)
733
+
#define RT5651_PWR_DAC_L1_BIT 12
734
+
#define RT5651_PWR_DAC_R1 (0x1 << 11)
735
+
#define RT5651_PWR_DAC_R1_BIT 11
736
+
#define RT5651_PWR_ADC_L (0x1 << 2)
737
+
#define RT5651_PWR_ADC_L_BIT 2
738
+
#define RT5651_PWR_ADC_R (0x1 << 1)
739
+
#define RT5651_PWR_ADC_R_BIT 1
740
+
741
+
/* Power Management for Digital 2 (0x62) */
742
+
#define RT5651_PWR_ADC_STO1_F (0x1 << 15)
743
+
#define RT5651_PWR_ADC_STO1_F_BIT 15
744
+
#define RT5651_PWR_ADC_STO2_F (0x1 << 14)
745
+
#define RT5651_PWR_ADC_STO2_F_BIT 14
746
+
#define RT5651_PWR_DAC_STO1_F (0x1 << 11)
747
+
#define RT5651_PWR_DAC_STO1_F_BIT 11
748
+
#define RT5651_PWR_DAC_STO2_F (0x1 << 10)
749
+
#define RT5651_PWR_DAC_STO2_F_BIT 10
750
+
#define RT5651_PWR_PDM (0x1 << 9)
751
+
#define RT5651_PWR_PDM_BIT 9
752
+
753
+
/* Power Management for Analog 1 (0x63) */
754
+
#define RT5651_PWR_VREF1 (0x1 << 15)
755
+
#define RT5651_PWR_VREF1_BIT 15
756
+
#define RT5651_PWR_FV1 (0x1 << 14)
757
+
#define RT5651_PWR_FV1_BIT 14
758
+
#define RT5651_PWR_MB (0x1 << 13)
759
+
#define RT5651_PWR_MB_BIT 13
760
+
#define RT5651_PWR_LM (0x1 << 12)
761
+
#define RT5651_PWR_LM_BIT 12
762
+
#define RT5651_PWR_BG (0x1 << 11)
763
+
#define RT5651_PWR_BG_BIT 11
764
+
#define RT5651_PWR_HP_L (0x1 << 7)
765
+
#define RT5651_PWR_HP_L_BIT 7
766
+
#define RT5651_PWR_HP_R (0x1 << 6)
767
+
#define RT5651_PWR_HP_R_BIT 6
768
+
#define RT5651_PWR_HA (0x1 << 5)
769
+
#define RT5651_PWR_HA_BIT 5
770
+
#define RT5651_PWR_VREF2 (0x1 << 4)
771
+
#define RT5651_PWR_VREF2_BIT 4
772
+
#define RT5651_PWR_FV2 (0x1 << 3)
773
+
#define RT5651_PWR_FV2_BIT 3
774
+
#define RT5651_PWR_LDO (0x1 << 2)
775
+
#define RT5651_PWR_LDO_BIT 2
776
+
#define RT5651_PWR_LDO_DVO_MASK (0x3)
777
+
#define RT5651_PWR_LDO_DVO_1_0V 0
778
+
#define RT5651_PWR_LDO_DVO_1_1V 1
779
+
#define RT5651_PWR_LDO_DVO_1_2V 2
780
+
#define RT5651_PWR_LDO_DVO_1_3V 3
781
+
782
+
/* Power Management for Analog 2 (0x64) */
783
+
#define RT5651_PWR_BST1 (0x1 << 15)
784
+
#define RT5651_PWR_BST1_BIT 15
785
+
#define RT5651_PWR_BST2 (0x1 << 14)
786
+
#define RT5651_PWR_BST2_BIT 14
787
+
#define RT5651_PWR_BST3 (0x1 << 13)
788
+
#define RT5651_PWR_BST3_BIT 13
789
+
#define RT5651_PWR_MB1 (0x1 << 11)
790
+
#define RT5651_PWR_MB1_BIT 11
791
+
#define RT5651_PWR_PLL (0x1 << 9)
792
+
#define RT5651_PWR_PLL_BIT 9
793
+
#define RT5651_PWR_BST1_OP2 (0x1 << 5)
794
+
#define RT5651_PWR_BST1_OP2_BIT 5
795
+
#define RT5651_PWR_BST2_OP2 (0x1 << 4)
796
+
#define RT5651_PWR_BST2_OP2_BIT 4
797
+
#define RT5651_PWR_BST3_OP2 (0x1 << 3)
798
+
#define RT5651_PWR_BST3_OP2_BIT 3
799
+
#define RT5651_PWR_JD_M (0x1 << 2)
800
+
#define RT5651_PWM_JD_M_BIT 2
801
+
#define RT5651_PWR_JD2 (0x1 << 1)
802
+
#define RT5651_PWM_JD2_BIT 1
803
+
#define RT5651_PWR_JD3 (0x1)
804
+
#define RT5651_PWM_JD3_BIT 0
805
+
806
+
/* Power Management for Mixer (0x65) */
807
+
#define RT5651_PWR_OM_L (0x1 << 15)
808
+
#define RT5651_PWR_OM_L_BIT 15
809
+
#define RT5651_PWR_OM_R (0x1 << 14)
810
+
#define RT5651_PWR_OM_R_BIT 14
811
+
#define RT5651_PWR_RM_L (0x1 << 11)
812
+
#define RT5651_PWR_RM_L_BIT 11
813
+
#define RT5651_PWR_RM_R (0x1 << 10)
814
+
#define RT5651_PWR_RM_R_BIT 10
815
+
816
+
/* Power Management for Volume (0x66) */
817
+
#define RT5651_PWR_OV_L (0x1 << 13)
818
+
#define RT5651_PWR_OV_L_BIT 13
819
+
#define RT5651_PWR_OV_R (0x1 << 12)
820
+
#define RT5651_PWR_OV_R_BIT 12
821
+
#define RT5651_PWR_HV_L (0x1 << 11)
822
+
#define RT5651_PWR_HV_L_BIT 11
823
+
#define RT5651_PWR_HV_R (0x1 << 10)
824
+
#define RT5651_PWR_HV_R_BIT 10
825
+
#define RT5651_PWR_IN1_L (0x1 << 9)
826
+
#define RT5651_PWR_IN1_L_BIT 9
827
+
#define RT5651_PWR_IN1_R (0x1 << 8)
828
+
#define RT5651_PWR_IN1_R_BIT 8
829
+
#define RT5651_PWR_IN2_L (0x1 << 7)
830
+
#define RT5651_PWR_IN2_L_BIT 7
831
+
#define RT5651_PWR_IN2_R (0x1 << 6)
832
+
#define RT5651_PWR_IN2_R_BIT 6
833
+
834
+
/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71) */
835
+
#define RT5651_I2S_MS_MASK (0x1 << 15)
836
+
#define RT5651_I2S_MS_SFT 15
837
+
#define RT5651_I2S_MS_M (0x0 << 15)
838
+
#define RT5651_I2S_MS_S (0x1 << 15)
839
+
#define RT5651_I2S_O_CP_MASK (0x3 << 10)
840
+
#define RT5651_I2S_O_CP_SFT 10
841
+
#define RT5651_I2S_O_CP_OFF (0x0 << 10)
842
+
#define RT5651_I2S_O_CP_U_LAW (0x1 << 10)
843
+
#define RT5651_I2S_O_CP_A_LAW (0x2 << 10)
844
+
#define RT5651_I2S_I_CP_MASK (0x3 << 8)
845
+
#define RT5651_I2S_I_CP_SFT 8
846
+
#define RT5651_I2S_I_CP_OFF (0x0 << 8)
847
+
#define RT5651_I2S_I_CP_U_LAW (0x1 << 8)
848
+
#define RT5651_I2S_I_CP_A_LAW (0x2 << 8)
849
+
#define RT5651_I2S_BP_MASK (0x1 << 7)
850
+
#define RT5651_I2S_BP_SFT 7
851
+
#define RT5651_I2S_BP_NOR (0x0 << 7)
852
+
#define RT5651_I2S_BP_INV (0x1 << 7)
853
+
#define RT5651_I2S_DL_MASK (0x3 << 2)
854
+
#define RT5651_I2S_DL_SFT 2
855
+
#define RT5651_I2S_DL_16 (0x0 << 2)
856
+
#define RT5651_I2S_DL_20 (0x1 << 2)
857
+
#define RT5651_I2S_DL_24 (0x2 << 2)
858
+
#define RT5651_I2S_DL_8 (0x3 << 2)
859
+
#define RT5651_I2S_DF_MASK (0x3)
860
+
#define RT5651_I2S_DF_SFT 0
861
+
#define RT5651_I2S_DF_I2S (0x0)
862
+
#define RT5651_I2S_DF_LEFT (0x1)
863
+
#define RT5651_I2S_DF_PCM_A (0x2)
864
+
#define RT5651_I2S_DF_PCM_B (0x3)
865
+
866
+
/* ADC/DAC Clock Control 1 (0x73) */
867
+
#define RT5651_I2S_PD1_MASK (0x7 << 12)
868
+
#define RT5651_I2S_PD1_SFT 12
869
+
#define RT5651_I2S_PD1_1 (0x0 << 12)
870
+
#define RT5651_I2S_PD1_2 (0x1 << 12)
871
+
#define RT5651_I2S_PD1_3 (0x2 << 12)
872
+
#define RT5651_I2S_PD1_4 (0x3 << 12)
873
+
#define RT5651_I2S_PD1_6 (0x4 << 12)
874
+
#define RT5651_I2S_PD1_8 (0x5 << 12)
875
+
#define RT5651_I2S_PD1_12 (0x6 << 12)
876
+
#define RT5651_I2S_PD1_16 (0x7 << 12)
877
+
#define RT5651_I2S_BCLK_MS2_MASK (0x1 << 11)
878
+
#define RT5651_I2S_BCLK_MS2_SFT 11
879
+
#define RT5651_I2S_BCLK_MS2_32 (0x0 << 11)
880
+
#define RT5651_I2S_BCLK_MS2_64 (0x1 << 11)
881
+
#define RT5651_I2S_PD2_MASK (0x7 << 8)
882
+
#define RT5651_I2S_PD2_SFT 8
883
+
#define RT5651_I2S_PD2_1 (0x0 << 8)
884
+
#define RT5651_I2S_PD2_2 (0x1 << 8)
885
+
#define RT5651_I2S_PD2_3 (0x2 << 8)
886
+
#define RT5651_I2S_PD2_4 (0x3 << 8)
887
+
#define RT5651_I2S_PD2_6 (0x4 << 8)
888
+
#define RT5651_I2S_PD2_8 (0x5 << 8)
889
+
#define RT5651_I2S_PD2_12 (0x6 << 8)
890
+
#define RT5651_I2S_PD2_16 (0x7 << 8)
891
+
#define RT5651_DAC_OSR_MASK (0x3 << 2)
892
+
#define RT5651_DAC_OSR_SFT 2
893
+
#define RT5651_DAC_OSR_128 (0x0 << 2)
894
+
#define RT5651_DAC_OSR_64 (0x1 << 2)
895
+
#define RT5651_DAC_OSR_32 (0x2 << 2)
896
+
#define RT5651_DAC_OSR_128_3 (0x3 << 2)
897
+
#define RT5651_ADC_OSR_MASK (0x3)
898
+
#define RT5651_ADC_OSR_SFT 0
899
+
#define RT5651_ADC_OSR_128 (0x0)
900
+
#define RT5651_ADC_OSR_64 (0x1)
901
+
#define RT5651_ADC_OSR_32 (0x2)
902
+
#define RT5651_ADC_OSR_128_3 (0x3)
903
+
904
+
/* ADC/DAC Clock Control 2 (0x74) */
905
+
#define RT5651_DAHPF_EN (0x1 << 11)
906
+
#define RT5651_DAHPF_EN_SFT 11
907
+
#define RT5651_ADHPF_EN (0x1 << 10)
908
+
#define RT5651_ADHPF_EN_SFT 10
909
+
910
+
/* Digital Microphone Control (0x75) */
911
+
#define RT5651_DMIC_1_EN_MASK (0x1 << 15)
912
+
#define RT5651_DMIC_1_EN_SFT 15
913
+
#define RT5651_DMIC_1_DIS (0x0 << 15)
914
+
#define RT5651_DMIC_1_EN (0x1 << 15)
915
+
#define RT5651_DMIC_1L_LH_MASK (0x1 << 13)
916
+
#define RT5651_DMIC_1L_LH_SFT 13
917
+
#define RT5651_DMIC_1L_LH_FALLING (0x0 << 13)
918
+
#define RT5651_DMIC_1L_LH_RISING (0x1 << 13)
919
+
#define RT5651_DMIC_1R_LH_MASK (0x1 << 12)
920
+
#define RT5651_DMIC_1R_LH_SFT 12
921
+
#define RT5651_DMIC_1R_LH_FALLING (0x0 << 12)
922
+
#define RT5651_DMIC_1R_LH_RISING (0x1 << 12)
923
+
#define RT5651_DMIC_1_DP_MASK (0x3 << 10)
924
+
#define RT5651_DMIC_1_DP_SFT 10
925
+
#define RT5651_DMIC_1_DP_GPIO6 (0x0 << 10)
926
+
#define RT5651_DMIC_1_DP_IN1P (0x1 << 10)
927
+
#define RT5651_DMIC_2_DP_GPIO8 (0x2 << 10)
928
+
#define RT5651_DMIC_CLK_MASK (0x7 << 5)
929
+
#define RT5651_DMIC_CLK_SFT 5
930
+
931
+
/* TDM Control 1 (0x77) */
932
+
#define RT5651_TDM_INTEL_SEL_MASK (0x1 << 15)
933
+
#define RT5651_TDM_INTEL_SEL_SFT 15
934
+
#define RT5651_TDM_INTEL_SEL_64 (0x0 << 15)
935
+
#define RT5651_TDM_INTEL_SEL_50 (0x1 << 15)
936
+
#define RT5651_TDM_MODE_SEL_MASK (0x1 << 14)
937
+
#define RT5651_TDM_MODE_SEL_SFT 14
938
+
#define RT5651_TDM_MODE_SEL_NOR (0x0 << 14)
939
+
#define RT5651_TDM_MODE_SEL_TDM (0x1 << 14)
940
+
#define RT5651_TDM_CH_NUM_SEL_MASK (0x3 << 12)
941
+
#define RT5651_TDM_CH_NUM_SEL_SFT 12
942
+
#define RT5651_TDM_CH_NUM_SEL_2 (0x0 << 12)
943
+
#define RT5651_TDM_CH_NUM_SEL_4 (0x1 << 12)
944
+
#define RT5651_TDM_CH_NUM_SEL_6 (0x2 << 12)
945
+
#define RT5651_TDM_CH_NUM_SEL_8 (0x3 << 12)
946
+
#define RT5651_TDM_CH_LEN_SEL_MASK (0x3 << 10)
947
+
#define RT5651_TDM_CH_LEN_SEL_SFT 10
948
+
#define RT5651_TDM_CH_LEN_SEL_16 (0x0 << 10)
949
+
#define RT5651_TDM_CH_LEN_SEL_20 (0x1 << 10)
950
+
#define RT5651_TDM_CH_LEN_SEL_24 (0x2 << 10)
951
+
#define RT5651_TDM_CH_LEN_SEL_32 (0x3 << 10)
952
+
#define RT5651_TDM_ADC_SEL_MASK (0x1 << 9)
953
+
#define RT5651_TDM_ADC_SEL_SFT 9
954
+
#define RT5651_TDM_ADC_SEL_NOR (0x0 << 9)
955
+
#define RT5651_TDM_ADC_SEL_SWAP (0x1 << 9)
956
+
#define RT5651_TDM_ADC_START_SEL_MASK (0x1 << 8)
957
+
#define RT5651_TDM_ADC_START_SEL_SFT 8
958
+
#define RT5651_TDM_ADC_START_SEL_SL0 (0x0 << 8)
959
+
#define RT5651_TDM_ADC_START_SEL_SL4 (0x1 << 8)
960
+
#define RT5651_TDM_I2S_CH2_SEL_MASK (0x3 << 6)
961
+
#define RT5651_TDM_I2S_CH2_SEL_SFT 6
962
+
#define RT5651_TDM_I2S_CH2_SEL_LR (0x0 << 6)
963
+
#define RT5651_TDM_I2S_CH2_SEL_RL (0x1 << 6)
964
+
#define RT5651_TDM_I2S_CH2_SEL_LL (0x2 << 6)
965
+
#define RT5651_TDM_I2S_CH2_SEL_RR (0x3 << 6)
966
+
#define RT5651_TDM_I2S_CH4_SEL_MASK (0x3 << 4)
967
+
#define RT5651_TDM_I2S_CH4_SEL_SFT 4
968
+
#define RT5651_TDM_I2S_CH4_SEL_LR (0x0 << 4)
969
+
#define RT5651_TDM_I2S_CH4_SEL_RL (0x1 << 4)
970
+
#define RT5651_TDM_I2S_CH4_SEL_LL (0x2 << 4)
971
+
#define RT5651_TDM_I2S_CH4_SEL_RR (0x3 << 4)
972
+
#define RT5651_TDM_I2S_CH6_SEL_MASK (0x3 << 2)
973
+
#define RT5651_TDM_I2S_CH6_SEL_SFT 2
974
+
#define RT5651_TDM_I2S_CH6_SEL_LR (0x0 << 2)
975
+
#define RT5651_TDM_I2S_CH6_SEL_RL (0x1 << 2)
976
+
#define RT5651_TDM_I2S_CH6_SEL_LL (0x2 << 2)
977
+
#define RT5651_TDM_I2S_CH6_SEL_RR (0x3 << 2)
978
+
#define RT5651_TDM_I2S_CH8_SEL_MASK (0x3)
979
+
#define RT5651_TDM_I2S_CH8_SEL_SFT 0
980
+
#define RT5651_TDM_I2S_CH8_SEL_LR (0x0)
981
+
#define RT5651_TDM_I2S_CH8_SEL_RL (0x1)
982
+
#define RT5651_TDM_I2S_CH8_SEL_LL (0x2)
983
+
#define RT5651_TDM_I2S_CH8_SEL_RR (0x3)
984
+
985
+
/* TDM Control 2 (0x78) */
986
+
#define RT5651_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
987
+
#define RT5651_TDM_LRCK_POL_SEL_SFT 15
988
+
#define RT5651_TDM_LRCK_POL_SEL_NOR (0x0 << 15)
989
+
#define RT5651_TDM_LRCK_POL_SEL_INV (0x1 << 15)
990
+
#define RT5651_TDM_CH_VAL_SEL_MASK (0x1 << 14)
991
+
#define RT5651_TDM_CH_VAL_SEL_SFT 14
992
+
#define RT5651_TDM_CH_VAL_SEL_CH01 (0x0 << 14)
993
+
#define RT5651_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
994
+
#define RT5651_TDM_CH_VAL_EN (0x1 << 13)
995
+
#define RT5651_TDM_CH_VAL_SFT 13
996
+
#define RT5651_TDM_LPBK_EN (0x1 << 12)
997
+
#define RT5651_TDM_LPBK_SFT 12
998
+
#define RT5651_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
999
+
#define RT5651_TDM_LRCK_PULSE_SEL_SFT 11
1000
+
#define RT5651_TDM_LRCK_PULSE_SEL_BCLK (0x0 << 11)
1001
+
#define RT5651_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
1002
+
#define RT5651_TDM_END_EDGE_SEL_MASK (0x1 << 10)
1003
+
#define RT5651_TDM_END_EDGE_SEL_SFT 10
1004
+
#define RT5651_TDM_END_EDGE_SEL_POS (0x0 << 10)
1005
+
#define RT5651_TDM_END_EDGE_SEL_NEG (0x1 << 10)
1006
+
#define RT5651_TDM_END_EDGE_EN (0x1 << 9)
1007
+
#define RT5651_TDM_END_EDGE_EN_SFT 9
1008
+
#define RT5651_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
1009
+
#define RT5651_TDM_TRAN_EDGE_SEL_SFT 8
1010
+
#define RT5651_TDM_TRAN_EDGE_SEL_POS (0x0 << 8)
1011
+
#define RT5651_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
1012
+
#define RT5651_M_TDM2_L (0x1 << 7)
1013
+
#define RT5651_M_TDM2_L_SFT 7
1014
+
#define RT5651_M_TDM2_R (0x1 << 6)
1015
+
#define RT5651_M_TDM2_R_SFT 6
1016
+
#define RT5651_M_TDM4_L (0x1 << 5)
1017
+
#define RT5651_M_TDM4_L_SFT 5
1018
+
#define RT5651_M_TDM4_R (0x1 << 4)
1019
+
#define RT5651_M_TDM4_R_SFT 4
1020
+
1021
+
/* TDM Control 3 (0x79) */
1022
+
#define RT5651_CH2_L_SEL_MASK (0x7 << 12)
1023
+
#define RT5651_CH2_L_SEL_SFT 12
1024
+
#define RT5651_CH2_L_SEL_SL0 (0x0 << 12)
1025
+
#define RT5651_CH2_L_SEL_SL1 (0x1 << 12)
1026
+
#define RT5651_CH2_L_SEL_SL2 (0x2 << 12)
1027
+
#define RT5651_CH2_L_SEL_SL3 (0x3 << 12)
1028
+
#define RT5651_CH2_L_SEL_SL4 (0x4 << 12)
1029
+
#define RT5651_CH2_L_SEL_SL5 (0x5 << 12)
1030
+
#define RT5651_CH2_L_SEL_SL6 (0x6 << 12)
1031
+
#define RT5651_CH2_L_SEL_SL7 (0x7 << 12)
1032
+
#define RT5651_CH2_R_SEL_MASK (0x7 << 8)
1033
+
#define RT5651_CH2_R_SEL_SFT 8
1034
+
#define RT5651_CH2_R_SEL_SL0 (0x0 << 8)
1035
+
#define RT5651_CH2_R_SEL_SL1 (0x1 << 8)
1036
+
#define RT5651_CH2_R_SEL_SL2 (0x2 << 8)
1037
+
#define RT5651_CH2_R_SEL_SL3 (0x3 << 8)
1038
+
#define RT5651_CH2_R_SEL_SL4 (0x4 << 8)
1039
+
#define RT5651_CH2_R_SEL_SL5 (0x5 << 8)
1040
+
#define RT5651_CH2_R_SEL_SL6 (0x6 << 8)
1041
+
#define RT5651_CH2_R_SEL_SL7 (0x7 << 8)
1042
+
#define RT5651_CH4_L_SEL_MASK (0x7 << 4)
1043
+
#define RT5651_CH4_L_SEL_SFT 4
1044
+
#define RT5651_CH4_L_SEL_SL0 (0x0 << 4)
1045
+
#define RT5651_CH4_L_SEL_SL1 (0x1 << 4)
1046
+
#define RT5651_CH4_L_SEL_SL2 (0x2 << 4)
1047
+
#define RT5651_CH4_L_SEL_SL3 (0x3 << 4)
1048
+
#define RT5651_CH4_L_SEL_SL4 (0x4 << 4)
1049
+
#define RT5651_CH4_L_SEL_SL5 (0x5 << 4)
1050
+
#define RT5651_CH4_L_SEL_SL6 (0x6 << 4)
1051
+
#define RT5651_CH4_L_SEL_SL7 (0x7 << 4)
1052
+
#define RT5651_CH4_R_SEL_MASK (0x7)
1053
+
#define RT5651_CH4_R_SEL_SFT 0
1054
+
#define RT5651_CH4_R_SEL_SL0 (0x0)
1055
+
#define RT5651_CH4_R_SEL_SL1 (0x1)
1056
+
#define RT5651_CH4_R_SEL_SL2 (0x2)
1057
+
#define RT5651_CH4_R_SEL_SL3 (0x3)
1058
+
#define RT5651_CH4_R_SEL_SL4 (0x4)
1059
+
#define RT5651_CH4_R_SEL_SL5 (0x5)
1060
+
#define RT5651_CH4_R_SEL_SL6 (0x6)
1061
+
#define RT5651_CH4_R_SEL_SL7 (0x7)
1062
+
1063
+
/* Global Clock Control (0x80) */
1064
+
#define RT5651_SCLK_SRC_MASK (0x3 << 14)
1065
+
#define RT5651_SCLK_SRC_SFT 14
1066
+
#define RT5651_SCLK_SRC_MCLK (0x0 << 14)
1067
+
#define RT5651_SCLK_SRC_PLL1 (0x1 << 14)
1068
+
#define RT5651_SCLK_SRC_RCCLK (0x2 << 14)
1069
+
#define RT5651_PLL1_SRC_MASK (0x3 << 12)
1070
+
#define RT5651_PLL1_SRC_SFT 12
1071
+
#define RT5651_PLL1_SRC_MCLK (0x0 << 12)
1072
+
#define RT5651_PLL1_SRC_BCLK1 (0x1 << 12)
1073
+
#define RT5651_PLL1_SRC_BCLK2 (0x2 << 12)
1074
+
#define RT5651_PLL1_PD_MASK (0x1 << 3)
1075
+
#define RT5651_PLL1_PD_SFT 3
1076
+
#define RT5651_PLL1_PD_1 (0x0 << 3)
1077
+
#define RT5651_PLL1_PD_2 (0x1 << 3)
1078
+
1079
+
#define RT5651_PLL_INP_MAX 40000000
1080
+
#define RT5651_PLL_INP_MIN 256000
1081
+
/* PLL M/N/K Code Control 1 (0x81) */
1082
+
#define RT5651_PLL_N_MAX 0x1ff
1083
+
#define RT5651_PLL_N_MASK (RT5651_PLL_N_MAX << 7)
1084
+
#define RT5651_PLL_N_SFT 7
1085
+
#define RT5651_PLL_K_MAX 0x1f
1086
+
#define RT5651_PLL_K_MASK (RT5651_PLL_K_MAX)
1087
+
#define RT5651_PLL_K_SFT 0
1088
+
1089
+
/* PLL M/N/K Code Control 2 (0x82) */
1090
+
#define RT5651_PLL_M_MAX 0xf
1091
+
#define RT5651_PLL_M_MASK (RT5651_PLL_M_MAX << 12)
1092
+
#define RT5651_PLL_M_SFT 12
1093
+
#define RT5651_PLL_M_BP (0x1 << 11)
1094
+
#define RT5651_PLL_M_BP_SFT 11
1095
+
1096
+
/* PLL tracking mode 1 (0x83) */
1097
+
#define RT5651_STO1_T_MASK (0x1 << 15)
1098
+
#define RT5651_STO1_T_SFT 15
1099
+
#define RT5651_STO1_T_SCLK (0x0 << 15)
1100
+
#define RT5651_STO1_T_LRCK1 (0x1 << 15)
1101
+
#define RT5651_STO2_T_MASK (0x1 << 12)
1102
+
#define RT5651_STO2_T_SFT 12
1103
+
#define RT5651_STO2_T_I2S2 (0x0 << 12)
1104
+
#define RT5651_STO2_T_LRCK2 (0x1 << 12)
1105
+
#define RT5651_ASRC2_REF_MASK (0x1 << 11)
1106
+
#define RT5651_ASRC2_REF_SFT 11
1107
+
#define RT5651_ASRC2_REF_LRCK2 (0x0 << 11)
1108
+
#define RT5651_ASRC2_REF_LRCK1 (0x1 << 11)
1109
+
#define RT5651_DMIC_1_M_MASK (0x1 << 9)
1110
+
#define RT5651_DMIC_1_M_SFT 9
1111
+
#define RT5651_DMIC_1_M_NOR (0x0 << 9)
1112
+
#define RT5651_DMIC_1_M_ASYN (0x1 << 9)
1113
+
1114
+
/* PLL tracking mode 2 (0x84) */
1115
+
#define RT5651_STO1_ASRC_EN (0x1 << 15)
1116
+
#define RT5651_STO1_ASRC_EN_SFT 15
1117
+
#define RT5651_STO2_ASRC_EN (0x1 << 14)
1118
+
#define RT5651_STO2_ASRC_EN_SFT 14
1119
+
#define RT5651_STO1_DAC_M_MASK (0x1 << 13)
1120
+
#define RT5651_STO1_DAC_M_SFT 13
1121
+
#define RT5651_STO1_DAC_M_NOR (0x0 << 13)
1122
+
#define RT5651_STO1_DAC_M_ASRC (0x1 << 13)
1123
+
#define RT5651_STO2_DAC_M_MASK (0x1 << 12)
1124
+
#define RT5651_STO2_DAC_M_SFT 12
1125
+
#define RT5651_STO2_DAC_M_NOR (0x0 << 12)
1126
+
#define RT5651_STO2_DAC_M_ASRC (0x1 << 12)
1127
+
#define RT5651_ADC_M_MASK (0x1 << 11)
1128
+
#define RT5651_ADC_M_SFT 11
1129
+
#define RT5651_ADC_M_NOR (0x0 << 11)
1130
+
#define RT5651_ADC_M_ASRC (0x1 << 11)
1131
+
#define RT5651_I2S1_R_D_MASK (0x1 << 4)
1132
+
#define RT5651_I2S1_R_D_SFT 4
1133
+
#define RT5651_I2S1_R_D_DIS (0x0 << 4)
1134
+
#define RT5651_I2S1_R_D_EN (0x1 << 4)
1135
+
#define RT5651_I2S2_R_D_MASK (0x1 << 3)
1136
+
#define RT5651_I2S2_R_D_SFT 3
1137
+
#define RT5651_I2S2_R_D_DIS (0x0 << 3)
1138
+
#define RT5651_I2S2_R_D_EN (0x1 << 3)
1139
+
#define RT5651_PRE_SCLK_MASK (0x3)
1140
+
#define RT5651_PRE_SCLK_SFT 0
1141
+
#define RT5651_PRE_SCLK_512 (0x0)
1142
+
#define RT5651_PRE_SCLK_1024 (0x1)
1143
+
#define RT5651_PRE_SCLK_2048 (0x2)
1144
+
1145
+
/* PLL tracking mode 3 (0x85) */
1146
+
#define RT5651_I2S1_RATE_MASK (0xf << 12)
1147
+
#define RT5651_I2S1_RATE_SFT 12
1148
+
#define RT5651_I2S2_RATE_MASK (0xf << 8)
1149
+
#define RT5651_I2S2_RATE_SFT 8
1150
+
#define RT5651_G_ASRC_LP_MASK (0x1 << 3)
1151
+
#define RT5651_G_ASRC_LP_SFT 3
1152
+
#define RT5651_ASRC_LP_F_M (0x1 << 2)
1153
+
#define RT5651_ASRC_LP_F_SFT 2
1154
+
#define RT5651_ASRC_LP_F_NOR (0x0 << 2)
1155
+
#define RT5651_ASRC_LP_F_SB (0x1 << 2)
1156
+
#define RT5651_FTK_PH_DET_MASK (0x3)
1157
+
#define RT5651_FTK_PH_DET_SFT 0
1158
+
#define RT5651_FTK_PH_DET_DIV1 (0x0)
1159
+
#define RT5651_FTK_PH_DET_DIV2 (0x1)
1160
+
#define RT5651_FTK_PH_DET_DIV4 (0x2)
1161
+
#define RT5651_FTK_PH_DET_DIV8 (0x3)
1162
+
1163
+
/*PLL tracking mode 6 (0x89) */
1164
+
#define RT5651_I2S1_PD_MASK (0x7 << 12)
1165
+
#define RT5651_I2S1_PD_SFT 12
1166
+
#define RT5651_I2S2_PD_MASK (0x7 << 8)
1167
+
#define RT5651_I2S2_PD_SFT 8
1168
+
1169
+
/*PLL tracking mode 7 (0x8a) */
1170
+
#define RT5651_FSI1_RATE_MASK (0xf << 12)
1171
+
#define RT5651_FSI1_RATE_SFT 12
1172
+
#define RT5651_FSI2_RATE_MASK (0xf << 8)
1173
+
#define RT5651_FSI2_RATE_SFT 8
1174
+
1175
+
/* HPOUT Over Current Detection (0x8b) */
1176
+
#define RT5651_HP_OVCD_MASK (0x1 << 10)
1177
+
#define RT5651_HP_OVCD_SFT 10
1178
+
#define RT5651_HP_OVCD_DIS (0x0 << 10)
1179
+
#define RT5651_HP_OVCD_EN (0x1 << 10)
1180
+
#define RT5651_HP_OC_TH_MASK (0x3 << 8)
1181
+
#define RT5651_HP_OC_TH_SFT 8
1182
+
#define RT5651_HP_OC_TH_90 (0x0 << 8)
1183
+
#define RT5651_HP_OC_TH_105 (0x1 << 8)
1184
+
#define RT5651_HP_OC_TH_120 (0x2 << 8)
1185
+
#define RT5651_HP_OC_TH_135 (0x3 << 8)
1186
+
1187
+
/* Depop Mode Control 1 (0x8e) */
1188
+
#define RT5651_SMT_TRIG_MASK (0x1 << 15)
1189
+
#define RT5651_SMT_TRIG_SFT 15
1190
+
#define RT5651_SMT_TRIG_DIS (0x0 << 15)
1191
+
#define RT5651_SMT_TRIG_EN (0x1 << 15)
1192
+
#define RT5651_HP_L_SMT_MASK (0x1 << 9)
1193
+
#define RT5651_HP_L_SMT_SFT 9
1194
+
#define RT5651_HP_L_SMT_DIS (0x0 << 9)
1195
+
#define RT5651_HP_L_SMT_EN (0x1 << 9)
1196
+
#define RT5651_HP_R_SMT_MASK (0x1 << 8)
1197
+
#define RT5651_HP_R_SMT_SFT 8
1198
+
#define RT5651_HP_R_SMT_DIS (0x0 << 8)
1199
+
#define RT5651_HP_R_SMT_EN (0x1 << 8)
1200
+
#define RT5651_HP_CD_PD_MASK (0x1 << 7)
1201
+
#define RT5651_HP_CD_PD_SFT 7
1202
+
#define RT5651_HP_CD_PD_DIS (0x0 << 7)
1203
+
#define RT5651_HP_CD_PD_EN (0x1 << 7)
1204
+
#define RT5651_RSTN_MASK (0x1 << 6)
1205
+
#define RT5651_RSTN_SFT 6
1206
+
#define RT5651_RSTN_DIS (0x0 << 6)
1207
+
#define RT5651_RSTN_EN (0x1 << 6)
1208
+
#define RT5651_RSTP_MASK (0x1 << 5)
1209
+
#define RT5651_RSTP_SFT 5
1210
+
#define RT5651_RSTP_DIS (0x0 << 5)
1211
+
#define RT5651_RSTP_EN (0x1 << 5)
1212
+
#define RT5651_HP_CO_MASK (0x1 << 4)
1213
+
#define RT5651_HP_CO_SFT 4
1214
+
#define RT5651_HP_CO_DIS (0x0 << 4)
1215
+
#define RT5651_HP_CO_EN (0x1 << 4)
1216
+
#define RT5651_HP_CP_MASK (0x1 << 3)
1217
+
#define RT5651_HP_CP_SFT 3
1218
+
#define RT5651_HP_CP_PD (0x0 << 3)
1219
+
#define RT5651_HP_CP_PU (0x1 << 3)
1220
+
#define RT5651_HP_SG_MASK (0x1 << 2)
1221
+
#define RT5651_HP_SG_SFT 2
1222
+
#define RT5651_HP_SG_DIS (0x0 << 2)
1223
+
#define RT5651_HP_SG_EN (0x1 << 2)
1224
+
#define RT5651_HP_DP_MASK (0x1 << 1)
1225
+
#define RT5651_HP_DP_SFT 1
1226
+
#define RT5651_HP_DP_PD (0x0 << 1)
1227
+
#define RT5651_HP_DP_PU (0x1 << 1)
1228
+
#define RT5651_HP_CB_MASK (0x1)
1229
+
#define RT5651_HP_CB_SFT 0
1230
+
#define RT5651_HP_CB_PD (0x0)
1231
+
#define RT5651_HP_CB_PU (0x1)
1232
+
1233
+
/* Depop Mode Control 2 (0x8f) */
1234
+
#define RT5651_DEPOP_MASK (0x1 << 13)
1235
+
#define RT5651_DEPOP_SFT 13
1236
+
#define RT5651_DEPOP_AUTO (0x0 << 13)
1237
+
#define RT5651_DEPOP_MAN (0x1 << 13)
1238
+
#define RT5651_RAMP_MASK (0x1 << 12)
1239
+
#define RT5651_RAMP_SFT 12
1240
+
#define RT5651_RAMP_DIS (0x0 << 12)
1241
+
#define RT5651_RAMP_EN (0x1 << 12)
1242
+
#define RT5651_BPS_MASK (0x1 << 11)
1243
+
#define RT5651_BPS_SFT 11
1244
+
#define RT5651_BPS_DIS (0x0 << 11)
1245
+
#define RT5651_BPS_EN (0x1 << 11)
1246
+
#define RT5651_FAST_UPDN_MASK (0x1 << 10)
1247
+
#define RT5651_FAST_UPDN_SFT 10
1248
+
#define RT5651_FAST_UPDN_DIS (0x0 << 10)
1249
+
#define RT5651_FAST_UPDN_EN (0x1 << 10)
1250
+
#define RT5651_MRES_MASK (0x3 << 8)
1251
+
#define RT5651_MRES_SFT 8
1252
+
#define RT5651_MRES_15MO (0x0 << 8)
1253
+
#define RT5651_MRES_25MO (0x1 << 8)
1254
+
#define RT5651_MRES_35MO (0x2 << 8)
1255
+
#define RT5651_MRES_45MO (0x3 << 8)
1256
+
#define RT5651_VLO_MASK (0x1 << 7)
1257
+
#define RT5651_VLO_SFT 7
1258
+
#define RT5651_VLO_3V (0x0 << 7)
1259
+
#define RT5651_VLO_32V (0x1 << 7)
1260
+
#define RT5651_DIG_DP_MASK (0x1 << 6)
1261
+
#define RT5651_DIG_DP_SFT 6
1262
+
#define RT5651_DIG_DP_DIS (0x0 << 6)
1263
+
#define RT5651_DIG_DP_EN (0x1 << 6)
1264
+
#define RT5651_DP_TH_MASK (0x3 << 4)
1265
+
#define RT5651_DP_TH_SFT 4
1266
+
1267
+
/* Depop Mode Control 3 (0x90) */
1268
+
#define RT5651_CP_SYS_MASK (0x7 << 12)
1269
+
#define RT5651_CP_SYS_SFT 12
1270
+
#define RT5651_CP_FQ1_MASK (0x7 << 8)
1271
+
#define RT5651_CP_FQ1_SFT 8
1272
+
#define RT5651_CP_FQ2_MASK (0x7 << 4)
1273
+
#define RT5651_CP_FQ2_SFT 4
1274
+
#define RT5651_CP_FQ3_MASK (0x7)
1275
+
#define RT5651_CP_FQ3_SFT 0
1276
+
#define RT5651_CP_FQ_1_5_KHZ 0
1277
+
#define RT5651_CP_FQ_3_KHZ 1
1278
+
#define RT5651_CP_FQ_6_KHZ 2
1279
+
#define RT5651_CP_FQ_12_KHZ 3
1280
+
#define RT5651_CP_FQ_24_KHZ 4
1281
+
#define RT5651_CP_FQ_48_KHZ 5
1282
+
#define RT5651_CP_FQ_96_KHZ 6
1283
+
#define RT5651_CP_FQ_192_KHZ 7
1284
+
1285
+
/* HPOUT charge pump (0x91) */
1286
+
#define RT5651_OSW_L_MASK (0x1 << 11)
1287
+
#define RT5651_OSW_L_SFT 11
1288
+
#define RT5651_OSW_L_DIS (0x0 << 11)
1289
+
#define RT5651_OSW_L_EN (0x1 << 11)
1290
+
#define RT5651_OSW_R_MASK (0x1 << 10)
1291
+
#define RT5651_OSW_R_SFT 10
1292
+
#define RT5651_OSW_R_DIS (0x0 << 10)
1293
+
#define RT5651_OSW_R_EN (0x1 << 10)
1294
+
#define RT5651_PM_HP_MASK (0x3 << 8)
1295
+
#define RT5651_PM_HP_SFT 8
1296
+
#define RT5651_PM_HP_LV (0x0 << 8)
1297
+
#define RT5651_PM_HP_MV (0x1 << 8)
1298
+
#define RT5651_PM_HP_HV (0x2 << 8)
1299
+
#define RT5651_IB_HP_MASK (0x3 << 6)
1300
+
#define RT5651_IB_HP_SFT 6
1301
+
#define RT5651_IB_HP_125IL (0x0 << 6)
1302
+
#define RT5651_IB_HP_25IL (0x1 << 6)
1303
+
#define RT5651_IB_HP_5IL (0x2 << 6)
1304
+
#define RT5651_IB_HP_1IL (0x3 << 6)
1305
+
1306
+
/* Micbias Control (0x93) */
1307
+
#define RT5651_MIC1_BS_MASK (0x1 << 15)
1308
+
#define RT5651_MIC1_BS_SFT 15
1309
+
#define RT5651_MIC1_BS_9AV (0x0 << 15)
1310
+
#define RT5651_MIC1_BS_75AV (0x1 << 15)
1311
+
#define RT5651_MIC1_CLK_MASK (0x1 << 13)
1312
+
#define RT5651_MIC1_CLK_SFT 13
1313
+
#define RT5651_MIC1_CLK_DIS (0x0 << 13)
1314
+
#define RT5651_MIC1_CLK_EN (0x1 << 13)
1315
+
#define RT5651_MIC1_OVCD_MASK (0x1 << 11)
1316
+
#define RT5651_MIC1_OVCD_SFT 11
1317
+
#define RT5651_MIC1_OVCD_DIS (0x0 << 11)
1318
+
#define RT5651_MIC1_OVCD_EN (0x1 << 11)
1319
+
#define RT5651_MIC1_OVTH_MASK (0x3 << 9)
1320
+
#define RT5651_MIC1_OVTH_SFT 9
1321
+
#define RT5651_MIC1_OVTH_600UA (0x0 << 9)
1322
+
#define RT5651_MIC1_OVTH_1500UA (0x1 << 9)
1323
+
#define RT5651_MIC1_OVTH_2000UA (0x2 << 9)
1324
+
#define RT5651_PWR_MB_MASK (0x1 << 5)
1325
+
#define RT5651_PWR_MB_SFT 5
1326
+
#define RT5651_PWR_MB_PD (0x0 << 5)
1327
+
#define RT5651_PWR_MB_PU (0x1 << 5)
1328
+
#define RT5651_PWR_CLK12M_MASK (0x1 << 4)
1329
+
#define RT5651_PWR_CLK12M_SFT 4
1330
+
#define RT5651_PWR_CLK12M_PD (0x0 << 4)
1331
+
#define RT5651_PWR_CLK12M_PU (0x1 << 4)
1332
+
1333
+
/* Analog JD Control 1 (0x94) */
1334
+
#define RT5651_JD2_CMP_MASK (0x7 << 12)
1335
+
#define RT5651_JD2_CMP_SFT 12
1336
+
#define RT5651_JD_PU (0x1 << 11)
1337
+
#define RT5651_JD_PU_SFT 11
1338
+
#define RT5651_JD_PD (0x1 << 10)
1339
+
#define RT5651_JD_PD_SFT 10
1340
+
#define RT5651_JD_MODE_SEL_MASK (0x3 << 8)
1341
+
#define RT5651_JD_MODE_SEL_SFT 8
1342
+
#define RT5651_JD_MODE_SEL_M0 (0x0 << 8)
1343
+
#define RT5651_JD_MODE_SEL_M1 (0x1 << 8)
1344
+
#define RT5651_JD_MODE_SEL_M2 (0x2 << 8)
1345
+
#define RT5651_JD_M_CMP (0x7 << 4)
1346
+
#define RT5651_JD_M_CMP_SFT 4
1347
+
#define RT5651_JD_M_PU (0x1 << 3)
1348
+
#define RT5651_JD_M_PU_SFT 3
1349
+
#define RT5651_JD_M_PD (0x1 << 2)
1350
+
#define RT5651_JD_M_PD_SFT 2
1351
+
#define RT5651_JD_M_MODE_SEL_MASK (0x3)
1352
+
#define RT5651_JD_M_MODE_SEL_SFT 0
1353
+
#define RT5651_JD_M_MODE_SEL_M0 (0x0)
1354
+
#define RT5651_JD_M_MODE_SEL_M1 (0x1)
1355
+
#define RT5651_JD_M_MODE_SEL_M2 (0x2)
1356
+
1357
+
/* Analog JD Control 2 (0x95) */
1358
+
#define RT5651_JD3_CMP_MASK (0x7 << 12)
1359
+
#define RT5651_JD3_CMP_SFT 12
1360
+
1361
+
/* EQ Control 1 (0xb0) */
1362
+
#define RT5651_EQ_SRC_MASK (0x1 << 15)
1363
+
#define RT5651_EQ_SRC_SFT 15
1364
+
#define RT5651_EQ_SRC_DAC (0x0 << 15)
1365
+
#define RT5651_EQ_SRC_ADC (0x1 << 15)
1366
+
#define RT5651_EQ_UPD (0x1 << 14)
1367
+
#define RT5651_EQ_UPD_BIT 14
1368
+
#define RT5651_EQ_CD_MASK (0x1 << 13)
1369
+
#define RT5651_EQ_CD_SFT 13
1370
+
#define RT5651_EQ_CD_DIS (0x0 << 13)
1371
+
#define RT5651_EQ_CD_EN (0x1 << 13)
1372
+
#define RT5651_EQ_DITH_MASK (0x3 << 8)
1373
+
#define RT5651_EQ_DITH_SFT 8
1374
+
#define RT5651_EQ_DITH_NOR (0x0 << 8)
1375
+
#define RT5651_EQ_DITH_LSB (0x1 << 8)
1376
+
#define RT5651_EQ_DITH_LSB_1 (0x2 << 8)
1377
+
#define RT5651_EQ_DITH_LSB_2 (0x3 << 8)
1378
+
#define RT5651_EQ_CD_F (0x1 << 7)
1379
+
#define RT5651_EQ_CD_F_BIT 7
1380
+
#define RT5651_EQ_STA_HP2 (0x1 << 6)
1381
+
#define RT5651_EQ_STA_HP2_BIT 6
1382
+
#define RT5651_EQ_STA_HP1 (0x1 << 5)
1383
+
#define RT5651_EQ_STA_HP1_BIT 5
1384
+
#define RT5651_EQ_STA_BP4 (0x1 << 4)
1385
+
#define RT5651_EQ_STA_BP4_BIT 4
1386
+
#define RT5651_EQ_STA_BP3 (0x1 << 3)
1387
+
#define RT5651_EQ_STA_BP3_BIT 3
1388
+
#define RT5651_EQ_STA_BP2 (0x1 << 2)
1389
+
#define RT5651_EQ_STA_BP2_BIT 2
1390
+
#define RT5651_EQ_STA_BP1 (0x1 << 1)
1391
+
#define RT5651_EQ_STA_BP1_BIT 1
1392
+
#define RT5651_EQ_STA_LP (0x1)
1393
+
#define RT5651_EQ_STA_LP_BIT 0
1394
+
1395
+
/* EQ Control 2 (0xb1) */
1396
+
#define RT5651_EQ_HPF1_M_MASK (0x1 << 8)
1397
+
#define RT5651_EQ_HPF1_M_SFT 8
1398
+
#define RT5651_EQ_HPF1_M_HI (0x0 << 8)
1399
+
#define RT5651_EQ_HPF1_M_1ST (0x1 << 8)
1400
+
#define RT5651_EQ_LPF1_M_MASK (0x1 << 7)
1401
+
#define RT5651_EQ_LPF1_M_SFT 7
1402
+
#define RT5651_EQ_LPF1_M_LO (0x0 << 7)
1403
+
#define RT5651_EQ_LPF1_M_1ST (0x1 << 7)
1404
+
#define RT5651_EQ_HPF2_MASK (0x1 << 6)
1405
+
#define RT5651_EQ_HPF2_SFT 6
1406
+
#define RT5651_EQ_HPF2_DIS (0x0 << 6)
1407
+
#define RT5651_EQ_HPF2_EN (0x1 << 6)
1408
+
#define RT5651_EQ_HPF1_MASK (0x1 << 5)
1409
+
#define RT5651_EQ_HPF1_SFT 5
1410
+
#define RT5651_EQ_HPF1_DIS (0x0 << 5)
1411
+
#define RT5651_EQ_HPF1_EN (0x1 << 5)
1412
+
#define RT5651_EQ_BPF4_MASK (0x1 << 4)
1413
+
#define RT5651_EQ_BPF4_SFT 4
1414
+
#define RT5651_EQ_BPF4_DIS (0x0 << 4)
1415
+
#define RT5651_EQ_BPF4_EN (0x1 << 4)
1416
+
#define RT5651_EQ_BPF3_MASK (0x1 << 3)
1417
+
#define RT5651_EQ_BPF3_SFT 3
1418
+
#define RT5651_EQ_BPF3_DIS (0x0 << 3)
1419
+
#define RT5651_EQ_BPF3_EN (0x1 << 3)
1420
+
#define RT5651_EQ_BPF2_MASK (0x1 << 2)
1421
+
#define RT5651_EQ_BPF2_SFT 2
1422
+
#define RT5651_EQ_BPF2_DIS (0x0 << 2)
1423
+
#define RT5651_EQ_BPF2_EN (0x1 << 2)
1424
+
#define RT5651_EQ_BPF1_MASK (0x1 << 1)
1425
+
#define RT5651_EQ_BPF1_SFT 1
1426
+
#define RT5651_EQ_BPF1_DIS (0x0 << 1)
1427
+
#define RT5651_EQ_BPF1_EN (0x1 << 1)
1428
+
#define RT5651_EQ_LPF_MASK (0x1)
1429
+
#define RT5651_EQ_LPF_SFT 0
1430
+
#define RT5651_EQ_LPF_DIS (0x0)
1431
+
#define RT5651_EQ_LPF_EN (0x1)
1432
+
#define RT5651_EQ_CTRL_MASK (0x7f)
1433
+
1434
+
/* Memory Test (0xb2) */
1435
+
#define RT5651_MT_MASK (0x1 << 15)
1436
+
#define RT5651_MT_SFT 15
1437
+
#define RT5651_MT_DIS (0x0 << 15)
1438
+
#define RT5651_MT_EN (0x1 << 15)
1439
+
1440
+
/* ALC Control 1 (0xb4) */
1441
+
#define RT5651_ALC_P_MASK (0x1 << 15)
1442
+
#define RT5651_ALC_P_SFT 15
1443
+
#define RT5651_ALC_P_DAC (0x0 << 15)
1444
+
#define RT5651_ALC_P_ADC (0x1 << 15)
1445
+
#define RT5651_ALC_MASK (0x1 << 14)
1446
+
#define RT5651_ALC_SFT 14
1447
+
#define RT5651_ALC_DIS (0x0 << 14)
1448
+
#define RT5651_ALC_EN (0x1 << 14)
1449
+
#define RT5651_ALC_UPD (0x1 << 13)
1450
+
#define RT5651_ALC_UPD_BIT 13
1451
+
#define RT5651_ALC_AR_MASK (0x1f << 8)
1452
+
#define RT5651_ALC_AR_SFT 8
1453
+
#define RT5651_ALC_R_MASK (0x7 << 5)
1454
+
#define RT5651_ALC_R_SFT 5
1455
+
#define RT5651_ALC_R_48K (0x1 << 5)
1456
+
#define RT5651_ALC_R_96K (0x2 << 5)
1457
+
#define RT5651_ALC_R_192K (0x3 << 5)
1458
+
#define RT5651_ALC_R_441K (0x5 << 5)
1459
+
#define RT5651_ALC_R_882K (0x6 << 5)
1460
+
#define RT5651_ALC_R_1764K (0x7 << 5)
1461
+
#define RT5651_ALC_RC_MASK (0x1f)
1462
+
#define RT5651_ALC_RC_SFT 0
1463
+
1464
+
/* ALC Control 2 (0xb5) */
1465
+
#define RT5651_ALC_POB_MASK (0x3f << 8)
1466
+
#define RT5651_ALC_POB_SFT 8
1467
+
#define RT5651_ALC_DRC_MASK (0x1 << 7)
1468
+
#define RT5651_ALC_DRC_SFT 7
1469
+
#define RT5651_ALC_DRC_DIS (0x0 << 7)
1470
+
#define RT5651_ALC_DRC_EN (0x1 << 7)
1471
+
#define RT5651_ALC_CPR_MASK (0x3 << 5)
1472
+
#define RT5651_ALC_CPR_SFT 5
1473
+
#define RT5651_ALC_CPR_1_1 (0x0 << 5)
1474
+
#define RT5651_ALC_CPR_1_2 (0x1 << 5)
1475
+
#define RT5651_ALC_CPR_1_4 (0x2 << 5)
1476
+
#define RT5651_ALC_CPR_1_8 (0x3 << 5)
1477
+
#define RT5651_ALC_PRB_MASK (0x1f)
1478
+
#define RT5651_ALC_PRB_SFT 0
1479
+
1480
+
/* ALC Control 3 (0xb6) */
1481
+
#define RT5651_ALC_NGB_MASK (0xf << 12)
1482
+
#define RT5651_ALC_NGB_SFT 12
1483
+
#define RT5651_ALC_TAR_MASK (0x1f << 7)
1484
+
#define RT5651_ALC_TAR_SFT 7
1485
+
#define RT5651_ALC_NG_MASK (0x1 << 6)
1486
+
#define RT5651_ALC_NG_SFT 6
1487
+
#define RT5651_ALC_NG_DIS (0x0 << 6)
1488
+
#define RT5651_ALC_NG_EN (0x1 << 6)
1489
+
#define RT5651_ALC_NGH_MASK (0x1 << 5)
1490
+
#define RT5651_ALC_NGH_SFT 5
1491
+
#define RT5651_ALC_NGH_DIS (0x0 << 5)
1492
+
#define RT5651_ALC_NGH_EN (0x1 << 5)
1493
+
#define RT5651_ALC_NGT_MASK (0x1f)
1494
+
#define RT5651_ALC_NGT_SFT 0
1495
+
1496
+
/* Jack Detect Control 1 (0xbb) */
1497
+
#define RT5651_JD_MASK (0x7 << 13)
1498
+
#define RT5651_JD_SFT 13
1499
+
#define RT5651_JD_DIS (0x0 << 13)
1500
+
#define RT5651_JD_GPIO1 (0x1 << 13)
1501
+
#define RT5651_JD_GPIO2 (0x2 << 13)
1502
+
#define RT5651_JD_GPIO3 (0x3 << 13)
1503
+
#define RT5651_JD_GPIO4 (0x4 << 13)
1504
+
#define RT5651_JD_GPIO5 (0x5 << 13)
1505
+
#define RT5651_JD_GPIO6 (0x6 << 13)
1506
+
#define RT5651_JD_HP_MASK (0x1 << 11)
1507
+
#define RT5651_JD_HP_SFT 11
1508
+
#define RT5651_JD_HP_DIS (0x0 << 11)
1509
+
#define RT5651_JD_HP_EN (0x1 << 11)
1510
+
#define RT5651_JD_HP_TRG_MASK (0x1 << 10)
1511
+
#define RT5651_JD_HP_TRG_SFT 10
1512
+
#define RT5651_JD_HP_TRG_LO (0x0 << 10)
1513
+
#define RT5651_JD_HP_TRG_HI (0x1 << 10)
1514
+
#define RT5651_JD_SPL_MASK (0x1 << 9)
1515
+
#define RT5651_JD_SPL_SFT 9
1516
+
#define RT5651_JD_SPL_DIS (0x0 << 9)
1517
+
#define RT5651_JD_SPL_EN (0x1 << 9)
1518
+
#define RT5651_JD_SPL_TRG_MASK (0x1 << 8)
1519
+
#define RT5651_JD_SPL_TRG_SFT 8
1520
+
#define RT5651_JD_SPL_TRG_LO (0x0 << 8)
1521
+
#define RT5651_JD_SPL_TRG_HI (0x1 << 8)
1522
+
#define RT5651_JD_SPR_MASK (0x1 << 7)
1523
+
#define RT5651_JD_SPR_SFT 7
1524
+
#define RT5651_JD_SPR_DIS (0x0 << 7)
1525
+
#define RT5651_JD_SPR_EN (0x1 << 7)
1526
+
#define RT5651_JD_SPR_TRG_MASK (0x1 << 6)
1527
+
#define RT5651_JD_SPR_TRG_SFT 6
1528
+
#define RT5651_JD_SPR_TRG_LO (0x0 << 6)
1529
+
#define RT5651_JD_SPR_TRG_HI (0x1 << 6)
1530
+
#define RT5651_JD_LO_MASK (0x1 << 3)
1531
+
#define RT5651_JD_LO_SFT 3
1532
+
#define RT5651_JD_LO_DIS (0x0 << 3)
1533
+
#define RT5651_JD_LO_EN (0x1 << 3)
1534
+
#define RT5651_JD_LO_TRG_MASK (0x1 << 2)
1535
+
#define RT5651_JD_LO_TRG_SFT 2
1536
+
#define RT5651_JD_LO_TRG_LO (0x0 << 2)
1537
+
#define RT5651_JD_LO_TRG_HI (0x1 << 2)
1538
+
1539
+
/* Jack Detect Control 2 (0xbc) */
1540
+
#define RT5651_JD_TRG_SEL_MASK (0x7 << 9)
1541
+
#define RT5651_JD_TRG_SEL_SFT 9
1542
+
#define RT5651_JD_TRG_SEL_GPIO (0x0 << 9)
1543
+
#define RT5651_JD_TRG_SEL_JD1_1 (0x1 << 9)
1544
+
#define RT5651_JD_TRG_SEL_JD1_2 (0x2 << 9)
1545
+
#define RT5651_JD_TRG_SEL_JD2 (0x3 << 9)
1546
+
#define RT5651_JD_TRG_SEL_JD3 (0x4 << 9)
1547
+
#define RT5651_JD3_IRQ_EN (0x1 << 8)
1548
+
#define RT5651_JD3_IRQ_EN_SFT 8
1549
+
#define RT5651_JD3_EN_STKY (0x1 << 7)
1550
+
#define RT5651_JD3_EN_STKY_SFT 7
1551
+
#define RT5651_JD3_INV (0x1 << 6)
1552
+
#define RT5651_JD3_INV_SFT 6
1553
+
1554
+
/* IRQ Control 1 (0xbd) */
1555
+
#define RT5651_IRQ_JD_MASK (0x1 << 15)
1556
+
#define RT5651_IRQ_JD_SFT 15
1557
+
#define RT5651_IRQ_JD_BP (0x0 << 15)
1558
+
#define RT5651_IRQ_JD_NOR (0x1 << 15)
1559
+
#define RT5651_JD_STKY_MASK (0x1 << 13)
1560
+
#define RT5651_JD_STKY_SFT 13
1561
+
#define RT5651_JD_STKY_DIS (0x0 << 13)
1562
+
#define RT5651_JD_STKY_EN (0x1 << 13)
1563
+
#define RT5651_JD_P_MASK (0x1 << 11)
1564
+
#define RT5651_JD_P_SFT 11
1565
+
#define RT5651_JD_P_NOR (0x0 << 11)
1566
+
#define RT5651_JD_P_INV (0x1 << 11)
1567
+
#define RT5651_JD1_1_IRQ_EN (0x1 << 9)
1568
+
#define RT5651_JD1_1_IRQ_EN_SFT 9
1569
+
#define RT5651_JD1_1_EN_STKY (0x1 << 8)
1570
+
#define RT5651_JD1_1_EN_STKY_SFT 8
1571
+
#define RT5651_JD1_1_INV (0x1 << 7)
1572
+
#define RT5651_JD1_1_INV_SFT 7
1573
+
#define RT5651_JD1_2_IRQ_EN (0x1 << 6)
1574
+
#define RT5651_JD1_2_IRQ_EN_SFT 6
1575
+
#define RT5651_JD1_2_EN_STKY (0x1 << 5)
1576
+
#define RT5651_JD1_2_EN_STKY_SFT 5
1577
+
#define RT5651_JD1_2_INV (0x1 << 4)
1578
+
#define RT5651_JD1_2_INV_SFT 4
1579
+
#define RT5651_JD2_IRQ_EN (0x1 << 3)
1580
+
#define RT5651_JD2_IRQ_EN_SFT 3
1581
+
#define RT5651_JD2_EN_STKY (0x1 << 2)
1582
+
#define RT5651_JD2_EN_STKY_SFT 2
1583
+
#define RT5651_JD2_INV (0x1 << 1)
1584
+
#define RT5651_JD2_INV_SFT 1
1585
+
1586
+
/* IRQ Control 2 (0xbe) */
1587
+
#define RT5651_IRQ_MB1_OC_MASK (0x1 << 15)
1588
+
#define RT5651_IRQ_MB1_OC_SFT 15
1589
+
#define RT5651_IRQ_MB1_OC_BP (0x0 << 15)
1590
+
#define RT5651_IRQ_MB1_OC_NOR (0x1 << 15)
1591
+
#define RT5651_MB1_OC_STKY_MASK (0x1 << 11)
1592
+
#define RT5651_MB1_OC_STKY_SFT 11
1593
+
#define RT5651_MB1_OC_STKY_DIS (0x0 << 11)
1594
+
#define RT5651_MB1_OC_STKY_EN (0x1 << 11)
1595
+
#define RT5651_MB1_OC_P_MASK (0x1 << 7)
1596
+
#define RT5651_MB1_OC_P_SFT 7
1597
+
#define RT5651_MB1_OC_P_NOR (0x0 << 7)
1598
+
#define RT5651_MB1_OC_P_INV (0x1 << 7)
1599
+
#define RT5651_MB2_OC_P_MASK (0x1 << 6)
1600
+
#define RT5651_MB1_OC_CLR (0x1 << 3)
1601
+
#define RT5651_MB1_OC_CLR_SFT 3
1602
+
#define RT5651_STA_GPIO8 (0x1)
1603
+
#define RT5651_STA_GPIO8_BIT 0
1604
+
1605
+
/* Internal Status and GPIO status (0xbf) */
1606
+
#define RT5651_STA_JD3 (0x1 << 15)
1607
+
#define RT5651_STA_JD3_BIT 15
1608
+
#define RT5651_STA_JD2 (0x1 << 14)
1609
+
#define RT5651_STA_JD2_BIT 14
1610
+
#define RT5651_STA_JD1_2 (0x1 << 13)
1611
+
#define RT5651_STA_JD1_2_BIT 13
1612
+
#define RT5651_STA_JD1_1 (0x1 << 12)
1613
+
#define RT5651_STA_JD1_1_BIT 12
1614
+
#define RT5651_STA_GP7 (0x1 << 11)
1615
+
#define RT5651_STA_GP7_BIT 11
1616
+
#define RT5651_STA_GP6 (0x1 << 10)
1617
+
#define RT5651_STA_GP6_BIT 10
1618
+
#define RT5651_STA_GP5 (0x1 << 9)
1619
+
#define RT5651_STA_GP5_BIT 9
1620
+
#define RT5651_STA_GP1 (0x1 << 8)
1621
+
#define RT5651_STA_GP1_BIT 8
1622
+
#define RT5651_STA_GP2 (0x1 << 7)
1623
+
#define RT5651_STA_GP2_BIT 7
1624
+
#define RT5651_STA_GP3 (0x1 << 6)
1625
+
#define RT5651_STA_GP3_BIT 6
1626
+
#define RT5651_STA_GP4 (0x1 << 5)
1627
+
#define RT5651_STA_GP4_BIT 5
1628
+
#define RT5651_STA_GP_JD (0x1 << 4)
1629
+
#define RT5651_STA_GP_JD_BIT 4
1630
+
1631
+
/* GPIO Control 1 (0xc0) */
1632
+
#define RT5651_GP1_PIN_MASK (0x1 << 15)
1633
+
#define RT5651_GP1_PIN_SFT 15
1634
+
#define RT5651_GP1_PIN_GPIO1 (0x0 << 15)
1635
+
#define RT5651_GP1_PIN_IRQ (0x1 << 15)
1636
+
#define RT5651_GP2_PIN_MASK (0x1 << 14)
1637
+
#define RT5651_GP2_PIN_SFT 14
1638
+
#define RT5651_GP2_PIN_GPIO2 (0x0 << 14)
1639
+
#define RT5651_GP2_PIN_DMIC1_SCL (0x1 << 14)
1640
+
#define RT5651_GPIO_M_MASK (0x1 << 9)
1641
+
#define RT5651_GPIO_M_SFT 9
1642
+
#define RT5651_GPIO_M_FLT (0x0 << 9)
1643
+
#define RT5651_GPIO_M_PH (0x1 << 9)
1644
+
#define RT5651_I2S2_SEL_MASK (0x1 << 8)
1645
+
#define RT5651_I2S2_SEL_SFT 8
1646
+
#define RT5651_I2S2_SEL_I2S (0x0 << 8)
1647
+
#define RT5651_I2S2_SEL_GPIO (0x1 << 8)
1648
+
#define RT5651_GP5_PIN_MASK (0x1 << 7)
1649
+
#define RT5651_GP5_PIN_SFT 7
1650
+
#define RT5651_GP5_PIN_GPIO5 (0x0 << 7)
1651
+
#define RT5651_GP5_PIN_IRQ (0x1 << 7)
1652
+
#define RT5651_GP6_PIN_MASK (0x1 << 6)
1653
+
#define RT5651_GP6_PIN_SFT 6
1654
+
#define RT5651_GP6_PIN_GPIO6 (0x0 << 6)
1655
+
#define RT5651_GP6_PIN_DMIC_SDA (0x1 << 6)
1656
+
#define RT5651_GP7_PIN_MASK (0x1 << 5)
1657
+
#define RT5651_GP7_PIN_SFT 5
1658
+
#define RT5651_GP7_PIN_GPIO7 (0x0 << 5)
1659
+
#define RT5651_GP7_PIN_IRQ (0x1 << 5)
1660
+
#define RT5651_GP8_PIN_MASK (0x1 << 4)
1661
+
#define RT5651_GP8_PIN_SFT 4
1662
+
#define RT5651_GP8_PIN_GPIO8 (0x0 << 4)
1663
+
#define RT5651_GP8_PIN_DMIC_SDA (0x1 << 4)
1664
+
#define RT5651_GPIO_PDM_SEL_MASK (0x1 << 3)
1665
+
#define RT5651_GPIO_PDM_SEL_SFT 3
1666
+
#define RT5651_GPIO_PDM_SEL_GPIO (0x0 << 3)
1667
+
#define RT5651_GPIO_PDM_SEL_PDM (0x1 << 3)
1668
+
1669
+
/* GPIO Control 2 (0xc1) */
1670
+
#define RT5651_GP5_DR_MASK (0x1 << 14)
1671
+
#define RT5651_GP5_DR_SFT 14
1672
+
#define RT5651_GP5_DR_IN (0x0 << 14)
1673
+
#define RT5651_GP5_DR_OUT (0x1 << 14)
1674
+
#define RT5651_GP5_OUT_MASK (0x1 << 13)
1675
+
#define RT5651_GP5_OUT_SFT 13
1676
+
#define RT5651_GP5_OUT_LO (0x0 << 13)
1677
+
#define RT5651_GP5_OUT_HI (0x1 << 13)
1678
+
#define RT5651_GP5_P_MASK (0x1 << 12)
1679
+
#define RT5651_GP5_P_SFT 12
1680
+
#define RT5651_GP5_P_NOR (0x0 << 12)
1681
+
#define RT5651_GP5_P_INV (0x1 << 12)
1682
+
#define RT5651_GP4_DR_MASK (0x1 << 11)
1683
+
#define RT5651_GP4_DR_SFT 11
1684
+
#define RT5651_GP4_DR_IN (0x0 << 11)
1685
+
#define RT5651_GP4_DR_OUT (0x1 << 11)
1686
+
#define RT5651_GP4_OUT_MASK (0x1 << 10)
1687
+
#define RT5651_GP4_OUT_SFT 10
1688
+
#define RT5651_GP4_OUT_LO (0x0 << 10)
1689
+
#define RT5651_GP4_OUT_HI (0x1 << 10)
1690
+
#define RT5651_GP4_P_MASK (0x1 << 9)
1691
+
#define RT5651_GP4_P_SFT 9
1692
+
#define RT5651_GP4_P_NOR (0x0 << 9)
1693
+
#define RT5651_GP4_P_INV (0x1 << 9)
1694
+
#define RT5651_GP3_DR_MASK (0x1 << 8)
1695
+
#define RT5651_GP3_DR_SFT 8
1696
+
#define RT5651_GP3_DR_IN (0x0 << 8)
1697
+
#define RT5651_GP3_DR_OUT (0x1 << 8)
1698
+
#define RT5651_GP3_OUT_MASK (0x1 << 7)
1699
+
#define RT5651_GP3_OUT_SFT 7
1700
+
#define RT5651_GP3_OUT_LO (0x0 << 7)
1701
+
#define RT5651_GP3_OUT_HI (0x1 << 7)
1702
+
#define RT5651_GP3_P_MASK (0x1 << 6)
1703
+
#define RT5651_GP3_P_SFT 6
1704
+
#define RT5651_GP3_P_NOR (0x0 << 6)
1705
+
#define RT5651_GP3_P_INV (0x1 << 6)
1706
+
#define RT5651_GP2_DR_MASK (0x1 << 5)
1707
+
#define RT5651_GP2_DR_SFT 5
1708
+
#define RT5651_GP2_DR_IN (0x0 << 5)
1709
+
#define RT5651_GP2_DR_OUT (0x1 << 5)
1710
+
#define RT5651_GP2_OUT_MASK (0x1 << 4)
1711
+
#define RT5651_GP2_OUT_SFT 4
1712
+
#define RT5651_GP2_OUT_LO (0x0 << 4)
1713
+
#define RT5651_GP2_OUT_HI (0x1 << 4)
1714
+
#define RT5651_GP2_P_MASK (0x1 << 3)
1715
+
#define RT5651_GP2_P_SFT 3
1716
+
#define RT5651_GP2_P_NOR (0x0 << 3)
1717
+
#define RT5651_GP2_P_INV (0x1 << 3)
1718
+
#define RT5651_GP1_DR_MASK (0x1 << 2)
1719
+
#define RT5651_GP1_DR_SFT 2
1720
+
#define RT5651_GP1_DR_IN (0x0 << 2)
1721
+
#define RT5651_GP1_DR_OUT (0x1 << 2)
1722
+
#define RT5651_GP1_OUT_MASK (0x1 << 1)
1723
+
#define RT5651_GP1_OUT_SFT 1
1724
+
#define RT5651_GP1_OUT_LO (0x0 << 1)
1725
+
#define RT5651_GP1_OUT_HI (0x1 << 1)
1726
+
#define RT5651_GP1_P_MASK (0x1)
1727
+
#define RT5651_GP1_P_SFT 0
1728
+
#define RT5651_GP1_P_NOR (0x0)
1729
+
#define RT5651_GP1_P_INV (0x1)
1730
+
1731
+
/* GPIO Control 3 (0xc2) */
1732
+
#define RT5651_GP8_DR_MASK (0x1 << 8)
1733
+
#define RT5651_GP8_DR_SFT 8
1734
+
#define RT5651_GP8_DR_IN (0x0 << 8)
1735
+
#define RT5651_GP8_DR_OUT (0x1 << 8)
1736
+
#define RT5651_GP8_OUT_MASK (0x1 << 7)
1737
+
#define RT5651_GP8_OUT_SFT 7
1738
+
#define RT5651_GP8_OUT_LO (0x0 << 7)
1739
+
#define RT5651_GP8_OUT_HI (0x1 << 7)
1740
+
#define RT5651_GP8_P_MASK (0x1 << 6)
1741
+
#define RT5651_GP8_P_SFT 6
1742
+
#define RT5651_GP8_P_NOR (0x0 << 6)
1743
+
#define RT5651_GP8_P_INV (0x1 << 6)
1744
+
#define RT5651_GP7_DR_MASK (0x1 << 5)
1745
+
#define RT5651_GP7_DR_SFT 5
1746
+
#define RT5651_GP7_DR_IN (0x0 << 5)
1747
+
#define RT5651_GP7_DR_OUT (0x1 << 5)
1748
+
#define RT5651_GP7_OUT_MASK (0x1 << 4)
1749
+
#define RT5651_GP7_OUT_SFT 4
1750
+
#define RT5651_GP7_OUT_LO (0x0 << 4)
1751
+
#define RT5651_GP7_OUT_HI (0x1 << 4)
1752
+
#define RT5651_GP7_P_MASK (0x1 << 3)
1753
+
#define RT5651_GP7_P_SFT 3
1754
+
#define RT5651_GP7_P_NOR (0x0 << 3)
1755
+
#define RT5651_GP7_P_INV (0x1 << 3)
1756
+
#define RT5651_GP6_DR_MASK (0x1 << 2)
1757
+
#define RT5651_GP6_DR_SFT 2
1758
+
#define RT5651_GP6_DR_IN (0x0 << 2)
1759
+
#define RT5651_GP6_DR_OUT (0x1 << 2)
1760
+
#define RT5651_GP6_OUT_MASK (0x1 << 1)
1761
+
#define RT5651_GP6_OUT_SFT 1
1762
+
#define RT5651_GP6_OUT_LO (0x0 << 1)
1763
+
#define RT5651_GP6_OUT_HI (0x1 << 1)
1764
+
#define RT5651_GP6_P_MASK (0x1)
1765
+
#define RT5651_GP6_P_SFT 0
1766
+
#define RT5651_GP6_P_NOR (0x0)
1767
+
#define RT5651_GP6_P_INV (0x1)
1768
+
1769
+
/* Scramble Control (0xce) */
1770
+
#define RT5651_SCB_SWAP_MASK (0x1 << 15)
1771
+
#define RT5651_SCB_SWAP_SFT 15
1772
+
#define RT5651_SCB_SWAP_DIS (0x0 << 15)
1773
+
#define RT5651_SCB_SWAP_EN (0x1 << 15)
1774
+
#define RT5651_SCB_MASK (0x1 << 14)
1775
+
#define RT5651_SCB_SFT 14
1776
+
#define RT5651_SCB_DIS (0x0 << 14)
1777
+
#define RT5651_SCB_EN (0x1 << 14)
1778
+
1779
+
/* Baseback Control (0xcf) */
1780
+
#define RT5651_BB_MASK (0x1 << 15)
1781
+
#define RT5651_BB_SFT 15
1782
+
#define RT5651_BB_DIS (0x0 << 15)
1783
+
#define RT5651_BB_EN (0x1 << 15)
1784
+
#define RT5651_BB_CT_MASK (0x7 << 12)
1785
+
#define RT5651_BB_CT_SFT 12
1786
+
#define RT5651_BB_CT_A (0x0 << 12)
1787
+
#define RT5651_BB_CT_B (0x1 << 12)
1788
+
#define RT5651_BB_CT_C (0x2 << 12)
1789
+
#define RT5651_BB_CT_D (0x3 << 12)
1790
+
#define RT5651_M_BB_L_MASK (0x1 << 9)
1791
+
#define RT5651_M_BB_L_SFT 9
1792
+
#define RT5651_M_BB_R_MASK (0x1 << 8)
1793
+
#define RT5651_M_BB_R_SFT 8
1794
+
#define RT5651_M_BB_HPF_L_MASK (0x1 << 7)
1795
+
#define RT5651_M_BB_HPF_L_SFT 7
1796
+
#define RT5651_M_BB_HPF_R_MASK (0x1 << 6)
1797
+
#define RT5651_M_BB_HPF_R_SFT 6
1798
+
#define RT5651_G_BB_BST_MASK (0x3f)
1799
+
#define RT5651_G_BB_BST_SFT 0
1800
+
1801
+
/* MP3 Plus Control 1 (0xd0) */
1802
+
#define RT5651_M_MP3_L_MASK (0x1 << 15)
1803
+
#define RT5651_M_MP3_L_SFT 15
1804
+
#define RT5651_M_MP3_R_MASK (0x1 << 14)
1805
+
#define RT5651_M_MP3_R_SFT 14
1806
+
#define RT5651_M_MP3_MASK (0x1 << 13)
1807
+
#define RT5651_M_MP3_SFT 13
1808
+
#define RT5651_M_MP3_DIS (0x0 << 13)
1809
+
#define RT5651_M_MP3_EN (0x1 << 13)
1810
+
#define RT5651_EG_MP3_MASK (0x1f << 8)
1811
+
#define RT5651_EG_MP3_SFT 8
1812
+
#define RT5651_MP3_HLP_MASK (0x1 << 7)
1813
+
#define RT5651_MP3_HLP_SFT 7
1814
+
#define RT5651_MP3_HLP_DIS (0x0 << 7)
1815
+
#define RT5651_MP3_HLP_EN (0x1 << 7)
1816
+
#define RT5651_M_MP3_ORG_L_MASK (0x1 << 6)
1817
+
#define RT5651_M_MP3_ORG_L_SFT 6
1818
+
#define RT5651_M_MP3_ORG_R_MASK (0x1 << 5)
1819
+
#define RT5651_M_MP3_ORG_R_SFT 5
1820
+
1821
+
/* MP3 Plus Control 2 (0xd1) */
1822
+
#define RT5651_MP3_WT_MASK (0x1 << 13)
1823
+
#define RT5651_MP3_WT_SFT 13
1824
+
#define RT5651_MP3_WT_1_4 (0x0 << 13)
1825
+
#define RT5651_MP3_WT_1_2 (0x1 << 13)
1826
+
#define RT5651_OG_MP3_MASK (0x1f << 8)
1827
+
#define RT5651_OG_MP3_SFT 8
1828
+
#define RT5651_HG_MP3_MASK (0x3f)
1829
+
#define RT5651_HG_MP3_SFT 0
1830
+
1831
+
/* 3D HP Control 1 (0xd2) */
1832
+
#define RT5651_3D_CF_MASK (0x1 << 15)
1833
+
#define RT5651_3D_CF_SFT 15
1834
+
#define RT5651_3D_CF_DIS (0x0 << 15)
1835
+
#define RT5651_3D_CF_EN (0x1 << 15)
1836
+
#define RT5651_3D_HP_MASK (0x1 << 14)
1837
+
#define RT5651_3D_HP_SFT 14
1838
+
#define RT5651_3D_HP_DIS (0x0 << 14)
1839
+
#define RT5651_3D_HP_EN (0x1 << 14)
1840
+
#define RT5651_3D_BT_MASK (0x1 << 13)
1841
+
#define RT5651_3D_BT_SFT 13
1842
+
#define RT5651_3D_BT_DIS (0x0 << 13)
1843
+
#define RT5651_3D_BT_EN (0x1 << 13)
1844
+
#define RT5651_3D_1F_MIX_MASK (0x3 << 11)
1845
+
#define RT5651_3D_1F_MIX_SFT 11
1846
+
#define RT5651_3D_HP_M_MASK (0x1 << 10)
1847
+
#define RT5651_3D_HP_M_SFT 10
1848
+
#define RT5651_3D_HP_M_SUR (0x0 << 10)
1849
+
#define RT5651_3D_HP_M_FRO (0x1 << 10)
1850
+
#define RT5651_M_3D_HRTF_MASK (0x1 << 9)
1851
+
#define RT5651_M_3D_HRTF_SFT 9
1852
+
#define RT5651_M_3D_D2H_MASK (0x1 << 8)
1853
+
#define RT5651_M_3D_D2H_SFT 8
1854
+
#define RT5651_M_3D_D2R_MASK (0x1 << 7)
1855
+
#define RT5651_M_3D_D2R_SFT 7
1856
+
#define RT5651_M_3D_REVB_MASK (0x1 << 6)
1857
+
#define RT5651_M_3D_REVB_SFT 6
1858
+
1859
+
/* Adjustable high pass filter control 1 (0xd3) */
1860
+
#define RT5651_2ND_HPF_MASK (0x1 << 15)
1861
+
#define RT5651_2ND_HPF_SFT 15
1862
+
#define RT5651_2ND_HPF_DIS (0x0 << 15)
1863
+
#define RT5651_2ND_HPF_EN (0x1 << 15)
1864
+
#define RT5651_HPF_CF_L_MASK (0x7 << 12)
1865
+
#define RT5651_HPF_CF_L_SFT 12
1866
+
#define RT5651_HPF_CF_R_MASK (0x7 << 8)
1867
+
#define RT5651_HPF_CF_R_SFT 8
1868
+
#define RT5651_ZD_T_MASK (0x3 << 6)
1869
+
#define RT5651_ZD_T_SFT 6
1870
+
#define RT5651_ZD_F_MASK (0x3 << 4)
1871
+
#define RT5651_ZD_F_SFT 4
1872
+
#define RT5651_ZD_F_IM (0x0 << 4)
1873
+
#define RT5651_ZD_F_ZC_IM (0x1 << 4)
1874
+
#define RT5651_ZD_F_ZC_IOD (0x2 << 4)
1875
+
#define RT5651_ZD_F_UN (0x3 << 4)
1876
+
1877
+
/* Adjustable high pass filter control 2 (0xd4) */
1878
+
#define RT5651_HPF_CF_L_NUM_MASK (0x3f << 8)
1879
+
#define RT5651_HPF_CF_L_NUM_SFT 8
1880
+
#define RT5651_HPF_CF_R_NUM_MASK (0x3f)
1881
+
#define RT5651_HPF_CF_R_NUM_SFT 0
1882
+
1883
+
/* HP calibration control and Amp detection (0xd6) */
1884
+
#define RT5651_SI_DAC_MASK (0x1 << 11)
1885
+
#define RT5651_SI_DAC_SFT 11
1886
+
#define RT5651_SI_DAC_AUTO (0x0 << 11)
1887
+
#define RT5651_SI_DAC_TEST (0x1 << 11)
1888
+
#define RT5651_DC_CAL_M_MASK (0x1 << 10)
1889
+
#define RT5651_DC_CAL_M_SFT 10
1890
+
#define RT5651_DC_CAL_M_NOR (0x0 << 10)
1891
+
#define RT5651_DC_CAL_M_CAL (0x1 << 10)
1892
+
#define RT5651_DC_CAL_MASK (0x1 << 9)
1893
+
#define RT5651_DC_CAL_SFT 9
1894
+
#define RT5651_DC_CAL_DIS (0x0 << 9)
1895
+
#define RT5651_DC_CAL_EN (0x1 << 9)
1896
+
#define RT5651_HPD_RCV_MASK (0x7 << 6)
1897
+
#define RT5651_HPD_RCV_SFT 6
1898
+
#define RT5651_HPD_PS_MASK (0x1 << 5)
1899
+
#define RT5651_HPD_PS_SFT 5
1900
+
#define RT5651_HPD_PS_DIS (0x0 << 5)
1901
+
#define RT5651_HPD_PS_EN (0x1 << 5)
1902
+
#define RT5651_CAL_M_MASK (0x1 << 4)
1903
+
#define RT5651_CAL_M_SFT 4
1904
+
#define RT5651_CAL_M_DEP (0x0 << 4)
1905
+
#define RT5651_CAL_M_CAL (0x1 << 4)
1906
+
#define RT5651_CAL_MASK (0x1 << 3)
1907
+
#define RT5651_CAL_SFT 3
1908
+
#define RT5651_CAL_DIS (0x0 << 3)
1909
+
#define RT5651_CAL_EN (0x1 << 3)
1910
+
#define RT5651_CAL_TEST_MASK (0x1 << 2)
1911
+
#define RT5651_CAL_TEST_SFT 2
1912
+
#define RT5651_CAL_TEST_DIS (0x0 << 2)
1913
+
#define RT5651_CAL_TEST_EN (0x1 << 2)
1914
+
#define RT5651_CAL_P_MASK (0x3)
1915
+
#define RT5651_CAL_P_SFT 0
1916
+
#define RT5651_CAL_P_NONE (0x0)
1917
+
#define RT5651_CAL_P_CAL (0x1)
1918
+
#define RT5651_CAL_P_DAC_CAL (0x2)
1919
+
1920
+
/* Soft volume and zero cross control 1 (0xd9) */
1921
+
#define RT5651_SV_MASK (0x1 << 15)
1922
+
#define RT5651_SV_SFT 15
1923
+
#define RT5651_SV_DIS (0x0 << 15)
1924
+
#define RT5651_SV_EN (0x1 << 15)
1925
+
#define RT5651_OUT_SV_MASK (0x1 << 13)
1926
+
#define RT5651_OUT_SV_SFT 13
1927
+
#define RT5651_OUT_SV_DIS (0x0 << 13)
1928
+
#define RT5651_OUT_SV_EN (0x1 << 13)
1929
+
#define RT5651_HP_SV_MASK (0x1 << 12)
1930
+
#define RT5651_HP_SV_SFT 12
1931
+
#define RT5651_HP_SV_DIS (0x0 << 12)
1932
+
#define RT5651_HP_SV_EN (0x1 << 12)
1933
+
#define RT5651_ZCD_DIG_MASK (0x1 << 11)
1934
+
#define RT5651_ZCD_DIG_SFT 11
1935
+
#define RT5651_ZCD_DIG_DIS (0x0 << 11)
1936
+
#define RT5651_ZCD_DIG_EN (0x1 << 11)
1937
+
#define RT5651_ZCD_MASK (0x1 << 10)
1938
+
#define RT5651_ZCD_SFT 10
1939
+
#define RT5651_ZCD_PD (0x0 << 10)
1940
+
#define RT5651_ZCD_PU (0x1 << 10)
1941
+
#define RT5651_M_ZCD_MASK (0x3f << 4)
1942
+
#define RT5651_M_ZCD_SFT 4
1943
+
#define RT5651_M_ZCD_OM_L (0x1 << 7)
1944
+
#define RT5651_M_ZCD_OM_R (0x1 << 6)
1945
+
#define RT5651_M_ZCD_RM_L (0x1 << 5)
1946
+
#define RT5651_M_ZCD_RM_R (0x1 << 4)
1947
+
#define RT5651_SV_DLY_MASK (0xf)
1948
+
#define RT5651_SV_DLY_SFT 0
1949
+
1950
+
/* Soft volume and zero cross control 2 (0xda) */
1951
+
#define RT5651_ZCD_HP_MASK (0x1 << 15)
1952
+
#define RT5651_ZCD_HP_SFT 15
1953
+
#define RT5651_ZCD_HP_DIS (0x0 << 15)
1954
+
#define RT5651_ZCD_HP_EN (0x1 << 15)
1955
+
1956
+
/* Digital Misc Control (0xfa) */
1957
+
#define RT5651_I2S2_MS_SP_MASK (0x1 << 8)
1958
+
#define RT5651_I2S2_MS_SP_SEL 8
1959
+
#define RT5651_I2S2_MS_SP_64 (0x0 << 8)
1960
+
#define RT5651_I2S2_MS_SP_50 (0x1 << 8)
1961
+
#define RT5651_CLK_DET_EN (0x1 << 3)
1962
+
#define RT5651_CLK_DET_EN_SFT 3
1963
+
#define RT5651_AMP_DET_EN (0x1 << 1)
1964
+
#define RT5651_AMP_DET_EN_SFT 1
1965
+
#define RT5651_D_GATE_EN (0x1)
1966
+
#define RT5651_D_GATE_EN_SFT 0
1967
+
1968
+
/* Codec Private Register definition */
1969
+
/* 3D Speaker Control (0x63) */
1970
+
#define RT5651_3D_SPK_MASK (0x1 << 15)
1971
+
#define RT5651_3D_SPK_SFT 15
1972
+
#define RT5651_3D_SPK_DIS (0x0 << 15)
1973
+
#define RT5651_3D_SPK_EN (0x1 << 15)
1974
+
#define RT5651_3D_SPK_M_MASK (0x3 << 13)
1975
+
#define RT5651_3D_SPK_M_SFT 13
1976
+
#define RT5651_3D_SPK_CG_MASK (0x1f << 8)
1977
+
#define RT5651_3D_SPK_CG_SFT 8
1978
+
#define RT5651_3D_SPK_SG_MASK (0x1f)
1979
+
#define RT5651_3D_SPK_SG_SFT 0
1980
+
1981
+
/* Wind Noise Detection Control 1 (0x6c) */
1982
+
#define RT5651_WND_MASK (0x1 << 15)
1983
+
#define RT5651_WND_SFT 15
1984
+
#define RT5651_WND_DIS (0x0 << 15)
1985
+
#define RT5651_WND_EN (0x1 << 15)
1986
+
1987
+
/* Wind Noise Detection Control 2 (0x6d) */
1988
+
#define RT5651_WND_FC_NW_MASK (0x3f << 10)
1989
+
#define RT5651_WND_FC_NW_SFT 10
1990
+
#define RT5651_WND_FC_WK_MASK (0x3f << 4)
1991
+
#define RT5651_WND_FC_WK_SFT 4
1992
+
1993
+
/* Wind Noise Detection Control 3 (0x6e) */
1994
+
#define RT5651_HPF_FC_MASK (0x3f << 6)
1995
+
#define RT5651_HPF_FC_SFT 6
1996
+
#define RT5651_WND_FC_ST_MASK (0x3f)
1997
+
#define RT5651_WND_FC_ST_SFT 0
1998
+
1999
+
/* Wind Noise Detection Control 4 (0x6f) */
2000
+
#define RT5651_WND_TH_LO_MASK (0x3ff)
2001
+
#define RT5651_WND_TH_LO_SFT 0
2002
+
2003
+
/* Wind Noise Detection Control 5 (0x70) */
2004
+
#define RT5651_WND_TH_HI_MASK (0x3ff)
2005
+
#define RT5651_WND_TH_HI_SFT 0
2006
+
2007
+
/* Wind Noise Detection Control 8 (0x73) */
2008
+
#define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2009
+
#define RT5651_WND_WIND_SFT 13
2010
+
#define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2011
+
#define RT5651_WND_STRONG_SFT 12
2012
+
enum {
2013
+
RT5651_NO_WIND,
2014
+
RT5651_BREEZE,
2015
+
RT5651_STORM,
2016
+
};
2017
+
2018
+
/* Dipole Speaker Interface (0x75) */
2019
+
#define RT5651_DP_ATT_MASK (0x3 << 14)
2020
+
#define RT5651_DP_ATT_SFT 14
2021
+
#define RT5651_DP_SPK_MASK (0x1 << 10)
2022
+
#define RT5651_DP_SPK_SFT 10
2023
+
#define RT5651_DP_SPK_DIS (0x0 << 10)
2024
+
#define RT5651_DP_SPK_EN (0x1 << 10)
2025
+
2026
+
/* EQ Pre Volume Control (0xb3) */
2027
+
#define RT5651_EQ_PRE_VOL_MASK (0xffff)
2028
+
#define RT5651_EQ_PRE_VOL_SFT 0
2029
+
2030
+
/* EQ Post Volume Control (0xb4) */
2031
+
#define RT5651_EQ_PST_VOL_MASK (0xffff)
2032
+
#define RT5651_EQ_PST_VOL_SFT 0
2033
+
2034
+
/* System Clock Source */
2035
+
enum {
2036
+
RT5651_SCLK_S_MCLK,
2037
+
RT5651_SCLK_S_PLL1,
2038
+
RT5651_SCLK_S_RCCLK,
2039
+
};
2040
+
2041
+
/* PLL1 Source */
2042
+
enum {
2043
+
RT5651_PLL1_S_MCLK,
2044
+
RT5651_PLL1_S_BCLK1,
2045
+
RT5651_PLL1_S_BCLK2,
2046
+
};
2047
+
2048
+
enum {
2049
+
RT5651_AIF1,
2050
+
RT5651_AIF2,
2051
+
RT5651_AIFS,
2052
+
};
2053
+
2054
+
struct rt5651_pll_code {
2055
+
bool m_bp; /* Indicates bypass m code or not. */
2056
+
int m_code;
2057
+
int n_code;
2058
+
int k_code;
2059
+
};
2060
+
2061
+
struct rt5651_priv {
2062
+
struct snd_soc_codec *codec;
2063
+
struct rt5651_platform_data pdata;
2064
+
struct regmap *regmap;
2065
+
2066
+
int sysclk;
2067
+
int sysclk_src;
2068
+
int lrck[RT5651_AIFS];
2069
+
int bclk[RT5651_AIFS];
2070
+
int master[RT5651_AIFS];
2071
+
2072
+
struct rt5651_pll_code pll_code;
2073
+
int pll_src;
2074
+
int pll_in;
2075
+
int pll_out;
2076
+
2077
+
int dmic_en;
2078
+
bool hp_mute;
2079
+
};
2080
+
2081
+
#endif /* __RT5651_H__ */