tjh.dev
+11
drivers/i2c/busses/i2c-cadence.c
+11
drivers/i2c/busses/i2c-cadence.c
···
111
111
#define CDNS_I2C_DIVA_MAX 4
112
112
#define CDNS_I2C_DIVB_MAX 64
113
113
114
+
#define CDNS_I2C_TIMEOUT_MAX 0xFF
115
+
114
116
#define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
115
117
#define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
116
118
···
853
851
dev_err(&pdev->dev, "reg adap failed: %d\n", ret);
854
852
goto err_clk_dis;
855
853
}
854
+
855
+
/*
856
+
* Cadence I2C controller has a bug wherein it generates
857
+
* invalid read transaction after HW timeout in master receiver mode.
858
+
* HW timeout is not used by this driver and the interrupt is disabled.
859
+
* But the feature itself cannot be disabled. Hence maximum value
860
+
* is written to this register to reduce the chances of error.
861
+
*/
862
+
cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
856
863
857
864
dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
858
865
id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
+3
-5
drivers/i2c/busses/i2c-davinci.c
+3
-5
drivers/i2c/busses/i2c-davinci.c
···
407
407
if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
408
408
if (msg->flags & I2C_M_IGNORE_NAK)
409
409
return msg->len;
410
-
if (stop) {
411
-
w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
412
-
w |= DAVINCI_I2C_MDR_STP;
413
-
davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
414
-
}
410
+
w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
411
+
w |= DAVINCI_I2C_MDR_STP;
412
+
davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
415
413
return -EREMOTEIO;
416
414
}
417
415
return -EIO;