tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amd/display: rework macros for DWB register access

[Why]
A hack was used to access DWB register due to difference in the register
naming convention which was not compatible with existing SR/SRI* macros.
The additional macro needed were added to dwb ip specific header file
(dcnxx_dwb.h) instead of soc resource file (dcnxx_resource.c). Due to
this pattern, BASE macro had to be redefined in dcnxx_dwb.h, which in
turn needed us to undefine them in the resource file.

[How]
Add a separate macro for DWB access to the resource files that need it
instead of defining them in DWB ip header file. This will enable us to
reuse the BASE macro defined in the resource file.

Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Aurabindo Pillai and committed by
Alex Deucher 158858bf bcdc9158

+207 -250
+168 -195
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
··· 27 27 #define TO_DCN20_DWBC(dwbc_base) \ 28 28 container_of(dwbc_base, struct dcn20_dwbc, base) 29 29 30 - /* DCN */ 31 - #define BASE_INNER(seg) \ 32 - DCE_BASE__INST0_SEG ## seg 33 - 34 - #define BASE(seg) \ 35 - BASE_INNER(seg) 36 - 37 - #define SR(reg_name)\ 38 - .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 39 - mm ## reg_name 40 - 41 - #define SRI(reg_name, block, id)\ 42 - .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 43 - mm ## block ## id ## _ ## reg_name 44 - 45 - #define SRI2(reg_name, block, id)\ 46 - .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 47 - mm ## reg_name 48 - 49 - #define SRII(reg_name, block, id)\ 50 - .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 51 - mm ## block ## id ## _ ## reg_name 52 - 53 - #define SF(reg_name, field_name, post_fix)\ 54 - .field_name = reg_name ## __ ## field_name ## post_fix 55 - 56 - 57 30 #define DWBC_COMMON_REG_LIST_DCN2_0(inst) \ 58 - SRI2(WB_ENABLE, CNV, inst),\ 59 - SRI2(WB_EC_CONFIG, CNV, inst),\ 60 - SRI2(CNV_MODE, CNV, inst),\ 61 - SRI2(CNV_WINDOW_START, CNV, inst),\ 62 - SRI2(CNV_WINDOW_SIZE, CNV, inst),\ 63 - SRI2(CNV_UPDATE, CNV, inst),\ 64 - SRI2(CNV_SOURCE_SIZE, CNV, inst),\ 65 - SRI2(CNV_TEST_CNTL, CNV, inst),\ 66 - SRI2(CNV_TEST_CRC_RED, CNV, inst),\ 67 - SRI2(CNV_TEST_CRC_GREEN, CNV, inst),\ 68 - SRI2(CNV_TEST_CRC_BLUE, CNV, inst),\ 69 - SRI2(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\ 70 - SRI2(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\ 71 - SRI2(WBSCL_MODE, WBSCL, inst),\ 72 - SRI2(WBSCL_TAP_CONTROL, WBSCL, inst),\ 73 - SRI2(WBSCL_DEST_SIZE, WBSCL, inst),\ 74 - SRI2(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\ 75 - SRI2(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\ 76 - SRI2(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\ 77 - SRI2(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\ 78 - SRI2(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\ 79 - SRI2(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\ 80 - SRI2(WBSCL_ROUND_OFFSET, WBSCL, inst),\ 81 - SRI2(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\ 82 - SRI2(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\ 83 - SRI2(WBSCL_TEST_CNTL, WBSCL, inst),\ 84 - SRI2(WBSCL_TEST_CRC_RED, WBSCL, inst),\ 85 - SRI2(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\ 86 - SRI2(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\ 87 - SRI2(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\ 88 - SRI2(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\ 89 - SRI2(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\ 90 - SRI2(WBSCL_CLAMP_CBCR, WBSCL, inst),\ 91 - SRI2(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\ 92 - SRI2(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\ 93 - SRI2(WBSCL_DEBUG, WBSCL, inst),\ 94 - SRI2(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\ 95 - SRI2(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\ 96 - SRI2(WB_DEBUG_CTRL, CNV, inst),\ 97 - SRI2(WB_DBG_MODE, CNV, inst),\ 98 - SRI2(WB_HW_DEBUG, CNV, inst),\ 99 - SRI2(CNV_TEST_DEBUG_INDEX, CNV, inst),\ 100 - SRI2(CNV_TEST_DEBUG_DATA, CNV, inst),\ 101 - SRI2(WB_SOFT_RESET, CNV, inst),\ 102 - SRI2(WB_WARM_UP_MODE_CTL1, CNV, inst),\ 103 - SRI2(WB_WARM_UP_MODE_CTL2, CNV, inst) 31 + SRI2_DWB(WB_ENABLE, CNV, inst),\ 32 + SRI2_DWB(WB_EC_CONFIG, CNV, inst),\ 33 + SRI2_DWB(CNV_MODE, CNV, inst),\ 34 + SRI2_DWB(CNV_WINDOW_START, CNV, inst),\ 35 + SRI2_DWB(CNV_WINDOW_SIZE, CNV, inst),\ 36 + SRI2_DWB(CNV_UPDATE, CNV, inst),\ 37 + SRI2_DWB(CNV_SOURCE_SIZE, CNV, inst),\ 38 + SRI2_DWB(CNV_TEST_CNTL, CNV, inst),\ 39 + SRI2_DWB(CNV_TEST_CRC_RED, CNV, inst),\ 40 + SRI2_DWB(CNV_TEST_CRC_GREEN, CNV, inst),\ 41 + SRI2_DWB(CNV_TEST_CRC_BLUE, CNV, inst),\ 42 + SRI2_DWB(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\ 43 + SRI2_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\ 44 + SRI2_DWB(WBSCL_MODE, WBSCL, inst),\ 45 + SRI2_DWB(WBSCL_TAP_CONTROL, WBSCL, inst),\ 46 + SRI2_DWB(WBSCL_DEST_SIZE, WBSCL, inst),\ 47 + SRI2_DWB(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\ 48 + SRI2_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\ 49 + SRI2_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\ 50 + SRI2_DWB(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\ 51 + SRI2_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\ 52 + SRI2_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\ 53 + SRI2_DWB(WBSCL_ROUND_OFFSET, WBSCL, inst),\ 54 + SRI2_DWB(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\ 55 + SRI2_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\ 56 + SRI2_DWB(WBSCL_TEST_CNTL, WBSCL, inst),\ 57 + SRI2_DWB(WBSCL_TEST_CRC_RED, WBSCL, inst),\ 58 + SRI2_DWB(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\ 59 + SRI2_DWB(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\ 60 + SRI2_DWB(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\ 61 + SRI2_DWB(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\ 62 + SRI2_DWB(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\ 63 + SRI2_DWB(WBSCL_CLAMP_CBCR, WBSCL, inst),\ 64 + SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\ 65 + SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\ 66 + SRI2_DWB(WBSCL_DEBUG, WBSCL, inst),\ 67 + SRI2_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\ 68 + SRI2_DWB(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\ 69 + SRI2_DWB(WB_DEBUG_CTRL, CNV, inst),\ 70 + SRI2_DWB(WB_DBG_MODE, CNV, inst),\ 71 + SRI2_DWB(WB_HW_DEBUG, CNV, inst),\ 72 + SRI2_DWB(CNV_TEST_DEBUG_INDEX, CNV, inst),\ 73 + SRI2_DWB(CNV_TEST_DEBUG_DATA, CNV, inst),\ 74 + SRI2_DWB(WB_SOFT_RESET, CNV, inst),\ 75 + SRI2_DWB(WB_WARM_UP_MODE_CTL1, CNV, inst),\ 76 + SRI2_DWB(WB_WARM_UP_MODE_CTL2, CNV, inst) 104 77 105 78 #define DWBC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \ 106 - SF(WB_ENABLE, WB_ENABLE, mask_sh),\ 107 - SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\ 108 - SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\ 109 - SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\ 110 - SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\ 111 - SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\ 112 - SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\ 113 - SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\ 114 - SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\ 115 - SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\ 116 - SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\ 117 - SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\ 118 - SF(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\ 119 - SF(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\ 120 - SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\ 121 - SF(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\ 122 - SF(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\ 123 - SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\ 124 - SF(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\ 125 - SF(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\ 126 - SF(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\ 127 - SF(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\ 128 - SF(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\ 129 - SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\ 130 - SF(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\ 131 - SF(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\ 132 - SF(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\ 133 - SF(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\ 134 - SF(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\ 135 - SF(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\ 136 - SF(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\ 137 - SF(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\ 138 - SF(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\ 139 - SF(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\ 140 - SF(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\ 141 - SF(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\ 142 - SF(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\ 143 - SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\ 144 - SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\ 145 - SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\ 146 - SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\ 147 - SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\ 148 - SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\ 149 - SF(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\ 150 - SF(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\ 151 - SF(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\ 152 - SF(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\ 153 - SF(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\ 154 - SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\ 155 - SF(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\ 156 - SF(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\ 157 - SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\ 158 - SF(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\ 159 - SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\ 160 - SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\ 161 - SF(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\ 162 - SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\ 163 - SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\ 164 - SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\ 165 - SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\ 166 - SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\ 167 - SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\ 168 - SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\ 169 - SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\ 170 - SF(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\ 171 - SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\ 172 - SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\ 173 - SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\ 174 - SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\ 175 - SF(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\ 176 - SF(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\ 177 - SF(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\ 178 - SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\ 179 - SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\ 180 - SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\ 181 - SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\ 182 - SF(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\ 183 - SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\ 184 - SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\ 185 - SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\ 186 - SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\ 187 - SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\ 188 - SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\ 189 - SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\ 190 - SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\ 191 - SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\ 192 - SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\ 193 - SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\ 194 - SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\ 195 - SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\ 196 - SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\ 197 - SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\ 198 - SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\ 199 - SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\ 200 - SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\ 201 - SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\ 202 - SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\ 203 - SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\ 204 - SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\ 205 - SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\ 206 - SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\ 207 - SF(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\ 208 - SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\ 209 - SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\ 210 - SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\ 211 - SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\ 212 - SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\ 213 - SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\ 214 - SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\ 215 - SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\ 216 - SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\ 217 - SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\ 218 - SF(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\ 219 - SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\ 220 - SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\ 221 - SF(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\ 222 - SF(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\ 223 - SF(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\ 224 - SF(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\ 225 - SF(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\ 226 - SF(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\ 227 - SF(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh) 79 + SF_DWB(WB_ENABLE, WB_ENABLE, mask_sh),\ 80 + SF_DWB(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\ 81 + SF_DWB(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\ 82 + SF_DWB(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\ 83 + SF_DWB(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\ 84 + SF_DWB(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\ 85 + SF_DWB(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\ 86 + SF_DWB(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\ 87 + SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\ 88 + SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\ 89 + SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\ 90 + SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\ 91 + SF_DWB(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\ 92 + SF_DWB(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\ 93 + SF_DWB(CNV_MODE, CNV_OUT_BPC, mask_sh),\ 94 + SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\ 95 + SF_DWB(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\ 96 + SF_DWB(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\ 97 + SF_DWB(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\ 98 + SF_DWB(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\ 99 + SF_DWB(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\ 100 + SF_DWB(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\ 101 + SF_DWB(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\ 102 + SF_DWB(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\ 103 + SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\ 104 + SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\ 105 + SF_DWB(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\ 106 + SF_DWB(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\ 107 + SF_DWB(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\ 108 + SF_DWB(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\ 109 + SF_DWB(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\ 110 + SF_DWB(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\ 111 + SF_DWB(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\ 112 + SF_DWB(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\ 113 + SF_DWB(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\ 114 + SF_DWB(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\ 115 + SF_DWB(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\ 116 + SF_DWB(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\ 117 + SF_DWB(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\ 118 + SF_DWB(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\ 119 + SF_DWB(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\ 120 + SF_DWB(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\ 121 + SF_DWB(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\ 122 + SF_DWB(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\ 123 + SF_DWB(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\ 124 + SF_DWB(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\ 125 + SF_DWB(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\ 126 + SF_DWB(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\ 127 + SF_DWB(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\ 128 + SF_DWB(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\ 129 + SF_DWB(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\ 130 + SF_DWB(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\ 131 + SF_DWB(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\ 132 + SF_DWB(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\ 133 + SF_DWB(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\ 134 + SF_DWB(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\ 135 + SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\ 136 + SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\ 137 + SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\ 138 + SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\ 139 + SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\ 140 + SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\ 141 + SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\ 142 + SF_DWB(WBSCL_MODE, WBSCL_MODE, mask_sh),\ 143 + SF_DWB(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\ 144 + SF_DWB(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\ 145 + SF_DWB(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\ 146 + SF_DWB(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\ 147 + SF_DWB(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\ 148 + SF_DWB(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\ 149 + SF_DWB(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\ 150 + SF_DWB(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\ 151 + SF_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\ 152 + SF_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\ 153 + SF_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\ 154 + SF_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\ 155 + SF_DWB(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\ 156 + SF_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\ 157 + SF_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\ 158 + SF_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\ 159 + SF_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\ 160 + SF_DWB(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\ 161 + SF_DWB(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\ 162 + SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\ 163 + SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\ 164 + SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\ 165 + SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\ 166 + SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\ 167 + SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\ 168 + SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\ 169 + SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\ 170 + SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\ 171 + SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\ 172 + SF_DWB(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\ 173 + SF_DWB(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\ 174 + SF_DWB(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\ 175 + SF_DWB(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\ 176 + SF_DWB(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\ 177 + SF_DWB(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\ 178 + SF_DWB(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\ 179 + SF_DWB(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\ 180 + SF_DWB(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\ 181 + SF_DWB(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\ 182 + SF_DWB(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\ 183 + SF_DWB(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\ 184 + SF_DWB(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\ 185 + SF_DWB(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\ 186 + SF_DWB(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\ 187 + SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\ 188 + SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\ 189 + SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\ 190 + SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\ 191 + SF_DWB(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\ 192 + SF_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\ 193 + SF_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\ 194 + SF_DWB(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\ 195 + SF_DWB(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\ 196 + SF_DWB(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\ 197 + SF_DWB(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\ 198 + SF_DWB(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\ 199 + SF_DWB(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\ 200 + SF_DWB(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh) 228 201 229 202 #define DWBC_REG_FIELD_LIST_DCN2_0(type) \ 230 203 type WB_ENABLE;\
-7
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h
··· 29 29 #define TO_DCN20_MMHUBBUB(mcif_wb_base) \ 30 30 container_of(mcif_wb_base, struct dcn20_mmhubbub, base) 31 31 32 - /* DCN */ 33 - #define BASE_INNER(seg) \ 34 - DCE_BASE__INST0_SEG ## seg 35 - 36 - #define BASE(seg) \ 37 - BASE_INNER(seg) 38 - 39 32 #define MCIF_WB_COMMON_REG_LIST_DCN2_0(inst) \ 40 33 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\ 41 34 SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\
+9 -2
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
··· 124 124 * macros to expend register list macro defined in HW object header file */ 125 125 126 126 /* DCN */ 127 - /* TODO awful hack. fixup dcn20_dwb.h */ 128 - #undef BASE_INNER 129 127 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 130 128 131 129 #define BASE(seg) BASE_INNER(seg) ··· 135 137 #define SRI(reg_name, block, id)\ 136 138 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 137 139 mm ## block ## id ## _ ## reg_name 140 + 141 + #define SRI2_DWB(reg_name, block, id)\ 142 + .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 143 + mm ## reg_name 144 + #define SF_DWB(reg_name, field_name, post_fix)\ 145 + .field_name = reg_name ## __ ## field_name ## post_fix 146 + 147 + #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 148 + .field_name = reg_name ## __ ## field_name ## post_fix 138 149 139 150 #define SRIR(var_name, reg_name, block, id)\ 140 151 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-6
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h
··· 28 28 29 29 #include "vmid.h" 30 30 31 - #define BASE_INNER(seg) \ 32 - DCE_BASE__INST0_SEG ## seg 33 - 34 - #define BASE(seg) \ 35 - BASE_INNER(seg) 36 - 37 31 #define DCN20_VMID_REG_LIST(id)\ 38 32 SRI(CNTL, DCN_VM_CONTEXT, id),\ 39 33 SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\
-2
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
··· 94 94 * macros to expend register list macro defined in HW object header file */ 95 95 96 96 /* DCN */ 97 - /* TODO awful hack. fixup dcn20_dwb.h */ 98 - #undef BASE_INNER 99 97 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 100 98 101 99 #define BASE(seg) BASE_INNER(seg)
-15
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h
··· 27 27 #define TO_DCN30_DWBC(dwbc_base) \ 28 28 container_of(dwbc_base, struct dcn30_dwbc, base) 29 29 30 - /* DCN */ 31 - #define BASE_INNER(seg) \ 32 - DCE_BASE__INST0_SEG ## seg 33 - 34 - #define BASE(seg) \ 35 - BASE_INNER(seg) 36 - 37 - #define SF_DWB(reg_name, block, id, field_name, post_fix)\ 38 - .field_name = block ## id ## _ ## reg_name ## __ ## field_name ## post_fix 39 - 40 - /* set field name */ 41 - #define SF_DWB2(reg_name, block, id, field_name, post_fix)\ 42 - .field_name = reg_name ## __ ## field_name ## post_fix 43 - 44 - 45 30 #define DWBC_COMMON_REG_LIST_DCN30(inst) \ 46 31 SR(DWB_ENABLE_CLK_CTRL),\ 47 32 SR(DWB_MEM_PWR_CTRL),\
-7
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
··· 31 31 #define TO_DCN30_MMHUBBUB(mcif_wb_base) \ 32 32 container_of(mcif_wb_base, struct dcn30_mmhubbub, base) 33 33 34 - /* DCN */ 35 - #define BASE_INNER(seg) \ 36 - DCE_BASE__INST0_SEG ## seg 37 - 38 - #define BASE(seg) \ 39 - BASE_INNER(seg) 40 - 41 34 #define MCIF_WB_COMMON_REG_LIST_DCN3_0(inst) \ 42 35 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\ 43 36 SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
+3 -2
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
··· 108 108 */ 109 109 110 110 /* DCN */ 111 - /* TODO awful hack. fixup dcn20_dwb.h */ 112 - #undef BASE_INNER 113 111 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 114 112 115 113 #define BASE(seg) BASE_INNER(seg) ··· 139 141 #define SRII_DWB(reg_name, temp_name, block, id)\ 140 142 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 141 143 mm ## block ## id ## _ ## temp_name 144 + 145 + #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 146 + .field_name = reg_name ## __ ## field_name ## post_fix 142 147 143 148 #define DCCG_SRII(reg_name, block, id)\ 144 149 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+3 -2
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
··· 107 107 */ 108 108 109 109 /* DCN */ 110 - /* TODO awful hack. fixup dcn20_dwb.h */ 111 - #undef BASE_INNER 112 110 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 113 111 114 112 #define BASE(seg) BASE_INNER(seg) ··· 143 145 #define SRII_DWB(reg_name, temp_name, block, id)\ 144 146 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 145 147 mm ## block ## id ## _ ## temp_name 148 + 149 + #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 150 + .field_name = reg_name ## __ ## field_name ## post_fix 146 151 147 152 #define DCCG_SRII(reg_name, block, id)\ 148 153 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+3 -1
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
··· 183 183 mm ## reg_name 184 184 185 185 /* DCN */ 186 - #undef BASE_INNER 187 186 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 188 187 189 188 #define BASE(seg) BASE_INNER(seg) ··· 214 215 #define SRII_DWB(reg_name, temp_name, block, id)\ 215 216 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 216 217 mm ## block ## id ## _ ## temp_name 218 + 219 + #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 220 + .field_name = reg_name ## __ ## field_name ## post_fix 217 221 218 222 #define SRII_MPC_RMU(reg_name, block, id)\ 219 223 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+3 -1
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
··· 162 162 mm ## reg_name 163 163 164 164 /* DCN */ 165 - #undef BASE_INNER 166 165 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 167 166 168 167 #define BASE(seg) BASE_INNER(seg) ··· 193 194 #define SRII_DWB(reg_name, temp_name, block, id)\ 194 195 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 195 196 mm ## block ## id ## _ ## temp_name 197 + 198 + #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 199 + .field_name = reg_name ## __ ## field_name ## post_fix 196 200 197 201 #define SRII_MPC_RMU(reg_name, block, id)\ 198 202 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+3 -2
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
··· 119 119 */ 120 120 121 121 /* DCN */ 122 - /* TODO awful hack. fixup dcn20_dwb.h */ 123 - #undef BASE_INNER 124 122 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 125 123 126 124 #define BASE(seg) BASE_INNER(seg) ··· 150 152 #define SRII_DWB(reg_name, temp_name, block, id)\ 151 153 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 152 154 reg ## block ## id ## _ ## temp_name 155 + 156 + #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 157 + .field_name = reg_name ## __ ## field_name ## post_fix 153 158 154 159 #define DCCG_SRII(reg_name, block, id)\ 155 160 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+3
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
··· 184 184 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 185 185 reg ## block ## id ## _ ## temp_name 186 186 187 + #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 188 + .field_name = reg_name ## __ ## field_name ## post_fix 189 + 187 190 #define DCCG_SRII(reg_name, block, id)\ 188 191 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 189 192 reg ## block ## id ## _ ## reg_name
+3 -2
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
··· 151 151 */ 152 152 153 153 /* DCN */ 154 - /* TODO awful hack. fixup dcn20_dwb.h */ 155 - #undef BASE_INNER 156 154 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 157 155 158 156 #define BASE(seg) BASE_INNER(seg) ··· 182 184 #define SRII_DWB(reg_name, temp_name, block, id)\ 183 185 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 184 186 reg ## block ## id ## _ ## temp_name 187 + 188 + #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 189 + .field_name = reg_name ## __ ## field_name ## post_fix 185 190 186 191 #define DCCG_SRII(reg_name, block, id)\ 187 192 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+3 -2
drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
··· 142 142 */ 143 143 144 144 /* DCN */ 145 - /* TODO awful hack. fixup dcn20_dwb.h */ 146 - #undef BASE_INNER 147 145 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 148 146 149 147 #define BASE(seg) BASE_INNER(seg) ··· 173 175 #define SRII_DWB(reg_name, temp_name, block, id)\ 174 176 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 175 177 reg ## block ## id ## _ ## temp_name 178 + 179 + #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 180 + .field_name = reg_name ## __ ## field_name ## post_fix 176 181 177 182 #define DCCG_SRII(reg_name, block, id)\ 178 183 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+3 -2
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
··· 106 106 */ 107 107 108 108 /* DCN */ 109 - /* TODO awful hack. fixup dcn20_dwb.h */ 110 - #undef BASE_INNER 111 109 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 112 110 113 111 #define BASE(seg) BASE_INNER(seg) ··· 164 166 #define SRII_DWB(reg_name, temp_name, block, id)\ 165 167 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 166 168 reg ## block ## id ## _ ## temp_name 169 + 170 + #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 171 + .field_name = reg_name ## __ ## field_name ## post_fix 167 172 168 173 #define DCCG_SRII(reg_name, block, id)\ 169 174 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+3 -2
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
··· 109 109 */ 110 110 111 111 /* DCN */ 112 - /* TODO awful hack. fixup dcn20_dwb.h */ 113 - #undef BASE_INNER 114 112 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 115 113 116 114 #define BASE(seg) BASE_INNER(seg) ··· 171 173 #define DCCG_SRII(reg_name, block, id)\ 172 174 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 173 175 reg ## block ## id ## _ ## reg_name 176 + 177 + #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 178 + .field_name = reg_name ## __ ## field_name ## post_fix 174 179 175 180 #define VUPDATE_SRII(reg_name, block, id)\ 176 181 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \