clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock

The pll0_vote clock definitely should have pll0 as a parent (instead of
pll8).

Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers")
Cc: [e-mail]
Reviewed-by: Neil Armstrong <[e-mail]>
Signed-off-by: Dmitry Baryshkov <[e-mail]>
Reviewed-by: Konrad Dybcio <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]
Signed-off-by: Bjorn Andersson <[e-mail]>

drivers/clk/qcom/gcc-mdm9615.c

···
 	.enable_mask = BIT(0),
 	.hw.init = &(struct clk_init_data){
 		.name = "pll0_vote",
-		.parent_names = (const char *[]){ "pll8" },
+		.parent_names = (const char *[]){ "pll0" },
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},