Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge branch 'for-linus' of git://github.com/cmetcalf-tilera/linux-tile

* 'for-linus' of git://github.com/cmetcalf-tilera/linux-tile:
arch/tile: factor out <arch/opcode.h> header
arch/tile: add the <arch> headers to the set of installed kernel headers
arch/tile: avoid exporting a symbol no longer used by gcc
arch/tile: avoid ISO namespace pollution with <asm/sigcontext.h>

+4637 -4396
+17
arch/tile/include/arch/Kbuild
··· 1 + header-y += abi.h 2 + header-y += chip.h 3 + header-y += chip_tile64.h 4 + header-y += chip_tilegx.h 5 + header-y += chip_tilepro.h 6 + header-y += icache.h 7 + header-y += interrupts.h 8 + header-y += interrupts_32.h 9 + header-y += interrupts_64.h 10 + header-y += opcode.h 11 + header-y += opcode_tilegx.h 12 + header-y += opcode_tilepro.h 13 + header-y += sim.h 14 + header-y += sim_def.h 15 + header-y += spr_def.h 16 + header-y += spr_def_32.h 17 + header-y += spr_def_64.h
+72 -27
arch/tile/include/arch/abi.h
··· 15 15 /** 16 16 * @file 17 17 * 18 - * ABI-related register definitions helpful when writing assembly code. 18 + * ABI-related register definitions. 19 19 */ 20 20 21 21 #ifndef __ARCH_ABI_H__ 22 - #define __ARCH_ABI_H__ 23 22 24 - #include <arch/chip.h> 23 + #if !defined __need_int_reg_t && !defined __DOXYGEN__ 24 + # define __ARCH_ABI_H__ 25 + # include <arch/chip.h> 26 + #endif 27 + 28 + /* Provide the basic machine types. */ 29 + #ifndef __INT_REG_BITS 30 + 31 + /** Number of bits in a register. */ 32 + #if defined __tilegx__ 33 + # define __INT_REG_BITS 64 34 + #elif defined __tilepro__ 35 + # define __INT_REG_BITS 32 36 + #elif !defined __need_int_reg_t 37 + # include <arch/chip.h> 38 + # define __INT_REG_BITS CHIP_WORD_SIZE() 39 + #else 40 + # error Unrecognized architecture with __need_int_reg_t 41 + #endif 42 + 43 + #if __INT_REG_BITS == 64 44 + 45 + #ifndef __ASSEMBLER__ 46 + /** Unsigned type that can hold a register. */ 47 + typedef unsigned long long __uint_reg_t; 48 + 49 + /** Signed type that can hold a register. */ 50 + typedef long long __int_reg_t; 51 + #endif 52 + 53 + /** String prefix to use for printf(). */ 54 + #define __INT_REG_FMT "ll" 55 + 56 + #else 57 + 58 + #ifndef __ASSEMBLER__ 59 + /** Unsigned type that can hold a register. */ 60 + typedef unsigned long __uint_reg_t; 61 + 62 + /** Signed type that can hold a register. */ 63 + typedef long __int_reg_t; 64 + #endif 65 + 66 + /** String prefix to use for printf(). */ 67 + #define __INT_REG_FMT "l" 68 + 69 + #endif 70 + #endif /* __INT_REG_BITS */ 71 + 72 + 73 + #ifndef __need_int_reg_t 74 + 75 + 76 + #ifndef __ASSEMBLER__ 77 + /** Unsigned type that can hold a register. */ 78 + typedef __uint_reg_t uint_reg_t; 79 + 80 + /** Signed type that can hold a register. */ 81 + typedef __int_reg_t int_reg_t; 82 + #endif 83 + 84 + /** String prefix to use for printf(). */ 85 + #define INT_REG_FMT __INT_REG_FMT 86 + 87 + /** Number of bits in a register. */ 88 + #define INT_REG_BITS __INT_REG_BITS 89 + 25 90 26 91 /* Registers 0 - 55 are "normal", but some perform special roles. */ 27 92 ··· 124 59 * The ABI requires callers to allocate a caller state save area of 125 60 * this many bytes at the bottom of each stack frame. 126 61 */ 127 - #define C_ABI_SAVE_AREA_SIZE (2 * (CHIP_WORD_SIZE() / 8)) 62 + #define C_ABI_SAVE_AREA_SIZE (2 * (INT_REG_BITS / 8)) 128 63 129 64 /** 130 65 * The operand to an 'info' opcode directing the backtracer to not ··· 132 67 */ 133 68 #define INFO_OP_CANNOT_BACKTRACE 2 134 69 135 - #ifndef __ASSEMBLER__ 136 - #if CHIP_WORD_SIZE() > 32 137 70 138 - /** Unsigned type that can hold a register. */ 139 - typedef unsigned long long uint_reg_t; 71 + #endif /* !__need_int_reg_t */ 140 72 141 - /** Signed type that can hold a register. */ 142 - typedef long long int_reg_t; 143 - 144 - /** String prefix to use for printf(). */ 145 - #define INT_REG_FMT "ll" 146 - 147 - #elif !defined(__LP64__) /* avoid confusion with LP64 cross-build tools */ 148 - 149 - /** Unsigned type that can hold a register. */ 150 - typedef unsigned long uint_reg_t; 151 - 152 - /** Signed type that can hold a register. */ 153 - typedef long int_reg_t; 154 - 155 - /** String prefix to use for printf(). */ 156 - #define INT_REG_FMT "l" 157 - 158 - #endif 159 - #endif /* __ASSEMBLER__ */ 73 + /* Make sure we later can get all the definitions and declarations. */ 74 + #undef __need_int_reg_t 160 75 161 76 #endif /* !__ARCH_ABI_H__ */
+1471
arch/tile/include/arch/opcode_tilepro.h
··· 1 + /* TILEPro opcode information. 2 + * 3 + * Copyright 2011 Tilera Corporation. All Rights Reserved. 4 + * 5 + * This program is free software; you can redistribute it and/or 6 + * modify it under the terms of the GNU General Public License 7 + * as published by the Free Software Foundation, version 2. 8 + * 9 + * This program is distributed in the hope that it will be useful, but 10 + * WITHOUT ANY WARRANTY; without even the implied warranty of 11 + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 + * NON INFRINGEMENT. See the GNU General Public License for 13 + * more details. 14 + * 15 + * 16 + * 17 + * 18 + * 19 + */ 20 + 21 + #ifndef __ARCH_OPCODE_H__ 22 + #define __ARCH_OPCODE_H__ 23 + 24 + #ifndef __ASSEMBLER__ 25 + 26 + typedef unsigned long long tilepro_bundle_bits; 27 + 28 + /* This is the bit that determines if a bundle is in the Y encoding. */ 29 + #define TILEPRO_BUNDLE_Y_ENCODING_MASK ((tilepro_bundle_bits)1 << 63) 30 + 31 + enum 32 + { 33 + /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ 34 + TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE = 3, 35 + 36 + /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ 37 + TILEPRO_NUM_PIPELINE_ENCODINGS = 5, 38 + 39 + /* Log base 2 of TILEPRO_BUNDLE_SIZE_IN_BYTES. */ 40 + TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES = 3, 41 + 42 + /* Instructions take this many bytes. */ 43 + TILEPRO_BUNDLE_SIZE_IN_BYTES = 1 << TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES, 44 + 45 + /* Log base 2 of TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES. */ 46 + TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, 47 + 48 + /* Bundles should be aligned modulo this number of bytes. */ 49 + TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES = 50 + (1 << TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), 51 + 52 + /* Log base 2 of TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES. */ 53 + TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1, 54 + 55 + /* Static network instructions take this many bytes. */ 56 + TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES = 57 + (1 << TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES), 58 + 59 + /* Number of registers (some are magic, such as network I/O). */ 60 + TILEPRO_NUM_REGISTERS = 64, 61 + 62 + /* Number of static network registers. */ 63 + TILEPRO_NUM_SN_REGISTERS = 4 64 + }; 65 + 66 + /* Make a few "tile_" variables to simplify common code between 67 + architectures. */ 68 + 69 + typedef tilepro_bundle_bits tile_bundle_bits; 70 + #define TILE_BUNDLE_SIZE_IN_BYTES TILEPRO_BUNDLE_SIZE_IN_BYTES 71 + #define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES 72 + #define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \ 73 + TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES 74 + 75 + /* 64-bit pattern for a { bpt ; nop } bundle. */ 76 + #define TILEPRO_BPT_BUNDLE 0x400b3cae70166000ULL 77 + 78 + static __inline unsigned int 79 + get_BrOff_SN(tilepro_bundle_bits num) 80 + { 81 + const unsigned int n = (unsigned int)num; 82 + return (((n >> 0)) & 0x3ff); 83 + } 84 + 85 + static __inline unsigned int 86 + get_BrOff_X1(tilepro_bundle_bits n) 87 + { 88 + return (((unsigned int)(n >> 43)) & 0x00007fff) | 89 + (((unsigned int)(n >> 20)) & 0x00018000); 90 + } 91 + 92 + static __inline unsigned int 93 + get_BrType_X1(tilepro_bundle_bits n) 94 + { 95 + return (((unsigned int)(n >> 31)) & 0xf); 96 + } 97 + 98 + static __inline unsigned int 99 + get_Dest_Imm8_X1(tilepro_bundle_bits n) 100 + { 101 + return (((unsigned int)(n >> 31)) & 0x0000003f) | 102 + (((unsigned int)(n >> 43)) & 0x000000c0); 103 + } 104 + 105 + static __inline unsigned int 106 + get_Dest_SN(tilepro_bundle_bits num) 107 + { 108 + const unsigned int n = (unsigned int)num; 109 + return (((n >> 2)) & 0x3); 110 + } 111 + 112 + static __inline unsigned int 113 + get_Dest_X0(tilepro_bundle_bits num) 114 + { 115 + const unsigned int n = (unsigned int)num; 116 + return (((n >> 0)) & 0x3f); 117 + } 118 + 119 + static __inline unsigned int 120 + get_Dest_X1(tilepro_bundle_bits n) 121 + { 122 + return (((unsigned int)(n >> 31)) & 0x3f); 123 + } 124 + 125 + static __inline unsigned int 126 + get_Dest_Y0(tilepro_bundle_bits num) 127 + { 128 + const unsigned int n = (unsigned int)num; 129 + return (((n >> 0)) & 0x3f); 130 + } 131 + 132 + static __inline unsigned int 133 + get_Dest_Y1(tilepro_bundle_bits n) 134 + { 135 + return (((unsigned int)(n >> 31)) & 0x3f); 136 + } 137 + 138 + static __inline unsigned int 139 + get_Imm16_X0(tilepro_bundle_bits num) 140 + { 141 + const unsigned int n = (unsigned int)num; 142 + return (((n >> 12)) & 0xffff); 143 + } 144 + 145 + static __inline unsigned int 146 + get_Imm16_X1(tilepro_bundle_bits n) 147 + { 148 + return (((unsigned int)(n >> 43)) & 0xffff); 149 + } 150 + 151 + static __inline unsigned int 152 + get_Imm8_SN(tilepro_bundle_bits num) 153 + { 154 + const unsigned int n = (unsigned int)num; 155 + return (((n >> 0)) & 0xff); 156 + } 157 + 158 + static __inline unsigned int 159 + get_Imm8_X0(tilepro_bundle_bits num) 160 + { 161 + const unsigned int n = (unsigned int)num; 162 + return (((n >> 12)) & 0xff); 163 + } 164 + 165 + static __inline unsigned int 166 + get_Imm8_X1(tilepro_bundle_bits n) 167 + { 168 + return (((unsigned int)(n >> 43)) & 0xff); 169 + } 170 + 171 + static __inline unsigned int 172 + get_Imm8_Y0(tilepro_bundle_bits num) 173 + { 174 + const unsigned int n = (unsigned int)num; 175 + return (((n >> 12)) & 0xff); 176 + } 177 + 178 + static __inline unsigned int 179 + get_Imm8_Y1(tilepro_bundle_bits n) 180 + { 181 + return (((unsigned int)(n >> 43)) & 0xff); 182 + } 183 + 184 + static __inline unsigned int 185 + get_ImmOpcodeExtension_X0(tilepro_bundle_bits num) 186 + { 187 + const unsigned int n = (unsigned int)num; 188 + return (((n >> 20)) & 0x7f); 189 + } 190 + 191 + static __inline unsigned int 192 + get_ImmOpcodeExtension_X1(tilepro_bundle_bits n) 193 + { 194 + return (((unsigned int)(n >> 51)) & 0x7f); 195 + } 196 + 197 + static __inline unsigned int 198 + get_ImmRROpcodeExtension_SN(tilepro_bundle_bits num) 199 + { 200 + const unsigned int n = (unsigned int)num; 201 + return (((n >> 8)) & 0x3); 202 + } 203 + 204 + static __inline unsigned int 205 + get_JOffLong_X1(tilepro_bundle_bits n) 206 + { 207 + return (((unsigned int)(n >> 43)) & 0x00007fff) | 208 + (((unsigned int)(n >> 20)) & 0x00018000) | 209 + (((unsigned int)(n >> 14)) & 0x001e0000) | 210 + (((unsigned int)(n >> 16)) & 0x07e00000) | 211 + (((unsigned int)(n >> 31)) & 0x18000000); 212 + } 213 + 214 + static __inline unsigned int 215 + get_JOff_X1(tilepro_bundle_bits n) 216 + { 217 + return (((unsigned int)(n >> 43)) & 0x00007fff) | 218 + (((unsigned int)(n >> 20)) & 0x00018000) | 219 + (((unsigned int)(n >> 14)) & 0x001e0000) | 220 + (((unsigned int)(n >> 16)) & 0x07e00000) | 221 + (((unsigned int)(n >> 31)) & 0x08000000); 222 + } 223 + 224 + static __inline unsigned int 225 + get_MF_Imm15_X1(tilepro_bundle_bits n) 226 + { 227 + return (((unsigned int)(n >> 37)) & 0x00003fff) | 228 + (((unsigned int)(n >> 44)) & 0x00004000); 229 + } 230 + 231 + static __inline unsigned int 232 + get_MMEnd_X0(tilepro_bundle_bits num) 233 + { 234 + const unsigned int n = (unsigned int)num; 235 + return (((n >> 18)) & 0x1f); 236 + } 237 + 238 + static __inline unsigned int 239 + get_MMEnd_X1(tilepro_bundle_bits n) 240 + { 241 + return (((unsigned int)(n >> 49)) & 0x1f); 242 + } 243 + 244 + static __inline unsigned int 245 + get_MMStart_X0(tilepro_bundle_bits num) 246 + { 247 + const unsigned int n = (unsigned int)num; 248 + return (((n >> 23)) & 0x1f); 249 + } 250 + 251 + static __inline unsigned int 252 + get_MMStart_X1(tilepro_bundle_bits n) 253 + { 254 + return (((unsigned int)(n >> 54)) & 0x1f); 255 + } 256 + 257 + static __inline unsigned int 258 + get_MT_Imm15_X1(tilepro_bundle_bits n) 259 + { 260 + return (((unsigned int)(n >> 31)) & 0x0000003f) | 261 + (((unsigned int)(n >> 37)) & 0x00003fc0) | 262 + (((unsigned int)(n >> 44)) & 0x00004000); 263 + } 264 + 265 + static __inline unsigned int 266 + get_Mode(tilepro_bundle_bits n) 267 + { 268 + return (((unsigned int)(n >> 63)) & 0x1); 269 + } 270 + 271 + static __inline unsigned int 272 + get_NoRegOpcodeExtension_SN(tilepro_bundle_bits num) 273 + { 274 + const unsigned int n = (unsigned int)num; 275 + return (((n >> 0)) & 0xf); 276 + } 277 + 278 + static __inline unsigned int 279 + get_Opcode_SN(tilepro_bundle_bits num) 280 + { 281 + const unsigned int n = (unsigned int)num; 282 + return (((n >> 10)) & 0x3f); 283 + } 284 + 285 + static __inline unsigned int 286 + get_Opcode_X0(tilepro_bundle_bits num) 287 + { 288 + const unsigned int n = (unsigned int)num; 289 + return (((n >> 28)) & 0x7); 290 + } 291 + 292 + static __inline unsigned int 293 + get_Opcode_X1(tilepro_bundle_bits n) 294 + { 295 + return (((unsigned int)(n >> 59)) & 0xf); 296 + } 297 + 298 + static __inline unsigned int 299 + get_Opcode_Y0(tilepro_bundle_bits num) 300 + { 301 + const unsigned int n = (unsigned int)num; 302 + return (((n >> 27)) & 0xf); 303 + } 304 + 305 + static __inline unsigned int 306 + get_Opcode_Y1(tilepro_bundle_bits n) 307 + { 308 + return (((unsigned int)(n >> 59)) & 0xf); 309 + } 310 + 311 + static __inline unsigned int 312 + get_Opcode_Y2(tilepro_bundle_bits n) 313 + { 314 + return (((unsigned int)(n >> 56)) & 0x7); 315 + } 316 + 317 + static __inline unsigned int 318 + get_RROpcodeExtension_SN(tilepro_bundle_bits num) 319 + { 320 + const unsigned int n = (unsigned int)num; 321 + return (((n >> 4)) & 0xf); 322 + } 323 + 324 + static __inline unsigned int 325 + get_RRROpcodeExtension_X0(tilepro_bundle_bits num) 326 + { 327 + const unsigned int n = (unsigned int)num; 328 + return (((n >> 18)) & 0x1ff); 329 + } 330 + 331 + static __inline unsigned int 332 + get_RRROpcodeExtension_X1(tilepro_bundle_bits n) 333 + { 334 + return (((unsigned int)(n >> 49)) & 0x1ff); 335 + } 336 + 337 + static __inline unsigned int 338 + get_RRROpcodeExtension_Y0(tilepro_bundle_bits num) 339 + { 340 + const unsigned int n = (unsigned int)num; 341 + return (((n >> 18)) & 0x3); 342 + } 343 + 344 + static __inline unsigned int 345 + get_RRROpcodeExtension_Y1(tilepro_bundle_bits n) 346 + { 347 + return (((unsigned int)(n >> 49)) & 0x3); 348 + } 349 + 350 + static __inline unsigned int 351 + get_RouteOpcodeExtension_SN(tilepro_bundle_bits num) 352 + { 353 + const unsigned int n = (unsigned int)num; 354 + return (((n >> 0)) & 0x3ff); 355 + } 356 + 357 + static __inline unsigned int 358 + get_S_X0(tilepro_bundle_bits num) 359 + { 360 + const unsigned int n = (unsigned int)num; 361 + return (((n >> 27)) & 0x1); 362 + } 363 + 364 + static __inline unsigned int 365 + get_S_X1(tilepro_bundle_bits n) 366 + { 367 + return (((unsigned int)(n >> 58)) & 0x1); 368 + } 369 + 370 + static __inline unsigned int 371 + get_ShAmt_X0(tilepro_bundle_bits num) 372 + { 373 + const unsigned int n = (unsigned int)num; 374 + return (((n >> 12)) & 0x1f); 375 + } 376 + 377 + static __inline unsigned int 378 + get_ShAmt_X1(tilepro_bundle_bits n) 379 + { 380 + return (((unsigned int)(n >> 43)) & 0x1f); 381 + } 382 + 383 + static __inline unsigned int 384 + get_ShAmt_Y0(tilepro_bundle_bits num) 385 + { 386 + const unsigned int n = (unsigned int)num; 387 + return (((n >> 12)) & 0x1f); 388 + } 389 + 390 + static __inline unsigned int 391 + get_ShAmt_Y1(tilepro_bundle_bits n) 392 + { 393 + return (((unsigned int)(n >> 43)) & 0x1f); 394 + } 395 + 396 + static __inline unsigned int 397 + get_SrcA_X0(tilepro_bundle_bits num) 398 + { 399 + const unsigned int n = (unsigned int)num; 400 + return (((n >> 6)) & 0x3f); 401 + } 402 + 403 + static __inline unsigned int 404 + get_SrcA_X1(tilepro_bundle_bits n) 405 + { 406 + return (((unsigned int)(n >> 37)) & 0x3f); 407 + } 408 + 409 + static __inline unsigned int 410 + get_SrcA_Y0(tilepro_bundle_bits num) 411 + { 412 + const unsigned int n = (unsigned int)num; 413 + return (((n >> 6)) & 0x3f); 414 + } 415 + 416 + static __inline unsigned int 417 + get_SrcA_Y1(tilepro_bundle_bits n) 418 + { 419 + return (((unsigned int)(n >> 37)) & 0x3f); 420 + } 421 + 422 + static __inline unsigned int 423 + get_SrcA_Y2(tilepro_bundle_bits n) 424 + { 425 + return (((n >> 26)) & 0x00000001) | 426 + (((unsigned int)(n >> 50)) & 0x0000003e); 427 + } 428 + 429 + static __inline unsigned int 430 + get_SrcBDest_Y2(tilepro_bundle_bits num) 431 + { 432 + const unsigned int n = (unsigned int)num; 433 + return (((n >> 20)) & 0x3f); 434 + } 435 + 436 + static __inline unsigned int 437 + get_SrcB_X0(tilepro_bundle_bits num) 438 + { 439 + const unsigned int n = (unsigned int)num; 440 + return (((n >> 12)) & 0x3f); 441 + } 442 + 443 + static __inline unsigned int 444 + get_SrcB_X1(tilepro_bundle_bits n) 445 + { 446 + return (((unsigned int)(n >> 43)) & 0x3f); 447 + } 448 + 449 + static __inline unsigned int 450 + get_SrcB_Y0(tilepro_bundle_bits num) 451 + { 452 + const unsigned int n = (unsigned int)num; 453 + return (((n >> 12)) & 0x3f); 454 + } 455 + 456 + static __inline unsigned int 457 + get_SrcB_Y1(tilepro_bundle_bits n) 458 + { 459 + return (((unsigned int)(n >> 43)) & 0x3f); 460 + } 461 + 462 + static __inline unsigned int 463 + get_Src_SN(tilepro_bundle_bits num) 464 + { 465 + const unsigned int n = (unsigned int)num; 466 + return (((n >> 0)) & 0x3); 467 + } 468 + 469 + static __inline unsigned int 470 + get_UnOpcodeExtension_X0(tilepro_bundle_bits num) 471 + { 472 + const unsigned int n = (unsigned int)num; 473 + return (((n >> 12)) & 0x1f); 474 + } 475 + 476 + static __inline unsigned int 477 + get_UnOpcodeExtension_X1(tilepro_bundle_bits n) 478 + { 479 + return (((unsigned int)(n >> 43)) & 0x1f); 480 + } 481 + 482 + static __inline unsigned int 483 + get_UnOpcodeExtension_Y0(tilepro_bundle_bits num) 484 + { 485 + const unsigned int n = (unsigned int)num; 486 + return (((n >> 12)) & 0x1f); 487 + } 488 + 489 + static __inline unsigned int 490 + get_UnOpcodeExtension_Y1(tilepro_bundle_bits n) 491 + { 492 + return (((unsigned int)(n >> 43)) & 0x1f); 493 + } 494 + 495 + static __inline unsigned int 496 + get_UnShOpcodeExtension_X0(tilepro_bundle_bits num) 497 + { 498 + const unsigned int n = (unsigned int)num; 499 + return (((n >> 17)) & 0x3ff); 500 + } 501 + 502 + static __inline unsigned int 503 + get_UnShOpcodeExtension_X1(tilepro_bundle_bits n) 504 + { 505 + return (((unsigned int)(n >> 48)) & 0x3ff); 506 + } 507 + 508 + static __inline unsigned int 509 + get_UnShOpcodeExtension_Y0(tilepro_bundle_bits num) 510 + { 511 + const unsigned int n = (unsigned int)num; 512 + return (((n >> 17)) & 0x7); 513 + } 514 + 515 + static __inline unsigned int 516 + get_UnShOpcodeExtension_Y1(tilepro_bundle_bits n) 517 + { 518 + return (((unsigned int)(n >> 48)) & 0x7); 519 + } 520 + 521 + 522 + static __inline int 523 + sign_extend(int n, int num_bits) 524 + { 525 + int shift = (int)(sizeof(int) * 8 - num_bits); 526 + return (n << shift) >> shift; 527 + } 528 + 529 + 530 + 531 + static __inline tilepro_bundle_bits 532 + create_BrOff_SN(int num) 533 + { 534 + const unsigned int n = (unsigned int)num; 535 + return ((n & 0x3ff) << 0); 536 + } 537 + 538 + static __inline tilepro_bundle_bits 539 + create_BrOff_X1(int num) 540 + { 541 + const unsigned int n = (unsigned int)num; 542 + return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) | 543 + (((tilepro_bundle_bits)(n & 0x00018000)) << 20); 544 + } 545 + 546 + static __inline tilepro_bundle_bits 547 + create_BrType_X1(int num) 548 + { 549 + const unsigned int n = (unsigned int)num; 550 + return (((tilepro_bundle_bits)(n & 0xf)) << 31); 551 + } 552 + 553 + static __inline tilepro_bundle_bits 554 + create_Dest_Imm8_X1(int num) 555 + { 556 + const unsigned int n = (unsigned int)num; 557 + return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) | 558 + (((tilepro_bundle_bits)(n & 0x000000c0)) << 43); 559 + } 560 + 561 + static __inline tilepro_bundle_bits 562 + create_Dest_SN(int num) 563 + { 564 + const unsigned int n = (unsigned int)num; 565 + return ((n & 0x3) << 2); 566 + } 567 + 568 + static __inline tilepro_bundle_bits 569 + create_Dest_X0(int num) 570 + { 571 + const unsigned int n = (unsigned int)num; 572 + return ((n & 0x3f) << 0); 573 + } 574 + 575 + static __inline tilepro_bundle_bits 576 + create_Dest_X1(int num) 577 + { 578 + const unsigned int n = (unsigned int)num; 579 + return (((tilepro_bundle_bits)(n & 0x3f)) << 31); 580 + } 581 + 582 + static __inline tilepro_bundle_bits 583 + create_Dest_Y0(int num) 584 + { 585 + const unsigned int n = (unsigned int)num; 586 + return ((n & 0x3f) << 0); 587 + } 588 + 589 + static __inline tilepro_bundle_bits 590 + create_Dest_Y1(int num) 591 + { 592 + const unsigned int n = (unsigned int)num; 593 + return (((tilepro_bundle_bits)(n & 0x3f)) << 31); 594 + } 595 + 596 + static __inline tilepro_bundle_bits 597 + create_Imm16_X0(int num) 598 + { 599 + const unsigned int n = (unsigned int)num; 600 + return ((n & 0xffff) << 12); 601 + } 602 + 603 + static __inline tilepro_bundle_bits 604 + create_Imm16_X1(int num) 605 + { 606 + const unsigned int n = (unsigned int)num; 607 + return (((tilepro_bundle_bits)(n & 0xffff)) << 43); 608 + } 609 + 610 + static __inline tilepro_bundle_bits 611 + create_Imm8_SN(int num) 612 + { 613 + const unsigned int n = (unsigned int)num; 614 + return ((n & 0xff) << 0); 615 + } 616 + 617 + static __inline tilepro_bundle_bits 618 + create_Imm8_X0(int num) 619 + { 620 + const unsigned int n = (unsigned int)num; 621 + return ((n & 0xff) << 12); 622 + } 623 + 624 + static __inline tilepro_bundle_bits 625 + create_Imm8_X1(int num) 626 + { 627 + const unsigned int n = (unsigned int)num; 628 + return (((tilepro_bundle_bits)(n & 0xff)) << 43); 629 + } 630 + 631 + static __inline tilepro_bundle_bits 632 + create_Imm8_Y0(int num) 633 + { 634 + const unsigned int n = (unsigned int)num; 635 + return ((n & 0xff) << 12); 636 + } 637 + 638 + static __inline tilepro_bundle_bits 639 + create_Imm8_Y1(int num) 640 + { 641 + const unsigned int n = (unsigned int)num; 642 + return (((tilepro_bundle_bits)(n & 0xff)) << 43); 643 + } 644 + 645 + static __inline tilepro_bundle_bits 646 + create_ImmOpcodeExtension_X0(int num) 647 + { 648 + const unsigned int n = (unsigned int)num; 649 + return ((n & 0x7f) << 20); 650 + } 651 + 652 + static __inline tilepro_bundle_bits 653 + create_ImmOpcodeExtension_X1(int num) 654 + { 655 + const unsigned int n = (unsigned int)num; 656 + return (((tilepro_bundle_bits)(n & 0x7f)) << 51); 657 + } 658 + 659 + static __inline tilepro_bundle_bits 660 + create_ImmRROpcodeExtension_SN(int num) 661 + { 662 + const unsigned int n = (unsigned int)num; 663 + return ((n & 0x3) << 8); 664 + } 665 + 666 + static __inline tilepro_bundle_bits 667 + create_JOffLong_X1(int num) 668 + { 669 + const unsigned int n = (unsigned int)num; 670 + return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) | 671 + (((tilepro_bundle_bits)(n & 0x00018000)) << 20) | 672 + (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) | 673 + (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) | 674 + (((tilepro_bundle_bits)(n & 0x18000000)) << 31); 675 + } 676 + 677 + static __inline tilepro_bundle_bits 678 + create_JOff_X1(int num) 679 + { 680 + const unsigned int n = (unsigned int)num; 681 + return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) | 682 + (((tilepro_bundle_bits)(n & 0x00018000)) << 20) | 683 + (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) | 684 + (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) | 685 + (((tilepro_bundle_bits)(n & 0x08000000)) << 31); 686 + } 687 + 688 + static __inline tilepro_bundle_bits 689 + create_MF_Imm15_X1(int num) 690 + { 691 + const unsigned int n = (unsigned int)num; 692 + return (((tilepro_bundle_bits)(n & 0x00003fff)) << 37) | 693 + (((tilepro_bundle_bits)(n & 0x00004000)) << 44); 694 + } 695 + 696 + static __inline tilepro_bundle_bits 697 + create_MMEnd_X0(int num) 698 + { 699 + const unsigned int n = (unsigned int)num; 700 + return ((n & 0x1f) << 18); 701 + } 702 + 703 + static __inline tilepro_bundle_bits 704 + create_MMEnd_X1(int num) 705 + { 706 + const unsigned int n = (unsigned int)num; 707 + return (((tilepro_bundle_bits)(n & 0x1f)) << 49); 708 + } 709 + 710 + static __inline tilepro_bundle_bits 711 + create_MMStart_X0(int num) 712 + { 713 + const unsigned int n = (unsigned int)num; 714 + return ((n & 0x1f) << 23); 715 + } 716 + 717 + static __inline tilepro_bundle_bits 718 + create_MMStart_X1(int num) 719 + { 720 + const unsigned int n = (unsigned int)num; 721 + return (((tilepro_bundle_bits)(n & 0x1f)) << 54); 722 + } 723 + 724 + static __inline tilepro_bundle_bits 725 + create_MT_Imm15_X1(int num) 726 + { 727 + const unsigned int n = (unsigned int)num; 728 + return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) | 729 + (((tilepro_bundle_bits)(n & 0x00003fc0)) << 37) | 730 + (((tilepro_bundle_bits)(n & 0x00004000)) << 44); 731 + } 732 + 733 + static __inline tilepro_bundle_bits 734 + create_Mode(int num) 735 + { 736 + const unsigned int n = (unsigned int)num; 737 + return (((tilepro_bundle_bits)(n & 0x1)) << 63); 738 + } 739 + 740 + static __inline tilepro_bundle_bits 741 + create_NoRegOpcodeExtension_SN(int num) 742 + { 743 + const unsigned int n = (unsigned int)num; 744 + return ((n & 0xf) << 0); 745 + } 746 + 747 + static __inline tilepro_bundle_bits 748 + create_Opcode_SN(int num) 749 + { 750 + const unsigned int n = (unsigned int)num; 751 + return ((n & 0x3f) << 10); 752 + } 753 + 754 + static __inline tilepro_bundle_bits 755 + create_Opcode_X0(int num) 756 + { 757 + const unsigned int n = (unsigned int)num; 758 + return ((n & 0x7) << 28); 759 + } 760 + 761 + static __inline tilepro_bundle_bits 762 + create_Opcode_X1(int num) 763 + { 764 + const unsigned int n = (unsigned int)num; 765 + return (((tilepro_bundle_bits)(n & 0xf)) << 59); 766 + } 767 + 768 + static __inline tilepro_bundle_bits 769 + create_Opcode_Y0(int num) 770 + { 771 + const unsigned int n = (unsigned int)num; 772 + return ((n & 0xf) << 27); 773 + } 774 + 775 + static __inline tilepro_bundle_bits 776 + create_Opcode_Y1(int num) 777 + { 778 + const unsigned int n = (unsigned int)num; 779 + return (((tilepro_bundle_bits)(n & 0xf)) << 59); 780 + } 781 + 782 + static __inline tilepro_bundle_bits 783 + create_Opcode_Y2(int num) 784 + { 785 + const unsigned int n = (unsigned int)num; 786 + return (((tilepro_bundle_bits)(n & 0x7)) << 56); 787 + } 788 + 789 + static __inline tilepro_bundle_bits 790 + create_RROpcodeExtension_SN(int num) 791 + { 792 + const unsigned int n = (unsigned int)num; 793 + return ((n & 0xf) << 4); 794 + } 795 + 796 + static __inline tilepro_bundle_bits 797 + create_RRROpcodeExtension_X0(int num) 798 + { 799 + const unsigned int n = (unsigned int)num; 800 + return ((n & 0x1ff) << 18); 801 + } 802 + 803 + static __inline tilepro_bundle_bits 804 + create_RRROpcodeExtension_X1(int num) 805 + { 806 + const unsigned int n = (unsigned int)num; 807 + return (((tilepro_bundle_bits)(n & 0x1ff)) << 49); 808 + } 809 + 810 + static __inline tilepro_bundle_bits 811 + create_RRROpcodeExtension_Y0(int num) 812 + { 813 + const unsigned int n = (unsigned int)num; 814 + return ((n & 0x3) << 18); 815 + } 816 + 817 + static __inline tilepro_bundle_bits 818 + create_RRROpcodeExtension_Y1(int num) 819 + { 820 + const unsigned int n = (unsigned int)num; 821 + return (((tilepro_bundle_bits)(n & 0x3)) << 49); 822 + } 823 + 824 + static __inline tilepro_bundle_bits 825 + create_RouteOpcodeExtension_SN(int num) 826 + { 827 + const unsigned int n = (unsigned int)num; 828 + return ((n & 0x3ff) << 0); 829 + } 830 + 831 + static __inline tilepro_bundle_bits 832 + create_S_X0(int num) 833 + { 834 + const unsigned int n = (unsigned int)num; 835 + return ((n & 0x1) << 27); 836 + } 837 + 838 + static __inline tilepro_bundle_bits 839 + create_S_X1(int num) 840 + { 841 + const unsigned int n = (unsigned int)num; 842 + return (((tilepro_bundle_bits)(n & 0x1)) << 58); 843 + } 844 + 845 + static __inline tilepro_bundle_bits 846 + create_ShAmt_X0(int num) 847 + { 848 + const unsigned int n = (unsigned int)num; 849 + return ((n & 0x1f) << 12); 850 + } 851 + 852 + static __inline tilepro_bundle_bits 853 + create_ShAmt_X1(int num) 854 + { 855 + const unsigned int n = (unsigned int)num; 856 + return (((tilepro_bundle_bits)(n & 0x1f)) << 43); 857 + } 858 + 859 + static __inline tilepro_bundle_bits 860 + create_ShAmt_Y0(int num) 861 + { 862 + const unsigned int n = (unsigned int)num; 863 + return ((n & 0x1f) << 12); 864 + } 865 + 866 + static __inline tilepro_bundle_bits 867 + create_ShAmt_Y1(int num) 868 + { 869 + const unsigned int n = (unsigned int)num; 870 + return (((tilepro_bundle_bits)(n & 0x1f)) << 43); 871 + } 872 + 873 + static __inline tilepro_bundle_bits 874 + create_SrcA_X0(int num) 875 + { 876 + const unsigned int n = (unsigned int)num; 877 + return ((n & 0x3f) << 6); 878 + } 879 + 880 + static __inline tilepro_bundle_bits 881 + create_SrcA_X1(int num) 882 + { 883 + const unsigned int n = (unsigned int)num; 884 + return (((tilepro_bundle_bits)(n & 0x3f)) << 37); 885 + } 886 + 887 + static __inline tilepro_bundle_bits 888 + create_SrcA_Y0(int num) 889 + { 890 + const unsigned int n = (unsigned int)num; 891 + return ((n & 0x3f) << 6); 892 + } 893 + 894 + static __inline tilepro_bundle_bits 895 + create_SrcA_Y1(int num) 896 + { 897 + const unsigned int n = (unsigned int)num; 898 + return (((tilepro_bundle_bits)(n & 0x3f)) << 37); 899 + } 900 + 901 + static __inline tilepro_bundle_bits 902 + create_SrcA_Y2(int num) 903 + { 904 + const unsigned int n = (unsigned int)num; 905 + return ((n & 0x00000001) << 26) | 906 + (((tilepro_bundle_bits)(n & 0x0000003e)) << 50); 907 + } 908 + 909 + static __inline tilepro_bundle_bits 910 + create_SrcBDest_Y2(int num) 911 + { 912 + const unsigned int n = (unsigned int)num; 913 + return ((n & 0x3f) << 20); 914 + } 915 + 916 + static __inline tilepro_bundle_bits 917 + create_SrcB_X0(int num) 918 + { 919 + const unsigned int n = (unsigned int)num; 920 + return ((n & 0x3f) << 12); 921 + } 922 + 923 + static __inline tilepro_bundle_bits 924 + create_SrcB_X1(int num) 925 + { 926 + const unsigned int n = (unsigned int)num; 927 + return (((tilepro_bundle_bits)(n & 0x3f)) << 43); 928 + } 929 + 930 + static __inline tilepro_bundle_bits 931 + create_SrcB_Y0(int num) 932 + { 933 + const unsigned int n = (unsigned int)num; 934 + return ((n & 0x3f) << 12); 935 + } 936 + 937 + static __inline tilepro_bundle_bits 938 + create_SrcB_Y1(int num) 939 + { 940 + const unsigned int n = (unsigned int)num; 941 + return (((tilepro_bundle_bits)(n & 0x3f)) << 43); 942 + } 943 + 944 + static __inline tilepro_bundle_bits 945 + create_Src_SN(int num) 946 + { 947 + const unsigned int n = (unsigned int)num; 948 + return ((n & 0x3) << 0); 949 + } 950 + 951 + static __inline tilepro_bundle_bits 952 + create_UnOpcodeExtension_X0(int num) 953 + { 954 + const unsigned int n = (unsigned int)num; 955 + return ((n & 0x1f) << 12); 956 + } 957 + 958 + static __inline tilepro_bundle_bits 959 + create_UnOpcodeExtension_X1(int num) 960 + { 961 + const unsigned int n = (unsigned int)num; 962 + return (((tilepro_bundle_bits)(n & 0x1f)) << 43); 963 + } 964 + 965 + static __inline tilepro_bundle_bits 966 + create_UnOpcodeExtension_Y0(int num) 967 + { 968 + const unsigned int n = (unsigned int)num; 969 + return ((n & 0x1f) << 12); 970 + } 971 + 972 + static __inline tilepro_bundle_bits 973 + create_UnOpcodeExtension_Y1(int num) 974 + { 975 + const unsigned int n = (unsigned int)num; 976 + return (((tilepro_bundle_bits)(n & 0x1f)) << 43); 977 + } 978 + 979 + static __inline tilepro_bundle_bits 980 + create_UnShOpcodeExtension_X0(int num) 981 + { 982 + const unsigned int n = (unsigned int)num; 983 + return ((n & 0x3ff) << 17); 984 + } 985 + 986 + static __inline tilepro_bundle_bits 987 + create_UnShOpcodeExtension_X1(int num) 988 + { 989 + const unsigned int n = (unsigned int)num; 990 + return (((tilepro_bundle_bits)(n & 0x3ff)) << 48); 991 + } 992 + 993 + static __inline tilepro_bundle_bits 994 + create_UnShOpcodeExtension_Y0(int num) 995 + { 996 + const unsigned int n = (unsigned int)num; 997 + return ((n & 0x7) << 17); 998 + } 999 + 1000 + static __inline tilepro_bundle_bits 1001 + create_UnShOpcodeExtension_Y1(int num) 1002 + { 1003 + const unsigned int n = (unsigned int)num; 1004 + return (((tilepro_bundle_bits)(n & 0x7)) << 48); 1005 + } 1006 + 1007 + 1008 + enum 1009 + { 1010 + ADDBS_U_SPECIAL_0_OPCODE_X0 = 98, 1011 + ADDBS_U_SPECIAL_0_OPCODE_X1 = 68, 1012 + ADDB_SPECIAL_0_OPCODE_X0 = 1, 1013 + ADDB_SPECIAL_0_OPCODE_X1 = 1, 1014 + ADDHS_SPECIAL_0_OPCODE_X0 = 99, 1015 + ADDHS_SPECIAL_0_OPCODE_X1 = 69, 1016 + ADDH_SPECIAL_0_OPCODE_X0 = 2, 1017 + ADDH_SPECIAL_0_OPCODE_X1 = 2, 1018 + ADDIB_IMM_0_OPCODE_X0 = 1, 1019 + ADDIB_IMM_0_OPCODE_X1 = 1, 1020 + ADDIH_IMM_0_OPCODE_X0 = 2, 1021 + ADDIH_IMM_0_OPCODE_X1 = 2, 1022 + ADDI_IMM_0_OPCODE_X0 = 3, 1023 + ADDI_IMM_0_OPCODE_X1 = 3, 1024 + ADDI_IMM_1_OPCODE_SN = 1, 1025 + ADDI_OPCODE_Y0 = 9, 1026 + ADDI_OPCODE_Y1 = 7, 1027 + ADDLIS_OPCODE_X0 = 1, 1028 + ADDLIS_OPCODE_X1 = 2, 1029 + ADDLI_OPCODE_X0 = 2, 1030 + ADDLI_OPCODE_X1 = 3, 1031 + ADDS_SPECIAL_0_OPCODE_X0 = 96, 1032 + ADDS_SPECIAL_0_OPCODE_X1 = 66, 1033 + ADD_SPECIAL_0_OPCODE_X0 = 3, 1034 + ADD_SPECIAL_0_OPCODE_X1 = 3, 1035 + ADD_SPECIAL_0_OPCODE_Y0 = 0, 1036 + ADD_SPECIAL_0_OPCODE_Y1 = 0, 1037 + ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4, 1038 + ADIFFH_SPECIAL_0_OPCODE_X0 = 5, 1039 + ANDI_IMM_0_OPCODE_X0 = 1, 1040 + ANDI_IMM_0_OPCODE_X1 = 4, 1041 + ANDI_OPCODE_Y0 = 10, 1042 + ANDI_OPCODE_Y1 = 8, 1043 + AND_SPECIAL_0_OPCODE_X0 = 6, 1044 + AND_SPECIAL_0_OPCODE_X1 = 4, 1045 + AND_SPECIAL_2_OPCODE_Y0 = 0, 1046 + AND_SPECIAL_2_OPCODE_Y1 = 0, 1047 + AULI_OPCODE_X0 = 3, 1048 + AULI_OPCODE_X1 = 4, 1049 + AVGB_U_SPECIAL_0_OPCODE_X0 = 7, 1050 + AVGH_SPECIAL_0_OPCODE_X0 = 8, 1051 + BBNST_BRANCH_OPCODE_X1 = 15, 1052 + BBNS_BRANCH_OPCODE_X1 = 14, 1053 + BBNS_OPCODE_SN = 63, 1054 + BBST_BRANCH_OPCODE_X1 = 13, 1055 + BBS_BRANCH_OPCODE_X1 = 12, 1056 + BBS_OPCODE_SN = 62, 1057 + BGEZT_BRANCH_OPCODE_X1 = 7, 1058 + BGEZ_BRANCH_OPCODE_X1 = 6, 1059 + BGEZ_OPCODE_SN = 61, 1060 + BGZT_BRANCH_OPCODE_X1 = 5, 1061 + BGZ_BRANCH_OPCODE_X1 = 4, 1062 + BGZ_OPCODE_SN = 58, 1063 + BITX_UN_0_SHUN_0_OPCODE_X0 = 1, 1064 + BITX_UN_0_SHUN_0_OPCODE_Y0 = 1, 1065 + BLEZT_BRANCH_OPCODE_X1 = 11, 1066 + BLEZ_BRANCH_OPCODE_X1 = 10, 1067 + BLEZ_OPCODE_SN = 59, 1068 + BLZT_BRANCH_OPCODE_X1 = 9, 1069 + BLZ_BRANCH_OPCODE_X1 = 8, 1070 + BLZ_OPCODE_SN = 60, 1071 + BNZT_BRANCH_OPCODE_X1 = 3, 1072 + BNZ_BRANCH_OPCODE_X1 = 2, 1073 + BNZ_OPCODE_SN = 57, 1074 + BPT_NOREG_RR_IMM_0_OPCODE_SN = 1, 1075 + BRANCH_OPCODE_X1 = 5, 1076 + BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2, 1077 + BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2, 1078 + BZT_BRANCH_OPCODE_X1 = 1, 1079 + BZ_BRANCH_OPCODE_X1 = 0, 1080 + BZ_OPCODE_SN = 56, 1081 + CLZ_UN_0_SHUN_0_OPCODE_X0 = 3, 1082 + CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3, 1083 + CRC32_32_SPECIAL_0_OPCODE_X0 = 9, 1084 + CRC32_8_SPECIAL_0_OPCODE_X0 = 10, 1085 + CTZ_UN_0_SHUN_0_OPCODE_X0 = 4, 1086 + CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4, 1087 + DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1, 1088 + DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2, 1089 + DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95, 1090 + FINV_UN_0_SHUN_0_OPCODE_X1 = 3, 1091 + FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4, 1092 + FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3, 1093 + FNOP_UN_0_SHUN_0_OPCODE_X0 = 5, 1094 + FNOP_UN_0_SHUN_0_OPCODE_X1 = 5, 1095 + FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5, 1096 + FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1, 1097 + HALT_NOREG_RR_IMM_0_OPCODE_SN = 0, 1098 + ICOH_UN_0_SHUN_0_OPCODE_X1 = 6, 1099 + ILL_UN_0_SHUN_0_OPCODE_X1 = 7, 1100 + ILL_UN_0_SHUN_0_OPCODE_Y1 = 2, 1101 + IMM_0_OPCODE_SN = 0, 1102 + IMM_0_OPCODE_X0 = 4, 1103 + IMM_0_OPCODE_X1 = 6, 1104 + IMM_1_OPCODE_SN = 1, 1105 + IMM_OPCODE_0_X0 = 5, 1106 + INTHB_SPECIAL_0_OPCODE_X0 = 11, 1107 + INTHB_SPECIAL_0_OPCODE_X1 = 5, 1108 + INTHH_SPECIAL_0_OPCODE_X0 = 12, 1109 + INTHH_SPECIAL_0_OPCODE_X1 = 6, 1110 + INTLB_SPECIAL_0_OPCODE_X0 = 13, 1111 + INTLB_SPECIAL_0_OPCODE_X1 = 7, 1112 + INTLH_SPECIAL_0_OPCODE_X0 = 14, 1113 + INTLH_SPECIAL_0_OPCODE_X1 = 8, 1114 + INV_UN_0_SHUN_0_OPCODE_X1 = 8, 1115 + IRET_UN_0_SHUN_0_OPCODE_X1 = 9, 1116 + JALB_OPCODE_X1 = 13, 1117 + JALF_OPCODE_X1 = 12, 1118 + JALRP_SPECIAL_0_OPCODE_X1 = 9, 1119 + JALRR_IMM_1_OPCODE_SN = 3, 1120 + JALR_RR_IMM_0_OPCODE_SN = 5, 1121 + JALR_SPECIAL_0_OPCODE_X1 = 10, 1122 + JB_OPCODE_X1 = 11, 1123 + JF_OPCODE_X1 = 10, 1124 + JRP_SPECIAL_0_OPCODE_X1 = 11, 1125 + JRR_IMM_1_OPCODE_SN = 2, 1126 + JR_RR_IMM_0_OPCODE_SN = 4, 1127 + JR_SPECIAL_0_OPCODE_X1 = 12, 1128 + LBADD_IMM_0_OPCODE_X1 = 22, 1129 + LBADD_U_IMM_0_OPCODE_X1 = 23, 1130 + LB_OPCODE_Y2 = 0, 1131 + LB_UN_0_SHUN_0_OPCODE_X1 = 10, 1132 + LB_U_OPCODE_Y2 = 1, 1133 + LB_U_UN_0_SHUN_0_OPCODE_X1 = 11, 1134 + LHADD_IMM_0_OPCODE_X1 = 24, 1135 + LHADD_U_IMM_0_OPCODE_X1 = 25, 1136 + LH_OPCODE_Y2 = 2, 1137 + LH_UN_0_SHUN_0_OPCODE_X1 = 12, 1138 + LH_U_OPCODE_Y2 = 3, 1139 + LH_U_UN_0_SHUN_0_OPCODE_X1 = 13, 1140 + LNK_SPECIAL_0_OPCODE_X1 = 13, 1141 + LWADD_IMM_0_OPCODE_X1 = 26, 1142 + LWADD_NA_IMM_0_OPCODE_X1 = 27, 1143 + LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24, 1144 + LW_OPCODE_Y2 = 4, 1145 + LW_UN_0_SHUN_0_OPCODE_X1 = 14, 1146 + MAXB_U_SPECIAL_0_OPCODE_X0 = 15, 1147 + MAXB_U_SPECIAL_0_OPCODE_X1 = 14, 1148 + MAXH_SPECIAL_0_OPCODE_X0 = 16, 1149 + MAXH_SPECIAL_0_OPCODE_X1 = 15, 1150 + MAXIB_U_IMM_0_OPCODE_X0 = 4, 1151 + MAXIB_U_IMM_0_OPCODE_X1 = 5, 1152 + MAXIH_IMM_0_OPCODE_X0 = 5, 1153 + MAXIH_IMM_0_OPCODE_X1 = 6, 1154 + MFSPR_IMM_0_OPCODE_X1 = 7, 1155 + MF_UN_0_SHUN_0_OPCODE_X1 = 15, 1156 + MINB_U_SPECIAL_0_OPCODE_X0 = 17, 1157 + MINB_U_SPECIAL_0_OPCODE_X1 = 16, 1158 + MINH_SPECIAL_0_OPCODE_X0 = 18, 1159 + MINH_SPECIAL_0_OPCODE_X1 = 17, 1160 + MINIB_U_IMM_0_OPCODE_X0 = 6, 1161 + MINIB_U_IMM_0_OPCODE_X1 = 8, 1162 + MINIH_IMM_0_OPCODE_X0 = 7, 1163 + MINIH_IMM_0_OPCODE_X1 = 9, 1164 + MM_OPCODE_X0 = 6, 1165 + MM_OPCODE_X1 = 7, 1166 + MNZB_SPECIAL_0_OPCODE_X0 = 19, 1167 + MNZB_SPECIAL_0_OPCODE_X1 = 18, 1168 + MNZH_SPECIAL_0_OPCODE_X0 = 20, 1169 + MNZH_SPECIAL_0_OPCODE_X1 = 19, 1170 + MNZ_SPECIAL_0_OPCODE_X0 = 21, 1171 + MNZ_SPECIAL_0_OPCODE_X1 = 20, 1172 + MNZ_SPECIAL_1_OPCODE_Y0 = 0, 1173 + MNZ_SPECIAL_1_OPCODE_Y1 = 1, 1174 + MOVEI_IMM_1_OPCODE_SN = 0, 1175 + MOVE_RR_IMM_0_OPCODE_SN = 8, 1176 + MTSPR_IMM_0_OPCODE_X1 = 10, 1177 + MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22, 1178 + MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0, 1179 + MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23, 1180 + MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24, 1181 + MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1, 1182 + MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25, 1183 + MULHH_SS_SPECIAL_0_OPCODE_X0 = 26, 1184 + MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0, 1185 + MULHH_SU_SPECIAL_0_OPCODE_X0 = 27, 1186 + MULHH_UU_SPECIAL_0_OPCODE_X0 = 28, 1187 + MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1, 1188 + MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29, 1189 + MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30, 1190 + MULHLA_US_SPECIAL_0_OPCODE_X0 = 31, 1191 + MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32, 1192 + MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33, 1193 + MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0, 1194 + MULHL_SS_SPECIAL_0_OPCODE_X0 = 34, 1195 + MULHL_SU_SPECIAL_0_OPCODE_X0 = 35, 1196 + MULHL_US_SPECIAL_0_OPCODE_X0 = 36, 1197 + MULHL_UU_SPECIAL_0_OPCODE_X0 = 37, 1198 + MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38, 1199 + MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2, 1200 + MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39, 1201 + MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40, 1202 + MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3, 1203 + MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41, 1204 + MULLL_SS_SPECIAL_0_OPCODE_X0 = 42, 1205 + MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2, 1206 + MULLL_SU_SPECIAL_0_OPCODE_X0 = 43, 1207 + MULLL_UU_SPECIAL_0_OPCODE_X0 = 44, 1208 + MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3, 1209 + MVNZ_SPECIAL_0_OPCODE_X0 = 45, 1210 + MVNZ_SPECIAL_1_OPCODE_Y0 = 1, 1211 + MVZ_SPECIAL_0_OPCODE_X0 = 46, 1212 + MVZ_SPECIAL_1_OPCODE_Y0 = 2, 1213 + MZB_SPECIAL_0_OPCODE_X0 = 47, 1214 + MZB_SPECIAL_0_OPCODE_X1 = 21, 1215 + MZH_SPECIAL_0_OPCODE_X0 = 48, 1216 + MZH_SPECIAL_0_OPCODE_X1 = 22, 1217 + MZ_SPECIAL_0_OPCODE_X0 = 49, 1218 + MZ_SPECIAL_0_OPCODE_X1 = 23, 1219 + MZ_SPECIAL_1_OPCODE_Y0 = 3, 1220 + MZ_SPECIAL_1_OPCODE_Y1 = 2, 1221 + NAP_UN_0_SHUN_0_OPCODE_X1 = 16, 1222 + NOP_NOREG_RR_IMM_0_OPCODE_SN = 2, 1223 + NOP_UN_0_SHUN_0_OPCODE_X0 = 6, 1224 + NOP_UN_0_SHUN_0_OPCODE_X1 = 17, 1225 + NOP_UN_0_SHUN_0_OPCODE_Y0 = 6, 1226 + NOP_UN_0_SHUN_0_OPCODE_Y1 = 3, 1227 + NOREG_RR_IMM_0_OPCODE_SN = 0, 1228 + NOR_SPECIAL_0_OPCODE_X0 = 50, 1229 + NOR_SPECIAL_0_OPCODE_X1 = 24, 1230 + NOR_SPECIAL_2_OPCODE_Y0 = 1, 1231 + NOR_SPECIAL_2_OPCODE_Y1 = 1, 1232 + ORI_IMM_0_OPCODE_X0 = 8, 1233 + ORI_IMM_0_OPCODE_X1 = 11, 1234 + ORI_OPCODE_Y0 = 11, 1235 + ORI_OPCODE_Y1 = 9, 1236 + OR_SPECIAL_0_OPCODE_X0 = 51, 1237 + OR_SPECIAL_0_OPCODE_X1 = 25, 1238 + OR_SPECIAL_2_OPCODE_Y0 = 2, 1239 + OR_SPECIAL_2_OPCODE_Y1 = 2, 1240 + PACKBS_U_SPECIAL_0_OPCODE_X0 = 103, 1241 + PACKBS_U_SPECIAL_0_OPCODE_X1 = 73, 1242 + PACKHB_SPECIAL_0_OPCODE_X0 = 52, 1243 + PACKHB_SPECIAL_0_OPCODE_X1 = 26, 1244 + PACKHS_SPECIAL_0_OPCODE_X0 = 102, 1245 + PACKHS_SPECIAL_0_OPCODE_X1 = 72, 1246 + PACKLB_SPECIAL_0_OPCODE_X0 = 53, 1247 + PACKLB_SPECIAL_0_OPCODE_X1 = 27, 1248 + PCNT_UN_0_SHUN_0_OPCODE_X0 = 7, 1249 + PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7, 1250 + RLI_SHUN_0_OPCODE_X0 = 1, 1251 + RLI_SHUN_0_OPCODE_X1 = 1, 1252 + RLI_SHUN_0_OPCODE_Y0 = 1, 1253 + RLI_SHUN_0_OPCODE_Y1 = 1, 1254 + RL_SPECIAL_0_OPCODE_X0 = 54, 1255 + RL_SPECIAL_0_OPCODE_X1 = 28, 1256 + RL_SPECIAL_3_OPCODE_Y0 = 0, 1257 + RL_SPECIAL_3_OPCODE_Y1 = 0, 1258 + RR_IMM_0_OPCODE_SN = 0, 1259 + S1A_SPECIAL_0_OPCODE_X0 = 55, 1260 + S1A_SPECIAL_0_OPCODE_X1 = 29, 1261 + S1A_SPECIAL_0_OPCODE_Y0 = 1, 1262 + S1A_SPECIAL_0_OPCODE_Y1 = 1, 1263 + S2A_SPECIAL_0_OPCODE_X0 = 56, 1264 + S2A_SPECIAL_0_OPCODE_X1 = 30, 1265 + S2A_SPECIAL_0_OPCODE_Y0 = 2, 1266 + S2A_SPECIAL_0_OPCODE_Y1 = 2, 1267 + S3A_SPECIAL_0_OPCODE_X0 = 57, 1268 + S3A_SPECIAL_0_OPCODE_X1 = 31, 1269 + S3A_SPECIAL_5_OPCODE_Y0 = 1, 1270 + S3A_SPECIAL_5_OPCODE_Y1 = 1, 1271 + SADAB_U_SPECIAL_0_OPCODE_X0 = 58, 1272 + SADAH_SPECIAL_0_OPCODE_X0 = 59, 1273 + SADAH_U_SPECIAL_0_OPCODE_X0 = 60, 1274 + SADB_U_SPECIAL_0_OPCODE_X0 = 61, 1275 + SADH_SPECIAL_0_OPCODE_X0 = 62, 1276 + SADH_U_SPECIAL_0_OPCODE_X0 = 63, 1277 + SBADD_IMM_0_OPCODE_X1 = 28, 1278 + SB_OPCODE_Y2 = 5, 1279 + SB_SPECIAL_0_OPCODE_X1 = 32, 1280 + SEQB_SPECIAL_0_OPCODE_X0 = 64, 1281 + SEQB_SPECIAL_0_OPCODE_X1 = 33, 1282 + SEQH_SPECIAL_0_OPCODE_X0 = 65, 1283 + SEQH_SPECIAL_0_OPCODE_X1 = 34, 1284 + SEQIB_IMM_0_OPCODE_X0 = 9, 1285 + SEQIB_IMM_0_OPCODE_X1 = 12, 1286 + SEQIH_IMM_0_OPCODE_X0 = 10, 1287 + SEQIH_IMM_0_OPCODE_X1 = 13, 1288 + SEQI_IMM_0_OPCODE_X0 = 11, 1289 + SEQI_IMM_0_OPCODE_X1 = 14, 1290 + SEQI_OPCODE_Y0 = 12, 1291 + SEQI_OPCODE_Y1 = 10, 1292 + SEQ_SPECIAL_0_OPCODE_X0 = 66, 1293 + SEQ_SPECIAL_0_OPCODE_X1 = 35, 1294 + SEQ_SPECIAL_5_OPCODE_Y0 = 2, 1295 + SEQ_SPECIAL_5_OPCODE_Y1 = 2, 1296 + SHADD_IMM_0_OPCODE_X1 = 29, 1297 + SHL8II_IMM_0_OPCODE_SN = 3, 1298 + SHLB_SPECIAL_0_OPCODE_X0 = 67, 1299 + SHLB_SPECIAL_0_OPCODE_X1 = 36, 1300 + SHLH_SPECIAL_0_OPCODE_X0 = 68, 1301 + SHLH_SPECIAL_0_OPCODE_X1 = 37, 1302 + SHLIB_SHUN_0_OPCODE_X0 = 2, 1303 + SHLIB_SHUN_0_OPCODE_X1 = 2, 1304 + SHLIH_SHUN_0_OPCODE_X0 = 3, 1305 + SHLIH_SHUN_0_OPCODE_X1 = 3, 1306 + SHLI_SHUN_0_OPCODE_X0 = 4, 1307 + SHLI_SHUN_0_OPCODE_X1 = 4, 1308 + SHLI_SHUN_0_OPCODE_Y0 = 2, 1309 + SHLI_SHUN_0_OPCODE_Y1 = 2, 1310 + SHL_SPECIAL_0_OPCODE_X0 = 69, 1311 + SHL_SPECIAL_0_OPCODE_X1 = 38, 1312 + SHL_SPECIAL_3_OPCODE_Y0 = 1, 1313 + SHL_SPECIAL_3_OPCODE_Y1 = 1, 1314 + SHR1_RR_IMM_0_OPCODE_SN = 9, 1315 + SHRB_SPECIAL_0_OPCODE_X0 = 70, 1316 + SHRB_SPECIAL_0_OPCODE_X1 = 39, 1317 + SHRH_SPECIAL_0_OPCODE_X0 = 71, 1318 + SHRH_SPECIAL_0_OPCODE_X1 = 40, 1319 + SHRIB_SHUN_0_OPCODE_X0 = 5, 1320 + SHRIB_SHUN_0_OPCODE_X1 = 5, 1321 + SHRIH_SHUN_0_OPCODE_X0 = 6, 1322 + SHRIH_SHUN_0_OPCODE_X1 = 6, 1323 + SHRI_SHUN_0_OPCODE_X0 = 7, 1324 + SHRI_SHUN_0_OPCODE_X1 = 7, 1325 + SHRI_SHUN_0_OPCODE_Y0 = 3, 1326 + SHRI_SHUN_0_OPCODE_Y1 = 3, 1327 + SHR_SPECIAL_0_OPCODE_X0 = 72, 1328 + SHR_SPECIAL_0_OPCODE_X1 = 41, 1329 + SHR_SPECIAL_3_OPCODE_Y0 = 2, 1330 + SHR_SPECIAL_3_OPCODE_Y1 = 2, 1331 + SHUN_0_OPCODE_X0 = 7, 1332 + SHUN_0_OPCODE_X1 = 8, 1333 + SHUN_0_OPCODE_Y0 = 13, 1334 + SHUN_0_OPCODE_Y1 = 11, 1335 + SH_OPCODE_Y2 = 6, 1336 + SH_SPECIAL_0_OPCODE_X1 = 42, 1337 + SLTB_SPECIAL_0_OPCODE_X0 = 73, 1338 + SLTB_SPECIAL_0_OPCODE_X1 = 43, 1339 + SLTB_U_SPECIAL_0_OPCODE_X0 = 74, 1340 + SLTB_U_SPECIAL_0_OPCODE_X1 = 44, 1341 + SLTEB_SPECIAL_0_OPCODE_X0 = 75, 1342 + SLTEB_SPECIAL_0_OPCODE_X1 = 45, 1343 + SLTEB_U_SPECIAL_0_OPCODE_X0 = 76, 1344 + SLTEB_U_SPECIAL_0_OPCODE_X1 = 46, 1345 + SLTEH_SPECIAL_0_OPCODE_X0 = 77, 1346 + SLTEH_SPECIAL_0_OPCODE_X1 = 47, 1347 + SLTEH_U_SPECIAL_0_OPCODE_X0 = 78, 1348 + SLTEH_U_SPECIAL_0_OPCODE_X1 = 48, 1349 + SLTE_SPECIAL_0_OPCODE_X0 = 79, 1350 + SLTE_SPECIAL_0_OPCODE_X1 = 49, 1351 + SLTE_SPECIAL_4_OPCODE_Y0 = 0, 1352 + SLTE_SPECIAL_4_OPCODE_Y1 = 0, 1353 + SLTE_U_SPECIAL_0_OPCODE_X0 = 80, 1354 + SLTE_U_SPECIAL_0_OPCODE_X1 = 50, 1355 + SLTE_U_SPECIAL_4_OPCODE_Y0 = 1, 1356 + SLTE_U_SPECIAL_4_OPCODE_Y1 = 1, 1357 + SLTH_SPECIAL_0_OPCODE_X0 = 81, 1358 + SLTH_SPECIAL_0_OPCODE_X1 = 51, 1359 + SLTH_U_SPECIAL_0_OPCODE_X0 = 82, 1360 + SLTH_U_SPECIAL_0_OPCODE_X1 = 52, 1361 + SLTIB_IMM_0_OPCODE_X0 = 12, 1362 + SLTIB_IMM_0_OPCODE_X1 = 15, 1363 + SLTIB_U_IMM_0_OPCODE_X0 = 13, 1364 + SLTIB_U_IMM_0_OPCODE_X1 = 16, 1365 + SLTIH_IMM_0_OPCODE_X0 = 14, 1366 + SLTIH_IMM_0_OPCODE_X1 = 17, 1367 + SLTIH_U_IMM_0_OPCODE_X0 = 15, 1368 + SLTIH_U_IMM_0_OPCODE_X1 = 18, 1369 + SLTI_IMM_0_OPCODE_X0 = 16, 1370 + SLTI_IMM_0_OPCODE_X1 = 19, 1371 + SLTI_OPCODE_Y0 = 14, 1372 + SLTI_OPCODE_Y1 = 12, 1373 + SLTI_U_IMM_0_OPCODE_X0 = 17, 1374 + SLTI_U_IMM_0_OPCODE_X1 = 20, 1375 + SLTI_U_OPCODE_Y0 = 15, 1376 + SLTI_U_OPCODE_Y1 = 13, 1377 + SLT_SPECIAL_0_OPCODE_X0 = 83, 1378 + SLT_SPECIAL_0_OPCODE_X1 = 53, 1379 + SLT_SPECIAL_4_OPCODE_Y0 = 2, 1380 + SLT_SPECIAL_4_OPCODE_Y1 = 2, 1381 + SLT_U_SPECIAL_0_OPCODE_X0 = 84, 1382 + SLT_U_SPECIAL_0_OPCODE_X1 = 54, 1383 + SLT_U_SPECIAL_4_OPCODE_Y0 = 3, 1384 + SLT_U_SPECIAL_4_OPCODE_Y1 = 3, 1385 + SNEB_SPECIAL_0_OPCODE_X0 = 85, 1386 + SNEB_SPECIAL_0_OPCODE_X1 = 55, 1387 + SNEH_SPECIAL_0_OPCODE_X0 = 86, 1388 + SNEH_SPECIAL_0_OPCODE_X1 = 56, 1389 + SNE_SPECIAL_0_OPCODE_X0 = 87, 1390 + SNE_SPECIAL_0_OPCODE_X1 = 57, 1391 + SNE_SPECIAL_5_OPCODE_Y0 = 3, 1392 + SNE_SPECIAL_5_OPCODE_Y1 = 3, 1393 + SPECIAL_0_OPCODE_X0 = 0, 1394 + SPECIAL_0_OPCODE_X1 = 1, 1395 + SPECIAL_0_OPCODE_Y0 = 1, 1396 + SPECIAL_0_OPCODE_Y1 = 1, 1397 + SPECIAL_1_OPCODE_Y0 = 2, 1398 + SPECIAL_1_OPCODE_Y1 = 2, 1399 + SPECIAL_2_OPCODE_Y0 = 3, 1400 + SPECIAL_2_OPCODE_Y1 = 3, 1401 + SPECIAL_3_OPCODE_Y0 = 4, 1402 + SPECIAL_3_OPCODE_Y1 = 4, 1403 + SPECIAL_4_OPCODE_Y0 = 5, 1404 + SPECIAL_4_OPCODE_Y1 = 5, 1405 + SPECIAL_5_OPCODE_Y0 = 6, 1406 + SPECIAL_5_OPCODE_Y1 = 6, 1407 + SPECIAL_6_OPCODE_Y0 = 7, 1408 + SPECIAL_7_OPCODE_Y0 = 8, 1409 + SRAB_SPECIAL_0_OPCODE_X0 = 88, 1410 + SRAB_SPECIAL_0_OPCODE_X1 = 58, 1411 + SRAH_SPECIAL_0_OPCODE_X0 = 89, 1412 + SRAH_SPECIAL_0_OPCODE_X1 = 59, 1413 + SRAIB_SHUN_0_OPCODE_X0 = 8, 1414 + SRAIB_SHUN_0_OPCODE_X1 = 8, 1415 + SRAIH_SHUN_0_OPCODE_X0 = 9, 1416 + SRAIH_SHUN_0_OPCODE_X1 = 9, 1417 + SRAI_SHUN_0_OPCODE_X0 = 10, 1418 + SRAI_SHUN_0_OPCODE_X1 = 10, 1419 + SRAI_SHUN_0_OPCODE_Y0 = 4, 1420 + SRAI_SHUN_0_OPCODE_Y1 = 4, 1421 + SRA_SPECIAL_0_OPCODE_X0 = 90, 1422 + SRA_SPECIAL_0_OPCODE_X1 = 60, 1423 + SRA_SPECIAL_3_OPCODE_Y0 = 3, 1424 + SRA_SPECIAL_3_OPCODE_Y1 = 3, 1425 + SUBBS_U_SPECIAL_0_OPCODE_X0 = 100, 1426 + SUBBS_U_SPECIAL_0_OPCODE_X1 = 70, 1427 + SUBB_SPECIAL_0_OPCODE_X0 = 91, 1428 + SUBB_SPECIAL_0_OPCODE_X1 = 61, 1429 + SUBHS_SPECIAL_0_OPCODE_X0 = 101, 1430 + SUBHS_SPECIAL_0_OPCODE_X1 = 71, 1431 + SUBH_SPECIAL_0_OPCODE_X0 = 92, 1432 + SUBH_SPECIAL_0_OPCODE_X1 = 62, 1433 + SUBS_SPECIAL_0_OPCODE_X0 = 97, 1434 + SUBS_SPECIAL_0_OPCODE_X1 = 67, 1435 + SUB_SPECIAL_0_OPCODE_X0 = 93, 1436 + SUB_SPECIAL_0_OPCODE_X1 = 63, 1437 + SUB_SPECIAL_0_OPCODE_Y0 = 3, 1438 + SUB_SPECIAL_0_OPCODE_Y1 = 3, 1439 + SWADD_IMM_0_OPCODE_X1 = 30, 1440 + SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18, 1441 + SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19, 1442 + SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20, 1443 + SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21, 1444 + SW_OPCODE_Y2 = 7, 1445 + SW_SPECIAL_0_OPCODE_X1 = 64, 1446 + TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8, 1447 + TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8, 1448 + TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9, 1449 + TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9, 1450 + TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10, 1451 + TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10, 1452 + TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11, 1453 + TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11, 1454 + TNS_UN_0_SHUN_0_OPCODE_X1 = 22, 1455 + UN_0_SHUN_0_OPCODE_X0 = 11, 1456 + UN_0_SHUN_0_OPCODE_X1 = 11, 1457 + UN_0_SHUN_0_OPCODE_Y0 = 5, 1458 + UN_0_SHUN_0_OPCODE_Y1 = 5, 1459 + WH64_UN_0_SHUN_0_OPCODE_X1 = 23, 1460 + XORI_IMM_0_OPCODE_X0 = 2, 1461 + XORI_IMM_0_OPCODE_X1 = 21, 1462 + XOR_SPECIAL_0_OPCODE_X0 = 94, 1463 + XOR_SPECIAL_0_OPCODE_X1 = 65, 1464 + XOR_SPECIAL_2_OPCODE_Y0 = 3, 1465 + XOR_SPECIAL_2_OPCODE_Y1 = 3 1466 + }; 1467 + 1468 + 1469 + #endif /* __ASSEMBLER__ */ 1470 + 1471 + #endif /* __ARCH_OPCODE_H__ */
+2
arch/tile/include/asm/Kbuild
··· 1 1 include include/asm-generic/Kbuild.asm 2 2 3 + header-y += ../arch/ 4 + 3 5 header-y += ucontext.h 4 6 header-y += hardwall.h 5 7
+6 -15
arch/tile/include/asm/opcode-tile.h arch/tile/include/arch/opcode.h
··· 1 1 /* 2 - * Copyright 2010 Tilera Corporation. All Rights Reserved. 2 + * Copyright 2011 Tilera Corporation. All Rights Reserved. 3 3 * 4 4 * This program is free software; you can redistribute it and/or 5 5 * modify it under the terms of the GNU General Public License ··· 12 12 * more details. 13 13 */ 14 14 15 - #ifndef _ASM_TILE_OPCODE_TILE_H 16 - #define _ASM_TILE_OPCODE_TILE_H 17 - 18 - #include <arch/chip.h> 19 - 20 - #if CHIP_WORD_SIZE() == 64 21 - #include <asm/opcode-tile_64.h> 15 + #if defined(__tilepro__) 16 + #include <arch/opcode_tilepro.h> 17 + #elif defined(__tilegx__) 18 + #include <arch/opcode_tilegx.h> 22 19 #else 23 - #include <asm/opcode-tile_32.h> 20 + #error Unexpected Tilera chip type 24 21 #endif 25 - 26 - /* These definitions are not correct for TILE64, so just avoid them. */ 27 - #undef TILE_ELF_MACHINE_CODE 28 - #undef TILE_ELF_NAME 29 - 30 - #endif /* _ASM_TILE_OPCODE_TILE_H */
-1513
arch/tile/include/asm/opcode-tile_32.h
··· 1 - /* tile.h -- Header file for TILE opcode table 2 - Copyright (C) 2005 Free Software Foundation, Inc. 3 - Contributed by Tilera Corp. */ 4 - 5 - #ifndef opcode_tile_h 6 - #define opcode_tile_h 7 - 8 - typedef unsigned long long tile_bundle_bits; 9 - 10 - 11 - enum 12 - { 13 - TILE_MAX_OPERANDS = 5 /* mm */ 14 - }; 15 - 16 - typedef enum 17 - { 18 - TILE_OPC_BPT, 19 - TILE_OPC_INFO, 20 - TILE_OPC_INFOL, 21 - TILE_OPC_J, 22 - TILE_OPC_JAL, 23 - TILE_OPC_MOVE, 24 - TILE_OPC_MOVE_SN, 25 - TILE_OPC_MOVEI, 26 - TILE_OPC_MOVEI_SN, 27 - TILE_OPC_MOVELI, 28 - TILE_OPC_MOVELI_SN, 29 - TILE_OPC_MOVELIS, 30 - TILE_OPC_PREFETCH, 31 - TILE_OPC_RAISE, 32 - TILE_OPC_ADD, 33 - TILE_OPC_ADD_SN, 34 - TILE_OPC_ADDB, 35 - TILE_OPC_ADDB_SN, 36 - TILE_OPC_ADDBS_U, 37 - TILE_OPC_ADDBS_U_SN, 38 - TILE_OPC_ADDH, 39 - TILE_OPC_ADDH_SN, 40 - TILE_OPC_ADDHS, 41 - TILE_OPC_ADDHS_SN, 42 - TILE_OPC_ADDI, 43 - TILE_OPC_ADDI_SN, 44 - TILE_OPC_ADDIB, 45 - TILE_OPC_ADDIB_SN, 46 - TILE_OPC_ADDIH, 47 - TILE_OPC_ADDIH_SN, 48 - TILE_OPC_ADDLI, 49 - TILE_OPC_ADDLI_SN, 50 - TILE_OPC_ADDLIS, 51 - TILE_OPC_ADDS, 52 - TILE_OPC_ADDS_SN, 53 - TILE_OPC_ADIFFB_U, 54 - TILE_OPC_ADIFFB_U_SN, 55 - TILE_OPC_ADIFFH, 56 - TILE_OPC_ADIFFH_SN, 57 - TILE_OPC_AND, 58 - TILE_OPC_AND_SN, 59 - TILE_OPC_ANDI, 60 - TILE_OPC_ANDI_SN, 61 - TILE_OPC_AULI, 62 - TILE_OPC_AVGB_U, 63 - TILE_OPC_AVGB_U_SN, 64 - TILE_OPC_AVGH, 65 - TILE_OPC_AVGH_SN, 66 - TILE_OPC_BBNS, 67 - TILE_OPC_BBNS_SN, 68 - TILE_OPC_BBNST, 69 - TILE_OPC_BBNST_SN, 70 - TILE_OPC_BBS, 71 - TILE_OPC_BBS_SN, 72 - TILE_OPC_BBST, 73 - TILE_OPC_BBST_SN, 74 - TILE_OPC_BGEZ, 75 - TILE_OPC_BGEZ_SN, 76 - TILE_OPC_BGEZT, 77 - TILE_OPC_BGEZT_SN, 78 - TILE_OPC_BGZ, 79 - TILE_OPC_BGZ_SN, 80 - TILE_OPC_BGZT, 81 - TILE_OPC_BGZT_SN, 82 - TILE_OPC_BITX, 83 - TILE_OPC_BITX_SN, 84 - TILE_OPC_BLEZ, 85 - TILE_OPC_BLEZ_SN, 86 - TILE_OPC_BLEZT, 87 - TILE_OPC_BLEZT_SN, 88 - TILE_OPC_BLZ, 89 - TILE_OPC_BLZ_SN, 90 - TILE_OPC_BLZT, 91 - TILE_OPC_BLZT_SN, 92 - TILE_OPC_BNZ, 93 - TILE_OPC_BNZ_SN, 94 - TILE_OPC_BNZT, 95 - TILE_OPC_BNZT_SN, 96 - TILE_OPC_BYTEX, 97 - TILE_OPC_BYTEX_SN, 98 - TILE_OPC_BZ, 99 - TILE_OPC_BZ_SN, 100 - TILE_OPC_BZT, 101 - TILE_OPC_BZT_SN, 102 - TILE_OPC_CLZ, 103 - TILE_OPC_CLZ_SN, 104 - TILE_OPC_CRC32_32, 105 - TILE_OPC_CRC32_32_SN, 106 - TILE_OPC_CRC32_8, 107 - TILE_OPC_CRC32_8_SN, 108 - TILE_OPC_CTZ, 109 - TILE_OPC_CTZ_SN, 110 - TILE_OPC_DRAIN, 111 - TILE_OPC_DTLBPR, 112 - TILE_OPC_DWORD_ALIGN, 113 - TILE_OPC_DWORD_ALIGN_SN, 114 - TILE_OPC_FINV, 115 - TILE_OPC_FLUSH, 116 - TILE_OPC_FNOP, 117 - TILE_OPC_ICOH, 118 - TILE_OPC_ILL, 119 - TILE_OPC_INTHB, 120 - TILE_OPC_INTHB_SN, 121 - TILE_OPC_INTHH, 122 - TILE_OPC_INTHH_SN, 123 - TILE_OPC_INTLB, 124 - TILE_OPC_INTLB_SN, 125 - TILE_OPC_INTLH, 126 - TILE_OPC_INTLH_SN, 127 - TILE_OPC_INV, 128 - TILE_OPC_IRET, 129 - TILE_OPC_JALB, 130 - TILE_OPC_JALF, 131 - TILE_OPC_JALR, 132 - TILE_OPC_JALRP, 133 - TILE_OPC_JB, 134 - TILE_OPC_JF, 135 - TILE_OPC_JR, 136 - TILE_OPC_JRP, 137 - TILE_OPC_LB, 138 - TILE_OPC_LB_SN, 139 - TILE_OPC_LB_U, 140 - TILE_OPC_LB_U_SN, 141 - TILE_OPC_LBADD, 142 - TILE_OPC_LBADD_SN, 143 - TILE_OPC_LBADD_U, 144 - TILE_OPC_LBADD_U_SN, 145 - TILE_OPC_LH, 146 - TILE_OPC_LH_SN, 147 - TILE_OPC_LH_U, 148 - TILE_OPC_LH_U_SN, 149 - TILE_OPC_LHADD, 150 - TILE_OPC_LHADD_SN, 151 - TILE_OPC_LHADD_U, 152 - TILE_OPC_LHADD_U_SN, 153 - TILE_OPC_LNK, 154 - TILE_OPC_LNK_SN, 155 - TILE_OPC_LW, 156 - TILE_OPC_LW_SN, 157 - TILE_OPC_LW_NA, 158 - TILE_OPC_LW_NA_SN, 159 - TILE_OPC_LWADD, 160 - TILE_OPC_LWADD_SN, 161 - TILE_OPC_LWADD_NA, 162 - TILE_OPC_LWADD_NA_SN, 163 - TILE_OPC_MAXB_U, 164 - TILE_OPC_MAXB_U_SN, 165 - TILE_OPC_MAXH, 166 - TILE_OPC_MAXH_SN, 167 - TILE_OPC_MAXIB_U, 168 - TILE_OPC_MAXIB_U_SN, 169 - TILE_OPC_MAXIH, 170 - TILE_OPC_MAXIH_SN, 171 - TILE_OPC_MF, 172 - TILE_OPC_MFSPR, 173 - TILE_OPC_MINB_U, 174 - TILE_OPC_MINB_U_SN, 175 - TILE_OPC_MINH, 176 - TILE_OPC_MINH_SN, 177 - TILE_OPC_MINIB_U, 178 - TILE_OPC_MINIB_U_SN, 179 - TILE_OPC_MINIH, 180 - TILE_OPC_MINIH_SN, 181 - TILE_OPC_MM, 182 - TILE_OPC_MNZ, 183 - TILE_OPC_MNZ_SN, 184 - TILE_OPC_MNZB, 185 - TILE_OPC_MNZB_SN, 186 - TILE_OPC_MNZH, 187 - TILE_OPC_MNZH_SN, 188 - TILE_OPC_MTSPR, 189 - TILE_OPC_MULHH_SS, 190 - TILE_OPC_MULHH_SS_SN, 191 - TILE_OPC_MULHH_SU, 192 - TILE_OPC_MULHH_SU_SN, 193 - TILE_OPC_MULHH_UU, 194 - TILE_OPC_MULHH_UU_SN, 195 - TILE_OPC_MULHHA_SS, 196 - TILE_OPC_MULHHA_SS_SN, 197 - TILE_OPC_MULHHA_SU, 198 - TILE_OPC_MULHHA_SU_SN, 199 - TILE_OPC_MULHHA_UU, 200 - TILE_OPC_MULHHA_UU_SN, 201 - TILE_OPC_MULHHSA_UU, 202 - TILE_OPC_MULHHSA_UU_SN, 203 - TILE_OPC_MULHL_SS, 204 - TILE_OPC_MULHL_SS_SN, 205 - TILE_OPC_MULHL_SU, 206 - TILE_OPC_MULHL_SU_SN, 207 - TILE_OPC_MULHL_US, 208 - TILE_OPC_MULHL_US_SN, 209 - TILE_OPC_MULHL_UU, 210 - TILE_OPC_MULHL_UU_SN, 211 - TILE_OPC_MULHLA_SS, 212 - TILE_OPC_MULHLA_SS_SN, 213 - TILE_OPC_MULHLA_SU, 214 - TILE_OPC_MULHLA_SU_SN, 215 - TILE_OPC_MULHLA_US, 216 - TILE_OPC_MULHLA_US_SN, 217 - TILE_OPC_MULHLA_UU, 218 - TILE_OPC_MULHLA_UU_SN, 219 - TILE_OPC_MULHLSA_UU, 220 - TILE_OPC_MULHLSA_UU_SN, 221 - TILE_OPC_MULLL_SS, 222 - TILE_OPC_MULLL_SS_SN, 223 - TILE_OPC_MULLL_SU, 224 - TILE_OPC_MULLL_SU_SN, 225 - TILE_OPC_MULLL_UU, 226 - TILE_OPC_MULLL_UU_SN, 227 - TILE_OPC_MULLLA_SS, 228 - TILE_OPC_MULLLA_SS_SN, 229 - TILE_OPC_MULLLA_SU, 230 - TILE_OPC_MULLLA_SU_SN, 231 - TILE_OPC_MULLLA_UU, 232 - TILE_OPC_MULLLA_UU_SN, 233 - TILE_OPC_MULLLSA_UU, 234 - TILE_OPC_MULLLSA_UU_SN, 235 - TILE_OPC_MVNZ, 236 - TILE_OPC_MVNZ_SN, 237 - TILE_OPC_MVZ, 238 - TILE_OPC_MVZ_SN, 239 - TILE_OPC_MZ, 240 - TILE_OPC_MZ_SN, 241 - TILE_OPC_MZB, 242 - TILE_OPC_MZB_SN, 243 - TILE_OPC_MZH, 244 - TILE_OPC_MZH_SN, 245 - TILE_OPC_NAP, 246 - TILE_OPC_NOP, 247 - TILE_OPC_NOR, 248 - TILE_OPC_NOR_SN, 249 - TILE_OPC_OR, 250 - TILE_OPC_OR_SN, 251 - TILE_OPC_ORI, 252 - TILE_OPC_ORI_SN, 253 - TILE_OPC_PACKBS_U, 254 - TILE_OPC_PACKBS_U_SN, 255 - TILE_OPC_PACKHB, 256 - TILE_OPC_PACKHB_SN, 257 - TILE_OPC_PACKHS, 258 - TILE_OPC_PACKHS_SN, 259 - TILE_OPC_PACKLB, 260 - TILE_OPC_PACKLB_SN, 261 - TILE_OPC_PCNT, 262 - TILE_OPC_PCNT_SN, 263 - TILE_OPC_RL, 264 - TILE_OPC_RL_SN, 265 - TILE_OPC_RLI, 266 - TILE_OPC_RLI_SN, 267 - TILE_OPC_S1A, 268 - TILE_OPC_S1A_SN, 269 - TILE_OPC_S2A, 270 - TILE_OPC_S2A_SN, 271 - TILE_OPC_S3A, 272 - TILE_OPC_S3A_SN, 273 - TILE_OPC_SADAB_U, 274 - TILE_OPC_SADAB_U_SN, 275 - TILE_OPC_SADAH, 276 - TILE_OPC_SADAH_SN, 277 - TILE_OPC_SADAH_U, 278 - TILE_OPC_SADAH_U_SN, 279 - TILE_OPC_SADB_U, 280 - TILE_OPC_SADB_U_SN, 281 - TILE_OPC_SADH, 282 - TILE_OPC_SADH_SN, 283 - TILE_OPC_SADH_U, 284 - TILE_OPC_SADH_U_SN, 285 - TILE_OPC_SB, 286 - TILE_OPC_SBADD, 287 - TILE_OPC_SEQ, 288 - TILE_OPC_SEQ_SN, 289 - TILE_OPC_SEQB, 290 - TILE_OPC_SEQB_SN, 291 - TILE_OPC_SEQH, 292 - TILE_OPC_SEQH_SN, 293 - TILE_OPC_SEQI, 294 - TILE_OPC_SEQI_SN, 295 - TILE_OPC_SEQIB, 296 - TILE_OPC_SEQIB_SN, 297 - TILE_OPC_SEQIH, 298 - TILE_OPC_SEQIH_SN, 299 - TILE_OPC_SH, 300 - TILE_OPC_SHADD, 301 - TILE_OPC_SHL, 302 - TILE_OPC_SHL_SN, 303 - TILE_OPC_SHLB, 304 - TILE_OPC_SHLB_SN, 305 - TILE_OPC_SHLH, 306 - TILE_OPC_SHLH_SN, 307 - TILE_OPC_SHLI, 308 - TILE_OPC_SHLI_SN, 309 - TILE_OPC_SHLIB, 310 - TILE_OPC_SHLIB_SN, 311 - TILE_OPC_SHLIH, 312 - TILE_OPC_SHLIH_SN, 313 - TILE_OPC_SHR, 314 - TILE_OPC_SHR_SN, 315 - TILE_OPC_SHRB, 316 - TILE_OPC_SHRB_SN, 317 - TILE_OPC_SHRH, 318 - TILE_OPC_SHRH_SN, 319 - TILE_OPC_SHRI, 320 - TILE_OPC_SHRI_SN, 321 - TILE_OPC_SHRIB, 322 - TILE_OPC_SHRIB_SN, 323 - TILE_OPC_SHRIH, 324 - TILE_OPC_SHRIH_SN, 325 - TILE_OPC_SLT, 326 - TILE_OPC_SLT_SN, 327 - TILE_OPC_SLT_U, 328 - TILE_OPC_SLT_U_SN, 329 - TILE_OPC_SLTB, 330 - TILE_OPC_SLTB_SN, 331 - TILE_OPC_SLTB_U, 332 - TILE_OPC_SLTB_U_SN, 333 - TILE_OPC_SLTE, 334 - TILE_OPC_SLTE_SN, 335 - TILE_OPC_SLTE_U, 336 - TILE_OPC_SLTE_U_SN, 337 - TILE_OPC_SLTEB, 338 - TILE_OPC_SLTEB_SN, 339 - TILE_OPC_SLTEB_U, 340 - TILE_OPC_SLTEB_U_SN, 341 - TILE_OPC_SLTEH, 342 - TILE_OPC_SLTEH_SN, 343 - TILE_OPC_SLTEH_U, 344 - TILE_OPC_SLTEH_U_SN, 345 - TILE_OPC_SLTH, 346 - TILE_OPC_SLTH_SN, 347 - TILE_OPC_SLTH_U, 348 - TILE_OPC_SLTH_U_SN, 349 - TILE_OPC_SLTI, 350 - TILE_OPC_SLTI_SN, 351 - TILE_OPC_SLTI_U, 352 - TILE_OPC_SLTI_U_SN, 353 - TILE_OPC_SLTIB, 354 - TILE_OPC_SLTIB_SN, 355 - TILE_OPC_SLTIB_U, 356 - TILE_OPC_SLTIB_U_SN, 357 - TILE_OPC_SLTIH, 358 - TILE_OPC_SLTIH_SN, 359 - TILE_OPC_SLTIH_U, 360 - TILE_OPC_SLTIH_U_SN, 361 - TILE_OPC_SNE, 362 - TILE_OPC_SNE_SN, 363 - TILE_OPC_SNEB, 364 - TILE_OPC_SNEB_SN, 365 - TILE_OPC_SNEH, 366 - TILE_OPC_SNEH_SN, 367 - TILE_OPC_SRA, 368 - TILE_OPC_SRA_SN, 369 - TILE_OPC_SRAB, 370 - TILE_OPC_SRAB_SN, 371 - TILE_OPC_SRAH, 372 - TILE_OPC_SRAH_SN, 373 - TILE_OPC_SRAI, 374 - TILE_OPC_SRAI_SN, 375 - TILE_OPC_SRAIB, 376 - TILE_OPC_SRAIB_SN, 377 - TILE_OPC_SRAIH, 378 - TILE_OPC_SRAIH_SN, 379 - TILE_OPC_SUB, 380 - TILE_OPC_SUB_SN, 381 - TILE_OPC_SUBB, 382 - TILE_OPC_SUBB_SN, 383 - TILE_OPC_SUBBS_U, 384 - TILE_OPC_SUBBS_U_SN, 385 - TILE_OPC_SUBH, 386 - TILE_OPC_SUBH_SN, 387 - TILE_OPC_SUBHS, 388 - TILE_OPC_SUBHS_SN, 389 - TILE_OPC_SUBS, 390 - TILE_OPC_SUBS_SN, 391 - TILE_OPC_SW, 392 - TILE_OPC_SWADD, 393 - TILE_OPC_SWINT0, 394 - TILE_OPC_SWINT1, 395 - TILE_OPC_SWINT2, 396 - TILE_OPC_SWINT3, 397 - TILE_OPC_TBLIDXB0, 398 - TILE_OPC_TBLIDXB0_SN, 399 - TILE_OPC_TBLIDXB1, 400 - TILE_OPC_TBLIDXB1_SN, 401 - TILE_OPC_TBLIDXB2, 402 - TILE_OPC_TBLIDXB2_SN, 403 - TILE_OPC_TBLIDXB3, 404 - TILE_OPC_TBLIDXB3_SN, 405 - TILE_OPC_TNS, 406 - TILE_OPC_TNS_SN, 407 - TILE_OPC_WH64, 408 - TILE_OPC_XOR, 409 - TILE_OPC_XOR_SN, 410 - TILE_OPC_XORI, 411 - TILE_OPC_XORI_SN, 412 - TILE_OPC_NONE 413 - } tile_mnemonic; 414 - 415 - /* 64-bit pattern for a { bpt ; nop } bundle. */ 416 - #define TILE_BPT_BUNDLE 0x400b3cae70166000ULL 417 - 418 - 419 - #define TILE_ELF_MACHINE_CODE EM_TILEPRO 420 - 421 - #define TILE_ELF_NAME "elf32-tilepro" 422 - 423 - 424 - static __inline unsigned int 425 - get_BrOff_SN(tile_bundle_bits num) 426 - { 427 - const unsigned int n = (unsigned int)num; 428 - return (((n >> 0)) & 0x3ff); 429 - } 430 - 431 - static __inline unsigned int 432 - get_BrOff_X1(tile_bundle_bits n) 433 - { 434 - return (((unsigned int)(n >> 43)) & 0x00007fff) | 435 - (((unsigned int)(n >> 20)) & 0x00018000); 436 - } 437 - 438 - static __inline unsigned int 439 - get_BrType_X1(tile_bundle_bits n) 440 - { 441 - return (((unsigned int)(n >> 31)) & 0xf); 442 - } 443 - 444 - static __inline unsigned int 445 - get_Dest_Imm8_X1(tile_bundle_bits n) 446 - { 447 - return (((unsigned int)(n >> 31)) & 0x0000003f) | 448 - (((unsigned int)(n >> 43)) & 0x000000c0); 449 - } 450 - 451 - static __inline unsigned int 452 - get_Dest_SN(tile_bundle_bits num) 453 - { 454 - const unsigned int n = (unsigned int)num; 455 - return (((n >> 2)) & 0x3); 456 - } 457 - 458 - static __inline unsigned int 459 - get_Dest_X0(tile_bundle_bits num) 460 - { 461 - const unsigned int n = (unsigned int)num; 462 - return (((n >> 0)) & 0x3f); 463 - } 464 - 465 - static __inline unsigned int 466 - get_Dest_X1(tile_bundle_bits n) 467 - { 468 - return (((unsigned int)(n >> 31)) & 0x3f); 469 - } 470 - 471 - static __inline unsigned int 472 - get_Dest_Y0(tile_bundle_bits num) 473 - { 474 - const unsigned int n = (unsigned int)num; 475 - return (((n >> 0)) & 0x3f); 476 - } 477 - 478 - static __inline unsigned int 479 - get_Dest_Y1(tile_bundle_bits n) 480 - { 481 - return (((unsigned int)(n >> 31)) & 0x3f); 482 - } 483 - 484 - static __inline unsigned int 485 - get_Imm16_X0(tile_bundle_bits num) 486 - { 487 - const unsigned int n = (unsigned int)num; 488 - return (((n >> 12)) & 0xffff); 489 - } 490 - 491 - static __inline unsigned int 492 - get_Imm16_X1(tile_bundle_bits n) 493 - { 494 - return (((unsigned int)(n >> 43)) & 0xffff); 495 - } 496 - 497 - static __inline unsigned int 498 - get_Imm8_SN(tile_bundle_bits num) 499 - { 500 - const unsigned int n = (unsigned int)num; 501 - return (((n >> 0)) & 0xff); 502 - } 503 - 504 - static __inline unsigned int 505 - get_Imm8_X0(tile_bundle_bits num) 506 - { 507 - const unsigned int n = (unsigned int)num; 508 - return (((n >> 12)) & 0xff); 509 - } 510 - 511 - static __inline unsigned int 512 - get_Imm8_X1(tile_bundle_bits n) 513 - { 514 - return (((unsigned int)(n >> 43)) & 0xff); 515 - } 516 - 517 - static __inline unsigned int 518 - get_Imm8_Y0(tile_bundle_bits num) 519 - { 520 - const unsigned int n = (unsigned int)num; 521 - return (((n >> 12)) & 0xff); 522 - } 523 - 524 - static __inline unsigned int 525 - get_Imm8_Y1(tile_bundle_bits n) 526 - { 527 - return (((unsigned int)(n >> 43)) & 0xff); 528 - } 529 - 530 - static __inline unsigned int 531 - get_ImmOpcodeExtension_X0(tile_bundle_bits num) 532 - { 533 - const unsigned int n = (unsigned int)num; 534 - return (((n >> 20)) & 0x7f); 535 - } 536 - 537 - static __inline unsigned int 538 - get_ImmOpcodeExtension_X1(tile_bundle_bits n) 539 - { 540 - return (((unsigned int)(n >> 51)) & 0x7f); 541 - } 542 - 543 - static __inline unsigned int 544 - get_ImmRROpcodeExtension_SN(tile_bundle_bits num) 545 - { 546 - const unsigned int n = (unsigned int)num; 547 - return (((n >> 8)) & 0x3); 548 - } 549 - 550 - static __inline unsigned int 551 - get_JOffLong_X1(tile_bundle_bits n) 552 - { 553 - return (((unsigned int)(n >> 43)) & 0x00007fff) | 554 - (((unsigned int)(n >> 20)) & 0x00018000) | 555 - (((unsigned int)(n >> 14)) & 0x001e0000) | 556 - (((unsigned int)(n >> 16)) & 0x07e00000) | 557 - (((unsigned int)(n >> 31)) & 0x18000000); 558 - } 559 - 560 - static __inline unsigned int 561 - get_JOff_X1(tile_bundle_bits n) 562 - { 563 - return (((unsigned int)(n >> 43)) & 0x00007fff) | 564 - (((unsigned int)(n >> 20)) & 0x00018000) | 565 - (((unsigned int)(n >> 14)) & 0x001e0000) | 566 - (((unsigned int)(n >> 16)) & 0x07e00000) | 567 - (((unsigned int)(n >> 31)) & 0x08000000); 568 - } 569 - 570 - static __inline unsigned int 571 - get_MF_Imm15_X1(tile_bundle_bits n) 572 - { 573 - return (((unsigned int)(n >> 37)) & 0x00003fff) | 574 - (((unsigned int)(n >> 44)) & 0x00004000); 575 - } 576 - 577 - static __inline unsigned int 578 - get_MMEnd_X0(tile_bundle_bits num) 579 - { 580 - const unsigned int n = (unsigned int)num; 581 - return (((n >> 18)) & 0x1f); 582 - } 583 - 584 - static __inline unsigned int 585 - get_MMEnd_X1(tile_bundle_bits n) 586 - { 587 - return (((unsigned int)(n >> 49)) & 0x1f); 588 - } 589 - 590 - static __inline unsigned int 591 - get_MMStart_X0(tile_bundle_bits num) 592 - { 593 - const unsigned int n = (unsigned int)num; 594 - return (((n >> 23)) & 0x1f); 595 - } 596 - 597 - static __inline unsigned int 598 - get_MMStart_X1(tile_bundle_bits n) 599 - { 600 - return (((unsigned int)(n >> 54)) & 0x1f); 601 - } 602 - 603 - static __inline unsigned int 604 - get_MT_Imm15_X1(tile_bundle_bits n) 605 - { 606 - return (((unsigned int)(n >> 31)) & 0x0000003f) | 607 - (((unsigned int)(n >> 37)) & 0x00003fc0) | 608 - (((unsigned int)(n >> 44)) & 0x00004000); 609 - } 610 - 611 - static __inline unsigned int 612 - get_Mode(tile_bundle_bits n) 613 - { 614 - return (((unsigned int)(n >> 63)) & 0x1); 615 - } 616 - 617 - static __inline unsigned int 618 - get_NoRegOpcodeExtension_SN(tile_bundle_bits num) 619 - { 620 - const unsigned int n = (unsigned int)num; 621 - return (((n >> 0)) & 0xf); 622 - } 623 - 624 - static __inline unsigned int 625 - get_Opcode_SN(tile_bundle_bits num) 626 - { 627 - const unsigned int n = (unsigned int)num; 628 - return (((n >> 10)) & 0x3f); 629 - } 630 - 631 - static __inline unsigned int 632 - get_Opcode_X0(tile_bundle_bits num) 633 - { 634 - const unsigned int n = (unsigned int)num; 635 - return (((n >> 28)) & 0x7); 636 - } 637 - 638 - static __inline unsigned int 639 - get_Opcode_X1(tile_bundle_bits n) 640 - { 641 - return (((unsigned int)(n >> 59)) & 0xf); 642 - } 643 - 644 - static __inline unsigned int 645 - get_Opcode_Y0(tile_bundle_bits num) 646 - { 647 - const unsigned int n = (unsigned int)num; 648 - return (((n >> 27)) & 0xf); 649 - } 650 - 651 - static __inline unsigned int 652 - get_Opcode_Y1(tile_bundle_bits n) 653 - { 654 - return (((unsigned int)(n >> 59)) & 0xf); 655 - } 656 - 657 - static __inline unsigned int 658 - get_Opcode_Y2(tile_bundle_bits n) 659 - { 660 - return (((unsigned int)(n >> 56)) & 0x7); 661 - } 662 - 663 - static __inline unsigned int 664 - get_RROpcodeExtension_SN(tile_bundle_bits num) 665 - { 666 - const unsigned int n = (unsigned int)num; 667 - return (((n >> 4)) & 0xf); 668 - } 669 - 670 - static __inline unsigned int 671 - get_RRROpcodeExtension_X0(tile_bundle_bits num) 672 - { 673 - const unsigned int n = (unsigned int)num; 674 - return (((n >> 18)) & 0x1ff); 675 - } 676 - 677 - static __inline unsigned int 678 - get_RRROpcodeExtension_X1(tile_bundle_bits n) 679 - { 680 - return (((unsigned int)(n >> 49)) & 0x1ff); 681 - } 682 - 683 - static __inline unsigned int 684 - get_RRROpcodeExtension_Y0(tile_bundle_bits num) 685 - { 686 - const unsigned int n = (unsigned int)num; 687 - return (((n >> 18)) & 0x3); 688 - } 689 - 690 - static __inline unsigned int 691 - get_RRROpcodeExtension_Y1(tile_bundle_bits n) 692 - { 693 - return (((unsigned int)(n >> 49)) & 0x3); 694 - } 695 - 696 - static __inline unsigned int 697 - get_RouteOpcodeExtension_SN(tile_bundle_bits num) 698 - { 699 - const unsigned int n = (unsigned int)num; 700 - return (((n >> 0)) & 0x3ff); 701 - } 702 - 703 - static __inline unsigned int 704 - get_S_X0(tile_bundle_bits num) 705 - { 706 - const unsigned int n = (unsigned int)num; 707 - return (((n >> 27)) & 0x1); 708 - } 709 - 710 - static __inline unsigned int 711 - get_S_X1(tile_bundle_bits n) 712 - { 713 - return (((unsigned int)(n >> 58)) & 0x1); 714 - } 715 - 716 - static __inline unsigned int 717 - get_ShAmt_X0(tile_bundle_bits num) 718 - { 719 - const unsigned int n = (unsigned int)num; 720 - return (((n >> 12)) & 0x1f); 721 - } 722 - 723 - static __inline unsigned int 724 - get_ShAmt_X1(tile_bundle_bits n) 725 - { 726 - return (((unsigned int)(n >> 43)) & 0x1f); 727 - } 728 - 729 - static __inline unsigned int 730 - get_ShAmt_Y0(tile_bundle_bits num) 731 - { 732 - const unsigned int n = (unsigned int)num; 733 - return (((n >> 12)) & 0x1f); 734 - } 735 - 736 - static __inline unsigned int 737 - get_ShAmt_Y1(tile_bundle_bits n) 738 - { 739 - return (((unsigned int)(n >> 43)) & 0x1f); 740 - } 741 - 742 - static __inline unsigned int 743 - get_SrcA_X0(tile_bundle_bits num) 744 - { 745 - const unsigned int n = (unsigned int)num; 746 - return (((n >> 6)) & 0x3f); 747 - } 748 - 749 - static __inline unsigned int 750 - get_SrcA_X1(tile_bundle_bits n) 751 - { 752 - return (((unsigned int)(n >> 37)) & 0x3f); 753 - } 754 - 755 - static __inline unsigned int 756 - get_SrcA_Y0(tile_bundle_bits num) 757 - { 758 - const unsigned int n = (unsigned int)num; 759 - return (((n >> 6)) & 0x3f); 760 - } 761 - 762 - static __inline unsigned int 763 - get_SrcA_Y1(tile_bundle_bits n) 764 - { 765 - return (((unsigned int)(n >> 37)) & 0x3f); 766 - } 767 - 768 - static __inline unsigned int 769 - get_SrcA_Y2(tile_bundle_bits n) 770 - { 771 - return (((n >> 26)) & 0x00000001) | 772 - (((unsigned int)(n >> 50)) & 0x0000003e); 773 - } 774 - 775 - static __inline unsigned int 776 - get_SrcBDest_Y2(tile_bundle_bits num) 777 - { 778 - const unsigned int n = (unsigned int)num; 779 - return (((n >> 20)) & 0x3f); 780 - } 781 - 782 - static __inline unsigned int 783 - get_SrcB_X0(tile_bundle_bits num) 784 - { 785 - const unsigned int n = (unsigned int)num; 786 - return (((n >> 12)) & 0x3f); 787 - } 788 - 789 - static __inline unsigned int 790 - get_SrcB_X1(tile_bundle_bits n) 791 - { 792 - return (((unsigned int)(n >> 43)) & 0x3f); 793 - } 794 - 795 - static __inline unsigned int 796 - get_SrcB_Y0(tile_bundle_bits num) 797 - { 798 - const unsigned int n = (unsigned int)num; 799 - return (((n >> 12)) & 0x3f); 800 - } 801 - 802 - static __inline unsigned int 803 - get_SrcB_Y1(tile_bundle_bits n) 804 - { 805 - return (((unsigned int)(n >> 43)) & 0x3f); 806 - } 807 - 808 - static __inline unsigned int 809 - get_Src_SN(tile_bundle_bits num) 810 - { 811 - const unsigned int n = (unsigned int)num; 812 - return (((n >> 0)) & 0x3); 813 - } 814 - 815 - static __inline unsigned int 816 - get_UnOpcodeExtension_X0(tile_bundle_bits num) 817 - { 818 - const unsigned int n = (unsigned int)num; 819 - return (((n >> 12)) & 0x1f); 820 - } 821 - 822 - static __inline unsigned int 823 - get_UnOpcodeExtension_X1(tile_bundle_bits n) 824 - { 825 - return (((unsigned int)(n >> 43)) & 0x1f); 826 - } 827 - 828 - static __inline unsigned int 829 - get_UnOpcodeExtension_Y0(tile_bundle_bits num) 830 - { 831 - const unsigned int n = (unsigned int)num; 832 - return (((n >> 12)) & 0x1f); 833 - } 834 - 835 - static __inline unsigned int 836 - get_UnOpcodeExtension_Y1(tile_bundle_bits n) 837 - { 838 - return (((unsigned int)(n >> 43)) & 0x1f); 839 - } 840 - 841 - static __inline unsigned int 842 - get_UnShOpcodeExtension_X0(tile_bundle_bits num) 843 - { 844 - const unsigned int n = (unsigned int)num; 845 - return (((n >> 17)) & 0x3ff); 846 - } 847 - 848 - static __inline unsigned int 849 - get_UnShOpcodeExtension_X1(tile_bundle_bits n) 850 - { 851 - return (((unsigned int)(n >> 48)) & 0x3ff); 852 - } 853 - 854 - static __inline unsigned int 855 - get_UnShOpcodeExtension_Y0(tile_bundle_bits num) 856 - { 857 - const unsigned int n = (unsigned int)num; 858 - return (((n >> 17)) & 0x7); 859 - } 860 - 861 - static __inline unsigned int 862 - get_UnShOpcodeExtension_Y1(tile_bundle_bits n) 863 - { 864 - return (((unsigned int)(n >> 48)) & 0x7); 865 - } 866 - 867 - 868 - static __inline int 869 - sign_extend(int n, int num_bits) 870 - { 871 - int shift = (int)(sizeof(int) * 8 - num_bits); 872 - return (n << shift) >> shift; 873 - } 874 - 875 - 876 - 877 - static __inline tile_bundle_bits 878 - create_BrOff_SN(int num) 879 - { 880 - const unsigned int n = (unsigned int)num; 881 - return ((n & 0x3ff) << 0); 882 - } 883 - 884 - static __inline tile_bundle_bits 885 - create_BrOff_X1(int num) 886 - { 887 - const unsigned int n = (unsigned int)num; 888 - return (((tile_bundle_bits)(n & 0x00007fff)) << 43) | 889 - (((tile_bundle_bits)(n & 0x00018000)) << 20); 890 - } 891 - 892 - static __inline tile_bundle_bits 893 - create_BrType_X1(int num) 894 - { 895 - const unsigned int n = (unsigned int)num; 896 - return (((tile_bundle_bits)(n & 0xf)) << 31); 897 - } 898 - 899 - static __inline tile_bundle_bits 900 - create_Dest_Imm8_X1(int num) 901 - { 902 - const unsigned int n = (unsigned int)num; 903 - return (((tile_bundle_bits)(n & 0x0000003f)) << 31) | 904 - (((tile_bundle_bits)(n & 0x000000c0)) << 43); 905 - } 906 - 907 - static __inline tile_bundle_bits 908 - create_Dest_SN(int num) 909 - { 910 - const unsigned int n = (unsigned int)num; 911 - return ((n & 0x3) << 2); 912 - } 913 - 914 - static __inline tile_bundle_bits 915 - create_Dest_X0(int num) 916 - { 917 - const unsigned int n = (unsigned int)num; 918 - return ((n & 0x3f) << 0); 919 - } 920 - 921 - static __inline tile_bundle_bits 922 - create_Dest_X1(int num) 923 - { 924 - const unsigned int n = (unsigned int)num; 925 - return (((tile_bundle_bits)(n & 0x3f)) << 31); 926 - } 927 - 928 - static __inline tile_bundle_bits 929 - create_Dest_Y0(int num) 930 - { 931 - const unsigned int n = (unsigned int)num; 932 - return ((n & 0x3f) << 0); 933 - } 934 - 935 - static __inline tile_bundle_bits 936 - create_Dest_Y1(int num) 937 - { 938 - const unsigned int n = (unsigned int)num; 939 - return (((tile_bundle_bits)(n & 0x3f)) << 31); 940 - } 941 - 942 - static __inline tile_bundle_bits 943 - create_Imm16_X0(int num) 944 - { 945 - const unsigned int n = (unsigned int)num; 946 - return ((n & 0xffff) << 12); 947 - } 948 - 949 - static __inline tile_bundle_bits 950 - create_Imm16_X1(int num) 951 - { 952 - const unsigned int n = (unsigned int)num; 953 - return (((tile_bundle_bits)(n & 0xffff)) << 43); 954 - } 955 - 956 - static __inline tile_bundle_bits 957 - create_Imm8_SN(int num) 958 - { 959 - const unsigned int n = (unsigned int)num; 960 - return ((n & 0xff) << 0); 961 - } 962 - 963 - static __inline tile_bundle_bits 964 - create_Imm8_X0(int num) 965 - { 966 - const unsigned int n = (unsigned int)num; 967 - return ((n & 0xff) << 12); 968 - } 969 - 970 - static __inline tile_bundle_bits 971 - create_Imm8_X1(int num) 972 - { 973 - const unsigned int n = (unsigned int)num; 974 - return (((tile_bundle_bits)(n & 0xff)) << 43); 975 - } 976 - 977 - static __inline tile_bundle_bits 978 - create_Imm8_Y0(int num) 979 - { 980 - const unsigned int n = (unsigned int)num; 981 - return ((n & 0xff) << 12); 982 - } 983 - 984 - static __inline tile_bundle_bits 985 - create_Imm8_Y1(int num) 986 - { 987 - const unsigned int n = (unsigned int)num; 988 - return (((tile_bundle_bits)(n & 0xff)) << 43); 989 - } 990 - 991 - static __inline tile_bundle_bits 992 - create_ImmOpcodeExtension_X0(int num) 993 - { 994 - const unsigned int n = (unsigned int)num; 995 - return ((n & 0x7f) << 20); 996 - } 997 - 998 - static __inline tile_bundle_bits 999 - create_ImmOpcodeExtension_X1(int num) 1000 - { 1001 - const unsigned int n = (unsigned int)num; 1002 - return (((tile_bundle_bits)(n & 0x7f)) << 51); 1003 - } 1004 - 1005 - static __inline tile_bundle_bits 1006 - create_ImmRROpcodeExtension_SN(int num) 1007 - { 1008 - const unsigned int n = (unsigned int)num; 1009 - return ((n & 0x3) << 8); 1010 - } 1011 - 1012 - static __inline tile_bundle_bits 1013 - create_JOffLong_X1(int num) 1014 - { 1015 - const unsigned int n = (unsigned int)num; 1016 - return (((tile_bundle_bits)(n & 0x00007fff)) << 43) | 1017 - (((tile_bundle_bits)(n & 0x00018000)) << 20) | 1018 - (((tile_bundle_bits)(n & 0x001e0000)) << 14) | 1019 - (((tile_bundle_bits)(n & 0x07e00000)) << 16) | 1020 - (((tile_bundle_bits)(n & 0x18000000)) << 31); 1021 - } 1022 - 1023 - static __inline tile_bundle_bits 1024 - create_JOff_X1(int num) 1025 - { 1026 - const unsigned int n = (unsigned int)num; 1027 - return (((tile_bundle_bits)(n & 0x00007fff)) << 43) | 1028 - (((tile_bundle_bits)(n & 0x00018000)) << 20) | 1029 - (((tile_bundle_bits)(n & 0x001e0000)) << 14) | 1030 - (((tile_bundle_bits)(n & 0x07e00000)) << 16) | 1031 - (((tile_bundle_bits)(n & 0x08000000)) << 31); 1032 - } 1033 - 1034 - static __inline tile_bundle_bits 1035 - create_MF_Imm15_X1(int num) 1036 - { 1037 - const unsigned int n = (unsigned int)num; 1038 - return (((tile_bundle_bits)(n & 0x00003fff)) << 37) | 1039 - (((tile_bundle_bits)(n & 0x00004000)) << 44); 1040 - } 1041 - 1042 - static __inline tile_bundle_bits 1043 - create_MMEnd_X0(int num) 1044 - { 1045 - const unsigned int n = (unsigned int)num; 1046 - return ((n & 0x1f) << 18); 1047 - } 1048 - 1049 - static __inline tile_bundle_bits 1050 - create_MMEnd_X1(int num) 1051 - { 1052 - const unsigned int n = (unsigned int)num; 1053 - return (((tile_bundle_bits)(n & 0x1f)) << 49); 1054 - } 1055 - 1056 - static __inline tile_bundle_bits 1057 - create_MMStart_X0(int num) 1058 - { 1059 - const unsigned int n = (unsigned int)num; 1060 - return ((n & 0x1f) << 23); 1061 - } 1062 - 1063 - static __inline tile_bundle_bits 1064 - create_MMStart_X1(int num) 1065 - { 1066 - const unsigned int n = (unsigned int)num; 1067 - return (((tile_bundle_bits)(n & 0x1f)) << 54); 1068 - } 1069 - 1070 - static __inline tile_bundle_bits 1071 - create_MT_Imm15_X1(int num) 1072 - { 1073 - const unsigned int n = (unsigned int)num; 1074 - return (((tile_bundle_bits)(n & 0x0000003f)) << 31) | 1075 - (((tile_bundle_bits)(n & 0x00003fc0)) << 37) | 1076 - (((tile_bundle_bits)(n & 0x00004000)) << 44); 1077 - } 1078 - 1079 - static __inline tile_bundle_bits 1080 - create_Mode(int num) 1081 - { 1082 - const unsigned int n = (unsigned int)num; 1083 - return (((tile_bundle_bits)(n & 0x1)) << 63); 1084 - } 1085 - 1086 - static __inline tile_bundle_bits 1087 - create_NoRegOpcodeExtension_SN(int num) 1088 - { 1089 - const unsigned int n = (unsigned int)num; 1090 - return ((n & 0xf) << 0); 1091 - } 1092 - 1093 - static __inline tile_bundle_bits 1094 - create_Opcode_SN(int num) 1095 - { 1096 - const unsigned int n = (unsigned int)num; 1097 - return ((n & 0x3f) << 10); 1098 - } 1099 - 1100 - static __inline tile_bundle_bits 1101 - create_Opcode_X0(int num) 1102 - { 1103 - const unsigned int n = (unsigned int)num; 1104 - return ((n & 0x7) << 28); 1105 - } 1106 - 1107 - static __inline tile_bundle_bits 1108 - create_Opcode_X1(int num) 1109 - { 1110 - const unsigned int n = (unsigned int)num; 1111 - return (((tile_bundle_bits)(n & 0xf)) << 59); 1112 - } 1113 - 1114 - static __inline tile_bundle_bits 1115 - create_Opcode_Y0(int num) 1116 - { 1117 - const unsigned int n = (unsigned int)num; 1118 - return ((n & 0xf) << 27); 1119 - } 1120 - 1121 - static __inline tile_bundle_bits 1122 - create_Opcode_Y1(int num) 1123 - { 1124 - const unsigned int n = (unsigned int)num; 1125 - return (((tile_bundle_bits)(n & 0xf)) << 59); 1126 - } 1127 - 1128 - static __inline tile_bundle_bits 1129 - create_Opcode_Y2(int num) 1130 - { 1131 - const unsigned int n = (unsigned int)num; 1132 - return (((tile_bundle_bits)(n & 0x7)) << 56); 1133 - } 1134 - 1135 - static __inline tile_bundle_bits 1136 - create_RROpcodeExtension_SN(int num) 1137 - { 1138 - const unsigned int n = (unsigned int)num; 1139 - return ((n & 0xf) << 4); 1140 - } 1141 - 1142 - static __inline tile_bundle_bits 1143 - create_RRROpcodeExtension_X0(int num) 1144 - { 1145 - const unsigned int n = (unsigned int)num; 1146 - return ((n & 0x1ff) << 18); 1147 - } 1148 - 1149 - static __inline tile_bundle_bits 1150 - create_RRROpcodeExtension_X1(int num) 1151 - { 1152 - const unsigned int n = (unsigned int)num; 1153 - return (((tile_bundle_bits)(n & 0x1ff)) << 49); 1154 - } 1155 - 1156 - static __inline tile_bundle_bits 1157 - create_RRROpcodeExtension_Y0(int num) 1158 - { 1159 - const unsigned int n = (unsigned int)num; 1160 - return ((n & 0x3) << 18); 1161 - } 1162 - 1163 - static __inline tile_bundle_bits 1164 - create_RRROpcodeExtension_Y1(int num) 1165 - { 1166 - const unsigned int n = (unsigned int)num; 1167 - return (((tile_bundle_bits)(n & 0x3)) << 49); 1168 - } 1169 - 1170 - static __inline tile_bundle_bits 1171 - create_RouteOpcodeExtension_SN(int num) 1172 - { 1173 - const unsigned int n = (unsigned int)num; 1174 - return ((n & 0x3ff) << 0); 1175 - } 1176 - 1177 - static __inline tile_bundle_bits 1178 - create_S_X0(int num) 1179 - { 1180 - const unsigned int n = (unsigned int)num; 1181 - return ((n & 0x1) << 27); 1182 - } 1183 - 1184 - static __inline tile_bundle_bits 1185 - create_S_X1(int num) 1186 - { 1187 - const unsigned int n = (unsigned int)num; 1188 - return (((tile_bundle_bits)(n & 0x1)) << 58); 1189 - } 1190 - 1191 - static __inline tile_bundle_bits 1192 - create_ShAmt_X0(int num) 1193 - { 1194 - const unsigned int n = (unsigned int)num; 1195 - return ((n & 0x1f) << 12); 1196 - } 1197 - 1198 - static __inline tile_bundle_bits 1199 - create_ShAmt_X1(int num) 1200 - { 1201 - const unsigned int n = (unsigned int)num; 1202 - return (((tile_bundle_bits)(n & 0x1f)) << 43); 1203 - } 1204 - 1205 - static __inline tile_bundle_bits 1206 - create_ShAmt_Y0(int num) 1207 - { 1208 - const unsigned int n = (unsigned int)num; 1209 - return ((n & 0x1f) << 12); 1210 - } 1211 - 1212 - static __inline tile_bundle_bits 1213 - create_ShAmt_Y1(int num) 1214 - { 1215 - const unsigned int n = (unsigned int)num; 1216 - return (((tile_bundle_bits)(n & 0x1f)) << 43); 1217 - } 1218 - 1219 - static __inline tile_bundle_bits 1220 - create_SrcA_X0(int num) 1221 - { 1222 - const unsigned int n = (unsigned int)num; 1223 - return ((n & 0x3f) << 6); 1224 - } 1225 - 1226 - static __inline tile_bundle_bits 1227 - create_SrcA_X1(int num) 1228 - { 1229 - const unsigned int n = (unsigned int)num; 1230 - return (((tile_bundle_bits)(n & 0x3f)) << 37); 1231 - } 1232 - 1233 - static __inline tile_bundle_bits 1234 - create_SrcA_Y0(int num) 1235 - { 1236 - const unsigned int n = (unsigned int)num; 1237 - return ((n & 0x3f) << 6); 1238 - } 1239 - 1240 - static __inline tile_bundle_bits 1241 - create_SrcA_Y1(int num) 1242 - { 1243 - const unsigned int n = (unsigned int)num; 1244 - return (((tile_bundle_bits)(n & 0x3f)) << 37); 1245 - } 1246 - 1247 - static __inline tile_bundle_bits 1248 - create_SrcA_Y2(int num) 1249 - { 1250 - const unsigned int n = (unsigned int)num; 1251 - return ((n & 0x00000001) << 26) | 1252 - (((tile_bundle_bits)(n & 0x0000003e)) << 50); 1253 - } 1254 - 1255 - static __inline tile_bundle_bits 1256 - create_SrcBDest_Y2(int num) 1257 - { 1258 - const unsigned int n = (unsigned int)num; 1259 - return ((n & 0x3f) << 20); 1260 - } 1261 - 1262 - static __inline tile_bundle_bits 1263 - create_SrcB_X0(int num) 1264 - { 1265 - const unsigned int n = (unsigned int)num; 1266 - return ((n & 0x3f) << 12); 1267 - } 1268 - 1269 - static __inline tile_bundle_bits 1270 - create_SrcB_X1(int num) 1271 - { 1272 - const unsigned int n = (unsigned int)num; 1273 - return (((tile_bundle_bits)(n & 0x3f)) << 43); 1274 - } 1275 - 1276 - static __inline tile_bundle_bits 1277 - create_SrcB_Y0(int num) 1278 - { 1279 - const unsigned int n = (unsigned int)num; 1280 - return ((n & 0x3f) << 12); 1281 - } 1282 - 1283 - static __inline tile_bundle_bits 1284 - create_SrcB_Y1(int num) 1285 - { 1286 - const unsigned int n = (unsigned int)num; 1287 - return (((tile_bundle_bits)(n & 0x3f)) << 43); 1288 - } 1289 - 1290 - static __inline tile_bundle_bits 1291 - create_Src_SN(int num) 1292 - { 1293 - const unsigned int n = (unsigned int)num; 1294 - return ((n & 0x3) << 0); 1295 - } 1296 - 1297 - static __inline tile_bundle_bits 1298 - create_UnOpcodeExtension_X0(int num) 1299 - { 1300 - const unsigned int n = (unsigned int)num; 1301 - return ((n & 0x1f) << 12); 1302 - } 1303 - 1304 - static __inline tile_bundle_bits 1305 - create_UnOpcodeExtension_X1(int num) 1306 - { 1307 - const unsigned int n = (unsigned int)num; 1308 - return (((tile_bundle_bits)(n & 0x1f)) << 43); 1309 - } 1310 - 1311 - static __inline tile_bundle_bits 1312 - create_UnOpcodeExtension_Y0(int num) 1313 - { 1314 - const unsigned int n = (unsigned int)num; 1315 - return ((n & 0x1f) << 12); 1316 - } 1317 - 1318 - static __inline tile_bundle_bits 1319 - create_UnOpcodeExtension_Y1(int num) 1320 - { 1321 - const unsigned int n = (unsigned int)num; 1322 - return (((tile_bundle_bits)(n & 0x1f)) << 43); 1323 - } 1324 - 1325 - static __inline tile_bundle_bits 1326 - create_UnShOpcodeExtension_X0(int num) 1327 - { 1328 - const unsigned int n = (unsigned int)num; 1329 - return ((n & 0x3ff) << 17); 1330 - } 1331 - 1332 - static __inline tile_bundle_bits 1333 - create_UnShOpcodeExtension_X1(int num) 1334 - { 1335 - const unsigned int n = (unsigned int)num; 1336 - return (((tile_bundle_bits)(n & 0x3ff)) << 48); 1337 - } 1338 - 1339 - static __inline tile_bundle_bits 1340 - create_UnShOpcodeExtension_Y0(int num) 1341 - { 1342 - const unsigned int n = (unsigned int)num; 1343 - return ((n & 0x7) << 17); 1344 - } 1345 - 1346 - static __inline tile_bundle_bits 1347 - create_UnShOpcodeExtension_Y1(int num) 1348 - { 1349 - const unsigned int n = (unsigned int)num; 1350 - return (((tile_bundle_bits)(n & 0x7)) << 48); 1351 - } 1352 - 1353 - 1354 - 1355 - typedef enum 1356 - { 1357 - TILE_PIPELINE_X0, 1358 - TILE_PIPELINE_X1, 1359 - TILE_PIPELINE_Y0, 1360 - TILE_PIPELINE_Y1, 1361 - TILE_PIPELINE_Y2, 1362 - } tile_pipeline; 1363 - 1364 - #define tile_is_x_pipeline(p) ((int)(p) <= (int)TILE_PIPELINE_X1) 1365 - 1366 - typedef enum 1367 - { 1368 - TILE_OP_TYPE_REGISTER, 1369 - TILE_OP_TYPE_IMMEDIATE, 1370 - TILE_OP_TYPE_ADDRESS, 1371 - TILE_OP_TYPE_SPR 1372 - } tile_operand_type; 1373 - 1374 - /* This is the bit that determines if a bundle is in the Y encoding. */ 1375 - #define TILE_BUNDLE_Y_ENCODING_MASK ((tile_bundle_bits)1 << 63) 1376 - 1377 - enum 1378 - { 1379 - /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ 1380 - TILE_MAX_INSTRUCTIONS_PER_BUNDLE = 3, 1381 - 1382 - /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ 1383 - TILE_NUM_PIPELINE_ENCODINGS = 5, 1384 - 1385 - /* Log base 2 of TILE_BUNDLE_SIZE_IN_BYTES. */ 1386 - TILE_LOG2_BUNDLE_SIZE_IN_BYTES = 3, 1387 - 1388 - /* Instructions take this many bytes. */ 1389 - TILE_BUNDLE_SIZE_IN_BYTES = 1 << TILE_LOG2_BUNDLE_SIZE_IN_BYTES, 1390 - 1391 - /* Log base 2 of TILE_BUNDLE_ALIGNMENT_IN_BYTES. */ 1392 - TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, 1393 - 1394 - /* Bundles should be aligned modulo this number of bytes. */ 1395 - TILE_BUNDLE_ALIGNMENT_IN_BYTES = 1396 - (1 << TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), 1397 - 1398 - /* Log base 2 of TILE_SN_INSTRUCTION_SIZE_IN_BYTES. */ 1399 - TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1, 1400 - 1401 - /* Static network instructions take this many bytes. */ 1402 - TILE_SN_INSTRUCTION_SIZE_IN_BYTES = 1403 - (1 << TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES), 1404 - 1405 - /* Number of registers (some are magic, such as network I/O). */ 1406 - TILE_NUM_REGISTERS = 64, 1407 - 1408 - /* Number of static network registers. */ 1409 - TILE_NUM_SN_REGISTERS = 4 1410 - }; 1411 - 1412 - 1413 - struct tile_operand 1414 - { 1415 - /* Is this operand a register, immediate or address? */ 1416 - tile_operand_type type; 1417 - 1418 - /* The default relocation type for this operand. */ 1419 - signed int default_reloc : 16; 1420 - 1421 - /* How many bits is this value? (used for range checking) */ 1422 - unsigned int num_bits : 5; 1423 - 1424 - /* Is the value signed? (used for range checking) */ 1425 - unsigned int is_signed : 1; 1426 - 1427 - /* Is this operand a source register? */ 1428 - unsigned int is_src_reg : 1; 1429 - 1430 - /* Is this operand written? (i.e. is it a destination register) */ 1431 - unsigned int is_dest_reg : 1; 1432 - 1433 - /* Is this operand PC-relative? */ 1434 - unsigned int is_pc_relative : 1; 1435 - 1436 - /* By how many bits do we right shift the value before inserting? */ 1437 - unsigned int rightshift : 2; 1438 - 1439 - /* Return the bits for this operand to be ORed into an existing bundle. */ 1440 - tile_bundle_bits (*insert) (int op); 1441 - 1442 - /* Extract this operand and return it. */ 1443 - unsigned int (*extract) (tile_bundle_bits bundle); 1444 - }; 1445 - 1446 - 1447 - extern const struct tile_operand tile_operands[]; 1448 - 1449 - /* One finite-state machine per pipe for rapid instruction decoding. */ 1450 - extern const unsigned short * const 1451 - tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS]; 1452 - 1453 - 1454 - struct tile_opcode 1455 - { 1456 - /* The opcode mnemonic, e.g. "add" */ 1457 - const char *name; 1458 - 1459 - /* The enum value for this mnemonic. */ 1460 - tile_mnemonic mnemonic; 1461 - 1462 - /* A bit mask of which of the five pipes this instruction 1463 - is compatible with: 1464 - X0 0x01 1465 - X1 0x02 1466 - Y0 0x04 1467 - Y1 0x08 1468 - Y2 0x10 */ 1469 - unsigned char pipes; 1470 - 1471 - /* How many operands are there? */ 1472 - unsigned char num_operands; 1473 - 1474 - /* Which register does this write implicitly, or TREG_ZERO if none? */ 1475 - unsigned char implicitly_written_register; 1476 - 1477 - /* Can this be bundled with other instructions (almost always true). */ 1478 - unsigned char can_bundle; 1479 - 1480 - /* The description of the operands. Each of these is an 1481 - * index into the tile_operands[] table. */ 1482 - unsigned char operands[TILE_NUM_PIPELINE_ENCODINGS][TILE_MAX_OPERANDS]; 1483 - 1484 - }; 1485 - 1486 - extern const struct tile_opcode tile_opcodes[]; 1487 - 1488 - 1489 - /* Used for non-textual disassembly into structs. */ 1490 - struct tile_decoded_instruction 1491 - { 1492 - const struct tile_opcode *opcode; 1493 - const struct tile_operand *operands[TILE_MAX_OPERANDS]; 1494 - int operand_values[TILE_MAX_OPERANDS]; 1495 - }; 1496 - 1497 - 1498 - /* Disassemble a bundle into a struct for machine processing. */ 1499 - extern int parse_insn_tile(tile_bundle_bits bits, 1500 - unsigned int pc, 1501 - struct tile_decoded_instruction 1502 - decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]); 1503 - 1504 - 1505 - /* Given a set of bundle bits and a specific pipe, returns which 1506 - * instruction the bundle contains in that pipe. 1507 - */ 1508 - extern const struct tile_opcode * 1509 - find_opcode(tile_bundle_bits bits, tile_pipeline pipe); 1510 - 1511 - 1512 - 1513 - #endif /* opcode_tile_h */
-1248
arch/tile/include/asm/opcode-tile_64.h
··· 1 - /* tile.h -- Header file for TILE opcode table 2 - Copyright (C) 2005 Free Software Foundation, Inc. 3 - Contributed by Tilera Corp. */ 4 - 5 - #ifndef opcode_tile_h 6 - #define opcode_tile_h 7 - 8 - typedef unsigned long long tilegx_bundle_bits; 9 - 10 - 11 - enum 12 - { 13 - TILEGX_MAX_OPERANDS = 4 /* bfexts */ 14 - }; 15 - 16 - typedef enum 17 - { 18 - TILEGX_OPC_BPT, 19 - TILEGX_OPC_INFO, 20 - TILEGX_OPC_INFOL, 21 - TILEGX_OPC_MOVE, 22 - TILEGX_OPC_MOVEI, 23 - TILEGX_OPC_MOVELI, 24 - TILEGX_OPC_PREFETCH, 25 - TILEGX_OPC_PREFETCH_ADD_L1, 26 - TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 27 - TILEGX_OPC_PREFETCH_ADD_L2, 28 - TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 29 - TILEGX_OPC_PREFETCH_ADD_L3, 30 - TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 31 - TILEGX_OPC_PREFETCH_L1, 32 - TILEGX_OPC_PREFETCH_L1_FAULT, 33 - TILEGX_OPC_PREFETCH_L2, 34 - TILEGX_OPC_PREFETCH_L2_FAULT, 35 - TILEGX_OPC_PREFETCH_L3, 36 - TILEGX_OPC_PREFETCH_L3_FAULT, 37 - TILEGX_OPC_RAISE, 38 - TILEGX_OPC_ADD, 39 - TILEGX_OPC_ADDI, 40 - TILEGX_OPC_ADDLI, 41 - TILEGX_OPC_ADDX, 42 - TILEGX_OPC_ADDXI, 43 - TILEGX_OPC_ADDXLI, 44 - TILEGX_OPC_ADDXSC, 45 - TILEGX_OPC_AND, 46 - TILEGX_OPC_ANDI, 47 - TILEGX_OPC_BEQZ, 48 - TILEGX_OPC_BEQZT, 49 - TILEGX_OPC_BFEXTS, 50 - TILEGX_OPC_BFEXTU, 51 - TILEGX_OPC_BFINS, 52 - TILEGX_OPC_BGEZ, 53 - TILEGX_OPC_BGEZT, 54 - TILEGX_OPC_BGTZ, 55 - TILEGX_OPC_BGTZT, 56 - TILEGX_OPC_BLBC, 57 - TILEGX_OPC_BLBCT, 58 - TILEGX_OPC_BLBS, 59 - TILEGX_OPC_BLBST, 60 - TILEGX_OPC_BLEZ, 61 - TILEGX_OPC_BLEZT, 62 - TILEGX_OPC_BLTZ, 63 - TILEGX_OPC_BLTZT, 64 - TILEGX_OPC_BNEZ, 65 - TILEGX_OPC_BNEZT, 66 - TILEGX_OPC_CLZ, 67 - TILEGX_OPC_CMOVEQZ, 68 - TILEGX_OPC_CMOVNEZ, 69 - TILEGX_OPC_CMPEQ, 70 - TILEGX_OPC_CMPEQI, 71 - TILEGX_OPC_CMPEXCH, 72 - TILEGX_OPC_CMPEXCH4, 73 - TILEGX_OPC_CMPLES, 74 - TILEGX_OPC_CMPLEU, 75 - TILEGX_OPC_CMPLTS, 76 - TILEGX_OPC_CMPLTSI, 77 - TILEGX_OPC_CMPLTU, 78 - TILEGX_OPC_CMPLTUI, 79 - TILEGX_OPC_CMPNE, 80 - TILEGX_OPC_CMUL, 81 - TILEGX_OPC_CMULA, 82 - TILEGX_OPC_CMULAF, 83 - TILEGX_OPC_CMULF, 84 - TILEGX_OPC_CMULFR, 85 - TILEGX_OPC_CMULH, 86 - TILEGX_OPC_CMULHR, 87 - TILEGX_OPC_CRC32_32, 88 - TILEGX_OPC_CRC32_8, 89 - TILEGX_OPC_CTZ, 90 - TILEGX_OPC_DBLALIGN, 91 - TILEGX_OPC_DBLALIGN2, 92 - TILEGX_OPC_DBLALIGN4, 93 - TILEGX_OPC_DBLALIGN6, 94 - TILEGX_OPC_DRAIN, 95 - TILEGX_OPC_DTLBPR, 96 - TILEGX_OPC_EXCH, 97 - TILEGX_OPC_EXCH4, 98 - TILEGX_OPC_FDOUBLE_ADD_FLAGS, 99 - TILEGX_OPC_FDOUBLE_ADDSUB, 100 - TILEGX_OPC_FDOUBLE_MUL_FLAGS, 101 - TILEGX_OPC_FDOUBLE_PACK1, 102 - TILEGX_OPC_FDOUBLE_PACK2, 103 - TILEGX_OPC_FDOUBLE_SUB_FLAGS, 104 - TILEGX_OPC_FDOUBLE_UNPACK_MAX, 105 - TILEGX_OPC_FDOUBLE_UNPACK_MIN, 106 - TILEGX_OPC_FETCHADD, 107 - TILEGX_OPC_FETCHADD4, 108 - TILEGX_OPC_FETCHADDGEZ, 109 - TILEGX_OPC_FETCHADDGEZ4, 110 - TILEGX_OPC_FETCHAND, 111 - TILEGX_OPC_FETCHAND4, 112 - TILEGX_OPC_FETCHOR, 113 - TILEGX_OPC_FETCHOR4, 114 - TILEGX_OPC_FINV, 115 - TILEGX_OPC_FLUSH, 116 - TILEGX_OPC_FLUSHWB, 117 - TILEGX_OPC_FNOP, 118 - TILEGX_OPC_FSINGLE_ADD1, 119 - TILEGX_OPC_FSINGLE_ADDSUB2, 120 - TILEGX_OPC_FSINGLE_MUL1, 121 - TILEGX_OPC_FSINGLE_MUL2, 122 - TILEGX_OPC_FSINGLE_PACK1, 123 - TILEGX_OPC_FSINGLE_PACK2, 124 - TILEGX_OPC_FSINGLE_SUB1, 125 - TILEGX_OPC_ICOH, 126 - TILEGX_OPC_ILL, 127 - TILEGX_OPC_INV, 128 - TILEGX_OPC_IRET, 129 - TILEGX_OPC_J, 130 - TILEGX_OPC_JAL, 131 - TILEGX_OPC_JALR, 132 - TILEGX_OPC_JALRP, 133 - TILEGX_OPC_JR, 134 - TILEGX_OPC_JRP, 135 - TILEGX_OPC_LD, 136 - TILEGX_OPC_LD1S, 137 - TILEGX_OPC_LD1S_ADD, 138 - TILEGX_OPC_LD1U, 139 - TILEGX_OPC_LD1U_ADD, 140 - TILEGX_OPC_LD2S, 141 - TILEGX_OPC_LD2S_ADD, 142 - TILEGX_OPC_LD2U, 143 - TILEGX_OPC_LD2U_ADD, 144 - TILEGX_OPC_LD4S, 145 - TILEGX_OPC_LD4S_ADD, 146 - TILEGX_OPC_LD4U, 147 - TILEGX_OPC_LD4U_ADD, 148 - TILEGX_OPC_LD_ADD, 149 - TILEGX_OPC_LDNA, 150 - TILEGX_OPC_LDNA_ADD, 151 - TILEGX_OPC_LDNT, 152 - TILEGX_OPC_LDNT1S, 153 - TILEGX_OPC_LDNT1S_ADD, 154 - TILEGX_OPC_LDNT1U, 155 - TILEGX_OPC_LDNT1U_ADD, 156 - TILEGX_OPC_LDNT2S, 157 - TILEGX_OPC_LDNT2S_ADD, 158 - TILEGX_OPC_LDNT2U, 159 - TILEGX_OPC_LDNT2U_ADD, 160 - TILEGX_OPC_LDNT4S, 161 - TILEGX_OPC_LDNT4S_ADD, 162 - TILEGX_OPC_LDNT4U, 163 - TILEGX_OPC_LDNT4U_ADD, 164 - TILEGX_OPC_LDNT_ADD, 165 - TILEGX_OPC_LNK, 166 - TILEGX_OPC_MF, 167 - TILEGX_OPC_MFSPR, 168 - TILEGX_OPC_MM, 169 - TILEGX_OPC_MNZ, 170 - TILEGX_OPC_MTSPR, 171 - TILEGX_OPC_MUL_HS_HS, 172 - TILEGX_OPC_MUL_HS_HU, 173 - TILEGX_OPC_MUL_HS_LS, 174 - TILEGX_OPC_MUL_HS_LU, 175 - TILEGX_OPC_MUL_HU_HU, 176 - TILEGX_OPC_MUL_HU_LS, 177 - TILEGX_OPC_MUL_HU_LU, 178 - TILEGX_OPC_MUL_LS_LS, 179 - TILEGX_OPC_MUL_LS_LU, 180 - TILEGX_OPC_MUL_LU_LU, 181 - TILEGX_OPC_MULA_HS_HS, 182 - TILEGX_OPC_MULA_HS_HU, 183 - TILEGX_OPC_MULA_HS_LS, 184 - TILEGX_OPC_MULA_HS_LU, 185 - TILEGX_OPC_MULA_HU_HU, 186 - TILEGX_OPC_MULA_HU_LS, 187 - TILEGX_OPC_MULA_HU_LU, 188 - TILEGX_OPC_MULA_LS_LS, 189 - TILEGX_OPC_MULA_LS_LU, 190 - TILEGX_OPC_MULA_LU_LU, 191 - TILEGX_OPC_MULAX, 192 - TILEGX_OPC_MULX, 193 - TILEGX_OPC_MZ, 194 - TILEGX_OPC_NAP, 195 - TILEGX_OPC_NOP, 196 - TILEGX_OPC_NOR, 197 - TILEGX_OPC_OR, 198 - TILEGX_OPC_ORI, 199 - TILEGX_OPC_PCNT, 200 - TILEGX_OPC_REVBITS, 201 - TILEGX_OPC_REVBYTES, 202 - TILEGX_OPC_ROTL, 203 - TILEGX_OPC_ROTLI, 204 - TILEGX_OPC_SHL, 205 - TILEGX_OPC_SHL16INSLI, 206 - TILEGX_OPC_SHL1ADD, 207 - TILEGX_OPC_SHL1ADDX, 208 - TILEGX_OPC_SHL2ADD, 209 - TILEGX_OPC_SHL2ADDX, 210 - TILEGX_OPC_SHL3ADD, 211 - TILEGX_OPC_SHL3ADDX, 212 - TILEGX_OPC_SHLI, 213 - TILEGX_OPC_SHLX, 214 - TILEGX_OPC_SHLXI, 215 - TILEGX_OPC_SHRS, 216 - TILEGX_OPC_SHRSI, 217 - TILEGX_OPC_SHRU, 218 - TILEGX_OPC_SHRUI, 219 - TILEGX_OPC_SHRUX, 220 - TILEGX_OPC_SHRUXI, 221 - TILEGX_OPC_SHUFFLEBYTES, 222 - TILEGX_OPC_ST, 223 - TILEGX_OPC_ST1, 224 - TILEGX_OPC_ST1_ADD, 225 - TILEGX_OPC_ST2, 226 - TILEGX_OPC_ST2_ADD, 227 - TILEGX_OPC_ST4, 228 - TILEGX_OPC_ST4_ADD, 229 - TILEGX_OPC_ST_ADD, 230 - TILEGX_OPC_STNT, 231 - TILEGX_OPC_STNT1, 232 - TILEGX_OPC_STNT1_ADD, 233 - TILEGX_OPC_STNT2, 234 - TILEGX_OPC_STNT2_ADD, 235 - TILEGX_OPC_STNT4, 236 - TILEGX_OPC_STNT4_ADD, 237 - TILEGX_OPC_STNT_ADD, 238 - TILEGX_OPC_SUB, 239 - TILEGX_OPC_SUBX, 240 - TILEGX_OPC_SUBXSC, 241 - TILEGX_OPC_SWINT0, 242 - TILEGX_OPC_SWINT1, 243 - TILEGX_OPC_SWINT2, 244 - TILEGX_OPC_SWINT3, 245 - TILEGX_OPC_TBLIDXB0, 246 - TILEGX_OPC_TBLIDXB1, 247 - TILEGX_OPC_TBLIDXB2, 248 - TILEGX_OPC_TBLIDXB3, 249 - TILEGX_OPC_V1ADD, 250 - TILEGX_OPC_V1ADDI, 251 - TILEGX_OPC_V1ADDUC, 252 - TILEGX_OPC_V1ADIFFU, 253 - TILEGX_OPC_V1AVGU, 254 - TILEGX_OPC_V1CMPEQ, 255 - TILEGX_OPC_V1CMPEQI, 256 - TILEGX_OPC_V1CMPLES, 257 - TILEGX_OPC_V1CMPLEU, 258 - TILEGX_OPC_V1CMPLTS, 259 - TILEGX_OPC_V1CMPLTSI, 260 - TILEGX_OPC_V1CMPLTU, 261 - TILEGX_OPC_V1CMPLTUI, 262 - TILEGX_OPC_V1CMPNE, 263 - TILEGX_OPC_V1DDOTPU, 264 - TILEGX_OPC_V1DDOTPUA, 265 - TILEGX_OPC_V1DDOTPUS, 266 - TILEGX_OPC_V1DDOTPUSA, 267 - TILEGX_OPC_V1DOTP, 268 - TILEGX_OPC_V1DOTPA, 269 - TILEGX_OPC_V1DOTPU, 270 - TILEGX_OPC_V1DOTPUA, 271 - TILEGX_OPC_V1DOTPUS, 272 - TILEGX_OPC_V1DOTPUSA, 273 - TILEGX_OPC_V1INT_H, 274 - TILEGX_OPC_V1INT_L, 275 - TILEGX_OPC_V1MAXU, 276 - TILEGX_OPC_V1MAXUI, 277 - TILEGX_OPC_V1MINU, 278 - TILEGX_OPC_V1MINUI, 279 - TILEGX_OPC_V1MNZ, 280 - TILEGX_OPC_V1MULTU, 281 - TILEGX_OPC_V1MULU, 282 - TILEGX_OPC_V1MULUS, 283 - TILEGX_OPC_V1MZ, 284 - TILEGX_OPC_V1SADAU, 285 - TILEGX_OPC_V1SADU, 286 - TILEGX_OPC_V1SHL, 287 - TILEGX_OPC_V1SHLI, 288 - TILEGX_OPC_V1SHRS, 289 - TILEGX_OPC_V1SHRSI, 290 - TILEGX_OPC_V1SHRU, 291 - TILEGX_OPC_V1SHRUI, 292 - TILEGX_OPC_V1SUB, 293 - TILEGX_OPC_V1SUBUC, 294 - TILEGX_OPC_V2ADD, 295 - TILEGX_OPC_V2ADDI, 296 - TILEGX_OPC_V2ADDSC, 297 - TILEGX_OPC_V2ADIFFS, 298 - TILEGX_OPC_V2AVGS, 299 - TILEGX_OPC_V2CMPEQ, 300 - TILEGX_OPC_V2CMPEQI, 301 - TILEGX_OPC_V2CMPLES, 302 - TILEGX_OPC_V2CMPLEU, 303 - TILEGX_OPC_V2CMPLTS, 304 - TILEGX_OPC_V2CMPLTSI, 305 - TILEGX_OPC_V2CMPLTU, 306 - TILEGX_OPC_V2CMPLTUI, 307 - TILEGX_OPC_V2CMPNE, 308 - TILEGX_OPC_V2DOTP, 309 - TILEGX_OPC_V2DOTPA, 310 - TILEGX_OPC_V2INT_H, 311 - TILEGX_OPC_V2INT_L, 312 - TILEGX_OPC_V2MAXS, 313 - TILEGX_OPC_V2MAXSI, 314 - TILEGX_OPC_V2MINS, 315 - TILEGX_OPC_V2MINSI, 316 - TILEGX_OPC_V2MNZ, 317 - TILEGX_OPC_V2MULFSC, 318 - TILEGX_OPC_V2MULS, 319 - TILEGX_OPC_V2MULTS, 320 - TILEGX_OPC_V2MZ, 321 - TILEGX_OPC_V2PACKH, 322 - TILEGX_OPC_V2PACKL, 323 - TILEGX_OPC_V2PACKUC, 324 - TILEGX_OPC_V2SADAS, 325 - TILEGX_OPC_V2SADAU, 326 - TILEGX_OPC_V2SADS, 327 - TILEGX_OPC_V2SADU, 328 - TILEGX_OPC_V2SHL, 329 - TILEGX_OPC_V2SHLI, 330 - TILEGX_OPC_V2SHLSC, 331 - TILEGX_OPC_V2SHRS, 332 - TILEGX_OPC_V2SHRSI, 333 - TILEGX_OPC_V2SHRU, 334 - TILEGX_OPC_V2SHRUI, 335 - TILEGX_OPC_V2SUB, 336 - TILEGX_OPC_V2SUBSC, 337 - TILEGX_OPC_V4ADD, 338 - TILEGX_OPC_V4ADDSC, 339 - TILEGX_OPC_V4INT_H, 340 - TILEGX_OPC_V4INT_L, 341 - TILEGX_OPC_V4PACKSC, 342 - TILEGX_OPC_V4SHL, 343 - TILEGX_OPC_V4SHLSC, 344 - TILEGX_OPC_V4SHRS, 345 - TILEGX_OPC_V4SHRU, 346 - TILEGX_OPC_V4SUB, 347 - TILEGX_OPC_V4SUBSC, 348 - TILEGX_OPC_WH64, 349 - TILEGX_OPC_XOR, 350 - TILEGX_OPC_XORI, 351 - TILEGX_OPC_NONE 352 - } tilegx_mnemonic; 353 - 354 - /* 64-bit pattern for a { bpt ; nop } bundle. */ 355 - #define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL 356 - 357 - 358 - #define TILE_ELF_MACHINE_CODE EM_TILE64 359 - 360 - #define TILE_ELF_NAME "elf32-tile64" 361 - 362 - 363 - static __inline unsigned int 364 - get_BFEnd_X0(tilegx_bundle_bits num) 365 - { 366 - const unsigned int n = (unsigned int)num; 367 - return (((n >> 12)) & 0x3f); 368 - } 369 - 370 - static __inline unsigned int 371 - get_BFOpcodeExtension_X0(tilegx_bundle_bits num) 372 - { 373 - const unsigned int n = (unsigned int)num; 374 - return (((n >> 24)) & 0xf); 375 - } 376 - 377 - static __inline unsigned int 378 - get_BFStart_X0(tilegx_bundle_bits num) 379 - { 380 - const unsigned int n = (unsigned int)num; 381 - return (((n >> 18)) & 0x3f); 382 - } 383 - 384 - static __inline unsigned int 385 - get_BrOff_X1(tilegx_bundle_bits n) 386 - { 387 - return (((unsigned int)(n >> 31)) & 0x0000003f) | 388 - (((unsigned int)(n >> 37)) & 0x0001ffc0); 389 - } 390 - 391 - static __inline unsigned int 392 - get_BrType_X1(tilegx_bundle_bits n) 393 - { 394 - return (((unsigned int)(n >> 54)) & 0x1f); 395 - } 396 - 397 - static __inline unsigned int 398 - get_Dest_Imm8_X1(tilegx_bundle_bits n) 399 - { 400 - return (((unsigned int)(n >> 31)) & 0x0000003f) | 401 - (((unsigned int)(n >> 43)) & 0x000000c0); 402 - } 403 - 404 - static __inline unsigned int 405 - get_Dest_X0(tilegx_bundle_bits num) 406 - { 407 - const unsigned int n = (unsigned int)num; 408 - return (((n >> 0)) & 0x3f); 409 - } 410 - 411 - static __inline unsigned int 412 - get_Dest_X1(tilegx_bundle_bits n) 413 - { 414 - return (((unsigned int)(n >> 31)) & 0x3f); 415 - } 416 - 417 - static __inline unsigned int 418 - get_Dest_Y0(tilegx_bundle_bits num) 419 - { 420 - const unsigned int n = (unsigned int)num; 421 - return (((n >> 0)) & 0x3f); 422 - } 423 - 424 - static __inline unsigned int 425 - get_Dest_Y1(tilegx_bundle_bits n) 426 - { 427 - return (((unsigned int)(n >> 31)) & 0x3f); 428 - } 429 - 430 - static __inline unsigned int 431 - get_Imm16_X0(tilegx_bundle_bits num) 432 - { 433 - const unsigned int n = (unsigned int)num; 434 - return (((n >> 12)) & 0xffff); 435 - } 436 - 437 - static __inline unsigned int 438 - get_Imm16_X1(tilegx_bundle_bits n) 439 - { 440 - return (((unsigned int)(n >> 43)) & 0xffff); 441 - } 442 - 443 - static __inline unsigned int 444 - get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num) 445 - { 446 - const unsigned int n = (unsigned int)num; 447 - return (((n >> 20)) & 0xff); 448 - } 449 - 450 - static __inline unsigned int 451 - get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n) 452 - { 453 - return (((unsigned int)(n >> 51)) & 0xff); 454 - } 455 - 456 - static __inline unsigned int 457 - get_Imm8_X0(tilegx_bundle_bits num) 458 - { 459 - const unsigned int n = (unsigned int)num; 460 - return (((n >> 12)) & 0xff); 461 - } 462 - 463 - static __inline unsigned int 464 - get_Imm8_X1(tilegx_bundle_bits n) 465 - { 466 - return (((unsigned int)(n >> 43)) & 0xff); 467 - } 468 - 469 - static __inline unsigned int 470 - get_Imm8_Y0(tilegx_bundle_bits num) 471 - { 472 - const unsigned int n = (unsigned int)num; 473 - return (((n >> 12)) & 0xff); 474 - } 475 - 476 - static __inline unsigned int 477 - get_Imm8_Y1(tilegx_bundle_bits n) 478 - { 479 - return (((unsigned int)(n >> 43)) & 0xff); 480 - } 481 - 482 - static __inline unsigned int 483 - get_JumpOff_X1(tilegx_bundle_bits n) 484 - { 485 - return (((unsigned int)(n >> 31)) & 0x7ffffff); 486 - } 487 - 488 - static __inline unsigned int 489 - get_JumpOpcodeExtension_X1(tilegx_bundle_bits n) 490 - { 491 - return (((unsigned int)(n >> 58)) & 0x1); 492 - } 493 - 494 - static __inline unsigned int 495 - get_MF_Imm14_X1(tilegx_bundle_bits n) 496 - { 497 - return (((unsigned int)(n >> 37)) & 0x3fff); 498 - } 499 - 500 - static __inline unsigned int 501 - get_MT_Imm14_X1(tilegx_bundle_bits n) 502 - { 503 - return (((unsigned int)(n >> 31)) & 0x0000003f) | 504 - (((unsigned int)(n >> 37)) & 0x00003fc0); 505 - } 506 - 507 - static __inline unsigned int 508 - get_Mode(tilegx_bundle_bits n) 509 - { 510 - return (((unsigned int)(n >> 62)) & 0x3); 511 - } 512 - 513 - static __inline unsigned int 514 - get_Opcode_X0(tilegx_bundle_bits num) 515 - { 516 - const unsigned int n = (unsigned int)num; 517 - return (((n >> 28)) & 0x7); 518 - } 519 - 520 - static __inline unsigned int 521 - get_Opcode_X1(tilegx_bundle_bits n) 522 - { 523 - return (((unsigned int)(n >> 59)) & 0x7); 524 - } 525 - 526 - static __inline unsigned int 527 - get_Opcode_Y0(tilegx_bundle_bits num) 528 - { 529 - const unsigned int n = (unsigned int)num; 530 - return (((n >> 27)) & 0xf); 531 - } 532 - 533 - static __inline unsigned int 534 - get_Opcode_Y1(tilegx_bundle_bits n) 535 - { 536 - return (((unsigned int)(n >> 58)) & 0xf); 537 - } 538 - 539 - static __inline unsigned int 540 - get_Opcode_Y2(tilegx_bundle_bits n) 541 - { 542 - return (((n >> 26)) & 0x00000001) | 543 - (((unsigned int)(n >> 56)) & 0x00000002); 544 - } 545 - 546 - static __inline unsigned int 547 - get_RRROpcodeExtension_X0(tilegx_bundle_bits num) 548 - { 549 - const unsigned int n = (unsigned int)num; 550 - return (((n >> 18)) & 0x3ff); 551 - } 552 - 553 - static __inline unsigned int 554 - get_RRROpcodeExtension_X1(tilegx_bundle_bits n) 555 - { 556 - return (((unsigned int)(n >> 49)) & 0x3ff); 557 - } 558 - 559 - static __inline unsigned int 560 - get_RRROpcodeExtension_Y0(tilegx_bundle_bits num) 561 - { 562 - const unsigned int n = (unsigned int)num; 563 - return (((n >> 18)) & 0x3); 564 - } 565 - 566 - static __inline unsigned int 567 - get_RRROpcodeExtension_Y1(tilegx_bundle_bits n) 568 - { 569 - return (((unsigned int)(n >> 49)) & 0x3); 570 - } 571 - 572 - static __inline unsigned int 573 - get_ShAmt_X0(tilegx_bundle_bits num) 574 - { 575 - const unsigned int n = (unsigned int)num; 576 - return (((n >> 12)) & 0x3f); 577 - } 578 - 579 - static __inline unsigned int 580 - get_ShAmt_X1(tilegx_bundle_bits n) 581 - { 582 - return (((unsigned int)(n >> 43)) & 0x3f); 583 - } 584 - 585 - static __inline unsigned int 586 - get_ShAmt_Y0(tilegx_bundle_bits num) 587 - { 588 - const unsigned int n = (unsigned int)num; 589 - return (((n >> 12)) & 0x3f); 590 - } 591 - 592 - static __inline unsigned int 593 - get_ShAmt_Y1(tilegx_bundle_bits n) 594 - { 595 - return (((unsigned int)(n >> 43)) & 0x3f); 596 - } 597 - 598 - static __inline unsigned int 599 - get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num) 600 - { 601 - const unsigned int n = (unsigned int)num; 602 - return (((n >> 18)) & 0x3ff); 603 - } 604 - 605 - static __inline unsigned int 606 - get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n) 607 - { 608 - return (((unsigned int)(n >> 49)) & 0x3ff); 609 - } 610 - 611 - static __inline unsigned int 612 - get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num) 613 - { 614 - const unsigned int n = (unsigned int)num; 615 - return (((n >> 18)) & 0x3); 616 - } 617 - 618 - static __inline unsigned int 619 - get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n) 620 - { 621 - return (((unsigned int)(n >> 49)) & 0x3); 622 - } 623 - 624 - static __inline unsigned int 625 - get_SrcA_X0(tilegx_bundle_bits num) 626 - { 627 - const unsigned int n = (unsigned int)num; 628 - return (((n >> 6)) & 0x3f); 629 - } 630 - 631 - static __inline unsigned int 632 - get_SrcA_X1(tilegx_bundle_bits n) 633 - { 634 - return (((unsigned int)(n >> 37)) & 0x3f); 635 - } 636 - 637 - static __inline unsigned int 638 - get_SrcA_Y0(tilegx_bundle_bits num) 639 - { 640 - const unsigned int n = (unsigned int)num; 641 - return (((n >> 6)) & 0x3f); 642 - } 643 - 644 - static __inline unsigned int 645 - get_SrcA_Y1(tilegx_bundle_bits n) 646 - { 647 - return (((unsigned int)(n >> 37)) & 0x3f); 648 - } 649 - 650 - static __inline unsigned int 651 - get_SrcA_Y2(tilegx_bundle_bits num) 652 - { 653 - const unsigned int n = (unsigned int)num; 654 - return (((n >> 20)) & 0x3f); 655 - } 656 - 657 - static __inline unsigned int 658 - get_SrcBDest_Y2(tilegx_bundle_bits n) 659 - { 660 - return (((unsigned int)(n >> 51)) & 0x3f); 661 - } 662 - 663 - static __inline unsigned int 664 - get_SrcB_X0(tilegx_bundle_bits num) 665 - { 666 - const unsigned int n = (unsigned int)num; 667 - return (((n >> 12)) & 0x3f); 668 - } 669 - 670 - static __inline unsigned int 671 - get_SrcB_X1(tilegx_bundle_bits n) 672 - { 673 - return (((unsigned int)(n >> 43)) & 0x3f); 674 - } 675 - 676 - static __inline unsigned int 677 - get_SrcB_Y0(tilegx_bundle_bits num) 678 - { 679 - const unsigned int n = (unsigned int)num; 680 - return (((n >> 12)) & 0x3f); 681 - } 682 - 683 - static __inline unsigned int 684 - get_SrcB_Y1(tilegx_bundle_bits n) 685 - { 686 - return (((unsigned int)(n >> 43)) & 0x3f); 687 - } 688 - 689 - static __inline unsigned int 690 - get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num) 691 - { 692 - const unsigned int n = (unsigned int)num; 693 - return (((n >> 12)) & 0x3f); 694 - } 695 - 696 - static __inline unsigned int 697 - get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n) 698 - { 699 - return (((unsigned int)(n >> 43)) & 0x3f); 700 - } 701 - 702 - static __inline unsigned int 703 - get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num) 704 - { 705 - const unsigned int n = (unsigned int)num; 706 - return (((n >> 12)) & 0x3f); 707 - } 708 - 709 - static __inline unsigned int 710 - get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n) 711 - { 712 - return (((unsigned int)(n >> 43)) & 0x3f); 713 - } 714 - 715 - 716 - static __inline int 717 - sign_extend(int n, int num_bits) 718 - { 719 - int shift = (int)(sizeof(int) * 8 - num_bits); 720 - return (n << shift) >> shift; 721 - } 722 - 723 - 724 - 725 - static __inline tilegx_bundle_bits 726 - create_BFEnd_X0(int num) 727 - { 728 - const unsigned int n = (unsigned int)num; 729 - return ((n & 0x3f) << 12); 730 - } 731 - 732 - static __inline tilegx_bundle_bits 733 - create_BFOpcodeExtension_X0(int num) 734 - { 735 - const unsigned int n = (unsigned int)num; 736 - return ((n & 0xf) << 24); 737 - } 738 - 739 - static __inline tilegx_bundle_bits 740 - create_BFStart_X0(int num) 741 - { 742 - const unsigned int n = (unsigned int)num; 743 - return ((n & 0x3f) << 18); 744 - } 745 - 746 - static __inline tilegx_bundle_bits 747 - create_BrOff_X1(int num) 748 - { 749 - const unsigned int n = (unsigned int)num; 750 - return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | 751 - (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37); 752 - } 753 - 754 - static __inline tilegx_bundle_bits 755 - create_BrType_X1(int num) 756 - { 757 - const unsigned int n = (unsigned int)num; 758 - return (((tilegx_bundle_bits)(n & 0x1f)) << 54); 759 - } 760 - 761 - static __inline tilegx_bundle_bits 762 - create_Dest_Imm8_X1(int num) 763 - { 764 - const unsigned int n = (unsigned int)num; 765 - return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | 766 - (((tilegx_bundle_bits)(n & 0x000000c0)) << 43); 767 - } 768 - 769 - static __inline tilegx_bundle_bits 770 - create_Dest_X0(int num) 771 - { 772 - const unsigned int n = (unsigned int)num; 773 - return ((n & 0x3f) << 0); 774 - } 775 - 776 - static __inline tilegx_bundle_bits 777 - create_Dest_X1(int num) 778 - { 779 - const unsigned int n = (unsigned int)num; 780 - return (((tilegx_bundle_bits)(n & 0x3f)) << 31); 781 - } 782 - 783 - static __inline tilegx_bundle_bits 784 - create_Dest_Y0(int num) 785 - { 786 - const unsigned int n = (unsigned int)num; 787 - return ((n & 0x3f) << 0); 788 - } 789 - 790 - static __inline tilegx_bundle_bits 791 - create_Dest_Y1(int num) 792 - { 793 - const unsigned int n = (unsigned int)num; 794 - return (((tilegx_bundle_bits)(n & 0x3f)) << 31); 795 - } 796 - 797 - static __inline tilegx_bundle_bits 798 - create_Imm16_X0(int num) 799 - { 800 - const unsigned int n = (unsigned int)num; 801 - return ((n & 0xffff) << 12); 802 - } 803 - 804 - static __inline tilegx_bundle_bits 805 - create_Imm16_X1(int num) 806 - { 807 - const unsigned int n = (unsigned int)num; 808 - return (((tilegx_bundle_bits)(n & 0xffff)) << 43); 809 - } 810 - 811 - static __inline tilegx_bundle_bits 812 - create_Imm8OpcodeExtension_X0(int num) 813 - { 814 - const unsigned int n = (unsigned int)num; 815 - return ((n & 0xff) << 20); 816 - } 817 - 818 - static __inline tilegx_bundle_bits 819 - create_Imm8OpcodeExtension_X1(int num) 820 - { 821 - const unsigned int n = (unsigned int)num; 822 - return (((tilegx_bundle_bits)(n & 0xff)) << 51); 823 - } 824 - 825 - static __inline tilegx_bundle_bits 826 - create_Imm8_X0(int num) 827 - { 828 - const unsigned int n = (unsigned int)num; 829 - return ((n & 0xff) << 12); 830 - } 831 - 832 - static __inline tilegx_bundle_bits 833 - create_Imm8_X1(int num) 834 - { 835 - const unsigned int n = (unsigned int)num; 836 - return (((tilegx_bundle_bits)(n & 0xff)) << 43); 837 - } 838 - 839 - static __inline tilegx_bundle_bits 840 - create_Imm8_Y0(int num) 841 - { 842 - const unsigned int n = (unsigned int)num; 843 - return ((n & 0xff) << 12); 844 - } 845 - 846 - static __inline tilegx_bundle_bits 847 - create_Imm8_Y1(int num) 848 - { 849 - const unsigned int n = (unsigned int)num; 850 - return (((tilegx_bundle_bits)(n & 0xff)) << 43); 851 - } 852 - 853 - static __inline tilegx_bundle_bits 854 - create_JumpOff_X1(int num) 855 - { 856 - const unsigned int n = (unsigned int)num; 857 - return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31); 858 - } 859 - 860 - static __inline tilegx_bundle_bits 861 - create_JumpOpcodeExtension_X1(int num) 862 - { 863 - const unsigned int n = (unsigned int)num; 864 - return (((tilegx_bundle_bits)(n & 0x1)) << 58); 865 - } 866 - 867 - static __inline tilegx_bundle_bits 868 - create_MF_Imm14_X1(int num) 869 - { 870 - const unsigned int n = (unsigned int)num; 871 - return (((tilegx_bundle_bits)(n & 0x3fff)) << 37); 872 - } 873 - 874 - static __inline tilegx_bundle_bits 875 - create_MT_Imm14_X1(int num) 876 - { 877 - const unsigned int n = (unsigned int)num; 878 - return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | 879 - (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37); 880 - } 881 - 882 - static __inline tilegx_bundle_bits 883 - create_Mode(int num) 884 - { 885 - const unsigned int n = (unsigned int)num; 886 - return (((tilegx_bundle_bits)(n & 0x3)) << 62); 887 - } 888 - 889 - static __inline tilegx_bundle_bits 890 - create_Opcode_X0(int num) 891 - { 892 - const unsigned int n = (unsigned int)num; 893 - return ((n & 0x7) << 28); 894 - } 895 - 896 - static __inline tilegx_bundle_bits 897 - create_Opcode_X1(int num) 898 - { 899 - const unsigned int n = (unsigned int)num; 900 - return (((tilegx_bundle_bits)(n & 0x7)) << 59); 901 - } 902 - 903 - static __inline tilegx_bundle_bits 904 - create_Opcode_Y0(int num) 905 - { 906 - const unsigned int n = (unsigned int)num; 907 - return ((n & 0xf) << 27); 908 - } 909 - 910 - static __inline tilegx_bundle_bits 911 - create_Opcode_Y1(int num) 912 - { 913 - const unsigned int n = (unsigned int)num; 914 - return (((tilegx_bundle_bits)(n & 0xf)) << 58); 915 - } 916 - 917 - static __inline tilegx_bundle_bits 918 - create_Opcode_Y2(int num) 919 - { 920 - const unsigned int n = (unsigned int)num; 921 - return ((n & 0x00000001) << 26) | 922 - (((tilegx_bundle_bits)(n & 0x00000002)) << 56); 923 - } 924 - 925 - static __inline tilegx_bundle_bits 926 - create_RRROpcodeExtension_X0(int num) 927 - { 928 - const unsigned int n = (unsigned int)num; 929 - return ((n & 0x3ff) << 18); 930 - } 931 - 932 - static __inline tilegx_bundle_bits 933 - create_RRROpcodeExtension_X1(int num) 934 - { 935 - const unsigned int n = (unsigned int)num; 936 - return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); 937 - } 938 - 939 - static __inline tilegx_bundle_bits 940 - create_RRROpcodeExtension_Y0(int num) 941 - { 942 - const unsigned int n = (unsigned int)num; 943 - return ((n & 0x3) << 18); 944 - } 945 - 946 - static __inline tilegx_bundle_bits 947 - create_RRROpcodeExtension_Y1(int num) 948 - { 949 - const unsigned int n = (unsigned int)num; 950 - return (((tilegx_bundle_bits)(n & 0x3)) << 49); 951 - } 952 - 953 - static __inline tilegx_bundle_bits 954 - create_ShAmt_X0(int num) 955 - { 956 - const unsigned int n = (unsigned int)num; 957 - return ((n & 0x3f) << 12); 958 - } 959 - 960 - static __inline tilegx_bundle_bits 961 - create_ShAmt_X1(int num) 962 - { 963 - const unsigned int n = (unsigned int)num; 964 - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); 965 - } 966 - 967 - static __inline tilegx_bundle_bits 968 - create_ShAmt_Y0(int num) 969 - { 970 - const unsigned int n = (unsigned int)num; 971 - return ((n & 0x3f) << 12); 972 - } 973 - 974 - static __inline tilegx_bundle_bits 975 - create_ShAmt_Y1(int num) 976 - { 977 - const unsigned int n = (unsigned int)num; 978 - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); 979 - } 980 - 981 - static __inline tilegx_bundle_bits 982 - create_ShiftOpcodeExtension_X0(int num) 983 - { 984 - const unsigned int n = (unsigned int)num; 985 - return ((n & 0x3ff) << 18); 986 - } 987 - 988 - static __inline tilegx_bundle_bits 989 - create_ShiftOpcodeExtension_X1(int num) 990 - { 991 - const unsigned int n = (unsigned int)num; 992 - return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); 993 - } 994 - 995 - static __inline tilegx_bundle_bits 996 - create_ShiftOpcodeExtension_Y0(int num) 997 - { 998 - const unsigned int n = (unsigned int)num; 999 - return ((n & 0x3) << 18); 1000 - } 1001 - 1002 - static __inline tilegx_bundle_bits 1003 - create_ShiftOpcodeExtension_Y1(int num) 1004 - { 1005 - const unsigned int n = (unsigned int)num; 1006 - return (((tilegx_bundle_bits)(n & 0x3)) << 49); 1007 - } 1008 - 1009 - static __inline tilegx_bundle_bits 1010 - create_SrcA_X0(int num) 1011 - { 1012 - const unsigned int n = (unsigned int)num; 1013 - return ((n & 0x3f) << 6); 1014 - } 1015 - 1016 - static __inline tilegx_bundle_bits 1017 - create_SrcA_X1(int num) 1018 - { 1019 - const unsigned int n = (unsigned int)num; 1020 - return (((tilegx_bundle_bits)(n & 0x3f)) << 37); 1021 - } 1022 - 1023 - static __inline tilegx_bundle_bits 1024 - create_SrcA_Y0(int num) 1025 - { 1026 - const unsigned int n = (unsigned int)num; 1027 - return ((n & 0x3f) << 6); 1028 - } 1029 - 1030 - static __inline tilegx_bundle_bits 1031 - create_SrcA_Y1(int num) 1032 - { 1033 - const unsigned int n = (unsigned int)num; 1034 - return (((tilegx_bundle_bits)(n & 0x3f)) << 37); 1035 - } 1036 - 1037 - static __inline tilegx_bundle_bits 1038 - create_SrcA_Y2(int num) 1039 - { 1040 - const unsigned int n = (unsigned int)num; 1041 - return ((n & 0x3f) << 20); 1042 - } 1043 - 1044 - static __inline tilegx_bundle_bits 1045 - create_SrcBDest_Y2(int num) 1046 - { 1047 - const unsigned int n = (unsigned int)num; 1048 - return (((tilegx_bundle_bits)(n & 0x3f)) << 51); 1049 - } 1050 - 1051 - static __inline tilegx_bundle_bits 1052 - create_SrcB_X0(int num) 1053 - { 1054 - const unsigned int n = (unsigned int)num; 1055 - return ((n & 0x3f) << 12); 1056 - } 1057 - 1058 - static __inline tilegx_bundle_bits 1059 - create_SrcB_X1(int num) 1060 - { 1061 - const unsigned int n = (unsigned int)num; 1062 - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); 1063 - } 1064 - 1065 - static __inline tilegx_bundle_bits 1066 - create_SrcB_Y0(int num) 1067 - { 1068 - const unsigned int n = (unsigned int)num; 1069 - return ((n & 0x3f) << 12); 1070 - } 1071 - 1072 - static __inline tilegx_bundle_bits 1073 - create_SrcB_Y1(int num) 1074 - { 1075 - const unsigned int n = (unsigned int)num; 1076 - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); 1077 - } 1078 - 1079 - static __inline tilegx_bundle_bits 1080 - create_UnaryOpcodeExtension_X0(int num) 1081 - { 1082 - const unsigned int n = (unsigned int)num; 1083 - return ((n & 0x3f) << 12); 1084 - } 1085 - 1086 - static __inline tilegx_bundle_bits 1087 - create_UnaryOpcodeExtension_X1(int num) 1088 - { 1089 - const unsigned int n = (unsigned int)num; 1090 - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); 1091 - } 1092 - 1093 - static __inline tilegx_bundle_bits 1094 - create_UnaryOpcodeExtension_Y0(int num) 1095 - { 1096 - const unsigned int n = (unsigned int)num; 1097 - return ((n & 0x3f) << 12); 1098 - } 1099 - 1100 - static __inline tilegx_bundle_bits 1101 - create_UnaryOpcodeExtension_Y1(int num) 1102 - { 1103 - const unsigned int n = (unsigned int)num; 1104 - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); 1105 - } 1106 - 1107 - 1108 - typedef enum 1109 - { 1110 - TILEGX_PIPELINE_X0, 1111 - TILEGX_PIPELINE_X1, 1112 - TILEGX_PIPELINE_Y0, 1113 - TILEGX_PIPELINE_Y1, 1114 - TILEGX_PIPELINE_Y2, 1115 - } tilegx_pipeline; 1116 - 1117 - #define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1) 1118 - 1119 - typedef enum 1120 - { 1121 - TILEGX_OP_TYPE_REGISTER, 1122 - TILEGX_OP_TYPE_IMMEDIATE, 1123 - TILEGX_OP_TYPE_ADDRESS, 1124 - TILEGX_OP_TYPE_SPR 1125 - } tilegx_operand_type; 1126 - 1127 - /* These are the bits that determine if a bundle is in the X encoding. */ 1128 - #define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62) 1129 - 1130 - enum 1131 - { 1132 - /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ 1133 - TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3, 1134 - 1135 - /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ 1136 - TILEGX_NUM_PIPELINE_ENCODINGS = 5, 1137 - 1138 - /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */ 1139 - TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3, 1140 - 1141 - /* Instructions take this many bytes. */ 1142 - TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES, 1143 - 1144 - /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */ 1145 - TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, 1146 - 1147 - /* Bundles should be aligned modulo this number of bytes. */ 1148 - TILEGX_BUNDLE_ALIGNMENT_IN_BYTES = 1149 - (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), 1150 - 1151 - /* Number of registers (some are magic, such as network I/O). */ 1152 - TILEGX_NUM_REGISTERS = 64, 1153 - }; 1154 - 1155 - 1156 - struct tilegx_operand 1157 - { 1158 - /* Is this operand a register, immediate or address? */ 1159 - tilegx_operand_type type; 1160 - 1161 - /* The default relocation type for this operand. */ 1162 - signed int default_reloc : 16; 1163 - 1164 - /* How many bits is this value? (used for range checking) */ 1165 - unsigned int num_bits : 5; 1166 - 1167 - /* Is the value signed? (used for range checking) */ 1168 - unsigned int is_signed : 1; 1169 - 1170 - /* Is this operand a source register? */ 1171 - unsigned int is_src_reg : 1; 1172 - 1173 - /* Is this operand written? (i.e. is it a destination register) */ 1174 - unsigned int is_dest_reg : 1; 1175 - 1176 - /* Is this operand PC-relative? */ 1177 - unsigned int is_pc_relative : 1; 1178 - 1179 - /* By how many bits do we right shift the value before inserting? */ 1180 - unsigned int rightshift : 2; 1181 - 1182 - /* Return the bits for this operand to be ORed into an existing bundle. */ 1183 - tilegx_bundle_bits (*insert) (int op); 1184 - 1185 - /* Extract this operand and return it. */ 1186 - unsigned int (*extract) (tilegx_bundle_bits bundle); 1187 - }; 1188 - 1189 - 1190 - extern const struct tilegx_operand tilegx_operands[]; 1191 - 1192 - /* One finite-state machine per pipe for rapid instruction decoding. */ 1193 - extern const unsigned short * const 1194 - tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS]; 1195 - 1196 - 1197 - struct tilegx_opcode 1198 - { 1199 - /* The opcode mnemonic, e.g. "add" */ 1200 - const char *name; 1201 - 1202 - /* The enum value for this mnemonic. */ 1203 - tilegx_mnemonic mnemonic; 1204 - 1205 - /* A bit mask of which of the five pipes this instruction 1206 - is compatible with: 1207 - X0 0x01 1208 - X1 0x02 1209 - Y0 0x04 1210 - Y1 0x08 1211 - Y2 0x10 */ 1212 - unsigned char pipes; 1213 - 1214 - /* How many operands are there? */ 1215 - unsigned char num_operands; 1216 - 1217 - /* Which register does this write implicitly, or TREG_ZERO if none? */ 1218 - unsigned char implicitly_written_register; 1219 - 1220 - /* Can this be bundled with other instructions (almost always true). */ 1221 - unsigned char can_bundle; 1222 - 1223 - /* The description of the operands. Each of these is an 1224 - * index into the tilegx_operands[] table. */ 1225 - unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS]; 1226 - 1227 - }; 1228 - 1229 - extern const struct tilegx_opcode tilegx_opcodes[]; 1230 - 1231 - /* Used for non-textual disassembly into structs. */ 1232 - struct tilegx_decoded_instruction 1233 - { 1234 - const struct tilegx_opcode *opcode; 1235 - const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS]; 1236 - long long operand_values[TILEGX_MAX_OPERANDS]; 1237 - }; 1238 - 1239 - 1240 - /* Disassemble a bundle into a struct for machine processing. */ 1241 - extern int parse_insn_tilegx(tilegx_bundle_bits bits, 1242 - unsigned long long pc, 1243 - struct tilegx_decoded_instruction 1244 - decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]); 1245 - 1246 - 1247 - 1248 - #endif /* opcode_tilegx_h */
+4 -11
arch/tile/include/asm/opcode_constants.h arch/tile/include/asm/tile-desc.h
··· 1 1 /* 2 - * Copyright 2010 Tilera Corporation. All Rights Reserved. 2 + * Copyright 2011 Tilera Corporation. All Rights Reserved. 3 3 * 4 4 * This program is free software; you can redistribute it and/or 5 5 * modify it under the terms of the GNU General Public License ··· 12 12 * more details. 13 13 */ 14 14 15 - #ifndef _ASM_TILE_OPCODE_CONSTANTS_H 16 - #define _ASM_TILE_OPCODE_CONSTANTS_H 17 - 18 - #include <arch/chip.h> 19 - 20 - #if CHIP_WORD_SIZE() == 64 21 - #include <asm/opcode_constants_64.h> 15 + #ifndef __tilegx__ 16 + #include <asm/tile-desc_32.h> 22 17 #else 23 - #include <asm/opcode_constants_32.h> 18 + #include <asm/tile-desc_64.h> 24 19 #endif 25 - 26 - #endif /* _ASM_TILE_OPCODE_CONSTANTS_H */
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arch/tile/include/asm/opcode_constants_32.h
··· 1 - /* 2 - * Copyright 2010 Tilera Corporation. All Rights Reserved. 3 - * 4 - * This program is free software; you can redistribute it and/or 5 - * modify it under the terms of the GNU General Public License 6 - * as published by the Free Software Foundation, version 2. 7 - * 8 - * This program is distributed in the hope that it will be useful, but 9 - * WITHOUT ANY WARRANTY; without even the implied warranty of 10 - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 - * NON INFRINGEMENT. See the GNU General Public License for 12 - * more details. 13 - */ 14 - 15 - /* This file is machine-generated; DO NOT EDIT! */ 16 - 17 - 18 - #ifndef _TILE_OPCODE_CONSTANTS_H 19 - #define _TILE_OPCODE_CONSTANTS_H 20 - enum 21 - { 22 - ADDBS_U_SPECIAL_0_OPCODE_X0 = 98, 23 - ADDBS_U_SPECIAL_0_OPCODE_X1 = 68, 24 - ADDB_SPECIAL_0_OPCODE_X0 = 1, 25 - ADDB_SPECIAL_0_OPCODE_X1 = 1, 26 - ADDHS_SPECIAL_0_OPCODE_X0 = 99, 27 - ADDHS_SPECIAL_0_OPCODE_X1 = 69, 28 - ADDH_SPECIAL_0_OPCODE_X0 = 2, 29 - ADDH_SPECIAL_0_OPCODE_X1 = 2, 30 - ADDIB_IMM_0_OPCODE_X0 = 1, 31 - ADDIB_IMM_0_OPCODE_X1 = 1, 32 - ADDIH_IMM_0_OPCODE_X0 = 2, 33 - ADDIH_IMM_0_OPCODE_X1 = 2, 34 - ADDI_IMM_0_OPCODE_X0 = 3, 35 - ADDI_IMM_0_OPCODE_X1 = 3, 36 - ADDI_IMM_1_OPCODE_SN = 1, 37 - ADDI_OPCODE_Y0 = 9, 38 - ADDI_OPCODE_Y1 = 7, 39 - ADDLIS_OPCODE_X0 = 1, 40 - ADDLIS_OPCODE_X1 = 2, 41 - ADDLI_OPCODE_X0 = 2, 42 - ADDLI_OPCODE_X1 = 3, 43 - ADDS_SPECIAL_0_OPCODE_X0 = 96, 44 - ADDS_SPECIAL_0_OPCODE_X1 = 66, 45 - ADD_SPECIAL_0_OPCODE_X0 = 3, 46 - ADD_SPECIAL_0_OPCODE_X1 = 3, 47 - ADD_SPECIAL_0_OPCODE_Y0 = 0, 48 - ADD_SPECIAL_0_OPCODE_Y1 = 0, 49 - ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4, 50 - ADIFFH_SPECIAL_0_OPCODE_X0 = 5, 51 - ANDI_IMM_0_OPCODE_X0 = 1, 52 - ANDI_IMM_0_OPCODE_X1 = 4, 53 - ANDI_OPCODE_Y0 = 10, 54 - ANDI_OPCODE_Y1 = 8, 55 - AND_SPECIAL_0_OPCODE_X0 = 6, 56 - AND_SPECIAL_0_OPCODE_X1 = 4, 57 - AND_SPECIAL_2_OPCODE_Y0 = 0, 58 - AND_SPECIAL_2_OPCODE_Y1 = 0, 59 - AULI_OPCODE_X0 = 3, 60 - AULI_OPCODE_X1 = 4, 61 - AVGB_U_SPECIAL_0_OPCODE_X0 = 7, 62 - AVGH_SPECIAL_0_OPCODE_X0 = 8, 63 - BBNST_BRANCH_OPCODE_X1 = 15, 64 - BBNS_BRANCH_OPCODE_X1 = 14, 65 - BBNS_OPCODE_SN = 63, 66 - BBST_BRANCH_OPCODE_X1 = 13, 67 - BBS_BRANCH_OPCODE_X1 = 12, 68 - BBS_OPCODE_SN = 62, 69 - BGEZT_BRANCH_OPCODE_X1 = 7, 70 - BGEZ_BRANCH_OPCODE_X1 = 6, 71 - BGEZ_OPCODE_SN = 61, 72 - BGZT_BRANCH_OPCODE_X1 = 5, 73 - BGZ_BRANCH_OPCODE_X1 = 4, 74 - BGZ_OPCODE_SN = 58, 75 - BITX_UN_0_SHUN_0_OPCODE_X0 = 1, 76 - BITX_UN_0_SHUN_0_OPCODE_Y0 = 1, 77 - BLEZT_BRANCH_OPCODE_X1 = 11, 78 - BLEZ_BRANCH_OPCODE_X1 = 10, 79 - BLEZ_OPCODE_SN = 59, 80 - BLZT_BRANCH_OPCODE_X1 = 9, 81 - BLZ_BRANCH_OPCODE_X1 = 8, 82 - BLZ_OPCODE_SN = 60, 83 - BNZT_BRANCH_OPCODE_X1 = 3, 84 - BNZ_BRANCH_OPCODE_X1 = 2, 85 - BNZ_OPCODE_SN = 57, 86 - BPT_NOREG_RR_IMM_0_OPCODE_SN = 1, 87 - BRANCH_OPCODE_X1 = 5, 88 - BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2, 89 - BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2, 90 - BZT_BRANCH_OPCODE_X1 = 1, 91 - BZ_BRANCH_OPCODE_X1 = 0, 92 - BZ_OPCODE_SN = 56, 93 - CLZ_UN_0_SHUN_0_OPCODE_X0 = 3, 94 - CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3, 95 - CRC32_32_SPECIAL_0_OPCODE_X0 = 9, 96 - CRC32_8_SPECIAL_0_OPCODE_X0 = 10, 97 - CTZ_UN_0_SHUN_0_OPCODE_X0 = 4, 98 - CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4, 99 - DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1, 100 - DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2, 101 - DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95, 102 - FINV_UN_0_SHUN_0_OPCODE_X1 = 3, 103 - FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4, 104 - FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3, 105 - FNOP_UN_0_SHUN_0_OPCODE_X0 = 5, 106 - FNOP_UN_0_SHUN_0_OPCODE_X1 = 5, 107 - FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5, 108 - FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1, 109 - HALT_NOREG_RR_IMM_0_OPCODE_SN = 0, 110 - ICOH_UN_0_SHUN_0_OPCODE_X1 = 6, 111 - ILL_UN_0_SHUN_0_OPCODE_X1 = 7, 112 - ILL_UN_0_SHUN_0_OPCODE_Y1 = 2, 113 - IMM_0_OPCODE_SN = 0, 114 - IMM_0_OPCODE_X0 = 4, 115 - IMM_0_OPCODE_X1 = 6, 116 - IMM_1_OPCODE_SN = 1, 117 - IMM_OPCODE_0_X0 = 5, 118 - INTHB_SPECIAL_0_OPCODE_X0 = 11, 119 - INTHB_SPECIAL_0_OPCODE_X1 = 5, 120 - INTHH_SPECIAL_0_OPCODE_X0 = 12, 121 - INTHH_SPECIAL_0_OPCODE_X1 = 6, 122 - INTLB_SPECIAL_0_OPCODE_X0 = 13, 123 - INTLB_SPECIAL_0_OPCODE_X1 = 7, 124 - INTLH_SPECIAL_0_OPCODE_X0 = 14, 125 - INTLH_SPECIAL_0_OPCODE_X1 = 8, 126 - INV_UN_0_SHUN_0_OPCODE_X1 = 8, 127 - IRET_UN_0_SHUN_0_OPCODE_X1 = 9, 128 - JALB_OPCODE_X1 = 13, 129 - JALF_OPCODE_X1 = 12, 130 - JALRP_SPECIAL_0_OPCODE_X1 = 9, 131 - JALRR_IMM_1_OPCODE_SN = 3, 132 - JALR_RR_IMM_0_OPCODE_SN = 5, 133 - JALR_SPECIAL_0_OPCODE_X1 = 10, 134 - JB_OPCODE_X1 = 11, 135 - JF_OPCODE_X1 = 10, 136 - JRP_SPECIAL_0_OPCODE_X1 = 11, 137 - JRR_IMM_1_OPCODE_SN = 2, 138 - JR_RR_IMM_0_OPCODE_SN = 4, 139 - JR_SPECIAL_0_OPCODE_X1 = 12, 140 - LBADD_IMM_0_OPCODE_X1 = 22, 141 - LBADD_U_IMM_0_OPCODE_X1 = 23, 142 - LB_OPCODE_Y2 = 0, 143 - LB_UN_0_SHUN_0_OPCODE_X1 = 10, 144 - LB_U_OPCODE_Y2 = 1, 145 - LB_U_UN_0_SHUN_0_OPCODE_X1 = 11, 146 - LHADD_IMM_0_OPCODE_X1 = 24, 147 - LHADD_U_IMM_0_OPCODE_X1 = 25, 148 - LH_OPCODE_Y2 = 2, 149 - LH_UN_0_SHUN_0_OPCODE_X1 = 12, 150 - LH_U_OPCODE_Y2 = 3, 151 - LH_U_UN_0_SHUN_0_OPCODE_X1 = 13, 152 - LNK_SPECIAL_0_OPCODE_X1 = 13, 153 - LWADD_IMM_0_OPCODE_X1 = 26, 154 - LWADD_NA_IMM_0_OPCODE_X1 = 27, 155 - LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24, 156 - LW_OPCODE_Y2 = 4, 157 - LW_UN_0_SHUN_0_OPCODE_X1 = 14, 158 - MAXB_U_SPECIAL_0_OPCODE_X0 = 15, 159 - MAXB_U_SPECIAL_0_OPCODE_X1 = 14, 160 - MAXH_SPECIAL_0_OPCODE_X0 = 16, 161 - MAXH_SPECIAL_0_OPCODE_X1 = 15, 162 - MAXIB_U_IMM_0_OPCODE_X0 = 4, 163 - MAXIB_U_IMM_0_OPCODE_X1 = 5, 164 - MAXIH_IMM_0_OPCODE_X0 = 5, 165 - MAXIH_IMM_0_OPCODE_X1 = 6, 166 - MFSPR_IMM_0_OPCODE_X1 = 7, 167 - MF_UN_0_SHUN_0_OPCODE_X1 = 15, 168 - MINB_U_SPECIAL_0_OPCODE_X0 = 17, 169 - MINB_U_SPECIAL_0_OPCODE_X1 = 16, 170 - MINH_SPECIAL_0_OPCODE_X0 = 18, 171 - MINH_SPECIAL_0_OPCODE_X1 = 17, 172 - MINIB_U_IMM_0_OPCODE_X0 = 6, 173 - MINIB_U_IMM_0_OPCODE_X1 = 8, 174 - MINIH_IMM_0_OPCODE_X0 = 7, 175 - MINIH_IMM_0_OPCODE_X1 = 9, 176 - MM_OPCODE_X0 = 6, 177 - MM_OPCODE_X1 = 7, 178 - MNZB_SPECIAL_0_OPCODE_X0 = 19, 179 - MNZB_SPECIAL_0_OPCODE_X1 = 18, 180 - MNZH_SPECIAL_0_OPCODE_X0 = 20, 181 - MNZH_SPECIAL_0_OPCODE_X1 = 19, 182 - MNZ_SPECIAL_0_OPCODE_X0 = 21, 183 - MNZ_SPECIAL_0_OPCODE_X1 = 20, 184 - MNZ_SPECIAL_1_OPCODE_Y0 = 0, 185 - MNZ_SPECIAL_1_OPCODE_Y1 = 1, 186 - MOVEI_IMM_1_OPCODE_SN = 0, 187 - MOVE_RR_IMM_0_OPCODE_SN = 8, 188 - MTSPR_IMM_0_OPCODE_X1 = 10, 189 - MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22, 190 - MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0, 191 - MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23, 192 - MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24, 193 - MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1, 194 - MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25, 195 - MULHH_SS_SPECIAL_0_OPCODE_X0 = 26, 196 - MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0, 197 - MULHH_SU_SPECIAL_0_OPCODE_X0 = 27, 198 - MULHH_UU_SPECIAL_0_OPCODE_X0 = 28, 199 - MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1, 200 - MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29, 201 - MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30, 202 - MULHLA_US_SPECIAL_0_OPCODE_X0 = 31, 203 - MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32, 204 - MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33, 205 - MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0, 206 - MULHL_SS_SPECIAL_0_OPCODE_X0 = 34, 207 - MULHL_SU_SPECIAL_0_OPCODE_X0 = 35, 208 - MULHL_US_SPECIAL_0_OPCODE_X0 = 36, 209 - MULHL_UU_SPECIAL_0_OPCODE_X0 = 37, 210 - MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38, 211 - MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2, 212 - MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39, 213 - MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40, 214 - MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3, 215 - MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41, 216 - MULLL_SS_SPECIAL_0_OPCODE_X0 = 42, 217 - MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2, 218 - MULLL_SU_SPECIAL_0_OPCODE_X0 = 43, 219 - MULLL_UU_SPECIAL_0_OPCODE_X0 = 44, 220 - MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3, 221 - MVNZ_SPECIAL_0_OPCODE_X0 = 45, 222 - MVNZ_SPECIAL_1_OPCODE_Y0 = 1, 223 - MVZ_SPECIAL_0_OPCODE_X0 = 46, 224 - MVZ_SPECIAL_1_OPCODE_Y0 = 2, 225 - MZB_SPECIAL_0_OPCODE_X0 = 47, 226 - MZB_SPECIAL_0_OPCODE_X1 = 21, 227 - MZH_SPECIAL_0_OPCODE_X0 = 48, 228 - MZH_SPECIAL_0_OPCODE_X1 = 22, 229 - MZ_SPECIAL_0_OPCODE_X0 = 49, 230 - MZ_SPECIAL_0_OPCODE_X1 = 23, 231 - MZ_SPECIAL_1_OPCODE_Y0 = 3, 232 - MZ_SPECIAL_1_OPCODE_Y1 = 2, 233 - NAP_UN_0_SHUN_0_OPCODE_X1 = 16, 234 - NOP_NOREG_RR_IMM_0_OPCODE_SN = 2, 235 - NOP_UN_0_SHUN_0_OPCODE_X0 = 6, 236 - NOP_UN_0_SHUN_0_OPCODE_X1 = 17, 237 - NOP_UN_0_SHUN_0_OPCODE_Y0 = 6, 238 - NOP_UN_0_SHUN_0_OPCODE_Y1 = 3, 239 - NOREG_RR_IMM_0_OPCODE_SN = 0, 240 - NOR_SPECIAL_0_OPCODE_X0 = 50, 241 - NOR_SPECIAL_0_OPCODE_X1 = 24, 242 - NOR_SPECIAL_2_OPCODE_Y0 = 1, 243 - NOR_SPECIAL_2_OPCODE_Y1 = 1, 244 - ORI_IMM_0_OPCODE_X0 = 8, 245 - ORI_IMM_0_OPCODE_X1 = 11, 246 - ORI_OPCODE_Y0 = 11, 247 - ORI_OPCODE_Y1 = 9, 248 - OR_SPECIAL_0_OPCODE_X0 = 51, 249 - OR_SPECIAL_0_OPCODE_X1 = 25, 250 - OR_SPECIAL_2_OPCODE_Y0 = 2, 251 - OR_SPECIAL_2_OPCODE_Y1 = 2, 252 - PACKBS_U_SPECIAL_0_OPCODE_X0 = 103, 253 - PACKBS_U_SPECIAL_0_OPCODE_X1 = 73, 254 - PACKHB_SPECIAL_0_OPCODE_X0 = 52, 255 - PACKHB_SPECIAL_0_OPCODE_X1 = 26, 256 - PACKHS_SPECIAL_0_OPCODE_X0 = 102, 257 - PACKHS_SPECIAL_0_OPCODE_X1 = 72, 258 - PACKLB_SPECIAL_0_OPCODE_X0 = 53, 259 - PACKLB_SPECIAL_0_OPCODE_X1 = 27, 260 - PCNT_UN_0_SHUN_0_OPCODE_X0 = 7, 261 - PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7, 262 - RLI_SHUN_0_OPCODE_X0 = 1, 263 - RLI_SHUN_0_OPCODE_X1 = 1, 264 - RLI_SHUN_0_OPCODE_Y0 = 1, 265 - RLI_SHUN_0_OPCODE_Y1 = 1, 266 - RL_SPECIAL_0_OPCODE_X0 = 54, 267 - RL_SPECIAL_0_OPCODE_X1 = 28, 268 - RL_SPECIAL_3_OPCODE_Y0 = 0, 269 - RL_SPECIAL_3_OPCODE_Y1 = 0, 270 - RR_IMM_0_OPCODE_SN = 0, 271 - S1A_SPECIAL_0_OPCODE_X0 = 55, 272 - S1A_SPECIAL_0_OPCODE_X1 = 29, 273 - S1A_SPECIAL_0_OPCODE_Y0 = 1, 274 - S1A_SPECIAL_0_OPCODE_Y1 = 1, 275 - S2A_SPECIAL_0_OPCODE_X0 = 56, 276 - S2A_SPECIAL_0_OPCODE_X1 = 30, 277 - S2A_SPECIAL_0_OPCODE_Y0 = 2, 278 - S2A_SPECIAL_0_OPCODE_Y1 = 2, 279 - S3A_SPECIAL_0_OPCODE_X0 = 57, 280 - S3A_SPECIAL_0_OPCODE_X1 = 31, 281 - S3A_SPECIAL_5_OPCODE_Y0 = 1, 282 - S3A_SPECIAL_5_OPCODE_Y1 = 1, 283 - SADAB_U_SPECIAL_0_OPCODE_X0 = 58, 284 - SADAH_SPECIAL_0_OPCODE_X0 = 59, 285 - SADAH_U_SPECIAL_0_OPCODE_X0 = 60, 286 - SADB_U_SPECIAL_0_OPCODE_X0 = 61, 287 - SADH_SPECIAL_0_OPCODE_X0 = 62, 288 - SADH_U_SPECIAL_0_OPCODE_X0 = 63, 289 - SBADD_IMM_0_OPCODE_X1 = 28, 290 - SB_OPCODE_Y2 = 5, 291 - SB_SPECIAL_0_OPCODE_X1 = 32, 292 - SEQB_SPECIAL_0_OPCODE_X0 = 64, 293 - SEQB_SPECIAL_0_OPCODE_X1 = 33, 294 - SEQH_SPECIAL_0_OPCODE_X0 = 65, 295 - SEQH_SPECIAL_0_OPCODE_X1 = 34, 296 - SEQIB_IMM_0_OPCODE_X0 = 9, 297 - SEQIB_IMM_0_OPCODE_X1 = 12, 298 - SEQIH_IMM_0_OPCODE_X0 = 10, 299 - SEQIH_IMM_0_OPCODE_X1 = 13, 300 - SEQI_IMM_0_OPCODE_X0 = 11, 301 - SEQI_IMM_0_OPCODE_X1 = 14, 302 - SEQI_OPCODE_Y0 = 12, 303 - SEQI_OPCODE_Y1 = 10, 304 - SEQ_SPECIAL_0_OPCODE_X0 = 66, 305 - SEQ_SPECIAL_0_OPCODE_X1 = 35, 306 - SEQ_SPECIAL_5_OPCODE_Y0 = 2, 307 - SEQ_SPECIAL_5_OPCODE_Y1 = 2, 308 - SHADD_IMM_0_OPCODE_X1 = 29, 309 - SHL8II_IMM_0_OPCODE_SN = 3, 310 - SHLB_SPECIAL_0_OPCODE_X0 = 67, 311 - SHLB_SPECIAL_0_OPCODE_X1 = 36, 312 - SHLH_SPECIAL_0_OPCODE_X0 = 68, 313 - SHLH_SPECIAL_0_OPCODE_X1 = 37, 314 - SHLIB_SHUN_0_OPCODE_X0 = 2, 315 - SHLIB_SHUN_0_OPCODE_X1 = 2, 316 - SHLIH_SHUN_0_OPCODE_X0 = 3, 317 - SHLIH_SHUN_0_OPCODE_X1 = 3, 318 - SHLI_SHUN_0_OPCODE_X0 = 4, 319 - SHLI_SHUN_0_OPCODE_X1 = 4, 320 - SHLI_SHUN_0_OPCODE_Y0 = 2, 321 - SHLI_SHUN_0_OPCODE_Y1 = 2, 322 - SHL_SPECIAL_0_OPCODE_X0 = 69, 323 - SHL_SPECIAL_0_OPCODE_X1 = 38, 324 - SHL_SPECIAL_3_OPCODE_Y0 = 1, 325 - SHL_SPECIAL_3_OPCODE_Y1 = 1, 326 - SHR1_RR_IMM_0_OPCODE_SN = 9, 327 - SHRB_SPECIAL_0_OPCODE_X0 = 70, 328 - SHRB_SPECIAL_0_OPCODE_X1 = 39, 329 - SHRH_SPECIAL_0_OPCODE_X0 = 71, 330 - SHRH_SPECIAL_0_OPCODE_X1 = 40, 331 - SHRIB_SHUN_0_OPCODE_X0 = 5, 332 - SHRIB_SHUN_0_OPCODE_X1 = 5, 333 - SHRIH_SHUN_0_OPCODE_X0 = 6, 334 - SHRIH_SHUN_0_OPCODE_X1 = 6, 335 - SHRI_SHUN_0_OPCODE_X0 = 7, 336 - SHRI_SHUN_0_OPCODE_X1 = 7, 337 - SHRI_SHUN_0_OPCODE_Y0 = 3, 338 - SHRI_SHUN_0_OPCODE_Y1 = 3, 339 - SHR_SPECIAL_0_OPCODE_X0 = 72, 340 - SHR_SPECIAL_0_OPCODE_X1 = 41, 341 - SHR_SPECIAL_3_OPCODE_Y0 = 2, 342 - SHR_SPECIAL_3_OPCODE_Y1 = 2, 343 - SHUN_0_OPCODE_X0 = 7, 344 - SHUN_0_OPCODE_X1 = 8, 345 - SHUN_0_OPCODE_Y0 = 13, 346 - SHUN_0_OPCODE_Y1 = 11, 347 - SH_OPCODE_Y2 = 6, 348 - SH_SPECIAL_0_OPCODE_X1 = 42, 349 - SLTB_SPECIAL_0_OPCODE_X0 = 73, 350 - SLTB_SPECIAL_0_OPCODE_X1 = 43, 351 - SLTB_U_SPECIAL_0_OPCODE_X0 = 74, 352 - SLTB_U_SPECIAL_0_OPCODE_X1 = 44, 353 - SLTEB_SPECIAL_0_OPCODE_X0 = 75, 354 - SLTEB_SPECIAL_0_OPCODE_X1 = 45, 355 - SLTEB_U_SPECIAL_0_OPCODE_X0 = 76, 356 - SLTEB_U_SPECIAL_0_OPCODE_X1 = 46, 357 - SLTEH_SPECIAL_0_OPCODE_X0 = 77, 358 - SLTEH_SPECIAL_0_OPCODE_X1 = 47, 359 - SLTEH_U_SPECIAL_0_OPCODE_X0 = 78, 360 - SLTEH_U_SPECIAL_0_OPCODE_X1 = 48, 361 - SLTE_SPECIAL_0_OPCODE_X0 = 79, 362 - SLTE_SPECIAL_0_OPCODE_X1 = 49, 363 - SLTE_SPECIAL_4_OPCODE_Y0 = 0, 364 - SLTE_SPECIAL_4_OPCODE_Y1 = 0, 365 - SLTE_U_SPECIAL_0_OPCODE_X0 = 80, 366 - SLTE_U_SPECIAL_0_OPCODE_X1 = 50, 367 - SLTE_U_SPECIAL_4_OPCODE_Y0 = 1, 368 - SLTE_U_SPECIAL_4_OPCODE_Y1 = 1, 369 - SLTH_SPECIAL_0_OPCODE_X0 = 81, 370 - SLTH_SPECIAL_0_OPCODE_X1 = 51, 371 - SLTH_U_SPECIAL_0_OPCODE_X0 = 82, 372 - SLTH_U_SPECIAL_0_OPCODE_X1 = 52, 373 - SLTIB_IMM_0_OPCODE_X0 = 12, 374 - SLTIB_IMM_0_OPCODE_X1 = 15, 375 - SLTIB_U_IMM_0_OPCODE_X0 = 13, 376 - SLTIB_U_IMM_0_OPCODE_X1 = 16, 377 - SLTIH_IMM_0_OPCODE_X0 = 14, 378 - SLTIH_IMM_0_OPCODE_X1 = 17, 379 - SLTIH_U_IMM_0_OPCODE_X0 = 15, 380 - SLTIH_U_IMM_0_OPCODE_X1 = 18, 381 - SLTI_IMM_0_OPCODE_X0 = 16, 382 - SLTI_IMM_0_OPCODE_X1 = 19, 383 - SLTI_OPCODE_Y0 = 14, 384 - SLTI_OPCODE_Y1 = 12, 385 - SLTI_U_IMM_0_OPCODE_X0 = 17, 386 - SLTI_U_IMM_0_OPCODE_X1 = 20, 387 - SLTI_U_OPCODE_Y0 = 15, 388 - SLTI_U_OPCODE_Y1 = 13, 389 - SLT_SPECIAL_0_OPCODE_X0 = 83, 390 - SLT_SPECIAL_0_OPCODE_X1 = 53, 391 - SLT_SPECIAL_4_OPCODE_Y0 = 2, 392 - SLT_SPECIAL_4_OPCODE_Y1 = 2, 393 - SLT_U_SPECIAL_0_OPCODE_X0 = 84, 394 - SLT_U_SPECIAL_0_OPCODE_X1 = 54, 395 - SLT_U_SPECIAL_4_OPCODE_Y0 = 3, 396 - SLT_U_SPECIAL_4_OPCODE_Y1 = 3, 397 - SNEB_SPECIAL_0_OPCODE_X0 = 85, 398 - SNEB_SPECIAL_0_OPCODE_X1 = 55, 399 - SNEH_SPECIAL_0_OPCODE_X0 = 86, 400 - SNEH_SPECIAL_0_OPCODE_X1 = 56, 401 - SNE_SPECIAL_0_OPCODE_X0 = 87, 402 - SNE_SPECIAL_0_OPCODE_X1 = 57, 403 - SNE_SPECIAL_5_OPCODE_Y0 = 3, 404 - SNE_SPECIAL_5_OPCODE_Y1 = 3, 405 - SPECIAL_0_OPCODE_X0 = 0, 406 - SPECIAL_0_OPCODE_X1 = 1, 407 - SPECIAL_0_OPCODE_Y0 = 1, 408 - SPECIAL_0_OPCODE_Y1 = 1, 409 - SPECIAL_1_OPCODE_Y0 = 2, 410 - SPECIAL_1_OPCODE_Y1 = 2, 411 - SPECIAL_2_OPCODE_Y0 = 3, 412 - SPECIAL_2_OPCODE_Y1 = 3, 413 - SPECIAL_3_OPCODE_Y0 = 4, 414 - SPECIAL_3_OPCODE_Y1 = 4, 415 - SPECIAL_4_OPCODE_Y0 = 5, 416 - SPECIAL_4_OPCODE_Y1 = 5, 417 - SPECIAL_5_OPCODE_Y0 = 6, 418 - SPECIAL_5_OPCODE_Y1 = 6, 419 - SPECIAL_6_OPCODE_Y0 = 7, 420 - SPECIAL_7_OPCODE_Y0 = 8, 421 - SRAB_SPECIAL_0_OPCODE_X0 = 88, 422 - SRAB_SPECIAL_0_OPCODE_X1 = 58, 423 - SRAH_SPECIAL_0_OPCODE_X0 = 89, 424 - SRAH_SPECIAL_0_OPCODE_X1 = 59, 425 - SRAIB_SHUN_0_OPCODE_X0 = 8, 426 - SRAIB_SHUN_0_OPCODE_X1 = 8, 427 - SRAIH_SHUN_0_OPCODE_X0 = 9, 428 - SRAIH_SHUN_0_OPCODE_X1 = 9, 429 - SRAI_SHUN_0_OPCODE_X0 = 10, 430 - SRAI_SHUN_0_OPCODE_X1 = 10, 431 - SRAI_SHUN_0_OPCODE_Y0 = 4, 432 - SRAI_SHUN_0_OPCODE_Y1 = 4, 433 - SRA_SPECIAL_0_OPCODE_X0 = 90, 434 - SRA_SPECIAL_0_OPCODE_X1 = 60, 435 - SRA_SPECIAL_3_OPCODE_Y0 = 3, 436 - SRA_SPECIAL_3_OPCODE_Y1 = 3, 437 - SUBBS_U_SPECIAL_0_OPCODE_X0 = 100, 438 - SUBBS_U_SPECIAL_0_OPCODE_X1 = 70, 439 - SUBB_SPECIAL_0_OPCODE_X0 = 91, 440 - SUBB_SPECIAL_0_OPCODE_X1 = 61, 441 - SUBHS_SPECIAL_0_OPCODE_X0 = 101, 442 - SUBHS_SPECIAL_0_OPCODE_X1 = 71, 443 - SUBH_SPECIAL_0_OPCODE_X0 = 92, 444 - SUBH_SPECIAL_0_OPCODE_X1 = 62, 445 - SUBS_SPECIAL_0_OPCODE_X0 = 97, 446 - SUBS_SPECIAL_0_OPCODE_X1 = 67, 447 - SUB_SPECIAL_0_OPCODE_X0 = 93, 448 - SUB_SPECIAL_0_OPCODE_X1 = 63, 449 - SUB_SPECIAL_0_OPCODE_Y0 = 3, 450 - SUB_SPECIAL_0_OPCODE_Y1 = 3, 451 - SWADD_IMM_0_OPCODE_X1 = 30, 452 - SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18, 453 - SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19, 454 - SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20, 455 - SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21, 456 - SW_OPCODE_Y2 = 7, 457 - SW_SPECIAL_0_OPCODE_X1 = 64, 458 - TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8, 459 - TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8, 460 - TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9, 461 - TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9, 462 - TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10, 463 - TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10, 464 - TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11, 465 - TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11, 466 - TNS_UN_0_SHUN_0_OPCODE_X1 = 22, 467 - UN_0_SHUN_0_OPCODE_X0 = 11, 468 - UN_0_SHUN_0_OPCODE_X1 = 11, 469 - UN_0_SHUN_0_OPCODE_Y0 = 5, 470 - UN_0_SHUN_0_OPCODE_Y1 = 5, 471 - WH64_UN_0_SHUN_0_OPCODE_X1 = 23, 472 - XORI_IMM_0_OPCODE_X0 = 2, 473 - XORI_IMM_0_OPCODE_X1 = 21, 474 - XOR_SPECIAL_0_OPCODE_X0 = 94, 475 - XOR_SPECIAL_0_OPCODE_X1 = 65, 476 - XOR_SPECIAL_2_OPCODE_Y0 = 3, 477 - XOR_SPECIAL_2_OPCODE_Y1 = 3 478 - }; 479 - 480 - #endif /* !_TILE_OPCODE_CONSTANTS_H */
+801 -5
arch/tile/include/asm/opcode_constants_64.h arch/tile/include/arch/opcode_tilegx.h
··· 1 - /* 1 + /* TILE-Gx opcode information. 2 + * 2 3 * Copyright 2011 Tilera Corporation. All Rights Reserved. 3 4 * 4 5 * This program is free software; you can redistribute it and/or ··· 11 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 11 * NON INFRINGEMENT. See the GNU General Public License for 13 12 * more details. 13 + * 14 + * 15 + * 16 + * 17 + * 14 18 */ 15 19 16 - /* This file is machine-generated; DO NOT EDIT! */ 20 + #ifndef __ARCH_OPCODE_H__ 21 + #define __ARCH_OPCODE_H__ 22 + 23 + #ifndef __ASSEMBLER__ 24 + 25 + typedef unsigned long long tilegx_bundle_bits; 26 + 27 + /* These are the bits that determine if a bundle is in the X encoding. */ 28 + #define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62) 29 + 30 + enum 31 + { 32 + /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ 33 + TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3, 34 + 35 + /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ 36 + TILEGX_NUM_PIPELINE_ENCODINGS = 5, 37 + 38 + /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */ 39 + TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3, 40 + 41 + /* Instructions take this many bytes. */ 42 + TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES, 43 + 44 + /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */ 45 + TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, 46 + 47 + /* Bundles should be aligned modulo this number of bytes. */ 48 + TILEGX_BUNDLE_ALIGNMENT_IN_BYTES = 49 + (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), 50 + 51 + /* Number of registers (some are magic, such as network I/O). */ 52 + TILEGX_NUM_REGISTERS = 64, 53 + }; 54 + 55 + /* Make a few "tile_" variables to simplify common code between 56 + architectures. */ 57 + 58 + typedef tilegx_bundle_bits tile_bundle_bits; 59 + #define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES 60 + #define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES 61 + #define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \ 62 + TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES 63 + 64 + /* 64-bit pattern for a { bpt ; nop } bundle. */ 65 + #define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL 66 + 67 + static __inline unsigned int 68 + get_BFEnd_X0(tilegx_bundle_bits num) 69 + { 70 + const unsigned int n = (unsigned int)num; 71 + return (((n >> 12)) & 0x3f); 72 + } 73 + 74 + static __inline unsigned int 75 + get_BFOpcodeExtension_X0(tilegx_bundle_bits num) 76 + { 77 + const unsigned int n = (unsigned int)num; 78 + return (((n >> 24)) & 0xf); 79 + } 80 + 81 + static __inline unsigned int 82 + get_BFStart_X0(tilegx_bundle_bits num) 83 + { 84 + const unsigned int n = (unsigned int)num; 85 + return (((n >> 18)) & 0x3f); 86 + } 87 + 88 + static __inline unsigned int 89 + get_BrOff_X1(tilegx_bundle_bits n) 90 + { 91 + return (((unsigned int)(n >> 31)) & 0x0000003f) | 92 + (((unsigned int)(n >> 37)) & 0x0001ffc0); 93 + } 94 + 95 + static __inline unsigned int 96 + get_BrType_X1(tilegx_bundle_bits n) 97 + { 98 + return (((unsigned int)(n >> 54)) & 0x1f); 99 + } 100 + 101 + static __inline unsigned int 102 + get_Dest_Imm8_X1(tilegx_bundle_bits n) 103 + { 104 + return (((unsigned int)(n >> 31)) & 0x0000003f) | 105 + (((unsigned int)(n >> 43)) & 0x000000c0); 106 + } 107 + 108 + static __inline unsigned int 109 + get_Dest_X0(tilegx_bundle_bits num) 110 + { 111 + const unsigned int n = (unsigned int)num; 112 + return (((n >> 0)) & 0x3f); 113 + } 114 + 115 + static __inline unsigned int 116 + get_Dest_X1(tilegx_bundle_bits n) 117 + { 118 + return (((unsigned int)(n >> 31)) & 0x3f); 119 + } 120 + 121 + static __inline unsigned int 122 + get_Dest_Y0(tilegx_bundle_bits num) 123 + { 124 + const unsigned int n = (unsigned int)num; 125 + return (((n >> 0)) & 0x3f); 126 + } 127 + 128 + static __inline unsigned int 129 + get_Dest_Y1(tilegx_bundle_bits n) 130 + { 131 + return (((unsigned int)(n >> 31)) & 0x3f); 132 + } 133 + 134 + static __inline unsigned int 135 + get_Imm16_X0(tilegx_bundle_bits num) 136 + { 137 + const unsigned int n = (unsigned int)num; 138 + return (((n >> 12)) & 0xffff); 139 + } 140 + 141 + static __inline unsigned int 142 + get_Imm16_X1(tilegx_bundle_bits n) 143 + { 144 + return (((unsigned int)(n >> 43)) & 0xffff); 145 + } 146 + 147 + static __inline unsigned int 148 + get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num) 149 + { 150 + const unsigned int n = (unsigned int)num; 151 + return (((n >> 20)) & 0xff); 152 + } 153 + 154 + static __inline unsigned int 155 + get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n) 156 + { 157 + return (((unsigned int)(n >> 51)) & 0xff); 158 + } 159 + 160 + static __inline unsigned int 161 + get_Imm8_X0(tilegx_bundle_bits num) 162 + { 163 + const unsigned int n = (unsigned int)num; 164 + return (((n >> 12)) & 0xff); 165 + } 166 + 167 + static __inline unsigned int 168 + get_Imm8_X1(tilegx_bundle_bits n) 169 + { 170 + return (((unsigned int)(n >> 43)) & 0xff); 171 + } 172 + 173 + static __inline unsigned int 174 + get_Imm8_Y0(tilegx_bundle_bits num) 175 + { 176 + const unsigned int n = (unsigned int)num; 177 + return (((n >> 12)) & 0xff); 178 + } 179 + 180 + static __inline unsigned int 181 + get_Imm8_Y1(tilegx_bundle_bits n) 182 + { 183 + return (((unsigned int)(n >> 43)) & 0xff); 184 + } 185 + 186 + static __inline unsigned int 187 + get_JumpOff_X1(tilegx_bundle_bits n) 188 + { 189 + return (((unsigned int)(n >> 31)) & 0x7ffffff); 190 + } 191 + 192 + static __inline unsigned int 193 + get_JumpOpcodeExtension_X1(tilegx_bundle_bits n) 194 + { 195 + return (((unsigned int)(n >> 58)) & 0x1); 196 + } 197 + 198 + static __inline unsigned int 199 + get_MF_Imm14_X1(tilegx_bundle_bits n) 200 + { 201 + return (((unsigned int)(n >> 37)) & 0x3fff); 202 + } 203 + 204 + static __inline unsigned int 205 + get_MT_Imm14_X1(tilegx_bundle_bits n) 206 + { 207 + return (((unsigned int)(n >> 31)) & 0x0000003f) | 208 + (((unsigned int)(n >> 37)) & 0x00003fc0); 209 + } 210 + 211 + static __inline unsigned int 212 + get_Mode(tilegx_bundle_bits n) 213 + { 214 + return (((unsigned int)(n >> 62)) & 0x3); 215 + } 216 + 217 + static __inline unsigned int 218 + get_Opcode_X0(tilegx_bundle_bits num) 219 + { 220 + const unsigned int n = (unsigned int)num; 221 + return (((n >> 28)) & 0x7); 222 + } 223 + 224 + static __inline unsigned int 225 + get_Opcode_X1(tilegx_bundle_bits n) 226 + { 227 + return (((unsigned int)(n >> 59)) & 0x7); 228 + } 229 + 230 + static __inline unsigned int 231 + get_Opcode_Y0(tilegx_bundle_bits num) 232 + { 233 + const unsigned int n = (unsigned int)num; 234 + return (((n >> 27)) & 0xf); 235 + } 236 + 237 + static __inline unsigned int 238 + get_Opcode_Y1(tilegx_bundle_bits n) 239 + { 240 + return (((unsigned int)(n >> 58)) & 0xf); 241 + } 242 + 243 + static __inline unsigned int 244 + get_Opcode_Y2(tilegx_bundle_bits n) 245 + { 246 + return (((n >> 26)) & 0x00000001) | 247 + (((unsigned int)(n >> 56)) & 0x00000002); 248 + } 249 + 250 + static __inline unsigned int 251 + get_RRROpcodeExtension_X0(tilegx_bundle_bits num) 252 + { 253 + const unsigned int n = (unsigned int)num; 254 + return (((n >> 18)) & 0x3ff); 255 + } 256 + 257 + static __inline unsigned int 258 + get_RRROpcodeExtension_X1(tilegx_bundle_bits n) 259 + { 260 + return (((unsigned int)(n >> 49)) & 0x3ff); 261 + } 262 + 263 + static __inline unsigned int 264 + get_RRROpcodeExtension_Y0(tilegx_bundle_bits num) 265 + { 266 + const unsigned int n = (unsigned int)num; 267 + return (((n >> 18)) & 0x3); 268 + } 269 + 270 + static __inline unsigned int 271 + get_RRROpcodeExtension_Y1(tilegx_bundle_bits n) 272 + { 273 + return (((unsigned int)(n >> 49)) & 0x3); 274 + } 275 + 276 + static __inline unsigned int 277 + get_ShAmt_X0(tilegx_bundle_bits num) 278 + { 279 + const unsigned int n = (unsigned int)num; 280 + return (((n >> 12)) & 0x3f); 281 + } 282 + 283 + static __inline unsigned int 284 + get_ShAmt_X1(tilegx_bundle_bits n) 285 + { 286 + return (((unsigned int)(n >> 43)) & 0x3f); 287 + } 288 + 289 + static __inline unsigned int 290 + get_ShAmt_Y0(tilegx_bundle_bits num) 291 + { 292 + const unsigned int n = (unsigned int)num; 293 + return (((n >> 12)) & 0x3f); 294 + } 295 + 296 + static __inline unsigned int 297 + get_ShAmt_Y1(tilegx_bundle_bits n) 298 + { 299 + return (((unsigned int)(n >> 43)) & 0x3f); 300 + } 301 + 302 + static __inline unsigned int 303 + get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num) 304 + { 305 + const unsigned int n = (unsigned int)num; 306 + return (((n >> 18)) & 0x3ff); 307 + } 308 + 309 + static __inline unsigned int 310 + get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n) 311 + { 312 + return (((unsigned int)(n >> 49)) & 0x3ff); 313 + } 314 + 315 + static __inline unsigned int 316 + get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num) 317 + { 318 + const unsigned int n = (unsigned int)num; 319 + return (((n >> 18)) & 0x3); 320 + } 321 + 322 + static __inline unsigned int 323 + get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n) 324 + { 325 + return (((unsigned int)(n >> 49)) & 0x3); 326 + } 327 + 328 + static __inline unsigned int 329 + get_SrcA_X0(tilegx_bundle_bits num) 330 + { 331 + const unsigned int n = (unsigned int)num; 332 + return (((n >> 6)) & 0x3f); 333 + } 334 + 335 + static __inline unsigned int 336 + get_SrcA_X1(tilegx_bundle_bits n) 337 + { 338 + return (((unsigned int)(n >> 37)) & 0x3f); 339 + } 340 + 341 + static __inline unsigned int 342 + get_SrcA_Y0(tilegx_bundle_bits num) 343 + { 344 + const unsigned int n = (unsigned int)num; 345 + return (((n >> 6)) & 0x3f); 346 + } 347 + 348 + static __inline unsigned int 349 + get_SrcA_Y1(tilegx_bundle_bits n) 350 + { 351 + return (((unsigned int)(n >> 37)) & 0x3f); 352 + } 353 + 354 + static __inline unsigned int 355 + get_SrcA_Y2(tilegx_bundle_bits num) 356 + { 357 + const unsigned int n = (unsigned int)num; 358 + return (((n >> 20)) & 0x3f); 359 + } 360 + 361 + static __inline unsigned int 362 + get_SrcBDest_Y2(tilegx_bundle_bits n) 363 + { 364 + return (((unsigned int)(n >> 51)) & 0x3f); 365 + } 366 + 367 + static __inline unsigned int 368 + get_SrcB_X0(tilegx_bundle_bits num) 369 + { 370 + const unsigned int n = (unsigned int)num; 371 + return (((n >> 12)) & 0x3f); 372 + } 373 + 374 + static __inline unsigned int 375 + get_SrcB_X1(tilegx_bundle_bits n) 376 + { 377 + return (((unsigned int)(n >> 43)) & 0x3f); 378 + } 379 + 380 + static __inline unsigned int 381 + get_SrcB_Y0(tilegx_bundle_bits num) 382 + { 383 + const unsigned int n = (unsigned int)num; 384 + return (((n >> 12)) & 0x3f); 385 + } 386 + 387 + static __inline unsigned int 388 + get_SrcB_Y1(tilegx_bundle_bits n) 389 + { 390 + return (((unsigned int)(n >> 43)) & 0x3f); 391 + } 392 + 393 + static __inline unsigned int 394 + get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num) 395 + { 396 + const unsigned int n = (unsigned int)num; 397 + return (((n >> 12)) & 0x3f); 398 + } 399 + 400 + static __inline unsigned int 401 + get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n) 402 + { 403 + return (((unsigned int)(n >> 43)) & 0x3f); 404 + } 405 + 406 + static __inline unsigned int 407 + get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num) 408 + { 409 + const unsigned int n = (unsigned int)num; 410 + return (((n >> 12)) & 0x3f); 411 + } 412 + 413 + static __inline unsigned int 414 + get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n) 415 + { 416 + return (((unsigned int)(n >> 43)) & 0x3f); 417 + } 17 418 18 419 19 - #ifndef _TILE_OPCODE_CONSTANTS_H 20 - #define _TILE_OPCODE_CONSTANTS_H 420 + static __inline int 421 + sign_extend(int n, int num_bits) 422 + { 423 + int shift = (int)(sizeof(int) * 8 - num_bits); 424 + return (n << shift) >> shift; 425 + } 426 + 427 + 428 + 429 + static __inline tilegx_bundle_bits 430 + create_BFEnd_X0(int num) 431 + { 432 + const unsigned int n = (unsigned int)num; 433 + return ((n & 0x3f) << 12); 434 + } 435 + 436 + static __inline tilegx_bundle_bits 437 + create_BFOpcodeExtension_X0(int num) 438 + { 439 + const unsigned int n = (unsigned int)num; 440 + return ((n & 0xf) << 24); 441 + } 442 + 443 + static __inline tilegx_bundle_bits 444 + create_BFStart_X0(int num) 445 + { 446 + const unsigned int n = (unsigned int)num; 447 + return ((n & 0x3f) << 18); 448 + } 449 + 450 + static __inline tilegx_bundle_bits 451 + create_BrOff_X1(int num) 452 + { 453 + const unsigned int n = (unsigned int)num; 454 + return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | 455 + (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37); 456 + } 457 + 458 + static __inline tilegx_bundle_bits 459 + create_BrType_X1(int num) 460 + { 461 + const unsigned int n = (unsigned int)num; 462 + return (((tilegx_bundle_bits)(n & 0x1f)) << 54); 463 + } 464 + 465 + static __inline tilegx_bundle_bits 466 + create_Dest_Imm8_X1(int num) 467 + { 468 + const unsigned int n = (unsigned int)num; 469 + return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | 470 + (((tilegx_bundle_bits)(n & 0x000000c0)) << 43); 471 + } 472 + 473 + static __inline tilegx_bundle_bits 474 + create_Dest_X0(int num) 475 + { 476 + const unsigned int n = (unsigned int)num; 477 + return ((n & 0x3f) << 0); 478 + } 479 + 480 + static __inline tilegx_bundle_bits 481 + create_Dest_X1(int num) 482 + { 483 + const unsigned int n = (unsigned int)num; 484 + return (((tilegx_bundle_bits)(n & 0x3f)) << 31); 485 + } 486 + 487 + static __inline tilegx_bundle_bits 488 + create_Dest_Y0(int num) 489 + { 490 + const unsigned int n = (unsigned int)num; 491 + return ((n & 0x3f) << 0); 492 + } 493 + 494 + static __inline tilegx_bundle_bits 495 + create_Dest_Y1(int num) 496 + { 497 + const unsigned int n = (unsigned int)num; 498 + return (((tilegx_bundle_bits)(n & 0x3f)) << 31); 499 + } 500 + 501 + static __inline tilegx_bundle_bits 502 + create_Imm16_X0(int num) 503 + { 504 + const unsigned int n = (unsigned int)num; 505 + return ((n & 0xffff) << 12); 506 + } 507 + 508 + static __inline tilegx_bundle_bits 509 + create_Imm16_X1(int num) 510 + { 511 + const unsigned int n = (unsigned int)num; 512 + return (((tilegx_bundle_bits)(n & 0xffff)) << 43); 513 + } 514 + 515 + static __inline tilegx_bundle_bits 516 + create_Imm8OpcodeExtension_X0(int num) 517 + { 518 + const unsigned int n = (unsigned int)num; 519 + return ((n & 0xff) << 20); 520 + } 521 + 522 + static __inline tilegx_bundle_bits 523 + create_Imm8OpcodeExtension_X1(int num) 524 + { 525 + const unsigned int n = (unsigned int)num; 526 + return (((tilegx_bundle_bits)(n & 0xff)) << 51); 527 + } 528 + 529 + static __inline tilegx_bundle_bits 530 + create_Imm8_X0(int num) 531 + { 532 + const unsigned int n = (unsigned int)num; 533 + return ((n & 0xff) << 12); 534 + } 535 + 536 + static __inline tilegx_bundle_bits 537 + create_Imm8_X1(int num) 538 + { 539 + const unsigned int n = (unsigned int)num; 540 + return (((tilegx_bundle_bits)(n & 0xff)) << 43); 541 + } 542 + 543 + static __inline tilegx_bundle_bits 544 + create_Imm8_Y0(int num) 545 + { 546 + const unsigned int n = (unsigned int)num; 547 + return ((n & 0xff) << 12); 548 + } 549 + 550 + static __inline tilegx_bundle_bits 551 + create_Imm8_Y1(int num) 552 + { 553 + const unsigned int n = (unsigned int)num; 554 + return (((tilegx_bundle_bits)(n & 0xff)) << 43); 555 + } 556 + 557 + static __inline tilegx_bundle_bits 558 + create_JumpOff_X1(int num) 559 + { 560 + const unsigned int n = (unsigned int)num; 561 + return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31); 562 + } 563 + 564 + static __inline tilegx_bundle_bits 565 + create_JumpOpcodeExtension_X1(int num) 566 + { 567 + const unsigned int n = (unsigned int)num; 568 + return (((tilegx_bundle_bits)(n & 0x1)) << 58); 569 + } 570 + 571 + static __inline tilegx_bundle_bits 572 + create_MF_Imm14_X1(int num) 573 + { 574 + const unsigned int n = (unsigned int)num; 575 + return (((tilegx_bundle_bits)(n & 0x3fff)) << 37); 576 + } 577 + 578 + static __inline tilegx_bundle_bits 579 + create_MT_Imm14_X1(int num) 580 + { 581 + const unsigned int n = (unsigned int)num; 582 + return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | 583 + (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37); 584 + } 585 + 586 + static __inline tilegx_bundle_bits 587 + create_Mode(int num) 588 + { 589 + const unsigned int n = (unsigned int)num; 590 + return (((tilegx_bundle_bits)(n & 0x3)) << 62); 591 + } 592 + 593 + static __inline tilegx_bundle_bits 594 + create_Opcode_X0(int num) 595 + { 596 + const unsigned int n = (unsigned int)num; 597 + return ((n & 0x7) << 28); 598 + } 599 + 600 + static __inline tilegx_bundle_bits 601 + create_Opcode_X1(int num) 602 + { 603 + const unsigned int n = (unsigned int)num; 604 + return (((tilegx_bundle_bits)(n & 0x7)) << 59); 605 + } 606 + 607 + static __inline tilegx_bundle_bits 608 + create_Opcode_Y0(int num) 609 + { 610 + const unsigned int n = (unsigned int)num; 611 + return ((n & 0xf) << 27); 612 + } 613 + 614 + static __inline tilegx_bundle_bits 615 + create_Opcode_Y1(int num) 616 + { 617 + const unsigned int n = (unsigned int)num; 618 + return (((tilegx_bundle_bits)(n & 0xf)) << 58); 619 + } 620 + 621 + static __inline tilegx_bundle_bits 622 + create_Opcode_Y2(int num) 623 + { 624 + const unsigned int n = (unsigned int)num; 625 + return ((n & 0x00000001) << 26) | 626 + (((tilegx_bundle_bits)(n & 0x00000002)) << 56); 627 + } 628 + 629 + static __inline tilegx_bundle_bits 630 + create_RRROpcodeExtension_X0(int num) 631 + { 632 + const unsigned int n = (unsigned int)num; 633 + return ((n & 0x3ff) << 18); 634 + } 635 + 636 + static __inline tilegx_bundle_bits 637 + create_RRROpcodeExtension_X1(int num) 638 + { 639 + const unsigned int n = (unsigned int)num; 640 + return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); 641 + } 642 + 643 + static __inline tilegx_bundle_bits 644 + create_RRROpcodeExtension_Y0(int num) 645 + { 646 + const unsigned int n = (unsigned int)num; 647 + return ((n & 0x3) << 18); 648 + } 649 + 650 + static __inline tilegx_bundle_bits 651 + create_RRROpcodeExtension_Y1(int num) 652 + { 653 + const unsigned int n = (unsigned int)num; 654 + return (((tilegx_bundle_bits)(n & 0x3)) << 49); 655 + } 656 + 657 + static __inline tilegx_bundle_bits 658 + create_ShAmt_X0(int num) 659 + { 660 + const unsigned int n = (unsigned int)num; 661 + return ((n & 0x3f) << 12); 662 + } 663 + 664 + static __inline tilegx_bundle_bits 665 + create_ShAmt_X1(int num) 666 + { 667 + const unsigned int n = (unsigned int)num; 668 + return (((tilegx_bundle_bits)(n & 0x3f)) << 43); 669 + } 670 + 671 + static __inline tilegx_bundle_bits 672 + create_ShAmt_Y0(int num) 673 + { 674 + const unsigned int n = (unsigned int)num; 675 + return ((n & 0x3f) << 12); 676 + } 677 + 678 + static __inline tilegx_bundle_bits 679 + create_ShAmt_Y1(int num) 680 + { 681 + const unsigned int n = (unsigned int)num; 682 + return (((tilegx_bundle_bits)(n & 0x3f)) << 43); 683 + } 684 + 685 + static __inline tilegx_bundle_bits 686 + create_ShiftOpcodeExtension_X0(int num) 687 + { 688 + const unsigned int n = (unsigned int)num; 689 + return ((n & 0x3ff) << 18); 690 + } 691 + 692 + static __inline tilegx_bundle_bits 693 + create_ShiftOpcodeExtension_X1(int num) 694 + { 695 + const unsigned int n = (unsigned int)num; 696 + return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); 697 + } 698 + 699 + static __inline tilegx_bundle_bits 700 + create_ShiftOpcodeExtension_Y0(int num) 701 + { 702 + const unsigned int n = (unsigned int)num; 703 + return ((n & 0x3) << 18); 704 + } 705 + 706 + static __inline tilegx_bundle_bits 707 + create_ShiftOpcodeExtension_Y1(int num) 708 + { 709 + const unsigned int n = (unsigned int)num; 710 + return (((tilegx_bundle_bits)(n & 0x3)) << 49); 711 + } 712 + 713 + static __inline tilegx_bundle_bits 714 + create_SrcA_X0(int num) 715 + { 716 + const unsigned int n = (unsigned int)num; 717 + return ((n & 0x3f) << 6); 718 + } 719 + 720 + static __inline tilegx_bundle_bits 721 + create_SrcA_X1(int num) 722 + { 723 + const unsigned int n = (unsigned int)num; 724 + return (((tilegx_bundle_bits)(n & 0x3f)) << 37); 725 + } 726 + 727 + static __inline tilegx_bundle_bits 728 + create_SrcA_Y0(int num) 729 + { 730 + const unsigned int n = (unsigned int)num; 731 + return ((n & 0x3f) << 6); 732 + } 733 + 734 + static __inline tilegx_bundle_bits 735 + create_SrcA_Y1(int num) 736 + { 737 + const unsigned int n = (unsigned int)num; 738 + return (((tilegx_bundle_bits)(n & 0x3f)) << 37); 739 + } 740 + 741 + static __inline tilegx_bundle_bits 742 + create_SrcA_Y2(int num) 743 + { 744 + const unsigned int n = (unsigned int)num; 745 + return ((n & 0x3f) << 20); 746 + } 747 + 748 + static __inline tilegx_bundle_bits 749 + create_SrcBDest_Y2(int num) 750 + { 751 + const unsigned int n = (unsigned int)num; 752 + return (((tilegx_bundle_bits)(n & 0x3f)) << 51); 753 + } 754 + 755 + static __inline tilegx_bundle_bits 756 + create_SrcB_X0(int num) 757 + { 758 + const unsigned int n = (unsigned int)num; 759 + return ((n & 0x3f) << 12); 760 + } 761 + 762 + static __inline tilegx_bundle_bits 763 + create_SrcB_X1(int num) 764 + { 765 + const unsigned int n = (unsigned int)num; 766 + return (((tilegx_bundle_bits)(n & 0x3f)) << 43); 767 + } 768 + 769 + static __inline tilegx_bundle_bits 770 + create_SrcB_Y0(int num) 771 + { 772 + const unsigned int n = (unsigned int)num; 773 + return ((n & 0x3f) << 12); 774 + } 775 + 776 + static __inline tilegx_bundle_bits 777 + create_SrcB_Y1(int num) 778 + { 779 + const unsigned int n = (unsigned int)num; 780 + return (((tilegx_bundle_bits)(n & 0x3f)) << 43); 781 + } 782 + 783 + static __inline tilegx_bundle_bits 784 + create_UnaryOpcodeExtension_X0(int num) 785 + { 786 + const unsigned int n = (unsigned int)num; 787 + return ((n & 0x3f) << 12); 788 + } 789 + 790 + static __inline tilegx_bundle_bits 791 + create_UnaryOpcodeExtension_X1(int num) 792 + { 793 + const unsigned int n = (unsigned int)num; 794 + return (((tilegx_bundle_bits)(n & 0x3f)) << 43); 795 + } 796 + 797 + static __inline tilegx_bundle_bits 798 + create_UnaryOpcodeExtension_Y0(int num) 799 + { 800 + const unsigned int n = (unsigned int)num; 801 + return ((n & 0x3f) << 12); 802 + } 803 + 804 + static __inline tilegx_bundle_bits 805 + create_UnaryOpcodeExtension_Y1(int num) 806 + { 807 + const unsigned int n = (unsigned int)num; 808 + return (((tilegx_bundle_bits)(n & 0x3f)) << 43); 809 + } 810 + 811 + 21 812 enum 22 813 { 23 814 ADDI_IMM8_OPCODE_X0 = 1, ··· 1399 606 XOR_RRR_5_OPCODE_Y1 = 3 1400 607 }; 1401 608 1402 - #endif /* !_TILE_OPCODE_CONSTANTS_H */ 609 + 610 + #endif /* __ASSEMBLER__ */ 611 + 612 + #endif /* __ARCH_OPCODE_H__ */
+10 -8
arch/tile/include/asm/sigcontext.h
··· 15 15 #ifndef _ASM_TILE_SIGCONTEXT_H 16 16 #define _ASM_TILE_SIGCONTEXT_H 17 17 18 + /* Don't pollute the namespace since <signal.h> includes this file. */ 19 + #define __need_int_reg_t 18 20 #include <arch/abi.h> 19 21 20 22 /* ··· 24 22 * but is simplified since we know the fault is from userspace. 25 23 */ 26 24 struct sigcontext { 27 - uint_reg_t gregs[53]; /* General-purpose registers. */ 28 - uint_reg_t tp; /* Aliases gregs[TREG_TP]. */ 29 - uint_reg_t sp; /* Aliases gregs[TREG_SP]. */ 30 - uint_reg_t lr; /* Aliases gregs[TREG_LR]. */ 31 - uint_reg_t pc; /* Program counter. */ 32 - uint_reg_t ics; /* In Interrupt Critical Section? */ 33 - uint_reg_t faultnum; /* Fault number. */ 34 - uint_reg_t pad[5]; 25 + __uint_reg_t gregs[53]; /* General-purpose registers. */ 26 + __uint_reg_t tp; /* Aliases gregs[TREG_TP]. */ 27 + __uint_reg_t sp; /* Aliases gregs[TREG_SP]. */ 28 + __uint_reg_t lr; /* Aliases gregs[TREG_LR]. */ 29 + __uint_reg_t pc; /* Program counter. */ 30 + __uint_reg_t ics; /* In Interrupt Critical Section? */ 31 + __uint_reg_t faultnum; /* Fault number. */ 32 + __uint_reg_t pad[5]; 35 33 }; 36 34 37 35 #endif /* _ASM_TILE_SIGCONTEXT_H */
+553
arch/tile/include/asm/tile-desc_32.h
··· 1 + /* TILEPro opcode information. 2 + * 3 + * Copyright 2011 Tilera Corporation. All Rights Reserved. 4 + * 5 + * This program is free software; you can redistribute it and/or 6 + * modify it under the terms of the GNU General Public License 7 + * as published by the Free Software Foundation, version 2. 8 + * 9 + * This program is distributed in the hope that it will be useful, but 10 + * WITHOUT ANY WARRANTY; without even the implied warranty of 11 + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 + * NON INFRINGEMENT. See the GNU General Public License for 13 + * more details. 14 + * 15 + * 16 + * 17 + * 18 + * 19 + */ 20 + 21 + #ifndef opcode_tilepro_h 22 + #define opcode_tilepro_h 23 + 24 + #include <arch/opcode.h> 25 + 26 + 27 + enum 28 + { 29 + TILEPRO_MAX_OPERANDS = 5 /* mm */ 30 + }; 31 + 32 + typedef enum 33 + { 34 + TILEPRO_OPC_BPT, 35 + TILEPRO_OPC_INFO, 36 + TILEPRO_OPC_INFOL, 37 + TILEPRO_OPC_J, 38 + TILEPRO_OPC_JAL, 39 + TILEPRO_OPC_MOVE, 40 + TILEPRO_OPC_MOVE_SN, 41 + TILEPRO_OPC_MOVEI, 42 + TILEPRO_OPC_MOVEI_SN, 43 + TILEPRO_OPC_MOVELI, 44 + TILEPRO_OPC_MOVELI_SN, 45 + TILEPRO_OPC_MOVELIS, 46 + TILEPRO_OPC_PREFETCH, 47 + TILEPRO_OPC_RAISE, 48 + TILEPRO_OPC_ADD, 49 + TILEPRO_OPC_ADD_SN, 50 + TILEPRO_OPC_ADDB, 51 + TILEPRO_OPC_ADDB_SN, 52 + TILEPRO_OPC_ADDBS_U, 53 + TILEPRO_OPC_ADDBS_U_SN, 54 + TILEPRO_OPC_ADDH, 55 + TILEPRO_OPC_ADDH_SN, 56 + TILEPRO_OPC_ADDHS, 57 + TILEPRO_OPC_ADDHS_SN, 58 + TILEPRO_OPC_ADDI, 59 + TILEPRO_OPC_ADDI_SN, 60 + TILEPRO_OPC_ADDIB, 61 + TILEPRO_OPC_ADDIB_SN, 62 + TILEPRO_OPC_ADDIH, 63 + TILEPRO_OPC_ADDIH_SN, 64 + TILEPRO_OPC_ADDLI, 65 + TILEPRO_OPC_ADDLI_SN, 66 + TILEPRO_OPC_ADDLIS, 67 + TILEPRO_OPC_ADDS, 68 + TILEPRO_OPC_ADDS_SN, 69 + TILEPRO_OPC_ADIFFB_U, 70 + TILEPRO_OPC_ADIFFB_U_SN, 71 + TILEPRO_OPC_ADIFFH, 72 + TILEPRO_OPC_ADIFFH_SN, 73 + TILEPRO_OPC_AND, 74 + TILEPRO_OPC_AND_SN, 75 + TILEPRO_OPC_ANDI, 76 + TILEPRO_OPC_ANDI_SN, 77 + TILEPRO_OPC_AULI, 78 + TILEPRO_OPC_AVGB_U, 79 + TILEPRO_OPC_AVGB_U_SN, 80 + TILEPRO_OPC_AVGH, 81 + TILEPRO_OPC_AVGH_SN, 82 + TILEPRO_OPC_BBNS, 83 + TILEPRO_OPC_BBNS_SN, 84 + TILEPRO_OPC_BBNST, 85 + TILEPRO_OPC_BBNST_SN, 86 + TILEPRO_OPC_BBS, 87 + TILEPRO_OPC_BBS_SN, 88 + TILEPRO_OPC_BBST, 89 + TILEPRO_OPC_BBST_SN, 90 + TILEPRO_OPC_BGEZ, 91 + TILEPRO_OPC_BGEZ_SN, 92 + TILEPRO_OPC_BGEZT, 93 + TILEPRO_OPC_BGEZT_SN, 94 + TILEPRO_OPC_BGZ, 95 + TILEPRO_OPC_BGZ_SN, 96 + TILEPRO_OPC_BGZT, 97 + TILEPRO_OPC_BGZT_SN, 98 + TILEPRO_OPC_BITX, 99 + TILEPRO_OPC_BITX_SN, 100 + TILEPRO_OPC_BLEZ, 101 + TILEPRO_OPC_BLEZ_SN, 102 + TILEPRO_OPC_BLEZT, 103 + TILEPRO_OPC_BLEZT_SN, 104 + TILEPRO_OPC_BLZ, 105 + TILEPRO_OPC_BLZ_SN, 106 + TILEPRO_OPC_BLZT, 107 + TILEPRO_OPC_BLZT_SN, 108 + TILEPRO_OPC_BNZ, 109 + TILEPRO_OPC_BNZ_SN, 110 + TILEPRO_OPC_BNZT, 111 + TILEPRO_OPC_BNZT_SN, 112 + TILEPRO_OPC_BYTEX, 113 + TILEPRO_OPC_BYTEX_SN, 114 + TILEPRO_OPC_BZ, 115 + TILEPRO_OPC_BZ_SN, 116 + TILEPRO_OPC_BZT, 117 + TILEPRO_OPC_BZT_SN, 118 + TILEPRO_OPC_CLZ, 119 + TILEPRO_OPC_CLZ_SN, 120 + TILEPRO_OPC_CRC32_32, 121 + TILEPRO_OPC_CRC32_32_SN, 122 + TILEPRO_OPC_CRC32_8, 123 + TILEPRO_OPC_CRC32_8_SN, 124 + TILEPRO_OPC_CTZ, 125 + TILEPRO_OPC_CTZ_SN, 126 + TILEPRO_OPC_DRAIN, 127 + TILEPRO_OPC_DTLBPR, 128 + TILEPRO_OPC_DWORD_ALIGN, 129 + TILEPRO_OPC_DWORD_ALIGN_SN, 130 + TILEPRO_OPC_FINV, 131 + TILEPRO_OPC_FLUSH, 132 + TILEPRO_OPC_FNOP, 133 + TILEPRO_OPC_ICOH, 134 + TILEPRO_OPC_ILL, 135 + TILEPRO_OPC_INTHB, 136 + TILEPRO_OPC_INTHB_SN, 137 + TILEPRO_OPC_INTHH, 138 + TILEPRO_OPC_INTHH_SN, 139 + TILEPRO_OPC_INTLB, 140 + TILEPRO_OPC_INTLB_SN, 141 + TILEPRO_OPC_INTLH, 142 + TILEPRO_OPC_INTLH_SN, 143 + TILEPRO_OPC_INV, 144 + TILEPRO_OPC_IRET, 145 + TILEPRO_OPC_JALB, 146 + TILEPRO_OPC_JALF, 147 + TILEPRO_OPC_JALR, 148 + TILEPRO_OPC_JALRP, 149 + TILEPRO_OPC_JB, 150 + TILEPRO_OPC_JF, 151 + TILEPRO_OPC_JR, 152 + TILEPRO_OPC_JRP, 153 + TILEPRO_OPC_LB, 154 + TILEPRO_OPC_LB_SN, 155 + TILEPRO_OPC_LB_U, 156 + TILEPRO_OPC_LB_U_SN, 157 + TILEPRO_OPC_LBADD, 158 + TILEPRO_OPC_LBADD_SN, 159 + TILEPRO_OPC_LBADD_U, 160 + TILEPRO_OPC_LBADD_U_SN, 161 + TILEPRO_OPC_LH, 162 + TILEPRO_OPC_LH_SN, 163 + TILEPRO_OPC_LH_U, 164 + TILEPRO_OPC_LH_U_SN, 165 + TILEPRO_OPC_LHADD, 166 + TILEPRO_OPC_LHADD_SN, 167 + TILEPRO_OPC_LHADD_U, 168 + TILEPRO_OPC_LHADD_U_SN, 169 + TILEPRO_OPC_LNK, 170 + TILEPRO_OPC_LNK_SN, 171 + TILEPRO_OPC_LW, 172 + TILEPRO_OPC_LW_SN, 173 + TILEPRO_OPC_LW_NA, 174 + TILEPRO_OPC_LW_NA_SN, 175 + TILEPRO_OPC_LWADD, 176 + TILEPRO_OPC_LWADD_SN, 177 + TILEPRO_OPC_LWADD_NA, 178 + TILEPRO_OPC_LWADD_NA_SN, 179 + TILEPRO_OPC_MAXB_U, 180 + TILEPRO_OPC_MAXB_U_SN, 181 + TILEPRO_OPC_MAXH, 182 + TILEPRO_OPC_MAXH_SN, 183 + TILEPRO_OPC_MAXIB_U, 184 + TILEPRO_OPC_MAXIB_U_SN, 185 + TILEPRO_OPC_MAXIH, 186 + TILEPRO_OPC_MAXIH_SN, 187 + TILEPRO_OPC_MF, 188 + TILEPRO_OPC_MFSPR, 189 + TILEPRO_OPC_MINB_U, 190 + TILEPRO_OPC_MINB_U_SN, 191 + TILEPRO_OPC_MINH, 192 + TILEPRO_OPC_MINH_SN, 193 + TILEPRO_OPC_MINIB_U, 194 + TILEPRO_OPC_MINIB_U_SN, 195 + TILEPRO_OPC_MINIH, 196 + TILEPRO_OPC_MINIH_SN, 197 + TILEPRO_OPC_MM, 198 + TILEPRO_OPC_MNZ, 199 + TILEPRO_OPC_MNZ_SN, 200 + TILEPRO_OPC_MNZB, 201 + TILEPRO_OPC_MNZB_SN, 202 + TILEPRO_OPC_MNZH, 203 + TILEPRO_OPC_MNZH_SN, 204 + TILEPRO_OPC_MTSPR, 205 + TILEPRO_OPC_MULHH_SS, 206 + TILEPRO_OPC_MULHH_SS_SN, 207 + TILEPRO_OPC_MULHH_SU, 208 + TILEPRO_OPC_MULHH_SU_SN, 209 + TILEPRO_OPC_MULHH_UU, 210 + TILEPRO_OPC_MULHH_UU_SN, 211 + TILEPRO_OPC_MULHHA_SS, 212 + TILEPRO_OPC_MULHHA_SS_SN, 213 + TILEPRO_OPC_MULHHA_SU, 214 + TILEPRO_OPC_MULHHA_SU_SN, 215 + TILEPRO_OPC_MULHHA_UU, 216 + TILEPRO_OPC_MULHHA_UU_SN, 217 + TILEPRO_OPC_MULHHSA_UU, 218 + TILEPRO_OPC_MULHHSA_UU_SN, 219 + TILEPRO_OPC_MULHL_SS, 220 + TILEPRO_OPC_MULHL_SS_SN, 221 + TILEPRO_OPC_MULHL_SU, 222 + TILEPRO_OPC_MULHL_SU_SN, 223 + TILEPRO_OPC_MULHL_US, 224 + TILEPRO_OPC_MULHL_US_SN, 225 + TILEPRO_OPC_MULHL_UU, 226 + TILEPRO_OPC_MULHL_UU_SN, 227 + TILEPRO_OPC_MULHLA_SS, 228 + TILEPRO_OPC_MULHLA_SS_SN, 229 + TILEPRO_OPC_MULHLA_SU, 230 + TILEPRO_OPC_MULHLA_SU_SN, 231 + TILEPRO_OPC_MULHLA_US, 232 + TILEPRO_OPC_MULHLA_US_SN, 233 + TILEPRO_OPC_MULHLA_UU, 234 + TILEPRO_OPC_MULHLA_UU_SN, 235 + TILEPRO_OPC_MULHLSA_UU, 236 + TILEPRO_OPC_MULHLSA_UU_SN, 237 + TILEPRO_OPC_MULLL_SS, 238 + TILEPRO_OPC_MULLL_SS_SN, 239 + TILEPRO_OPC_MULLL_SU, 240 + TILEPRO_OPC_MULLL_SU_SN, 241 + TILEPRO_OPC_MULLL_UU, 242 + TILEPRO_OPC_MULLL_UU_SN, 243 + TILEPRO_OPC_MULLLA_SS, 244 + TILEPRO_OPC_MULLLA_SS_SN, 245 + TILEPRO_OPC_MULLLA_SU, 246 + TILEPRO_OPC_MULLLA_SU_SN, 247 + TILEPRO_OPC_MULLLA_UU, 248 + TILEPRO_OPC_MULLLA_UU_SN, 249 + TILEPRO_OPC_MULLLSA_UU, 250 + TILEPRO_OPC_MULLLSA_UU_SN, 251 + TILEPRO_OPC_MVNZ, 252 + TILEPRO_OPC_MVNZ_SN, 253 + TILEPRO_OPC_MVZ, 254 + TILEPRO_OPC_MVZ_SN, 255 + TILEPRO_OPC_MZ, 256 + TILEPRO_OPC_MZ_SN, 257 + TILEPRO_OPC_MZB, 258 + TILEPRO_OPC_MZB_SN, 259 + TILEPRO_OPC_MZH, 260 + TILEPRO_OPC_MZH_SN, 261 + TILEPRO_OPC_NAP, 262 + TILEPRO_OPC_NOP, 263 + TILEPRO_OPC_NOR, 264 + TILEPRO_OPC_NOR_SN, 265 + TILEPRO_OPC_OR, 266 + TILEPRO_OPC_OR_SN, 267 + TILEPRO_OPC_ORI, 268 + TILEPRO_OPC_ORI_SN, 269 + TILEPRO_OPC_PACKBS_U, 270 + TILEPRO_OPC_PACKBS_U_SN, 271 + TILEPRO_OPC_PACKHB, 272 + TILEPRO_OPC_PACKHB_SN, 273 + TILEPRO_OPC_PACKHS, 274 + TILEPRO_OPC_PACKHS_SN, 275 + TILEPRO_OPC_PACKLB, 276 + TILEPRO_OPC_PACKLB_SN, 277 + TILEPRO_OPC_PCNT, 278 + TILEPRO_OPC_PCNT_SN, 279 + TILEPRO_OPC_RL, 280 + TILEPRO_OPC_RL_SN, 281 + TILEPRO_OPC_RLI, 282 + TILEPRO_OPC_RLI_SN, 283 + TILEPRO_OPC_S1A, 284 + TILEPRO_OPC_S1A_SN, 285 + TILEPRO_OPC_S2A, 286 + TILEPRO_OPC_S2A_SN, 287 + TILEPRO_OPC_S3A, 288 + TILEPRO_OPC_S3A_SN, 289 + TILEPRO_OPC_SADAB_U, 290 + TILEPRO_OPC_SADAB_U_SN, 291 + TILEPRO_OPC_SADAH, 292 + TILEPRO_OPC_SADAH_SN, 293 + TILEPRO_OPC_SADAH_U, 294 + TILEPRO_OPC_SADAH_U_SN, 295 + TILEPRO_OPC_SADB_U, 296 + TILEPRO_OPC_SADB_U_SN, 297 + TILEPRO_OPC_SADH, 298 + TILEPRO_OPC_SADH_SN, 299 + TILEPRO_OPC_SADH_U, 300 + TILEPRO_OPC_SADH_U_SN, 301 + TILEPRO_OPC_SB, 302 + TILEPRO_OPC_SBADD, 303 + TILEPRO_OPC_SEQ, 304 + TILEPRO_OPC_SEQ_SN, 305 + TILEPRO_OPC_SEQB, 306 + TILEPRO_OPC_SEQB_SN, 307 + TILEPRO_OPC_SEQH, 308 + TILEPRO_OPC_SEQH_SN, 309 + TILEPRO_OPC_SEQI, 310 + TILEPRO_OPC_SEQI_SN, 311 + TILEPRO_OPC_SEQIB, 312 + TILEPRO_OPC_SEQIB_SN, 313 + TILEPRO_OPC_SEQIH, 314 + TILEPRO_OPC_SEQIH_SN, 315 + TILEPRO_OPC_SH, 316 + TILEPRO_OPC_SHADD, 317 + TILEPRO_OPC_SHL, 318 + TILEPRO_OPC_SHL_SN, 319 + TILEPRO_OPC_SHLB, 320 + TILEPRO_OPC_SHLB_SN, 321 + TILEPRO_OPC_SHLH, 322 + TILEPRO_OPC_SHLH_SN, 323 + TILEPRO_OPC_SHLI, 324 + TILEPRO_OPC_SHLI_SN, 325 + TILEPRO_OPC_SHLIB, 326 + TILEPRO_OPC_SHLIB_SN, 327 + TILEPRO_OPC_SHLIH, 328 + TILEPRO_OPC_SHLIH_SN, 329 + TILEPRO_OPC_SHR, 330 + TILEPRO_OPC_SHR_SN, 331 + TILEPRO_OPC_SHRB, 332 + TILEPRO_OPC_SHRB_SN, 333 + TILEPRO_OPC_SHRH, 334 + TILEPRO_OPC_SHRH_SN, 335 + TILEPRO_OPC_SHRI, 336 + TILEPRO_OPC_SHRI_SN, 337 + TILEPRO_OPC_SHRIB, 338 + TILEPRO_OPC_SHRIB_SN, 339 + TILEPRO_OPC_SHRIH, 340 + TILEPRO_OPC_SHRIH_SN, 341 + TILEPRO_OPC_SLT, 342 + TILEPRO_OPC_SLT_SN, 343 + TILEPRO_OPC_SLT_U, 344 + TILEPRO_OPC_SLT_U_SN, 345 + TILEPRO_OPC_SLTB, 346 + TILEPRO_OPC_SLTB_SN, 347 + TILEPRO_OPC_SLTB_U, 348 + TILEPRO_OPC_SLTB_U_SN, 349 + TILEPRO_OPC_SLTE, 350 + TILEPRO_OPC_SLTE_SN, 351 + TILEPRO_OPC_SLTE_U, 352 + TILEPRO_OPC_SLTE_U_SN, 353 + TILEPRO_OPC_SLTEB, 354 + TILEPRO_OPC_SLTEB_SN, 355 + TILEPRO_OPC_SLTEB_U, 356 + TILEPRO_OPC_SLTEB_U_SN, 357 + TILEPRO_OPC_SLTEH, 358 + TILEPRO_OPC_SLTEH_SN, 359 + TILEPRO_OPC_SLTEH_U, 360 + TILEPRO_OPC_SLTEH_U_SN, 361 + TILEPRO_OPC_SLTH, 362 + TILEPRO_OPC_SLTH_SN, 363 + TILEPRO_OPC_SLTH_U, 364 + TILEPRO_OPC_SLTH_U_SN, 365 + TILEPRO_OPC_SLTI, 366 + TILEPRO_OPC_SLTI_SN, 367 + TILEPRO_OPC_SLTI_U, 368 + TILEPRO_OPC_SLTI_U_SN, 369 + TILEPRO_OPC_SLTIB, 370 + TILEPRO_OPC_SLTIB_SN, 371 + TILEPRO_OPC_SLTIB_U, 372 + TILEPRO_OPC_SLTIB_U_SN, 373 + TILEPRO_OPC_SLTIH, 374 + TILEPRO_OPC_SLTIH_SN, 375 + TILEPRO_OPC_SLTIH_U, 376 + TILEPRO_OPC_SLTIH_U_SN, 377 + TILEPRO_OPC_SNE, 378 + TILEPRO_OPC_SNE_SN, 379 + TILEPRO_OPC_SNEB, 380 + TILEPRO_OPC_SNEB_SN, 381 + TILEPRO_OPC_SNEH, 382 + TILEPRO_OPC_SNEH_SN, 383 + TILEPRO_OPC_SRA, 384 + TILEPRO_OPC_SRA_SN, 385 + TILEPRO_OPC_SRAB, 386 + TILEPRO_OPC_SRAB_SN, 387 + TILEPRO_OPC_SRAH, 388 + TILEPRO_OPC_SRAH_SN, 389 + TILEPRO_OPC_SRAI, 390 + TILEPRO_OPC_SRAI_SN, 391 + TILEPRO_OPC_SRAIB, 392 + TILEPRO_OPC_SRAIB_SN, 393 + TILEPRO_OPC_SRAIH, 394 + TILEPRO_OPC_SRAIH_SN, 395 + TILEPRO_OPC_SUB, 396 + TILEPRO_OPC_SUB_SN, 397 + TILEPRO_OPC_SUBB, 398 + TILEPRO_OPC_SUBB_SN, 399 + TILEPRO_OPC_SUBBS_U, 400 + TILEPRO_OPC_SUBBS_U_SN, 401 + TILEPRO_OPC_SUBH, 402 + TILEPRO_OPC_SUBH_SN, 403 + TILEPRO_OPC_SUBHS, 404 + TILEPRO_OPC_SUBHS_SN, 405 + TILEPRO_OPC_SUBS, 406 + TILEPRO_OPC_SUBS_SN, 407 + TILEPRO_OPC_SW, 408 + TILEPRO_OPC_SWADD, 409 + TILEPRO_OPC_SWINT0, 410 + TILEPRO_OPC_SWINT1, 411 + TILEPRO_OPC_SWINT2, 412 + TILEPRO_OPC_SWINT3, 413 + TILEPRO_OPC_TBLIDXB0, 414 + TILEPRO_OPC_TBLIDXB0_SN, 415 + TILEPRO_OPC_TBLIDXB1, 416 + TILEPRO_OPC_TBLIDXB1_SN, 417 + TILEPRO_OPC_TBLIDXB2, 418 + TILEPRO_OPC_TBLIDXB2_SN, 419 + TILEPRO_OPC_TBLIDXB3, 420 + TILEPRO_OPC_TBLIDXB3_SN, 421 + TILEPRO_OPC_TNS, 422 + TILEPRO_OPC_TNS_SN, 423 + TILEPRO_OPC_WH64, 424 + TILEPRO_OPC_XOR, 425 + TILEPRO_OPC_XOR_SN, 426 + TILEPRO_OPC_XORI, 427 + TILEPRO_OPC_XORI_SN, 428 + TILEPRO_OPC_NONE 429 + } tilepro_mnemonic; 430 + 431 + 432 + 433 + 434 + typedef enum 435 + { 436 + TILEPRO_PIPELINE_X0, 437 + TILEPRO_PIPELINE_X1, 438 + TILEPRO_PIPELINE_Y0, 439 + TILEPRO_PIPELINE_Y1, 440 + TILEPRO_PIPELINE_Y2, 441 + } tilepro_pipeline; 442 + 443 + #define tilepro_is_x_pipeline(p) ((int)(p) <= (int)TILEPRO_PIPELINE_X1) 444 + 445 + typedef enum 446 + { 447 + TILEPRO_OP_TYPE_REGISTER, 448 + TILEPRO_OP_TYPE_IMMEDIATE, 449 + TILEPRO_OP_TYPE_ADDRESS, 450 + TILEPRO_OP_TYPE_SPR 451 + } tilepro_operand_type; 452 + 453 + struct tilepro_operand 454 + { 455 + /* Is this operand a register, immediate or address? */ 456 + tilepro_operand_type type; 457 + 458 + /* The default relocation type for this operand. */ 459 + signed int default_reloc : 16; 460 + 461 + /* How many bits is this value? (used for range checking) */ 462 + unsigned int num_bits : 5; 463 + 464 + /* Is the value signed? (used for range checking) */ 465 + unsigned int is_signed : 1; 466 + 467 + /* Is this operand a source register? */ 468 + unsigned int is_src_reg : 1; 469 + 470 + /* Is this operand written? (i.e. is it a destination register) */ 471 + unsigned int is_dest_reg : 1; 472 + 473 + /* Is this operand PC-relative? */ 474 + unsigned int is_pc_relative : 1; 475 + 476 + /* By how many bits do we right shift the value before inserting? */ 477 + unsigned int rightshift : 2; 478 + 479 + /* Return the bits for this operand to be ORed into an existing bundle. */ 480 + tilepro_bundle_bits (*insert) (int op); 481 + 482 + /* Extract this operand and return it. */ 483 + unsigned int (*extract) (tilepro_bundle_bits bundle); 484 + }; 485 + 486 + 487 + extern const struct tilepro_operand tilepro_operands[]; 488 + 489 + /* One finite-state machine per pipe for rapid instruction decoding. */ 490 + extern const unsigned short * const 491 + tilepro_bundle_decoder_fsms[TILEPRO_NUM_PIPELINE_ENCODINGS]; 492 + 493 + 494 + struct tilepro_opcode 495 + { 496 + /* The opcode mnemonic, e.g. "add" */ 497 + const char *name; 498 + 499 + /* The enum value for this mnemonic. */ 500 + tilepro_mnemonic mnemonic; 501 + 502 + /* A bit mask of which of the five pipes this instruction 503 + is compatible with: 504 + X0 0x01 505 + X1 0x02 506 + Y0 0x04 507 + Y1 0x08 508 + Y2 0x10 */ 509 + unsigned char pipes; 510 + 511 + /* How many operands are there? */ 512 + unsigned char num_operands; 513 + 514 + /* Which register does this write implicitly, or TREG_ZERO if none? */ 515 + unsigned char implicitly_written_register; 516 + 517 + /* Can this be bundled with other instructions (almost always true). */ 518 + unsigned char can_bundle; 519 + 520 + /* The description of the operands. Each of these is an 521 + * index into the tilepro_operands[] table. */ 522 + unsigned char operands[TILEPRO_NUM_PIPELINE_ENCODINGS][TILEPRO_MAX_OPERANDS]; 523 + 524 + }; 525 + 526 + extern const struct tilepro_opcode tilepro_opcodes[]; 527 + 528 + 529 + /* Used for non-textual disassembly into structs. */ 530 + struct tilepro_decoded_instruction 531 + { 532 + const struct tilepro_opcode *opcode; 533 + const struct tilepro_operand *operands[TILEPRO_MAX_OPERANDS]; 534 + int operand_values[TILEPRO_MAX_OPERANDS]; 535 + }; 536 + 537 + 538 + /* Disassemble a bundle into a struct for machine processing. */ 539 + extern int parse_insn_tilepro(tilepro_bundle_bits bits, 540 + unsigned int pc, 541 + struct tilepro_decoded_instruction 542 + decoded[TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE]); 543 + 544 + 545 + /* Given a set of bundle bits and a specific pipe, returns which 546 + * instruction the bundle contains in that pipe. 547 + */ 548 + extern const struct tilepro_opcode * 549 + find_opcode(tilepro_bundle_bits bits, tilepro_pipeline pipe); 550 + 551 + 552 + 553 + #endif /* opcode_tilepro_h */
+483
arch/tile/include/asm/tile-desc_64.h
··· 1 + /* TILE-Gx opcode information. 2 + * 3 + * Copyright 2011 Tilera Corporation. All Rights Reserved. 4 + * 5 + * This program is free software; you can redistribute it and/or 6 + * modify it under the terms of the GNU General Public License 7 + * as published by the Free Software Foundation, version 2. 8 + * 9 + * This program is distributed in the hope that it will be useful, but 10 + * WITHOUT ANY WARRANTY; without even the implied warranty of 11 + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 + * NON INFRINGEMENT. See the GNU General Public License for 13 + * more details. 14 + * 15 + * 16 + * 17 + * 18 + * 19 + */ 20 + 21 + #ifndef opcode_tile_h 22 + #define opcode_tile_h 23 + 24 + #include <arch/opcode.h> 25 + 26 + 27 + enum 28 + { 29 + TILEGX_MAX_OPERANDS = 4 /* bfexts */ 30 + }; 31 + 32 + typedef enum 33 + { 34 + TILEGX_OPC_BPT, 35 + TILEGX_OPC_INFO, 36 + TILEGX_OPC_INFOL, 37 + TILEGX_OPC_MOVE, 38 + TILEGX_OPC_MOVEI, 39 + TILEGX_OPC_MOVELI, 40 + TILEGX_OPC_PREFETCH, 41 + TILEGX_OPC_PREFETCH_ADD_L1, 42 + TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 43 + TILEGX_OPC_PREFETCH_ADD_L2, 44 + TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 45 + TILEGX_OPC_PREFETCH_ADD_L3, 46 + TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 47 + TILEGX_OPC_PREFETCH_L1, 48 + TILEGX_OPC_PREFETCH_L1_FAULT, 49 + TILEGX_OPC_PREFETCH_L2, 50 + TILEGX_OPC_PREFETCH_L2_FAULT, 51 + TILEGX_OPC_PREFETCH_L3, 52 + TILEGX_OPC_PREFETCH_L3_FAULT, 53 + TILEGX_OPC_RAISE, 54 + TILEGX_OPC_ADD, 55 + TILEGX_OPC_ADDI, 56 + TILEGX_OPC_ADDLI, 57 + TILEGX_OPC_ADDX, 58 + TILEGX_OPC_ADDXI, 59 + TILEGX_OPC_ADDXLI, 60 + TILEGX_OPC_ADDXSC, 61 + TILEGX_OPC_AND, 62 + TILEGX_OPC_ANDI, 63 + TILEGX_OPC_BEQZ, 64 + TILEGX_OPC_BEQZT, 65 + TILEGX_OPC_BFEXTS, 66 + TILEGX_OPC_BFEXTU, 67 + TILEGX_OPC_BFINS, 68 + TILEGX_OPC_BGEZ, 69 + TILEGX_OPC_BGEZT, 70 + TILEGX_OPC_BGTZ, 71 + TILEGX_OPC_BGTZT, 72 + TILEGX_OPC_BLBC, 73 + TILEGX_OPC_BLBCT, 74 + TILEGX_OPC_BLBS, 75 + TILEGX_OPC_BLBST, 76 + TILEGX_OPC_BLEZ, 77 + TILEGX_OPC_BLEZT, 78 + TILEGX_OPC_BLTZ, 79 + TILEGX_OPC_BLTZT, 80 + TILEGX_OPC_BNEZ, 81 + TILEGX_OPC_BNEZT, 82 + TILEGX_OPC_CLZ, 83 + TILEGX_OPC_CMOVEQZ, 84 + TILEGX_OPC_CMOVNEZ, 85 + TILEGX_OPC_CMPEQ, 86 + TILEGX_OPC_CMPEQI, 87 + TILEGX_OPC_CMPEXCH, 88 + TILEGX_OPC_CMPEXCH4, 89 + TILEGX_OPC_CMPLES, 90 + TILEGX_OPC_CMPLEU, 91 + TILEGX_OPC_CMPLTS, 92 + TILEGX_OPC_CMPLTSI, 93 + TILEGX_OPC_CMPLTU, 94 + TILEGX_OPC_CMPLTUI, 95 + TILEGX_OPC_CMPNE, 96 + TILEGX_OPC_CMUL, 97 + TILEGX_OPC_CMULA, 98 + TILEGX_OPC_CMULAF, 99 + TILEGX_OPC_CMULF, 100 + TILEGX_OPC_CMULFR, 101 + TILEGX_OPC_CMULH, 102 + TILEGX_OPC_CMULHR, 103 + TILEGX_OPC_CRC32_32, 104 + TILEGX_OPC_CRC32_8, 105 + TILEGX_OPC_CTZ, 106 + TILEGX_OPC_DBLALIGN, 107 + TILEGX_OPC_DBLALIGN2, 108 + TILEGX_OPC_DBLALIGN4, 109 + TILEGX_OPC_DBLALIGN6, 110 + TILEGX_OPC_DRAIN, 111 + TILEGX_OPC_DTLBPR, 112 + TILEGX_OPC_EXCH, 113 + TILEGX_OPC_EXCH4, 114 + TILEGX_OPC_FDOUBLE_ADD_FLAGS, 115 + TILEGX_OPC_FDOUBLE_ADDSUB, 116 + TILEGX_OPC_FDOUBLE_MUL_FLAGS, 117 + TILEGX_OPC_FDOUBLE_PACK1, 118 + TILEGX_OPC_FDOUBLE_PACK2, 119 + TILEGX_OPC_FDOUBLE_SUB_FLAGS, 120 + TILEGX_OPC_FDOUBLE_UNPACK_MAX, 121 + TILEGX_OPC_FDOUBLE_UNPACK_MIN, 122 + TILEGX_OPC_FETCHADD, 123 + TILEGX_OPC_FETCHADD4, 124 + TILEGX_OPC_FETCHADDGEZ, 125 + TILEGX_OPC_FETCHADDGEZ4, 126 + TILEGX_OPC_FETCHAND, 127 + TILEGX_OPC_FETCHAND4, 128 + TILEGX_OPC_FETCHOR, 129 + TILEGX_OPC_FETCHOR4, 130 + TILEGX_OPC_FINV, 131 + TILEGX_OPC_FLUSH, 132 + TILEGX_OPC_FLUSHWB, 133 + TILEGX_OPC_FNOP, 134 + TILEGX_OPC_FSINGLE_ADD1, 135 + TILEGX_OPC_FSINGLE_ADDSUB2, 136 + TILEGX_OPC_FSINGLE_MUL1, 137 + TILEGX_OPC_FSINGLE_MUL2, 138 + TILEGX_OPC_FSINGLE_PACK1, 139 + TILEGX_OPC_FSINGLE_PACK2, 140 + TILEGX_OPC_FSINGLE_SUB1, 141 + TILEGX_OPC_ICOH, 142 + TILEGX_OPC_ILL, 143 + TILEGX_OPC_INV, 144 + TILEGX_OPC_IRET, 145 + TILEGX_OPC_J, 146 + TILEGX_OPC_JAL, 147 + TILEGX_OPC_JALR, 148 + TILEGX_OPC_JALRP, 149 + TILEGX_OPC_JR, 150 + TILEGX_OPC_JRP, 151 + TILEGX_OPC_LD, 152 + TILEGX_OPC_LD1S, 153 + TILEGX_OPC_LD1S_ADD, 154 + TILEGX_OPC_LD1U, 155 + TILEGX_OPC_LD1U_ADD, 156 + TILEGX_OPC_LD2S, 157 + TILEGX_OPC_LD2S_ADD, 158 + TILEGX_OPC_LD2U, 159 + TILEGX_OPC_LD2U_ADD, 160 + TILEGX_OPC_LD4S, 161 + TILEGX_OPC_LD4S_ADD, 162 + TILEGX_OPC_LD4U, 163 + TILEGX_OPC_LD4U_ADD, 164 + TILEGX_OPC_LD_ADD, 165 + TILEGX_OPC_LDNA, 166 + TILEGX_OPC_LDNA_ADD, 167 + TILEGX_OPC_LDNT, 168 + TILEGX_OPC_LDNT1S, 169 + TILEGX_OPC_LDNT1S_ADD, 170 + TILEGX_OPC_LDNT1U, 171 + TILEGX_OPC_LDNT1U_ADD, 172 + TILEGX_OPC_LDNT2S, 173 + TILEGX_OPC_LDNT2S_ADD, 174 + TILEGX_OPC_LDNT2U, 175 + TILEGX_OPC_LDNT2U_ADD, 176 + TILEGX_OPC_LDNT4S, 177 + TILEGX_OPC_LDNT4S_ADD, 178 + TILEGX_OPC_LDNT4U, 179 + TILEGX_OPC_LDNT4U_ADD, 180 + TILEGX_OPC_LDNT_ADD, 181 + TILEGX_OPC_LNK, 182 + TILEGX_OPC_MF, 183 + TILEGX_OPC_MFSPR, 184 + TILEGX_OPC_MM, 185 + TILEGX_OPC_MNZ, 186 + TILEGX_OPC_MTSPR, 187 + TILEGX_OPC_MUL_HS_HS, 188 + TILEGX_OPC_MUL_HS_HU, 189 + TILEGX_OPC_MUL_HS_LS, 190 + TILEGX_OPC_MUL_HS_LU, 191 + TILEGX_OPC_MUL_HU_HU, 192 + TILEGX_OPC_MUL_HU_LS, 193 + TILEGX_OPC_MUL_HU_LU, 194 + TILEGX_OPC_MUL_LS_LS, 195 + TILEGX_OPC_MUL_LS_LU, 196 + TILEGX_OPC_MUL_LU_LU, 197 + TILEGX_OPC_MULA_HS_HS, 198 + TILEGX_OPC_MULA_HS_HU, 199 + TILEGX_OPC_MULA_HS_LS, 200 + TILEGX_OPC_MULA_HS_LU, 201 + TILEGX_OPC_MULA_HU_HU, 202 + TILEGX_OPC_MULA_HU_LS, 203 + TILEGX_OPC_MULA_HU_LU, 204 + TILEGX_OPC_MULA_LS_LS, 205 + TILEGX_OPC_MULA_LS_LU, 206 + TILEGX_OPC_MULA_LU_LU, 207 + TILEGX_OPC_MULAX, 208 + TILEGX_OPC_MULX, 209 + TILEGX_OPC_MZ, 210 + TILEGX_OPC_NAP, 211 + TILEGX_OPC_NOP, 212 + TILEGX_OPC_NOR, 213 + TILEGX_OPC_OR, 214 + TILEGX_OPC_ORI, 215 + TILEGX_OPC_PCNT, 216 + TILEGX_OPC_REVBITS, 217 + TILEGX_OPC_REVBYTES, 218 + TILEGX_OPC_ROTL, 219 + TILEGX_OPC_ROTLI, 220 + TILEGX_OPC_SHL, 221 + TILEGX_OPC_SHL16INSLI, 222 + TILEGX_OPC_SHL1ADD, 223 + TILEGX_OPC_SHL1ADDX, 224 + TILEGX_OPC_SHL2ADD, 225 + TILEGX_OPC_SHL2ADDX, 226 + TILEGX_OPC_SHL3ADD, 227 + TILEGX_OPC_SHL3ADDX, 228 + TILEGX_OPC_SHLI, 229 + TILEGX_OPC_SHLX, 230 + TILEGX_OPC_SHLXI, 231 + TILEGX_OPC_SHRS, 232 + TILEGX_OPC_SHRSI, 233 + TILEGX_OPC_SHRU, 234 + TILEGX_OPC_SHRUI, 235 + TILEGX_OPC_SHRUX, 236 + TILEGX_OPC_SHRUXI, 237 + TILEGX_OPC_SHUFFLEBYTES, 238 + TILEGX_OPC_ST, 239 + TILEGX_OPC_ST1, 240 + TILEGX_OPC_ST1_ADD, 241 + TILEGX_OPC_ST2, 242 + TILEGX_OPC_ST2_ADD, 243 + TILEGX_OPC_ST4, 244 + TILEGX_OPC_ST4_ADD, 245 + TILEGX_OPC_ST_ADD, 246 + TILEGX_OPC_STNT, 247 + TILEGX_OPC_STNT1, 248 + TILEGX_OPC_STNT1_ADD, 249 + TILEGX_OPC_STNT2, 250 + TILEGX_OPC_STNT2_ADD, 251 + TILEGX_OPC_STNT4, 252 + TILEGX_OPC_STNT4_ADD, 253 + TILEGX_OPC_STNT_ADD, 254 + TILEGX_OPC_SUB, 255 + TILEGX_OPC_SUBX, 256 + TILEGX_OPC_SUBXSC, 257 + TILEGX_OPC_SWINT0, 258 + TILEGX_OPC_SWINT1, 259 + TILEGX_OPC_SWINT2, 260 + TILEGX_OPC_SWINT3, 261 + TILEGX_OPC_TBLIDXB0, 262 + TILEGX_OPC_TBLIDXB1, 263 + TILEGX_OPC_TBLIDXB2, 264 + TILEGX_OPC_TBLIDXB3, 265 + TILEGX_OPC_V1ADD, 266 + TILEGX_OPC_V1ADDI, 267 + TILEGX_OPC_V1ADDUC, 268 + TILEGX_OPC_V1ADIFFU, 269 + TILEGX_OPC_V1AVGU, 270 + TILEGX_OPC_V1CMPEQ, 271 + TILEGX_OPC_V1CMPEQI, 272 + TILEGX_OPC_V1CMPLES, 273 + TILEGX_OPC_V1CMPLEU, 274 + TILEGX_OPC_V1CMPLTS, 275 + TILEGX_OPC_V1CMPLTSI, 276 + TILEGX_OPC_V1CMPLTU, 277 + TILEGX_OPC_V1CMPLTUI, 278 + TILEGX_OPC_V1CMPNE, 279 + TILEGX_OPC_V1DDOTPU, 280 + TILEGX_OPC_V1DDOTPUA, 281 + TILEGX_OPC_V1DDOTPUS, 282 + TILEGX_OPC_V1DDOTPUSA, 283 + TILEGX_OPC_V1DOTP, 284 + TILEGX_OPC_V1DOTPA, 285 + TILEGX_OPC_V1DOTPU, 286 + TILEGX_OPC_V1DOTPUA, 287 + TILEGX_OPC_V1DOTPUS, 288 + TILEGX_OPC_V1DOTPUSA, 289 + TILEGX_OPC_V1INT_H, 290 + TILEGX_OPC_V1INT_L, 291 + TILEGX_OPC_V1MAXU, 292 + TILEGX_OPC_V1MAXUI, 293 + TILEGX_OPC_V1MINU, 294 + TILEGX_OPC_V1MINUI, 295 + TILEGX_OPC_V1MNZ, 296 + TILEGX_OPC_V1MULTU, 297 + TILEGX_OPC_V1MULU, 298 + TILEGX_OPC_V1MULUS, 299 + TILEGX_OPC_V1MZ, 300 + TILEGX_OPC_V1SADAU, 301 + TILEGX_OPC_V1SADU, 302 + TILEGX_OPC_V1SHL, 303 + TILEGX_OPC_V1SHLI, 304 + TILEGX_OPC_V1SHRS, 305 + TILEGX_OPC_V1SHRSI, 306 + TILEGX_OPC_V1SHRU, 307 + TILEGX_OPC_V1SHRUI, 308 + TILEGX_OPC_V1SUB, 309 + TILEGX_OPC_V1SUBUC, 310 + TILEGX_OPC_V2ADD, 311 + TILEGX_OPC_V2ADDI, 312 + TILEGX_OPC_V2ADDSC, 313 + TILEGX_OPC_V2ADIFFS, 314 + TILEGX_OPC_V2AVGS, 315 + TILEGX_OPC_V2CMPEQ, 316 + TILEGX_OPC_V2CMPEQI, 317 + TILEGX_OPC_V2CMPLES, 318 + TILEGX_OPC_V2CMPLEU, 319 + TILEGX_OPC_V2CMPLTS, 320 + TILEGX_OPC_V2CMPLTSI, 321 + TILEGX_OPC_V2CMPLTU, 322 + TILEGX_OPC_V2CMPLTUI, 323 + TILEGX_OPC_V2CMPNE, 324 + TILEGX_OPC_V2DOTP, 325 + TILEGX_OPC_V2DOTPA, 326 + TILEGX_OPC_V2INT_H, 327 + TILEGX_OPC_V2INT_L, 328 + TILEGX_OPC_V2MAXS, 329 + TILEGX_OPC_V2MAXSI, 330 + TILEGX_OPC_V2MINS, 331 + TILEGX_OPC_V2MINSI, 332 + TILEGX_OPC_V2MNZ, 333 + TILEGX_OPC_V2MULFSC, 334 + TILEGX_OPC_V2MULS, 335 + TILEGX_OPC_V2MULTS, 336 + TILEGX_OPC_V2MZ, 337 + TILEGX_OPC_V2PACKH, 338 + TILEGX_OPC_V2PACKL, 339 + TILEGX_OPC_V2PACKUC, 340 + TILEGX_OPC_V2SADAS, 341 + TILEGX_OPC_V2SADAU, 342 + TILEGX_OPC_V2SADS, 343 + TILEGX_OPC_V2SADU, 344 + TILEGX_OPC_V2SHL, 345 + TILEGX_OPC_V2SHLI, 346 + TILEGX_OPC_V2SHLSC, 347 + TILEGX_OPC_V2SHRS, 348 + TILEGX_OPC_V2SHRSI, 349 + TILEGX_OPC_V2SHRU, 350 + TILEGX_OPC_V2SHRUI, 351 + TILEGX_OPC_V2SUB, 352 + TILEGX_OPC_V2SUBSC, 353 + TILEGX_OPC_V4ADD, 354 + TILEGX_OPC_V4ADDSC, 355 + TILEGX_OPC_V4INT_H, 356 + TILEGX_OPC_V4INT_L, 357 + TILEGX_OPC_V4PACKSC, 358 + TILEGX_OPC_V4SHL, 359 + TILEGX_OPC_V4SHLSC, 360 + TILEGX_OPC_V4SHRS, 361 + TILEGX_OPC_V4SHRU, 362 + TILEGX_OPC_V4SUB, 363 + TILEGX_OPC_V4SUBSC, 364 + TILEGX_OPC_WH64, 365 + TILEGX_OPC_XOR, 366 + TILEGX_OPC_XORI, 367 + TILEGX_OPC_NONE 368 + } tilegx_mnemonic; 369 + 370 + 371 + 372 + typedef enum 373 + { 374 + TILEGX_PIPELINE_X0, 375 + TILEGX_PIPELINE_X1, 376 + TILEGX_PIPELINE_Y0, 377 + TILEGX_PIPELINE_Y1, 378 + TILEGX_PIPELINE_Y2, 379 + } tilegx_pipeline; 380 + 381 + #define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1) 382 + 383 + typedef enum 384 + { 385 + TILEGX_OP_TYPE_REGISTER, 386 + TILEGX_OP_TYPE_IMMEDIATE, 387 + TILEGX_OP_TYPE_ADDRESS, 388 + TILEGX_OP_TYPE_SPR 389 + } tilegx_operand_type; 390 + 391 + struct tilegx_operand 392 + { 393 + /* Is this operand a register, immediate or address? */ 394 + tilegx_operand_type type; 395 + 396 + /* The default relocation type for this operand. */ 397 + signed int default_reloc : 16; 398 + 399 + /* How many bits is this value? (used for range checking) */ 400 + unsigned int num_bits : 5; 401 + 402 + /* Is the value signed? (used for range checking) */ 403 + unsigned int is_signed : 1; 404 + 405 + /* Is this operand a source register? */ 406 + unsigned int is_src_reg : 1; 407 + 408 + /* Is this operand written? (i.e. is it a destination register) */ 409 + unsigned int is_dest_reg : 1; 410 + 411 + /* Is this operand PC-relative? */ 412 + unsigned int is_pc_relative : 1; 413 + 414 + /* By how many bits do we right shift the value before inserting? */ 415 + unsigned int rightshift : 2; 416 + 417 + /* Return the bits for this operand to be ORed into an existing bundle. */ 418 + tilegx_bundle_bits (*insert) (int op); 419 + 420 + /* Extract this operand and return it. */ 421 + unsigned int (*extract) (tilegx_bundle_bits bundle); 422 + }; 423 + 424 + 425 + extern const struct tilegx_operand tilegx_operands[]; 426 + 427 + /* One finite-state machine per pipe for rapid instruction decoding. */ 428 + extern const unsigned short * const 429 + tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS]; 430 + 431 + 432 + struct tilegx_opcode 433 + { 434 + /* The opcode mnemonic, e.g. "add" */ 435 + const char *name; 436 + 437 + /* The enum value for this mnemonic. */ 438 + tilegx_mnemonic mnemonic; 439 + 440 + /* A bit mask of which of the five pipes this instruction 441 + is compatible with: 442 + X0 0x01 443 + X1 0x02 444 + Y0 0x04 445 + Y1 0x08 446 + Y2 0x10 */ 447 + unsigned char pipes; 448 + 449 + /* How many operands are there? */ 450 + unsigned char num_operands; 451 + 452 + /* Which register does this write implicitly, or TREG_ZERO if none? */ 453 + unsigned char implicitly_written_register; 454 + 455 + /* Can this be bundled with other instructions (almost always true). */ 456 + unsigned char can_bundle; 457 + 458 + /* The description of the operands. Each of these is an 459 + * index into the tilegx_operands[] table. */ 460 + unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS]; 461 + 462 + }; 463 + 464 + extern const struct tilegx_opcode tilegx_opcodes[]; 465 + 466 + /* Used for non-textual disassembly into structs. */ 467 + struct tilegx_decoded_instruction 468 + { 469 + const struct tilegx_opcode *opcode; 470 + const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS]; 471 + long long operand_values[TILEGX_MAX_OPERANDS]; 472 + }; 473 + 474 + 475 + /* Disassemble a bundle into a struct for machine processing. */ 476 + extern int parse_insn_tilegx(tilegx_bundle_bits bits, 477 + unsigned long long pc, 478 + struct tilegx_decoded_instruction 479 + decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]); 480 + 481 + 482 + 483 + #endif /* opcode_tilegx_h */
+14 -5
arch/tile/kernel/backtrace.c
··· 1 1 /* 2 - * Copyright 2010 Tilera Corporation. All Rights Reserved. 2 + * Copyright 2011 Tilera Corporation. All Rights Reserved. 3 3 * 4 4 * This program is free software; you can redistribute it and/or 5 5 * modify it under the terms of the GNU General Public License ··· 15 15 #include <linux/kernel.h> 16 16 #include <linux/string.h> 17 17 #include <asm/backtrace.h> 18 - #include <asm/opcode-tile.h> 18 + #include <asm/tile-desc.h> 19 19 #include <arch/abi.h> 20 20 21 21 #ifdef __tilegx__ 22 - #define tile_bundle_bits tilegx_bundle_bits 23 22 #define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE 24 - #define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES 25 23 #define tile_decoded_instruction tilegx_decoded_instruction 26 24 #define tile_mnemonic tilegx_mnemonic 27 25 #define parse_insn_tile parse_insn_tilegx ··· 33 35 #define OPCODE_STORE TILEGX_OPC_ST 34 36 typedef long long bt_int_reg_t; 35 37 #else 36 - #define OPCODE_STORE TILE_OPC_SW 38 + #define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE 39 + #define tile_decoded_instruction tilepro_decoded_instruction 40 + #define tile_mnemonic tilepro_mnemonic 41 + #define parse_insn_tile parse_insn_tilepro 42 + #define TILE_OPC_IRET TILEPRO_OPC_IRET 43 + #define TILE_OPC_ADDI TILEPRO_OPC_ADDI 44 + #define TILE_OPC_ADDLI TILEPRO_OPC_ADDLI 45 + #define TILE_OPC_INFO TILEPRO_OPC_INFO 46 + #define TILE_OPC_INFOL TILEPRO_OPC_INFOL 47 + #define TILE_OPC_JRP TILEPRO_OPC_JRP 48 + #define TILE_OPC_MOVE TILEPRO_OPC_MOVE 49 + #define OPCODE_STORE TILEPRO_OPC_SW 37 50 typedef int bt_int_reg_t; 38 51 #endif 39 52
+1 -1
arch/tile/kernel/module.c
··· 20 20 #include <linux/fs.h> 21 21 #include <linux/string.h> 22 22 #include <linux/kernel.h> 23 - #include <asm/opcode-tile.h> 24 23 #include <asm/pgtable.h> 25 24 #include <asm/homecache.h> 25 + #include <arch/opcode.h> 26 26 27 27 #ifdef __tilegx__ 28 28 # define Elf_Rela Elf64_Rela
+4 -5
arch/tile/kernel/single_step.c
··· 25 25 #include <linux/types.h> 26 26 #include <linux/err.h> 27 27 #include <asm/cacheflush.h> 28 - #include <asm/opcode-tile.h> 29 - #include <asm/opcode_constants.h> 30 28 #include <arch/abi.h> 29 + #include <arch/opcode.h> 31 30 32 31 #define signExtend17(val) sign_extend((val), 17) 33 32 #define TILE_X1_MASK (0xffffffffULL << 31) ··· 117 118 int val_reg, addr_reg, err, val; 118 119 119 120 /* Get address and value registers */ 120 - if (bundle & TILE_BUNDLE_Y_ENCODING_MASK) { 121 + if (bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK) { 121 122 addr_reg = get_SrcA_Y2(bundle); 122 123 val_reg = get_SrcBDest_Y2(bundle); 123 124 } else if (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) { ··· 228 229 } 229 230 ++unaligned_fixup_count; 230 231 231 - if (bundle & TILE_BUNDLE_Y_ENCODING_MASK) { 232 + if (bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK) { 232 233 /* Convert the Y2 instruction to a prefetch. */ 233 234 bundle &= ~(create_SrcBDest_Y2(-1) | 234 235 create_Opcode_Y2(-1)); ··· 388 389 state->branch_next_pc = 0; 389 390 state->update = 0; 390 391 391 - if (!(bundle & TILE_BUNDLE_Y_ENCODING_MASK)) { 392 + if (!(bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK)) { 392 393 /* two wide, check for control flow */ 393 394 int opcode = get_Opcode_X1(bundle); 394 395
+1174 -1068
arch/tile/kernel/tile-desc_32.c
··· 1 + /* TILEPro opcode information. 2 + * 3 + * Copyright 2011 Tilera Corporation. All Rights Reserved. 4 + * 5 + * This program is free software; you can redistribute it and/or 6 + * modify it under the terms of the GNU General Public License 7 + * as published by the Free Software Foundation, version 2. 8 + * 9 + * This program is distributed in the hope that it will be useful, but 10 + * WITHOUT ANY WARRANTY; without even the implied warranty of 11 + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 + * NON INFRINGEMENT. See the GNU General Public License for 13 + * more details. 14 + * 15 + * 16 + * 17 + * 18 + * 19 + */ 20 + 1 21 /* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */ 2 22 #define BFD_RELOC(x) -1 3 23 ··· 26 6 #define TREG_SN 56 27 7 #define TREG_ZERO 63 28 8 29 - /* FIXME: Rename this. */ 30 - #include <asm/opcode-tile.h> 31 - 32 9 #include <linux/stddef.h> 10 + #include <asm/tile-desc.h> 33 11 34 - const struct tile_opcode tile_opcodes[395] = 12 + const struct tilepro_opcode tilepro_opcodes[395] = 35 13 { 36 - { "bpt", TILE_OPC_BPT, 0x2, 0, TREG_ZERO, 0, 14 + { "bpt", TILEPRO_OPC_BPT, 0x2, 0, TREG_ZERO, 0, 37 15 { { 0, }, { }, { 0, }, { 0, }, { 0, } }, 38 16 }, 39 - { "info", TILE_OPC_INFO, 0xf, 1, TREG_ZERO, 1, 17 + { "info", TILEPRO_OPC_INFO, 0xf, 1, TREG_ZERO, 1, 40 18 { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } }, 41 19 }, 42 - { "infol", TILE_OPC_INFOL, 0x3, 1, TREG_ZERO, 1, 20 + { "infol", TILEPRO_OPC_INFOL, 0x3, 1, TREG_ZERO, 1, 43 21 { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } }, 44 22 }, 45 - { "j", TILE_OPC_J, 0x2, 1, TREG_ZERO, 1, 23 + { "j", TILEPRO_OPC_J, 0x2, 1, TREG_ZERO, 1, 46 24 { { 0, }, { 6 }, { 0, }, { 0, }, { 0, } }, 47 25 }, 48 - { "jal", TILE_OPC_JAL, 0x2, 1, TREG_LR, 1, 26 + { "jal", TILEPRO_OPC_JAL, 0x2, 1, TREG_LR, 1, 49 27 { { 0, }, { 6 }, { 0, }, { 0, }, { 0, } }, 50 28 }, 51 - { "move", TILE_OPC_MOVE, 0xf, 2, TREG_ZERO, 1, 29 + { "move", TILEPRO_OPC_MOVE, 0xf, 2, TREG_ZERO, 1, 52 30 { { 7, 8 }, { 9, 10 }, { 11, 12 }, { 13, 14 }, { 0, } }, 53 31 }, 54 - { "move.sn", TILE_OPC_MOVE_SN, 0x3, 2, TREG_SN, 1, 32 + { "move.sn", TILEPRO_OPC_MOVE_SN, 0x3, 2, TREG_SN, 1, 55 33 { { 7, 8 }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, 56 34 }, 57 - { "movei", TILE_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1, 35 + { "movei", TILEPRO_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1, 58 36 { { 7, 0 }, { 9, 1 }, { 11, 2 }, { 13, 3 }, { 0, } }, 59 37 }, 60 - { "movei.sn", TILE_OPC_MOVEI_SN, 0x3, 2, TREG_SN, 1, 38 + { "movei.sn", TILEPRO_OPC_MOVEI_SN, 0x3, 2, TREG_SN, 1, 61 39 { { 7, 0 }, { 9, 1 }, { 0, }, { 0, }, { 0, } }, 62 40 }, 63 - { "moveli", TILE_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1, 41 + { "moveli", TILEPRO_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1, 64 42 { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } }, 65 43 }, 66 - { "moveli.sn", TILE_OPC_MOVELI_SN, 0x3, 2, TREG_SN, 1, 44 + { "moveli.sn", TILEPRO_OPC_MOVELI_SN, 0x3, 2, TREG_SN, 1, 67 45 { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } }, 68 46 }, 69 - { "movelis", TILE_OPC_MOVELIS, 0x3, 2, TREG_SN, 1, 47 + { "movelis", TILEPRO_OPC_MOVELIS, 0x3, 2, TREG_SN, 1, 70 48 { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } }, 71 49 }, 72 - { "prefetch", TILE_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1, 50 + { "prefetch", TILEPRO_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1, 73 51 { { 0, }, { 10 }, { 0, }, { 0, }, { 15 } }, 74 52 }, 75 - { "raise", TILE_OPC_RAISE, 0x2, 0, TREG_ZERO, 1, 53 + { "raise", TILEPRO_OPC_RAISE, 0x2, 0, TREG_ZERO, 1, 76 54 { { 0, }, { }, { 0, }, { 0, }, { 0, } }, 77 55 }, 78 - { "add", TILE_OPC_ADD, 0xf, 3, TREG_ZERO, 1, 56 + { "add", TILEPRO_OPC_ADD, 0xf, 3, TREG_ZERO, 1, 79 57 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 80 58 }, 81 - { "add.sn", TILE_OPC_ADD_SN, 0x3, 3, TREG_SN, 1, 59 + { "add.sn", TILEPRO_OPC_ADD_SN, 0x3, 3, TREG_SN, 1, 82 60 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 83 61 }, 84 - { "addb", TILE_OPC_ADDB, 0x3, 3, TREG_ZERO, 1, 62 + { "addb", TILEPRO_OPC_ADDB, 0x3, 3, TREG_ZERO, 1, 85 63 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 86 64 }, 87 - { "addb.sn", TILE_OPC_ADDB_SN, 0x3, 3, TREG_SN, 1, 65 + { "addb.sn", TILEPRO_OPC_ADDB_SN, 0x3, 3, TREG_SN, 1, 88 66 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 89 67 }, 90 - { "addbs_u", TILE_OPC_ADDBS_U, 0x3, 3, TREG_ZERO, 1, 68 + { "addbs_u", TILEPRO_OPC_ADDBS_U, 0x3, 3, TREG_ZERO, 1, 91 69 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 92 70 }, 93 - { "addbs_u.sn", TILE_OPC_ADDBS_U_SN, 0x3, 3, TREG_SN, 1, 71 + { "addbs_u.sn", TILEPRO_OPC_ADDBS_U_SN, 0x3, 3, TREG_SN, 1, 94 72 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 95 73 }, 96 - { "addh", TILE_OPC_ADDH, 0x3, 3, TREG_ZERO, 1, 74 + { "addh", TILEPRO_OPC_ADDH, 0x3, 3, TREG_ZERO, 1, 97 75 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 98 76 }, 99 - { "addh.sn", TILE_OPC_ADDH_SN, 0x3, 3, TREG_SN, 1, 77 + { "addh.sn", TILEPRO_OPC_ADDH_SN, 0x3, 3, TREG_SN, 1, 100 78 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 101 79 }, 102 - { "addhs", TILE_OPC_ADDHS, 0x3, 3, TREG_ZERO, 1, 80 + { "addhs", TILEPRO_OPC_ADDHS, 0x3, 3, TREG_ZERO, 1, 103 81 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 104 82 }, 105 - { "addhs.sn", TILE_OPC_ADDHS_SN, 0x3, 3, TREG_SN, 1, 83 + { "addhs.sn", TILEPRO_OPC_ADDHS_SN, 0x3, 3, TREG_SN, 1, 106 84 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 107 85 }, 108 - { "addi", TILE_OPC_ADDI, 0xf, 3, TREG_ZERO, 1, 86 + { "addi", TILEPRO_OPC_ADDI, 0xf, 3, TREG_ZERO, 1, 109 87 { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, 110 88 }, 111 - { "addi.sn", TILE_OPC_ADDI_SN, 0x3, 3, TREG_SN, 1, 89 + { "addi.sn", TILEPRO_OPC_ADDI_SN, 0x3, 3, TREG_SN, 1, 112 90 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 113 91 }, 114 - { "addib", TILE_OPC_ADDIB, 0x3, 3, TREG_ZERO, 1, 92 + { "addib", TILEPRO_OPC_ADDIB, 0x3, 3, TREG_ZERO, 1, 115 93 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 116 94 }, 117 - { "addib.sn", TILE_OPC_ADDIB_SN, 0x3, 3, TREG_SN, 1, 95 + { "addib.sn", TILEPRO_OPC_ADDIB_SN, 0x3, 3, TREG_SN, 1, 118 96 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 119 97 }, 120 - { "addih", TILE_OPC_ADDIH, 0x3, 3, TREG_ZERO, 1, 98 + { "addih", TILEPRO_OPC_ADDIH, 0x3, 3, TREG_ZERO, 1, 121 99 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 122 100 }, 123 - { "addih.sn", TILE_OPC_ADDIH_SN, 0x3, 3, TREG_SN, 1, 101 + { "addih.sn", TILEPRO_OPC_ADDIH_SN, 0x3, 3, TREG_SN, 1, 124 102 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 125 103 }, 126 - { "addli", TILE_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1, 104 + { "addli", TILEPRO_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1, 127 105 { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } }, 128 106 }, 129 - { "addli.sn", TILE_OPC_ADDLI_SN, 0x3, 3, TREG_SN, 1, 107 + { "addli.sn", TILEPRO_OPC_ADDLI_SN, 0x3, 3, TREG_SN, 1, 130 108 { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } }, 131 109 }, 132 - { "addlis", TILE_OPC_ADDLIS, 0x3, 3, TREG_SN, 1, 110 + { "addlis", TILEPRO_OPC_ADDLIS, 0x3, 3, TREG_SN, 1, 133 111 { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } }, 134 112 }, 135 - { "adds", TILE_OPC_ADDS, 0x3, 3, TREG_ZERO, 1, 113 + { "adds", TILEPRO_OPC_ADDS, 0x3, 3, TREG_ZERO, 1, 136 114 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 137 115 }, 138 - { "adds.sn", TILE_OPC_ADDS_SN, 0x3, 3, TREG_SN, 1, 116 + { "adds.sn", TILEPRO_OPC_ADDS_SN, 0x3, 3, TREG_SN, 1, 139 117 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 140 118 }, 141 - { "adiffb_u", TILE_OPC_ADIFFB_U, 0x1, 3, TREG_ZERO, 1, 119 + { "adiffb_u", TILEPRO_OPC_ADIFFB_U, 0x1, 3, TREG_ZERO, 1, 142 120 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 143 121 }, 144 - { "adiffb_u.sn", TILE_OPC_ADIFFB_U_SN, 0x1, 3, TREG_SN, 1, 122 + { "adiffb_u.sn", TILEPRO_OPC_ADIFFB_U_SN, 0x1, 3, TREG_SN, 1, 145 123 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 146 124 }, 147 - { "adiffh", TILE_OPC_ADIFFH, 0x1, 3, TREG_ZERO, 1, 125 + { "adiffh", TILEPRO_OPC_ADIFFH, 0x1, 3, TREG_ZERO, 1, 148 126 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 149 127 }, 150 - { "adiffh.sn", TILE_OPC_ADIFFH_SN, 0x1, 3, TREG_SN, 1, 128 + { "adiffh.sn", TILEPRO_OPC_ADIFFH_SN, 0x1, 3, TREG_SN, 1, 151 129 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 152 130 }, 153 - { "and", TILE_OPC_AND, 0xf, 3, TREG_ZERO, 1, 131 + { "and", TILEPRO_OPC_AND, 0xf, 3, TREG_ZERO, 1, 154 132 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 155 133 }, 156 - { "and.sn", TILE_OPC_AND_SN, 0x3, 3, TREG_SN, 1, 134 + { "and.sn", TILEPRO_OPC_AND_SN, 0x3, 3, TREG_SN, 1, 157 135 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 158 136 }, 159 - { "andi", TILE_OPC_ANDI, 0xf, 3, TREG_ZERO, 1, 137 + { "andi", TILEPRO_OPC_ANDI, 0xf, 3, TREG_ZERO, 1, 160 138 { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, 161 139 }, 162 - { "andi.sn", TILE_OPC_ANDI_SN, 0x3, 3, TREG_SN, 1, 140 + { "andi.sn", TILEPRO_OPC_ANDI_SN, 0x3, 3, TREG_SN, 1, 163 141 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 164 142 }, 165 - { "auli", TILE_OPC_AULI, 0x3, 3, TREG_ZERO, 1, 143 + { "auli", TILEPRO_OPC_AULI, 0x3, 3, TREG_ZERO, 1, 166 144 { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } }, 167 145 }, 168 - { "avgb_u", TILE_OPC_AVGB_U, 0x1, 3, TREG_ZERO, 1, 146 + { "avgb_u", TILEPRO_OPC_AVGB_U, 0x1, 3, TREG_ZERO, 1, 169 147 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 170 148 }, 171 - { "avgb_u.sn", TILE_OPC_AVGB_U_SN, 0x1, 3, TREG_SN, 1, 149 + { "avgb_u.sn", TILEPRO_OPC_AVGB_U_SN, 0x1, 3, TREG_SN, 1, 172 150 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 173 151 }, 174 - { "avgh", TILE_OPC_AVGH, 0x1, 3, TREG_ZERO, 1, 152 + { "avgh", TILEPRO_OPC_AVGH, 0x1, 3, TREG_ZERO, 1, 175 153 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 176 154 }, 177 - { "avgh.sn", TILE_OPC_AVGH_SN, 0x1, 3, TREG_SN, 1, 155 + { "avgh.sn", TILEPRO_OPC_AVGH_SN, 0x1, 3, TREG_SN, 1, 178 156 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 179 157 }, 180 - { "bbns", TILE_OPC_BBNS, 0x2, 2, TREG_ZERO, 1, 158 + { "bbns", TILEPRO_OPC_BBNS, 0x2, 2, TREG_ZERO, 1, 181 159 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 182 160 }, 183 - { "bbns.sn", TILE_OPC_BBNS_SN, 0x2, 2, TREG_SN, 1, 161 + { "bbns.sn", TILEPRO_OPC_BBNS_SN, 0x2, 2, TREG_SN, 1, 184 162 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 185 163 }, 186 - { "bbnst", TILE_OPC_BBNST, 0x2, 2, TREG_ZERO, 1, 164 + { "bbnst", TILEPRO_OPC_BBNST, 0x2, 2, TREG_ZERO, 1, 187 165 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 188 166 }, 189 - { "bbnst.sn", TILE_OPC_BBNST_SN, 0x2, 2, TREG_SN, 1, 167 + { "bbnst.sn", TILEPRO_OPC_BBNST_SN, 0x2, 2, TREG_SN, 1, 190 168 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 191 169 }, 192 - { "bbs", TILE_OPC_BBS, 0x2, 2, TREG_ZERO, 1, 170 + { "bbs", TILEPRO_OPC_BBS, 0x2, 2, TREG_ZERO, 1, 193 171 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 194 172 }, 195 - { "bbs.sn", TILE_OPC_BBS_SN, 0x2, 2, TREG_SN, 1, 173 + { "bbs.sn", TILEPRO_OPC_BBS_SN, 0x2, 2, TREG_SN, 1, 196 174 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 197 175 }, 198 - { "bbst", TILE_OPC_BBST, 0x2, 2, TREG_ZERO, 1, 176 + { "bbst", TILEPRO_OPC_BBST, 0x2, 2, TREG_ZERO, 1, 199 177 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 200 178 }, 201 - { "bbst.sn", TILE_OPC_BBST_SN, 0x2, 2, TREG_SN, 1, 179 + { "bbst.sn", TILEPRO_OPC_BBST_SN, 0x2, 2, TREG_SN, 1, 202 180 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 203 181 }, 204 - { "bgez", TILE_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1, 182 + { "bgez", TILEPRO_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1, 205 183 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 206 184 }, 207 - { "bgez.sn", TILE_OPC_BGEZ_SN, 0x2, 2, TREG_SN, 1, 185 + { "bgez.sn", TILEPRO_OPC_BGEZ_SN, 0x2, 2, TREG_SN, 1, 208 186 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 209 187 }, 210 - { "bgezt", TILE_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1, 188 + { "bgezt", TILEPRO_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1, 211 189 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 212 190 }, 213 - { "bgezt.sn", TILE_OPC_BGEZT_SN, 0x2, 2, TREG_SN, 1, 191 + { "bgezt.sn", TILEPRO_OPC_BGEZT_SN, 0x2, 2, TREG_SN, 1, 214 192 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 215 193 }, 216 - { "bgz", TILE_OPC_BGZ, 0x2, 2, TREG_ZERO, 1, 194 + { "bgz", TILEPRO_OPC_BGZ, 0x2, 2, TREG_ZERO, 1, 217 195 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 218 196 }, 219 - { "bgz.sn", TILE_OPC_BGZ_SN, 0x2, 2, TREG_SN, 1, 197 + { "bgz.sn", TILEPRO_OPC_BGZ_SN, 0x2, 2, TREG_SN, 1, 220 198 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 221 199 }, 222 - { "bgzt", TILE_OPC_BGZT, 0x2, 2, TREG_ZERO, 1, 200 + { "bgzt", TILEPRO_OPC_BGZT, 0x2, 2, TREG_ZERO, 1, 223 201 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 224 202 }, 225 - { "bgzt.sn", TILE_OPC_BGZT_SN, 0x2, 2, TREG_SN, 1, 203 + { "bgzt.sn", TILEPRO_OPC_BGZT_SN, 0x2, 2, TREG_SN, 1, 226 204 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 227 205 }, 228 - { "bitx", TILE_OPC_BITX, 0x5, 2, TREG_ZERO, 1, 206 + { "bitx", TILEPRO_OPC_BITX, 0x5, 2, TREG_ZERO, 1, 229 207 { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, 230 208 }, 231 - { "bitx.sn", TILE_OPC_BITX_SN, 0x1, 2, TREG_SN, 1, 209 + { "bitx.sn", TILEPRO_OPC_BITX_SN, 0x1, 2, TREG_SN, 1, 232 210 { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, 233 211 }, 234 - { "blez", TILE_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1, 212 + { "blez", TILEPRO_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1, 235 213 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 236 214 }, 237 - { "blez.sn", TILE_OPC_BLEZ_SN, 0x2, 2, TREG_SN, 1, 215 + { "blez.sn", TILEPRO_OPC_BLEZ_SN, 0x2, 2, TREG_SN, 1, 238 216 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 239 217 }, 240 - { "blezt", TILE_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1, 218 + { "blezt", TILEPRO_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1, 241 219 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 242 220 }, 243 - { "blezt.sn", TILE_OPC_BLEZT_SN, 0x2, 2, TREG_SN, 1, 221 + { "blezt.sn", TILEPRO_OPC_BLEZT_SN, 0x2, 2, TREG_SN, 1, 244 222 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 245 223 }, 246 - { "blz", TILE_OPC_BLZ, 0x2, 2, TREG_ZERO, 1, 224 + { "blz", TILEPRO_OPC_BLZ, 0x2, 2, TREG_ZERO, 1, 247 225 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 248 226 }, 249 - { "blz.sn", TILE_OPC_BLZ_SN, 0x2, 2, TREG_SN, 1, 227 + { "blz.sn", TILEPRO_OPC_BLZ_SN, 0x2, 2, TREG_SN, 1, 250 228 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 251 229 }, 252 - { "blzt", TILE_OPC_BLZT, 0x2, 2, TREG_ZERO, 1, 230 + { "blzt", TILEPRO_OPC_BLZT, 0x2, 2, TREG_ZERO, 1, 253 231 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 254 232 }, 255 - { "blzt.sn", TILE_OPC_BLZT_SN, 0x2, 2, TREG_SN, 1, 233 + { "blzt.sn", TILEPRO_OPC_BLZT_SN, 0x2, 2, TREG_SN, 1, 256 234 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 257 235 }, 258 - { "bnz", TILE_OPC_BNZ, 0x2, 2, TREG_ZERO, 1, 236 + { "bnz", TILEPRO_OPC_BNZ, 0x2, 2, TREG_ZERO, 1, 259 237 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 260 238 }, 261 - { "bnz.sn", TILE_OPC_BNZ_SN, 0x2, 2, TREG_SN, 1, 239 + { "bnz.sn", TILEPRO_OPC_BNZ_SN, 0x2, 2, TREG_SN, 1, 262 240 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 263 241 }, 264 - { "bnzt", TILE_OPC_BNZT, 0x2, 2, TREG_ZERO, 1, 242 + { "bnzt", TILEPRO_OPC_BNZT, 0x2, 2, TREG_ZERO, 1, 265 243 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 266 244 }, 267 - { "bnzt.sn", TILE_OPC_BNZT_SN, 0x2, 2, TREG_SN, 1, 245 + { "bnzt.sn", TILEPRO_OPC_BNZT_SN, 0x2, 2, TREG_SN, 1, 268 246 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 269 247 }, 270 - { "bytex", TILE_OPC_BYTEX, 0x5, 2, TREG_ZERO, 1, 248 + { "bytex", TILEPRO_OPC_BYTEX, 0x5, 2, TREG_ZERO, 1, 271 249 { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, 272 250 }, 273 - { "bytex.sn", TILE_OPC_BYTEX_SN, 0x1, 2, TREG_SN, 1, 251 + { "bytex.sn", TILEPRO_OPC_BYTEX_SN, 0x1, 2, TREG_SN, 1, 274 252 { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, 275 253 }, 276 - { "bz", TILE_OPC_BZ, 0x2, 2, TREG_ZERO, 1, 254 + { "bz", TILEPRO_OPC_BZ, 0x2, 2, TREG_ZERO, 1, 277 255 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 278 256 }, 279 - { "bz.sn", TILE_OPC_BZ_SN, 0x2, 2, TREG_SN, 1, 257 + { "bz.sn", TILEPRO_OPC_BZ_SN, 0x2, 2, TREG_SN, 1, 280 258 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 281 259 }, 282 - { "bzt", TILE_OPC_BZT, 0x2, 2, TREG_ZERO, 1, 260 + { "bzt", TILEPRO_OPC_BZT, 0x2, 2, TREG_ZERO, 1, 283 261 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 284 262 }, 285 - { "bzt.sn", TILE_OPC_BZT_SN, 0x2, 2, TREG_SN, 1, 263 + { "bzt.sn", TILEPRO_OPC_BZT_SN, 0x2, 2, TREG_SN, 1, 286 264 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, 287 265 }, 288 - { "clz", TILE_OPC_CLZ, 0x5, 2, TREG_ZERO, 1, 266 + { "clz", TILEPRO_OPC_CLZ, 0x5, 2, TREG_ZERO, 1, 289 267 { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, 290 268 }, 291 - { "clz.sn", TILE_OPC_CLZ_SN, 0x1, 2, TREG_SN, 1, 269 + { "clz.sn", TILEPRO_OPC_CLZ_SN, 0x1, 2, TREG_SN, 1, 292 270 { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, 293 271 }, 294 - { "crc32_32", TILE_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1, 272 + { "crc32_32", TILEPRO_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1, 295 273 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 296 274 }, 297 - { "crc32_32.sn", TILE_OPC_CRC32_32_SN, 0x1, 3, TREG_SN, 1, 275 + { "crc32_32.sn", TILEPRO_OPC_CRC32_32_SN, 0x1, 3, TREG_SN, 1, 298 276 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 299 277 }, 300 - { "crc32_8", TILE_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1, 278 + { "crc32_8", TILEPRO_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1, 301 279 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 302 280 }, 303 - { "crc32_8.sn", TILE_OPC_CRC32_8_SN, 0x1, 3, TREG_SN, 1, 281 + { "crc32_8.sn", TILEPRO_OPC_CRC32_8_SN, 0x1, 3, TREG_SN, 1, 304 282 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 305 283 }, 306 - { "ctz", TILE_OPC_CTZ, 0x5, 2, TREG_ZERO, 1, 284 + { "ctz", TILEPRO_OPC_CTZ, 0x5, 2, TREG_ZERO, 1, 307 285 { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, 308 286 }, 309 - { "ctz.sn", TILE_OPC_CTZ_SN, 0x1, 2, TREG_SN, 1, 287 + { "ctz.sn", TILEPRO_OPC_CTZ_SN, 0x1, 2, TREG_SN, 1, 310 288 { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, 311 289 }, 312 - { "drain", TILE_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0, 290 + { "drain", TILEPRO_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0, 313 291 { { 0, }, { }, { 0, }, { 0, }, { 0, } }, 314 292 }, 315 - { "dtlbpr", TILE_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1, 293 + { "dtlbpr", TILEPRO_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1, 316 294 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, 317 295 }, 318 - { "dword_align", TILE_OPC_DWORD_ALIGN, 0x1, 3, TREG_ZERO, 1, 296 + { "dword_align", TILEPRO_OPC_DWORD_ALIGN, 0x1, 3, TREG_ZERO, 1, 319 297 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 320 298 }, 321 - { "dword_align.sn", TILE_OPC_DWORD_ALIGN_SN, 0x1, 3, TREG_SN, 1, 299 + { "dword_align.sn", TILEPRO_OPC_DWORD_ALIGN_SN, 0x1, 3, TREG_SN, 1, 322 300 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 323 301 }, 324 - { "finv", TILE_OPC_FINV, 0x2, 1, TREG_ZERO, 1, 302 + { "finv", TILEPRO_OPC_FINV, 0x2, 1, TREG_ZERO, 1, 325 303 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, 326 304 }, 327 - { "flush", TILE_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1, 305 + { "flush", TILEPRO_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1, 328 306 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, 329 307 }, 330 - { "fnop", TILE_OPC_FNOP, 0xf, 0, TREG_ZERO, 1, 308 + { "fnop", TILEPRO_OPC_FNOP, 0xf, 0, TREG_ZERO, 1, 331 309 { { }, { }, { }, { }, { 0, } }, 332 310 }, 333 - { "icoh", TILE_OPC_ICOH, 0x2, 1, TREG_ZERO, 1, 311 + { "icoh", TILEPRO_OPC_ICOH, 0x2, 1, TREG_ZERO, 1, 334 312 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, 335 313 }, 336 - { "ill", TILE_OPC_ILL, 0xa, 0, TREG_ZERO, 1, 314 + { "ill", TILEPRO_OPC_ILL, 0xa, 0, TREG_ZERO, 1, 337 315 { { 0, }, { }, { 0, }, { }, { 0, } }, 338 316 }, 339 - { "inthb", TILE_OPC_INTHB, 0x3, 3, TREG_ZERO, 1, 317 + { "inthb", TILEPRO_OPC_INTHB, 0x3, 3, TREG_ZERO, 1, 340 318 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 341 319 }, 342 - { "inthb.sn", TILE_OPC_INTHB_SN, 0x3, 3, TREG_SN, 1, 320 + { "inthb.sn", TILEPRO_OPC_INTHB_SN, 0x3, 3, TREG_SN, 1, 343 321 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 344 322 }, 345 - { "inthh", TILE_OPC_INTHH, 0x3, 3, TREG_ZERO, 1, 323 + { "inthh", TILEPRO_OPC_INTHH, 0x3, 3, TREG_ZERO, 1, 346 324 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 347 325 }, 348 - { "inthh.sn", TILE_OPC_INTHH_SN, 0x3, 3, TREG_SN, 1, 326 + { "inthh.sn", TILEPRO_OPC_INTHH_SN, 0x3, 3, TREG_SN, 1, 349 327 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 350 328 }, 351 - { "intlb", TILE_OPC_INTLB, 0x3, 3, TREG_ZERO, 1, 329 + { "intlb", TILEPRO_OPC_INTLB, 0x3, 3, TREG_ZERO, 1, 352 330 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 353 331 }, 354 - { "intlb.sn", TILE_OPC_INTLB_SN, 0x3, 3, TREG_SN, 1, 332 + { "intlb.sn", TILEPRO_OPC_INTLB_SN, 0x3, 3, TREG_SN, 1, 355 333 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 356 334 }, 357 - { "intlh", TILE_OPC_INTLH, 0x3, 3, TREG_ZERO, 1, 335 + { "intlh", TILEPRO_OPC_INTLH, 0x3, 3, TREG_ZERO, 1, 358 336 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 359 337 }, 360 - { "intlh.sn", TILE_OPC_INTLH_SN, 0x3, 3, TREG_SN, 1, 338 + { "intlh.sn", TILEPRO_OPC_INTLH_SN, 0x3, 3, TREG_SN, 1, 361 339 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 362 340 }, 363 - { "inv", TILE_OPC_INV, 0x2, 1, TREG_ZERO, 1, 341 + { "inv", TILEPRO_OPC_INV, 0x2, 1, TREG_ZERO, 1, 364 342 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, 365 343 }, 366 - { "iret", TILE_OPC_IRET, 0x2, 0, TREG_ZERO, 1, 344 + { "iret", TILEPRO_OPC_IRET, 0x2, 0, TREG_ZERO, 1, 367 345 { { 0, }, { }, { 0, }, { 0, }, { 0, } }, 368 346 }, 369 - { "jalb", TILE_OPC_JALB, 0x2, 1, TREG_LR, 1, 347 + { "jalb", TILEPRO_OPC_JALB, 0x2, 1, TREG_LR, 1, 370 348 { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } }, 371 349 }, 372 - { "jalf", TILE_OPC_JALF, 0x2, 1, TREG_LR, 1, 350 + { "jalf", TILEPRO_OPC_JALF, 0x2, 1, TREG_LR, 1, 373 351 { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } }, 374 352 }, 375 - { "jalr", TILE_OPC_JALR, 0x2, 1, TREG_LR, 1, 353 + { "jalr", TILEPRO_OPC_JALR, 0x2, 1, TREG_LR, 1, 376 354 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, 377 355 }, 378 - { "jalrp", TILE_OPC_JALRP, 0x2, 1, TREG_LR, 1, 356 + { "jalrp", TILEPRO_OPC_JALRP, 0x2, 1, TREG_LR, 1, 379 357 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, 380 358 }, 381 - { "jb", TILE_OPC_JB, 0x2, 1, TREG_ZERO, 1, 359 + { "jb", TILEPRO_OPC_JB, 0x2, 1, TREG_ZERO, 1, 382 360 { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } }, 383 361 }, 384 - { "jf", TILE_OPC_JF, 0x2, 1, TREG_ZERO, 1, 362 + { "jf", TILEPRO_OPC_JF, 0x2, 1, TREG_ZERO, 1, 385 363 { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } }, 386 364 }, 387 - { "jr", TILE_OPC_JR, 0x2, 1, TREG_ZERO, 1, 365 + { "jr", TILEPRO_OPC_JR, 0x2, 1, TREG_ZERO, 1, 388 366 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, 389 367 }, 390 - { "jrp", TILE_OPC_JRP, 0x2, 1, TREG_ZERO, 1, 368 + { "jrp", TILEPRO_OPC_JRP, 0x2, 1, TREG_ZERO, 1, 391 369 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, 392 370 }, 393 - { "lb", TILE_OPC_LB, 0x12, 2, TREG_ZERO, 1, 371 + { "lb", TILEPRO_OPC_LB, 0x12, 2, TREG_ZERO, 1, 394 372 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, 395 373 }, 396 - { "lb.sn", TILE_OPC_LB_SN, 0x2, 2, TREG_SN, 1, 374 + { "lb.sn", TILEPRO_OPC_LB_SN, 0x2, 2, TREG_SN, 1, 397 375 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, 398 376 }, 399 - { "lb_u", TILE_OPC_LB_U, 0x12, 2, TREG_ZERO, 1, 377 + { "lb_u", TILEPRO_OPC_LB_U, 0x12, 2, TREG_ZERO, 1, 400 378 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, 401 379 }, 402 - { "lb_u.sn", TILE_OPC_LB_U_SN, 0x2, 2, TREG_SN, 1, 380 + { "lb_u.sn", TILEPRO_OPC_LB_U_SN, 0x2, 2, TREG_SN, 1, 403 381 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, 404 382 }, 405 - { "lbadd", TILE_OPC_LBADD, 0x2, 3, TREG_ZERO, 1, 383 + { "lbadd", TILEPRO_OPC_LBADD, 0x2, 3, TREG_ZERO, 1, 406 384 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, 407 385 }, 408 - { "lbadd.sn", TILE_OPC_LBADD_SN, 0x2, 3, TREG_SN, 1, 386 + { "lbadd.sn", TILEPRO_OPC_LBADD_SN, 0x2, 3, TREG_SN, 1, 409 387 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, 410 388 }, 411 - { "lbadd_u", TILE_OPC_LBADD_U, 0x2, 3, TREG_ZERO, 1, 389 + { "lbadd_u", TILEPRO_OPC_LBADD_U, 0x2, 3, TREG_ZERO, 1, 412 390 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, 413 391 }, 414 - { "lbadd_u.sn", TILE_OPC_LBADD_U_SN, 0x2, 3, TREG_SN, 1, 392 + { "lbadd_u.sn", TILEPRO_OPC_LBADD_U_SN, 0x2, 3, TREG_SN, 1, 415 393 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, 416 394 }, 417 - { "lh", TILE_OPC_LH, 0x12, 2, TREG_ZERO, 1, 395 + { "lh", TILEPRO_OPC_LH, 0x12, 2, TREG_ZERO, 1, 418 396 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, 419 397 }, 420 - { "lh.sn", TILE_OPC_LH_SN, 0x2, 2, TREG_SN, 1, 398 + { "lh.sn", TILEPRO_OPC_LH_SN, 0x2, 2, TREG_SN, 1, 421 399 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, 422 400 }, 423 - { "lh_u", TILE_OPC_LH_U, 0x12, 2, TREG_ZERO, 1, 401 + { "lh_u", TILEPRO_OPC_LH_U, 0x12, 2, TREG_ZERO, 1, 424 402 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, 425 403 }, 426 - { "lh_u.sn", TILE_OPC_LH_U_SN, 0x2, 2, TREG_SN, 1, 404 + { "lh_u.sn", TILEPRO_OPC_LH_U_SN, 0x2, 2, TREG_SN, 1, 427 405 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, 428 406 }, 429 - { "lhadd", TILE_OPC_LHADD, 0x2, 3, TREG_ZERO, 1, 407 + { "lhadd", TILEPRO_OPC_LHADD, 0x2, 3, TREG_ZERO, 1, 430 408 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, 431 409 }, 432 - { "lhadd.sn", TILE_OPC_LHADD_SN, 0x2, 3, TREG_SN, 1, 410 + { "lhadd.sn", TILEPRO_OPC_LHADD_SN, 0x2, 3, TREG_SN, 1, 433 411 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, 434 412 }, 435 - { "lhadd_u", TILE_OPC_LHADD_U, 0x2, 3, TREG_ZERO, 1, 413 + { "lhadd_u", TILEPRO_OPC_LHADD_U, 0x2, 3, TREG_ZERO, 1, 436 414 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, 437 415 }, 438 - { "lhadd_u.sn", TILE_OPC_LHADD_U_SN, 0x2, 3, TREG_SN, 1, 416 + { "lhadd_u.sn", TILEPRO_OPC_LHADD_U_SN, 0x2, 3, TREG_SN, 1, 439 417 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, 440 418 }, 441 - { "lnk", TILE_OPC_LNK, 0x2, 1, TREG_ZERO, 1, 419 + { "lnk", TILEPRO_OPC_LNK, 0x2, 1, TREG_ZERO, 1, 442 420 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } }, 443 421 }, 444 - { "lnk.sn", TILE_OPC_LNK_SN, 0x2, 1, TREG_SN, 1, 422 + { "lnk.sn", TILEPRO_OPC_LNK_SN, 0x2, 1, TREG_SN, 1, 445 423 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } }, 446 424 }, 447 - { "lw", TILE_OPC_LW, 0x12, 2, TREG_ZERO, 1, 425 + { "lw", TILEPRO_OPC_LW, 0x12, 2, TREG_ZERO, 1, 448 426 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, 449 427 }, 450 - { "lw.sn", TILE_OPC_LW_SN, 0x2, 2, TREG_SN, 1, 428 + { "lw.sn", TILEPRO_OPC_LW_SN, 0x2, 2, TREG_SN, 1, 451 429 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, 452 430 }, 453 - { "lw_na", TILE_OPC_LW_NA, 0x2, 2, TREG_ZERO, 1, 431 + { "lw_na", TILEPRO_OPC_LW_NA, 0x2, 2, TREG_ZERO, 1, 454 432 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, 455 433 }, 456 - { "lw_na.sn", TILE_OPC_LW_NA_SN, 0x2, 2, TREG_SN, 1, 434 + { "lw_na.sn", TILEPRO_OPC_LW_NA_SN, 0x2, 2, TREG_SN, 1, 457 435 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, 458 436 }, 459 - { "lwadd", TILE_OPC_LWADD, 0x2, 3, TREG_ZERO, 1, 437 + { "lwadd", TILEPRO_OPC_LWADD, 0x2, 3, TREG_ZERO, 1, 460 438 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, 461 439 }, 462 - { "lwadd.sn", TILE_OPC_LWADD_SN, 0x2, 3, TREG_SN, 1, 440 + { "lwadd.sn", TILEPRO_OPC_LWADD_SN, 0x2, 3, TREG_SN, 1, 463 441 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, 464 442 }, 465 - { "lwadd_na", TILE_OPC_LWADD_NA, 0x2, 3, TREG_ZERO, 1, 443 + { "lwadd_na", TILEPRO_OPC_LWADD_NA, 0x2, 3, TREG_ZERO, 1, 466 444 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, 467 445 }, 468 - { "lwadd_na.sn", TILE_OPC_LWADD_NA_SN, 0x2, 3, TREG_SN, 1, 446 + { "lwadd_na.sn", TILEPRO_OPC_LWADD_NA_SN, 0x2, 3, TREG_SN, 1, 469 447 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, 470 448 }, 471 - { "maxb_u", TILE_OPC_MAXB_U, 0x3, 3, TREG_ZERO, 1, 449 + { "maxb_u", TILEPRO_OPC_MAXB_U, 0x3, 3, TREG_ZERO, 1, 472 450 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 473 451 }, 474 - { "maxb_u.sn", TILE_OPC_MAXB_U_SN, 0x3, 3, TREG_SN, 1, 452 + { "maxb_u.sn", TILEPRO_OPC_MAXB_U_SN, 0x3, 3, TREG_SN, 1, 475 453 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 476 454 }, 477 - { "maxh", TILE_OPC_MAXH, 0x3, 3, TREG_ZERO, 1, 455 + { "maxh", TILEPRO_OPC_MAXH, 0x3, 3, TREG_ZERO, 1, 478 456 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 479 457 }, 480 - { "maxh.sn", TILE_OPC_MAXH_SN, 0x3, 3, TREG_SN, 1, 458 + { "maxh.sn", TILEPRO_OPC_MAXH_SN, 0x3, 3, TREG_SN, 1, 481 459 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 482 460 }, 483 - { "maxib_u", TILE_OPC_MAXIB_U, 0x3, 3, TREG_ZERO, 1, 461 + { "maxib_u", TILEPRO_OPC_MAXIB_U, 0x3, 3, TREG_ZERO, 1, 484 462 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 485 463 }, 486 - { "maxib_u.sn", TILE_OPC_MAXIB_U_SN, 0x3, 3, TREG_SN, 1, 464 + { "maxib_u.sn", TILEPRO_OPC_MAXIB_U_SN, 0x3, 3, TREG_SN, 1, 487 465 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 488 466 }, 489 - { "maxih", TILE_OPC_MAXIH, 0x3, 3, TREG_ZERO, 1, 467 + { "maxih", TILEPRO_OPC_MAXIH, 0x3, 3, TREG_ZERO, 1, 490 468 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 491 469 }, 492 - { "maxih.sn", TILE_OPC_MAXIH_SN, 0x3, 3, TREG_SN, 1, 470 + { "maxih.sn", TILEPRO_OPC_MAXIH_SN, 0x3, 3, TREG_SN, 1, 493 471 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 494 472 }, 495 - { "mf", TILE_OPC_MF, 0x2, 0, TREG_ZERO, 1, 473 + { "mf", TILEPRO_OPC_MF, 0x2, 0, TREG_ZERO, 1, 496 474 { { 0, }, { }, { 0, }, { 0, }, { 0, } }, 497 475 }, 498 - { "mfspr", TILE_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1, 476 + { "mfspr", TILEPRO_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1, 499 477 { { 0, }, { 9, 25 }, { 0, }, { 0, }, { 0, } }, 500 478 }, 501 - { "minb_u", TILE_OPC_MINB_U, 0x3, 3, TREG_ZERO, 1, 479 + { "minb_u", TILEPRO_OPC_MINB_U, 0x3, 3, TREG_ZERO, 1, 502 480 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 503 481 }, 504 - { "minb_u.sn", TILE_OPC_MINB_U_SN, 0x3, 3, TREG_SN, 1, 482 + { "minb_u.sn", TILEPRO_OPC_MINB_U_SN, 0x3, 3, TREG_SN, 1, 505 483 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 506 484 }, 507 - { "minh", TILE_OPC_MINH, 0x3, 3, TREG_ZERO, 1, 485 + { "minh", TILEPRO_OPC_MINH, 0x3, 3, TREG_ZERO, 1, 508 486 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 509 487 }, 510 - { "minh.sn", TILE_OPC_MINH_SN, 0x3, 3, TREG_SN, 1, 488 + { "minh.sn", TILEPRO_OPC_MINH_SN, 0x3, 3, TREG_SN, 1, 511 489 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 512 490 }, 513 - { "minib_u", TILE_OPC_MINIB_U, 0x3, 3, TREG_ZERO, 1, 491 + { "minib_u", TILEPRO_OPC_MINIB_U, 0x3, 3, TREG_ZERO, 1, 514 492 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 515 493 }, 516 - { "minib_u.sn", TILE_OPC_MINIB_U_SN, 0x3, 3, TREG_SN, 1, 494 + { "minib_u.sn", TILEPRO_OPC_MINIB_U_SN, 0x3, 3, TREG_SN, 1, 517 495 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 518 496 }, 519 - { "minih", TILE_OPC_MINIH, 0x3, 3, TREG_ZERO, 1, 497 + { "minih", TILEPRO_OPC_MINIH, 0x3, 3, TREG_ZERO, 1, 520 498 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 521 499 }, 522 - { "minih.sn", TILE_OPC_MINIH_SN, 0x3, 3, TREG_SN, 1, 500 + { "minih.sn", TILEPRO_OPC_MINIH_SN, 0x3, 3, TREG_SN, 1, 523 501 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 524 502 }, 525 - { "mm", TILE_OPC_MM, 0x3, 5, TREG_ZERO, 1, 503 + { "mm", TILEPRO_OPC_MM, 0x3, 5, TREG_ZERO, 1, 526 504 { { 7, 8, 16, 26, 27 }, { 9, 10, 17, 28, 29 }, { 0, }, { 0, }, { 0, } }, 527 505 }, 528 - { "mnz", TILE_OPC_MNZ, 0xf, 3, TREG_ZERO, 1, 506 + { "mnz", TILEPRO_OPC_MNZ, 0xf, 3, TREG_ZERO, 1, 529 507 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 530 508 }, 531 - { "mnz.sn", TILE_OPC_MNZ_SN, 0x3, 3, TREG_SN, 1, 509 + { "mnz.sn", TILEPRO_OPC_MNZ_SN, 0x3, 3, TREG_SN, 1, 532 510 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 533 511 }, 534 - { "mnzb", TILE_OPC_MNZB, 0x3, 3, TREG_ZERO, 1, 512 + { "mnzb", TILEPRO_OPC_MNZB, 0x3, 3, TREG_ZERO, 1, 535 513 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 536 514 }, 537 - { "mnzb.sn", TILE_OPC_MNZB_SN, 0x3, 3, TREG_SN, 1, 515 + { "mnzb.sn", TILEPRO_OPC_MNZB_SN, 0x3, 3, TREG_SN, 1, 538 516 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 539 517 }, 540 - { "mnzh", TILE_OPC_MNZH, 0x3, 3, TREG_ZERO, 1, 518 + { "mnzh", TILEPRO_OPC_MNZH, 0x3, 3, TREG_ZERO, 1, 541 519 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 542 520 }, 543 - { "mnzh.sn", TILE_OPC_MNZH_SN, 0x3, 3, TREG_SN, 1, 521 + { "mnzh.sn", TILEPRO_OPC_MNZH_SN, 0x3, 3, TREG_SN, 1, 544 522 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 545 523 }, 546 - { "mtspr", TILE_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1, 524 + { "mtspr", TILEPRO_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1, 547 525 { { 0, }, { 30, 10 }, { 0, }, { 0, }, { 0, } }, 548 526 }, 549 - { "mulhh_ss", TILE_OPC_MULHH_SS, 0x5, 3, TREG_ZERO, 1, 527 + { "mulhh_ss", TILEPRO_OPC_MULHH_SS, 0x5, 3, TREG_ZERO, 1, 550 528 { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } }, 551 529 }, 552 - { "mulhh_ss.sn", TILE_OPC_MULHH_SS_SN, 0x1, 3, TREG_SN, 1, 530 + { "mulhh_ss.sn", TILEPRO_OPC_MULHH_SS_SN, 0x1, 3, TREG_SN, 1, 553 531 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 554 532 }, 555 - { "mulhh_su", TILE_OPC_MULHH_SU, 0x1, 3, TREG_ZERO, 1, 533 + { "mulhh_su", TILEPRO_OPC_MULHH_SU, 0x1, 3, TREG_ZERO, 1, 556 534 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 557 535 }, 558 - { "mulhh_su.sn", TILE_OPC_MULHH_SU_SN, 0x1, 3, TREG_SN, 1, 536 + { "mulhh_su.sn", TILEPRO_OPC_MULHH_SU_SN, 0x1, 3, TREG_SN, 1, 559 537 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 560 538 }, 561 - { "mulhh_uu", TILE_OPC_MULHH_UU, 0x5, 3, TREG_ZERO, 1, 539 + { "mulhh_uu", TILEPRO_OPC_MULHH_UU, 0x5, 3, TREG_ZERO, 1, 562 540 { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } }, 563 541 }, 564 - { "mulhh_uu.sn", TILE_OPC_MULHH_UU_SN, 0x1, 3, TREG_SN, 1, 542 + { "mulhh_uu.sn", TILEPRO_OPC_MULHH_UU_SN, 0x1, 3, TREG_SN, 1, 565 543 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 566 544 }, 567 - { "mulhha_ss", TILE_OPC_MULHHA_SS, 0x5, 3, TREG_ZERO, 1, 545 + { "mulhha_ss", TILEPRO_OPC_MULHHA_SS, 0x5, 3, TREG_ZERO, 1, 568 546 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, 569 547 }, 570 - { "mulhha_ss.sn", TILE_OPC_MULHHA_SS_SN, 0x1, 3, TREG_SN, 1, 548 + { "mulhha_ss.sn", TILEPRO_OPC_MULHHA_SS_SN, 0x1, 3, TREG_SN, 1, 571 549 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 572 550 }, 573 - { "mulhha_su", TILE_OPC_MULHHA_SU, 0x1, 3, TREG_ZERO, 1, 551 + { "mulhha_su", TILEPRO_OPC_MULHHA_SU, 0x1, 3, TREG_ZERO, 1, 574 552 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 575 553 }, 576 - { "mulhha_su.sn", TILE_OPC_MULHHA_SU_SN, 0x1, 3, TREG_SN, 1, 554 + { "mulhha_su.sn", TILEPRO_OPC_MULHHA_SU_SN, 0x1, 3, TREG_SN, 1, 577 555 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 578 556 }, 579 - { "mulhha_uu", TILE_OPC_MULHHA_UU, 0x5, 3, TREG_ZERO, 1, 557 + { "mulhha_uu", TILEPRO_OPC_MULHHA_UU, 0x5, 3, TREG_ZERO, 1, 580 558 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, 581 559 }, 582 - { "mulhha_uu.sn", TILE_OPC_MULHHA_UU_SN, 0x1, 3, TREG_SN, 1, 560 + { "mulhha_uu.sn", TILEPRO_OPC_MULHHA_UU_SN, 0x1, 3, TREG_SN, 1, 583 561 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 584 562 }, 585 - { "mulhhsa_uu", TILE_OPC_MULHHSA_UU, 0x1, 3, TREG_ZERO, 1, 563 + { "mulhhsa_uu", TILEPRO_OPC_MULHHSA_UU, 0x1, 3, TREG_ZERO, 1, 586 564 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 587 565 }, 588 - { "mulhhsa_uu.sn", TILE_OPC_MULHHSA_UU_SN, 0x1, 3, TREG_SN, 1, 566 + { "mulhhsa_uu.sn", TILEPRO_OPC_MULHHSA_UU_SN, 0x1, 3, TREG_SN, 1, 589 567 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 590 568 }, 591 - { "mulhl_ss", TILE_OPC_MULHL_SS, 0x1, 3, TREG_ZERO, 1, 569 + { "mulhl_ss", TILEPRO_OPC_MULHL_SS, 0x1, 3, TREG_ZERO, 1, 592 570 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 593 571 }, 594 - { "mulhl_ss.sn", TILE_OPC_MULHL_SS_SN, 0x1, 3, TREG_SN, 1, 572 + { "mulhl_ss.sn", TILEPRO_OPC_MULHL_SS_SN, 0x1, 3, TREG_SN, 1, 595 573 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 596 574 }, 597 - { "mulhl_su", TILE_OPC_MULHL_SU, 0x1, 3, TREG_ZERO, 1, 575 + { "mulhl_su", TILEPRO_OPC_MULHL_SU, 0x1, 3, TREG_ZERO, 1, 598 576 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 599 577 }, 600 - { "mulhl_su.sn", TILE_OPC_MULHL_SU_SN, 0x1, 3, TREG_SN, 1, 578 + { "mulhl_su.sn", TILEPRO_OPC_MULHL_SU_SN, 0x1, 3, TREG_SN, 1, 601 579 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 602 580 }, 603 - { "mulhl_us", TILE_OPC_MULHL_US, 0x1, 3, TREG_ZERO, 1, 581 + { "mulhl_us", TILEPRO_OPC_MULHL_US, 0x1, 3, TREG_ZERO, 1, 604 582 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 605 583 }, 606 - { "mulhl_us.sn", TILE_OPC_MULHL_US_SN, 0x1, 3, TREG_SN, 1, 584 + { "mulhl_us.sn", TILEPRO_OPC_MULHL_US_SN, 0x1, 3, TREG_SN, 1, 607 585 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 608 586 }, 609 - { "mulhl_uu", TILE_OPC_MULHL_UU, 0x1, 3, TREG_ZERO, 1, 587 + { "mulhl_uu", TILEPRO_OPC_MULHL_UU, 0x1, 3, TREG_ZERO, 1, 610 588 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 611 589 }, 612 - { "mulhl_uu.sn", TILE_OPC_MULHL_UU_SN, 0x1, 3, TREG_SN, 1, 590 + { "mulhl_uu.sn", TILEPRO_OPC_MULHL_UU_SN, 0x1, 3, TREG_SN, 1, 613 591 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 614 592 }, 615 - { "mulhla_ss", TILE_OPC_MULHLA_SS, 0x1, 3, TREG_ZERO, 1, 593 + { "mulhla_ss", TILEPRO_OPC_MULHLA_SS, 0x1, 3, TREG_ZERO, 1, 616 594 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 617 595 }, 618 - { "mulhla_ss.sn", TILE_OPC_MULHLA_SS_SN, 0x1, 3, TREG_SN, 1, 596 + { "mulhla_ss.sn", TILEPRO_OPC_MULHLA_SS_SN, 0x1, 3, TREG_SN, 1, 619 597 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 620 598 }, 621 - { "mulhla_su", TILE_OPC_MULHLA_SU, 0x1, 3, TREG_ZERO, 1, 599 + { "mulhla_su", TILEPRO_OPC_MULHLA_SU, 0x1, 3, TREG_ZERO, 1, 622 600 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 623 601 }, 624 - { "mulhla_su.sn", TILE_OPC_MULHLA_SU_SN, 0x1, 3, TREG_SN, 1, 602 + { "mulhla_su.sn", TILEPRO_OPC_MULHLA_SU_SN, 0x1, 3, TREG_SN, 1, 625 603 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 626 604 }, 627 - { "mulhla_us", TILE_OPC_MULHLA_US, 0x1, 3, TREG_ZERO, 1, 605 + { "mulhla_us", TILEPRO_OPC_MULHLA_US, 0x1, 3, TREG_ZERO, 1, 628 606 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 629 607 }, 630 - { "mulhla_us.sn", TILE_OPC_MULHLA_US_SN, 0x1, 3, TREG_SN, 1, 608 + { "mulhla_us.sn", TILEPRO_OPC_MULHLA_US_SN, 0x1, 3, TREG_SN, 1, 631 609 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 632 610 }, 633 - { "mulhla_uu", TILE_OPC_MULHLA_UU, 0x1, 3, TREG_ZERO, 1, 611 + { "mulhla_uu", TILEPRO_OPC_MULHLA_UU, 0x1, 3, TREG_ZERO, 1, 634 612 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 635 613 }, 636 - { "mulhla_uu.sn", TILE_OPC_MULHLA_UU_SN, 0x1, 3, TREG_SN, 1, 614 + { "mulhla_uu.sn", TILEPRO_OPC_MULHLA_UU_SN, 0x1, 3, TREG_SN, 1, 637 615 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 638 616 }, 639 - { "mulhlsa_uu", TILE_OPC_MULHLSA_UU, 0x5, 3, TREG_ZERO, 1, 617 + { "mulhlsa_uu", TILEPRO_OPC_MULHLSA_UU, 0x5, 3, TREG_ZERO, 1, 640 618 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, 641 619 }, 642 - { "mulhlsa_uu.sn", TILE_OPC_MULHLSA_UU_SN, 0x1, 3, TREG_SN, 1, 620 + { "mulhlsa_uu.sn", TILEPRO_OPC_MULHLSA_UU_SN, 0x1, 3, TREG_SN, 1, 643 621 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 644 622 }, 645 - { "mulll_ss", TILE_OPC_MULLL_SS, 0x5, 3, TREG_ZERO, 1, 623 + { "mulll_ss", TILEPRO_OPC_MULLL_SS, 0x5, 3, TREG_ZERO, 1, 646 624 { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } }, 647 625 }, 648 - { "mulll_ss.sn", TILE_OPC_MULLL_SS_SN, 0x1, 3, TREG_SN, 1, 626 + { "mulll_ss.sn", TILEPRO_OPC_MULLL_SS_SN, 0x1, 3, TREG_SN, 1, 649 627 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 650 628 }, 651 - { "mulll_su", TILE_OPC_MULLL_SU, 0x1, 3, TREG_ZERO, 1, 629 + { "mulll_su", TILEPRO_OPC_MULLL_SU, 0x1, 3, TREG_ZERO, 1, 652 630 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 653 631 }, 654 - { "mulll_su.sn", TILE_OPC_MULLL_SU_SN, 0x1, 3, TREG_SN, 1, 632 + { "mulll_su.sn", TILEPRO_OPC_MULLL_SU_SN, 0x1, 3, TREG_SN, 1, 655 633 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 656 634 }, 657 - { "mulll_uu", TILE_OPC_MULLL_UU, 0x5, 3, TREG_ZERO, 1, 635 + { "mulll_uu", TILEPRO_OPC_MULLL_UU, 0x5, 3, TREG_ZERO, 1, 658 636 { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } }, 659 637 }, 660 - { "mulll_uu.sn", TILE_OPC_MULLL_UU_SN, 0x1, 3, TREG_SN, 1, 638 + { "mulll_uu.sn", TILEPRO_OPC_MULLL_UU_SN, 0x1, 3, TREG_SN, 1, 661 639 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 662 640 }, 663 - { "mullla_ss", TILE_OPC_MULLLA_SS, 0x5, 3, TREG_ZERO, 1, 641 + { "mullla_ss", TILEPRO_OPC_MULLLA_SS, 0x5, 3, TREG_ZERO, 1, 664 642 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, 665 643 }, 666 - { "mullla_ss.sn", TILE_OPC_MULLLA_SS_SN, 0x1, 3, TREG_SN, 1, 644 + { "mullla_ss.sn", TILEPRO_OPC_MULLLA_SS_SN, 0x1, 3, TREG_SN, 1, 667 645 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 668 646 }, 669 - { "mullla_su", TILE_OPC_MULLLA_SU, 0x1, 3, TREG_ZERO, 1, 647 + { "mullla_su", TILEPRO_OPC_MULLLA_SU, 0x1, 3, TREG_ZERO, 1, 670 648 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 671 649 }, 672 - { "mullla_su.sn", TILE_OPC_MULLLA_SU_SN, 0x1, 3, TREG_SN, 1, 650 + { "mullla_su.sn", TILEPRO_OPC_MULLLA_SU_SN, 0x1, 3, TREG_SN, 1, 673 651 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 674 652 }, 675 - { "mullla_uu", TILE_OPC_MULLLA_UU, 0x5, 3, TREG_ZERO, 1, 653 + { "mullla_uu", TILEPRO_OPC_MULLLA_UU, 0x5, 3, TREG_ZERO, 1, 676 654 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, 677 655 }, 678 - { "mullla_uu.sn", TILE_OPC_MULLLA_UU_SN, 0x1, 3, TREG_SN, 1, 656 + { "mullla_uu.sn", TILEPRO_OPC_MULLLA_UU_SN, 0x1, 3, TREG_SN, 1, 679 657 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 680 658 }, 681 - { "mulllsa_uu", TILE_OPC_MULLLSA_UU, 0x1, 3, TREG_ZERO, 1, 659 + { "mulllsa_uu", TILEPRO_OPC_MULLLSA_UU, 0x1, 3, TREG_ZERO, 1, 682 660 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 683 661 }, 684 - { "mulllsa_uu.sn", TILE_OPC_MULLLSA_UU_SN, 0x1, 3, TREG_SN, 1, 662 + { "mulllsa_uu.sn", TILEPRO_OPC_MULLLSA_UU_SN, 0x1, 3, TREG_SN, 1, 685 663 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 686 664 }, 687 - { "mvnz", TILE_OPC_MVNZ, 0x5, 3, TREG_ZERO, 1, 665 + { "mvnz", TILEPRO_OPC_MVNZ, 0x5, 3, TREG_ZERO, 1, 688 666 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, 689 667 }, 690 - { "mvnz.sn", TILE_OPC_MVNZ_SN, 0x1, 3, TREG_SN, 1, 668 + { "mvnz.sn", TILEPRO_OPC_MVNZ_SN, 0x1, 3, TREG_SN, 1, 691 669 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 692 670 }, 693 - { "mvz", TILE_OPC_MVZ, 0x5, 3, TREG_ZERO, 1, 671 + { "mvz", TILEPRO_OPC_MVZ, 0x5, 3, TREG_ZERO, 1, 694 672 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, 695 673 }, 696 - { "mvz.sn", TILE_OPC_MVZ_SN, 0x1, 3, TREG_SN, 1, 674 + { "mvz.sn", TILEPRO_OPC_MVZ_SN, 0x1, 3, TREG_SN, 1, 697 675 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 698 676 }, 699 - { "mz", TILE_OPC_MZ, 0xf, 3, TREG_ZERO, 1, 677 + { "mz", TILEPRO_OPC_MZ, 0xf, 3, TREG_ZERO, 1, 700 678 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 701 679 }, 702 - { "mz.sn", TILE_OPC_MZ_SN, 0x3, 3, TREG_SN, 1, 680 + { "mz.sn", TILEPRO_OPC_MZ_SN, 0x3, 3, TREG_SN, 1, 703 681 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 704 682 }, 705 - { "mzb", TILE_OPC_MZB, 0x3, 3, TREG_ZERO, 1, 683 + { "mzb", TILEPRO_OPC_MZB, 0x3, 3, TREG_ZERO, 1, 706 684 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 707 685 }, 708 - { "mzb.sn", TILE_OPC_MZB_SN, 0x3, 3, TREG_SN, 1, 686 + { "mzb.sn", TILEPRO_OPC_MZB_SN, 0x3, 3, TREG_SN, 1, 709 687 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 710 688 }, 711 - { "mzh", TILE_OPC_MZH, 0x3, 3, TREG_ZERO, 1, 689 + { "mzh", TILEPRO_OPC_MZH, 0x3, 3, TREG_ZERO, 1, 712 690 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 713 691 }, 714 - { "mzh.sn", TILE_OPC_MZH_SN, 0x3, 3, TREG_SN, 1, 692 + { "mzh.sn", TILEPRO_OPC_MZH_SN, 0x3, 3, TREG_SN, 1, 715 693 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 716 694 }, 717 - { "nap", TILE_OPC_NAP, 0x2, 0, TREG_ZERO, 0, 695 + { "nap", TILEPRO_OPC_NAP, 0x2, 0, TREG_ZERO, 0, 718 696 { { 0, }, { }, { 0, }, { 0, }, { 0, } }, 719 697 }, 720 - { "nop", TILE_OPC_NOP, 0xf, 0, TREG_ZERO, 1, 698 + { "nop", TILEPRO_OPC_NOP, 0xf, 0, TREG_ZERO, 1, 721 699 { { }, { }, { }, { }, { 0, } }, 722 700 }, 723 - { "nor", TILE_OPC_NOR, 0xf, 3, TREG_ZERO, 1, 701 + { "nor", TILEPRO_OPC_NOR, 0xf, 3, TREG_ZERO, 1, 724 702 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 725 703 }, 726 - { "nor.sn", TILE_OPC_NOR_SN, 0x3, 3, TREG_SN, 1, 704 + { "nor.sn", TILEPRO_OPC_NOR_SN, 0x3, 3, TREG_SN, 1, 727 705 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 728 706 }, 729 - { "or", TILE_OPC_OR, 0xf, 3, TREG_ZERO, 1, 707 + { "or", TILEPRO_OPC_OR, 0xf, 3, TREG_ZERO, 1, 730 708 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 731 709 }, 732 - { "or.sn", TILE_OPC_OR_SN, 0x3, 3, TREG_SN, 1, 710 + { "or.sn", TILEPRO_OPC_OR_SN, 0x3, 3, TREG_SN, 1, 733 711 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 734 712 }, 735 - { "ori", TILE_OPC_ORI, 0xf, 3, TREG_ZERO, 1, 713 + { "ori", TILEPRO_OPC_ORI, 0xf, 3, TREG_ZERO, 1, 736 714 { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, 737 715 }, 738 - { "ori.sn", TILE_OPC_ORI_SN, 0x3, 3, TREG_SN, 1, 716 + { "ori.sn", TILEPRO_OPC_ORI_SN, 0x3, 3, TREG_SN, 1, 739 717 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 740 718 }, 741 - { "packbs_u", TILE_OPC_PACKBS_U, 0x3, 3, TREG_ZERO, 1, 719 + { "packbs_u", TILEPRO_OPC_PACKBS_U, 0x3, 3, TREG_ZERO, 1, 742 720 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 743 721 }, 744 - { "packbs_u.sn", TILE_OPC_PACKBS_U_SN, 0x3, 3, TREG_SN, 1, 722 + { "packbs_u.sn", TILEPRO_OPC_PACKBS_U_SN, 0x3, 3, TREG_SN, 1, 745 723 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 746 724 }, 747 - { "packhb", TILE_OPC_PACKHB, 0x3, 3, TREG_ZERO, 1, 725 + { "packhb", TILEPRO_OPC_PACKHB, 0x3, 3, TREG_ZERO, 1, 748 726 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 749 727 }, 750 - { "packhb.sn", TILE_OPC_PACKHB_SN, 0x3, 3, TREG_SN, 1, 728 + { "packhb.sn", TILEPRO_OPC_PACKHB_SN, 0x3, 3, TREG_SN, 1, 751 729 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 752 730 }, 753 - { "packhs", TILE_OPC_PACKHS, 0x3, 3, TREG_ZERO, 1, 731 + { "packhs", TILEPRO_OPC_PACKHS, 0x3, 3, TREG_ZERO, 1, 754 732 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 755 733 }, 756 - { "packhs.sn", TILE_OPC_PACKHS_SN, 0x3, 3, TREG_SN, 1, 734 + { "packhs.sn", TILEPRO_OPC_PACKHS_SN, 0x3, 3, TREG_SN, 1, 757 735 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 758 736 }, 759 - { "packlb", TILE_OPC_PACKLB, 0x3, 3, TREG_ZERO, 1, 737 + { "packlb", TILEPRO_OPC_PACKLB, 0x3, 3, TREG_ZERO, 1, 760 738 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 761 739 }, 762 - { "packlb.sn", TILE_OPC_PACKLB_SN, 0x3, 3, TREG_SN, 1, 740 + { "packlb.sn", TILEPRO_OPC_PACKLB_SN, 0x3, 3, TREG_SN, 1, 763 741 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 764 742 }, 765 - { "pcnt", TILE_OPC_PCNT, 0x5, 2, TREG_ZERO, 1, 743 + { "pcnt", TILEPRO_OPC_PCNT, 0x5, 2, TREG_ZERO, 1, 766 744 { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, 767 745 }, 768 - { "pcnt.sn", TILE_OPC_PCNT_SN, 0x1, 2, TREG_SN, 1, 746 + { "pcnt.sn", TILEPRO_OPC_PCNT_SN, 0x1, 2, TREG_SN, 1, 769 747 { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, 770 748 }, 771 - { "rl", TILE_OPC_RL, 0xf, 3, TREG_ZERO, 1, 749 + { "rl", TILEPRO_OPC_RL, 0xf, 3, TREG_ZERO, 1, 772 750 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 773 751 }, 774 - { "rl.sn", TILE_OPC_RL_SN, 0x3, 3, TREG_SN, 1, 752 + { "rl.sn", TILEPRO_OPC_RL_SN, 0x3, 3, TREG_SN, 1, 775 753 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 776 754 }, 777 - { "rli", TILE_OPC_RLI, 0xf, 3, TREG_ZERO, 1, 755 + { "rli", TILEPRO_OPC_RLI, 0xf, 3, TREG_ZERO, 1, 778 756 { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } }, 779 757 }, 780 - { "rli.sn", TILE_OPC_RLI_SN, 0x3, 3, TREG_SN, 1, 758 + { "rli.sn", TILEPRO_OPC_RLI_SN, 0x3, 3, TREG_SN, 1, 781 759 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 782 760 }, 783 - { "s1a", TILE_OPC_S1A, 0xf, 3, TREG_ZERO, 1, 761 + { "s1a", TILEPRO_OPC_S1A, 0xf, 3, TREG_ZERO, 1, 784 762 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 785 763 }, 786 - { "s1a.sn", TILE_OPC_S1A_SN, 0x3, 3, TREG_SN, 1, 764 + { "s1a.sn", TILEPRO_OPC_S1A_SN, 0x3, 3, TREG_SN, 1, 787 765 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 788 766 }, 789 - { "s2a", TILE_OPC_S2A, 0xf, 3, TREG_ZERO, 1, 767 + { "s2a", TILEPRO_OPC_S2A, 0xf, 3, TREG_ZERO, 1, 790 768 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 791 769 }, 792 - { "s2a.sn", TILE_OPC_S2A_SN, 0x3, 3, TREG_SN, 1, 770 + { "s2a.sn", TILEPRO_OPC_S2A_SN, 0x3, 3, TREG_SN, 1, 793 771 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 794 772 }, 795 - { "s3a", TILE_OPC_S3A, 0xf, 3, TREG_ZERO, 1, 773 + { "s3a", TILEPRO_OPC_S3A, 0xf, 3, TREG_ZERO, 1, 796 774 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 797 775 }, 798 - { "s3a.sn", TILE_OPC_S3A_SN, 0x3, 3, TREG_SN, 1, 776 + { "s3a.sn", TILEPRO_OPC_S3A_SN, 0x3, 3, TREG_SN, 1, 799 777 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 800 778 }, 801 - { "sadab_u", TILE_OPC_SADAB_U, 0x1, 3, TREG_ZERO, 1, 779 + { "sadab_u", TILEPRO_OPC_SADAB_U, 0x1, 3, TREG_ZERO, 1, 802 780 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 803 781 }, 804 - { "sadab_u.sn", TILE_OPC_SADAB_U_SN, 0x1, 3, TREG_SN, 1, 782 + { "sadab_u.sn", TILEPRO_OPC_SADAB_U_SN, 0x1, 3, TREG_SN, 1, 805 783 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 806 784 }, 807 - { "sadah", TILE_OPC_SADAH, 0x1, 3, TREG_ZERO, 1, 785 + { "sadah", TILEPRO_OPC_SADAH, 0x1, 3, TREG_ZERO, 1, 808 786 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 809 787 }, 810 - { "sadah.sn", TILE_OPC_SADAH_SN, 0x1, 3, TREG_SN, 1, 788 + { "sadah.sn", TILEPRO_OPC_SADAH_SN, 0x1, 3, TREG_SN, 1, 811 789 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 812 790 }, 813 - { "sadah_u", TILE_OPC_SADAH_U, 0x1, 3, TREG_ZERO, 1, 791 + { "sadah_u", TILEPRO_OPC_SADAH_U, 0x1, 3, TREG_ZERO, 1, 814 792 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 815 793 }, 816 - { "sadah_u.sn", TILE_OPC_SADAH_U_SN, 0x1, 3, TREG_SN, 1, 794 + { "sadah_u.sn", TILEPRO_OPC_SADAH_U_SN, 0x1, 3, TREG_SN, 1, 817 795 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 818 796 }, 819 - { "sadb_u", TILE_OPC_SADB_U, 0x1, 3, TREG_ZERO, 1, 797 + { "sadb_u", TILEPRO_OPC_SADB_U, 0x1, 3, TREG_ZERO, 1, 820 798 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 821 799 }, 822 - { "sadb_u.sn", TILE_OPC_SADB_U_SN, 0x1, 3, TREG_SN, 1, 800 + { "sadb_u.sn", TILEPRO_OPC_SADB_U_SN, 0x1, 3, TREG_SN, 1, 823 801 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 824 802 }, 825 - { "sadh", TILE_OPC_SADH, 0x1, 3, TREG_ZERO, 1, 803 + { "sadh", TILEPRO_OPC_SADH, 0x1, 3, TREG_ZERO, 1, 826 804 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 827 805 }, 828 - { "sadh.sn", TILE_OPC_SADH_SN, 0x1, 3, TREG_SN, 1, 806 + { "sadh.sn", TILEPRO_OPC_SADH_SN, 0x1, 3, TREG_SN, 1, 829 807 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 830 808 }, 831 - { "sadh_u", TILE_OPC_SADH_U, 0x1, 3, TREG_ZERO, 1, 809 + { "sadh_u", TILEPRO_OPC_SADH_U, 0x1, 3, TREG_ZERO, 1, 832 810 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 833 811 }, 834 - { "sadh_u.sn", TILE_OPC_SADH_U_SN, 0x1, 3, TREG_SN, 1, 812 + { "sadh_u.sn", TILEPRO_OPC_SADH_U_SN, 0x1, 3, TREG_SN, 1, 835 813 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, 836 814 }, 837 - { "sb", TILE_OPC_SB, 0x12, 2, TREG_ZERO, 1, 815 + { "sb", TILEPRO_OPC_SB, 0x12, 2, TREG_ZERO, 1, 838 816 { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } }, 839 817 }, 840 - { "sbadd", TILE_OPC_SBADD, 0x2, 3, TREG_ZERO, 1, 818 + { "sbadd", TILEPRO_OPC_SBADD, 0x2, 3, TREG_ZERO, 1, 841 819 { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } }, 842 820 }, 843 - { "seq", TILE_OPC_SEQ, 0xf, 3, TREG_ZERO, 1, 821 + { "seq", TILEPRO_OPC_SEQ, 0xf, 3, TREG_ZERO, 1, 844 822 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 845 823 }, 846 - { "seq.sn", TILE_OPC_SEQ_SN, 0x3, 3, TREG_SN, 1, 824 + { "seq.sn", TILEPRO_OPC_SEQ_SN, 0x3, 3, TREG_SN, 1, 847 825 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 848 826 }, 849 - { "seqb", TILE_OPC_SEQB, 0x3, 3, TREG_ZERO, 1, 827 + { "seqb", TILEPRO_OPC_SEQB, 0x3, 3, TREG_ZERO, 1, 850 828 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 851 829 }, 852 - { "seqb.sn", TILE_OPC_SEQB_SN, 0x3, 3, TREG_SN, 1, 830 + { "seqb.sn", TILEPRO_OPC_SEQB_SN, 0x3, 3, TREG_SN, 1, 853 831 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 854 832 }, 855 - { "seqh", TILE_OPC_SEQH, 0x3, 3, TREG_ZERO, 1, 833 + { "seqh", TILEPRO_OPC_SEQH, 0x3, 3, TREG_ZERO, 1, 856 834 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 857 835 }, 858 - { "seqh.sn", TILE_OPC_SEQH_SN, 0x3, 3, TREG_SN, 1, 836 + { "seqh.sn", TILEPRO_OPC_SEQH_SN, 0x3, 3, TREG_SN, 1, 859 837 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 860 838 }, 861 - { "seqi", TILE_OPC_SEQI, 0xf, 3, TREG_ZERO, 1, 839 + { "seqi", TILEPRO_OPC_SEQI, 0xf, 3, TREG_ZERO, 1, 862 840 { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, 863 841 }, 864 - { "seqi.sn", TILE_OPC_SEQI_SN, 0x3, 3, TREG_SN, 1, 842 + { "seqi.sn", TILEPRO_OPC_SEQI_SN, 0x3, 3, TREG_SN, 1, 865 843 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 866 844 }, 867 - { "seqib", TILE_OPC_SEQIB, 0x3, 3, TREG_ZERO, 1, 845 + { "seqib", TILEPRO_OPC_SEQIB, 0x3, 3, TREG_ZERO, 1, 868 846 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 869 847 }, 870 - { "seqib.sn", TILE_OPC_SEQIB_SN, 0x3, 3, TREG_SN, 1, 848 + { "seqib.sn", TILEPRO_OPC_SEQIB_SN, 0x3, 3, TREG_SN, 1, 871 849 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 872 850 }, 873 - { "seqih", TILE_OPC_SEQIH, 0x3, 3, TREG_ZERO, 1, 851 + { "seqih", TILEPRO_OPC_SEQIH, 0x3, 3, TREG_ZERO, 1, 874 852 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 875 853 }, 876 - { "seqih.sn", TILE_OPC_SEQIH_SN, 0x3, 3, TREG_SN, 1, 854 + { "seqih.sn", TILEPRO_OPC_SEQIH_SN, 0x3, 3, TREG_SN, 1, 877 855 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 878 856 }, 879 - { "sh", TILE_OPC_SH, 0x12, 2, TREG_ZERO, 1, 857 + { "sh", TILEPRO_OPC_SH, 0x12, 2, TREG_ZERO, 1, 880 858 { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } }, 881 859 }, 882 - { "shadd", TILE_OPC_SHADD, 0x2, 3, TREG_ZERO, 1, 860 + { "shadd", TILEPRO_OPC_SHADD, 0x2, 3, TREG_ZERO, 1, 883 861 { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } }, 884 862 }, 885 - { "shl", TILE_OPC_SHL, 0xf, 3, TREG_ZERO, 1, 863 + { "shl", TILEPRO_OPC_SHL, 0xf, 3, TREG_ZERO, 1, 886 864 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 887 865 }, 888 - { "shl.sn", TILE_OPC_SHL_SN, 0x3, 3, TREG_SN, 1, 866 + { "shl.sn", TILEPRO_OPC_SHL_SN, 0x3, 3, TREG_SN, 1, 889 867 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 890 868 }, 891 - { "shlb", TILE_OPC_SHLB, 0x3, 3, TREG_ZERO, 1, 869 + { "shlb", TILEPRO_OPC_SHLB, 0x3, 3, TREG_ZERO, 1, 892 870 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 893 871 }, 894 - { "shlb.sn", TILE_OPC_SHLB_SN, 0x3, 3, TREG_SN, 1, 872 + { "shlb.sn", TILEPRO_OPC_SHLB_SN, 0x3, 3, TREG_SN, 1, 895 873 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 896 874 }, 897 - { "shlh", TILE_OPC_SHLH, 0x3, 3, TREG_ZERO, 1, 875 + { "shlh", TILEPRO_OPC_SHLH, 0x3, 3, TREG_ZERO, 1, 898 876 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 899 877 }, 900 - { "shlh.sn", TILE_OPC_SHLH_SN, 0x3, 3, TREG_SN, 1, 878 + { "shlh.sn", TILEPRO_OPC_SHLH_SN, 0x3, 3, TREG_SN, 1, 901 879 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 902 880 }, 903 - { "shli", TILE_OPC_SHLI, 0xf, 3, TREG_ZERO, 1, 881 + { "shli", TILEPRO_OPC_SHLI, 0xf, 3, TREG_ZERO, 1, 904 882 { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } }, 905 883 }, 906 - { "shli.sn", TILE_OPC_SHLI_SN, 0x3, 3, TREG_SN, 1, 884 + { "shli.sn", TILEPRO_OPC_SHLI_SN, 0x3, 3, TREG_SN, 1, 907 885 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 908 886 }, 909 - { "shlib", TILE_OPC_SHLIB, 0x3, 3, TREG_ZERO, 1, 887 + { "shlib", TILEPRO_OPC_SHLIB, 0x3, 3, TREG_ZERO, 1, 910 888 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 911 889 }, 912 - { "shlib.sn", TILE_OPC_SHLIB_SN, 0x3, 3, TREG_SN, 1, 890 + { "shlib.sn", TILEPRO_OPC_SHLIB_SN, 0x3, 3, TREG_SN, 1, 913 891 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 914 892 }, 915 - { "shlih", TILE_OPC_SHLIH, 0x3, 3, TREG_ZERO, 1, 893 + { "shlih", TILEPRO_OPC_SHLIH, 0x3, 3, TREG_ZERO, 1, 916 894 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 917 895 }, 918 - { "shlih.sn", TILE_OPC_SHLIH_SN, 0x3, 3, TREG_SN, 1, 896 + { "shlih.sn", TILEPRO_OPC_SHLIH_SN, 0x3, 3, TREG_SN, 1, 919 897 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 920 898 }, 921 - { "shr", TILE_OPC_SHR, 0xf, 3, TREG_ZERO, 1, 899 + { "shr", TILEPRO_OPC_SHR, 0xf, 3, TREG_ZERO, 1, 922 900 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 923 901 }, 924 - { "shr.sn", TILE_OPC_SHR_SN, 0x3, 3, TREG_SN, 1, 902 + { "shr.sn", TILEPRO_OPC_SHR_SN, 0x3, 3, TREG_SN, 1, 925 903 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 926 904 }, 927 - { "shrb", TILE_OPC_SHRB, 0x3, 3, TREG_ZERO, 1, 905 + { "shrb", TILEPRO_OPC_SHRB, 0x3, 3, TREG_ZERO, 1, 928 906 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 929 907 }, 930 - { "shrb.sn", TILE_OPC_SHRB_SN, 0x3, 3, TREG_SN, 1, 908 + { "shrb.sn", TILEPRO_OPC_SHRB_SN, 0x3, 3, TREG_SN, 1, 931 909 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 932 910 }, 933 - { "shrh", TILE_OPC_SHRH, 0x3, 3, TREG_ZERO, 1, 911 + { "shrh", TILEPRO_OPC_SHRH, 0x3, 3, TREG_ZERO, 1, 934 912 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 935 913 }, 936 - { "shrh.sn", TILE_OPC_SHRH_SN, 0x3, 3, TREG_SN, 1, 914 + { "shrh.sn", TILEPRO_OPC_SHRH_SN, 0x3, 3, TREG_SN, 1, 937 915 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 938 916 }, 939 - { "shri", TILE_OPC_SHRI, 0xf, 3, TREG_ZERO, 1, 917 + { "shri", TILEPRO_OPC_SHRI, 0xf, 3, TREG_ZERO, 1, 940 918 { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } }, 941 919 }, 942 - { "shri.sn", TILE_OPC_SHRI_SN, 0x3, 3, TREG_SN, 1, 920 + { "shri.sn", TILEPRO_OPC_SHRI_SN, 0x3, 3, TREG_SN, 1, 943 921 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 944 922 }, 945 - { "shrib", TILE_OPC_SHRIB, 0x3, 3, TREG_ZERO, 1, 923 + { "shrib", TILEPRO_OPC_SHRIB, 0x3, 3, TREG_ZERO, 1, 946 924 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 947 925 }, 948 - { "shrib.sn", TILE_OPC_SHRIB_SN, 0x3, 3, TREG_SN, 1, 926 + { "shrib.sn", TILEPRO_OPC_SHRIB_SN, 0x3, 3, TREG_SN, 1, 949 927 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 950 928 }, 951 - { "shrih", TILE_OPC_SHRIH, 0x3, 3, TREG_ZERO, 1, 929 + { "shrih", TILEPRO_OPC_SHRIH, 0x3, 3, TREG_ZERO, 1, 952 930 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 953 931 }, 954 - { "shrih.sn", TILE_OPC_SHRIH_SN, 0x3, 3, TREG_SN, 1, 932 + { "shrih.sn", TILEPRO_OPC_SHRIH_SN, 0x3, 3, TREG_SN, 1, 955 933 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 956 934 }, 957 - { "slt", TILE_OPC_SLT, 0xf, 3, TREG_ZERO, 1, 935 + { "slt", TILEPRO_OPC_SLT, 0xf, 3, TREG_ZERO, 1, 958 936 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 959 937 }, 960 - { "slt.sn", TILE_OPC_SLT_SN, 0x3, 3, TREG_SN, 1, 938 + { "slt.sn", TILEPRO_OPC_SLT_SN, 0x3, 3, TREG_SN, 1, 961 939 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 962 940 }, 963 - { "slt_u", TILE_OPC_SLT_U, 0xf, 3, TREG_ZERO, 1, 941 + { "slt_u", TILEPRO_OPC_SLT_U, 0xf, 3, TREG_ZERO, 1, 964 942 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 965 943 }, 966 - { "slt_u.sn", TILE_OPC_SLT_U_SN, 0x3, 3, TREG_SN, 1, 944 + { "slt_u.sn", TILEPRO_OPC_SLT_U_SN, 0x3, 3, TREG_SN, 1, 967 945 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 968 946 }, 969 - { "sltb", TILE_OPC_SLTB, 0x3, 3, TREG_ZERO, 1, 947 + { "sltb", TILEPRO_OPC_SLTB, 0x3, 3, TREG_ZERO, 1, 970 948 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 971 949 }, 972 - { "sltb.sn", TILE_OPC_SLTB_SN, 0x3, 3, TREG_SN, 1, 950 + { "sltb.sn", TILEPRO_OPC_SLTB_SN, 0x3, 3, TREG_SN, 1, 973 951 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 974 952 }, 975 - { "sltb_u", TILE_OPC_SLTB_U, 0x3, 3, TREG_ZERO, 1, 953 + { "sltb_u", TILEPRO_OPC_SLTB_U, 0x3, 3, TREG_ZERO, 1, 976 954 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 977 955 }, 978 - { "sltb_u.sn", TILE_OPC_SLTB_U_SN, 0x3, 3, TREG_SN, 1, 956 + { "sltb_u.sn", TILEPRO_OPC_SLTB_U_SN, 0x3, 3, TREG_SN, 1, 979 957 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 980 958 }, 981 - { "slte", TILE_OPC_SLTE, 0xf, 3, TREG_ZERO, 1, 959 + { "slte", TILEPRO_OPC_SLTE, 0xf, 3, TREG_ZERO, 1, 982 960 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 983 961 }, 984 - { "slte.sn", TILE_OPC_SLTE_SN, 0x3, 3, TREG_SN, 1, 962 + { "slte.sn", TILEPRO_OPC_SLTE_SN, 0x3, 3, TREG_SN, 1, 985 963 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 986 964 }, 987 - { "slte_u", TILE_OPC_SLTE_U, 0xf, 3, TREG_ZERO, 1, 965 + { "slte_u", TILEPRO_OPC_SLTE_U, 0xf, 3, TREG_ZERO, 1, 988 966 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 989 967 }, 990 - { "slte_u.sn", TILE_OPC_SLTE_U_SN, 0x3, 3, TREG_SN, 1, 968 + { "slte_u.sn", TILEPRO_OPC_SLTE_U_SN, 0x3, 3, TREG_SN, 1, 991 969 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 992 970 }, 993 - { "slteb", TILE_OPC_SLTEB, 0x3, 3, TREG_ZERO, 1, 971 + { "slteb", TILEPRO_OPC_SLTEB, 0x3, 3, TREG_ZERO, 1, 994 972 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 995 973 }, 996 - { "slteb.sn", TILE_OPC_SLTEB_SN, 0x3, 3, TREG_SN, 1, 974 + { "slteb.sn", TILEPRO_OPC_SLTEB_SN, 0x3, 3, TREG_SN, 1, 997 975 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 998 976 }, 999 - { "slteb_u", TILE_OPC_SLTEB_U, 0x3, 3, TREG_ZERO, 1, 977 + { "slteb_u", TILEPRO_OPC_SLTEB_U, 0x3, 3, TREG_ZERO, 1, 1000 978 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1001 979 }, 1002 - { "slteb_u.sn", TILE_OPC_SLTEB_U_SN, 0x3, 3, TREG_SN, 1, 980 + { "slteb_u.sn", TILEPRO_OPC_SLTEB_U_SN, 0x3, 3, TREG_SN, 1, 1003 981 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1004 982 }, 1005 - { "slteh", TILE_OPC_SLTEH, 0x3, 3, TREG_ZERO, 1, 983 + { "slteh", TILEPRO_OPC_SLTEH, 0x3, 3, TREG_ZERO, 1, 1006 984 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1007 985 }, 1008 - { "slteh.sn", TILE_OPC_SLTEH_SN, 0x3, 3, TREG_SN, 1, 986 + { "slteh.sn", TILEPRO_OPC_SLTEH_SN, 0x3, 3, TREG_SN, 1, 1009 987 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1010 988 }, 1011 - { "slteh_u", TILE_OPC_SLTEH_U, 0x3, 3, TREG_ZERO, 1, 989 + { "slteh_u", TILEPRO_OPC_SLTEH_U, 0x3, 3, TREG_ZERO, 1, 1012 990 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1013 991 }, 1014 - { "slteh_u.sn", TILE_OPC_SLTEH_U_SN, 0x3, 3, TREG_SN, 1, 992 + { "slteh_u.sn", TILEPRO_OPC_SLTEH_U_SN, 0x3, 3, TREG_SN, 1, 1015 993 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1016 994 }, 1017 - { "slth", TILE_OPC_SLTH, 0x3, 3, TREG_ZERO, 1, 995 + { "slth", TILEPRO_OPC_SLTH, 0x3, 3, TREG_ZERO, 1, 1018 996 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1019 997 }, 1020 - { "slth.sn", TILE_OPC_SLTH_SN, 0x3, 3, TREG_SN, 1, 998 + { "slth.sn", TILEPRO_OPC_SLTH_SN, 0x3, 3, TREG_SN, 1, 1021 999 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1022 1000 }, 1023 - { "slth_u", TILE_OPC_SLTH_U, 0x3, 3, TREG_ZERO, 1, 1001 + { "slth_u", TILEPRO_OPC_SLTH_U, 0x3, 3, TREG_ZERO, 1, 1024 1002 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1025 1003 }, 1026 - { "slth_u.sn", TILE_OPC_SLTH_U_SN, 0x3, 3, TREG_SN, 1, 1004 + { "slth_u.sn", TILEPRO_OPC_SLTH_U_SN, 0x3, 3, TREG_SN, 1, 1027 1005 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1028 1006 }, 1029 - { "slti", TILE_OPC_SLTI, 0xf, 3, TREG_ZERO, 1, 1007 + { "slti", TILEPRO_OPC_SLTI, 0xf, 3, TREG_ZERO, 1, 1030 1008 { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, 1031 1009 }, 1032 - { "slti.sn", TILE_OPC_SLTI_SN, 0x3, 3, TREG_SN, 1, 1010 + { "slti.sn", TILEPRO_OPC_SLTI_SN, 0x3, 3, TREG_SN, 1, 1033 1011 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 1034 1012 }, 1035 - { "slti_u", TILE_OPC_SLTI_U, 0xf, 3, TREG_ZERO, 1, 1013 + { "slti_u", TILEPRO_OPC_SLTI_U, 0xf, 3, TREG_ZERO, 1, 1036 1014 { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, 1037 1015 }, 1038 - { "slti_u.sn", TILE_OPC_SLTI_U_SN, 0x3, 3, TREG_SN, 1, 1016 + { "slti_u.sn", TILEPRO_OPC_SLTI_U_SN, 0x3, 3, TREG_SN, 1, 1039 1017 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 1040 1018 }, 1041 - { "sltib", TILE_OPC_SLTIB, 0x3, 3, TREG_ZERO, 1, 1019 + { "sltib", TILEPRO_OPC_SLTIB, 0x3, 3, TREG_ZERO, 1, 1042 1020 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 1043 1021 }, 1044 - { "sltib.sn", TILE_OPC_SLTIB_SN, 0x3, 3, TREG_SN, 1, 1022 + { "sltib.sn", TILEPRO_OPC_SLTIB_SN, 0x3, 3, TREG_SN, 1, 1045 1023 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 1046 1024 }, 1047 - { "sltib_u", TILE_OPC_SLTIB_U, 0x3, 3, TREG_ZERO, 1, 1025 + { "sltib_u", TILEPRO_OPC_SLTIB_U, 0x3, 3, TREG_ZERO, 1, 1048 1026 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 1049 1027 }, 1050 - { "sltib_u.sn", TILE_OPC_SLTIB_U_SN, 0x3, 3, TREG_SN, 1, 1028 + { "sltib_u.sn", TILEPRO_OPC_SLTIB_U_SN, 0x3, 3, TREG_SN, 1, 1051 1029 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 1052 1030 }, 1053 - { "sltih", TILE_OPC_SLTIH, 0x3, 3, TREG_ZERO, 1, 1031 + { "sltih", TILEPRO_OPC_SLTIH, 0x3, 3, TREG_ZERO, 1, 1054 1032 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 1055 1033 }, 1056 - { "sltih.sn", TILE_OPC_SLTIH_SN, 0x3, 3, TREG_SN, 1, 1034 + { "sltih.sn", TILEPRO_OPC_SLTIH_SN, 0x3, 3, TREG_SN, 1, 1057 1035 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 1058 1036 }, 1059 - { "sltih_u", TILE_OPC_SLTIH_U, 0x3, 3, TREG_ZERO, 1, 1037 + { "sltih_u", TILEPRO_OPC_SLTIH_U, 0x3, 3, TREG_ZERO, 1, 1060 1038 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 1061 1039 }, 1062 - { "sltih_u.sn", TILE_OPC_SLTIH_U_SN, 0x3, 3, TREG_SN, 1, 1040 + { "sltih_u.sn", TILEPRO_OPC_SLTIH_U_SN, 0x3, 3, TREG_SN, 1, 1063 1041 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 1064 1042 }, 1065 - { "sne", TILE_OPC_SNE, 0xf, 3, TREG_ZERO, 1, 1043 + { "sne", TILEPRO_OPC_SNE, 0xf, 3, TREG_ZERO, 1, 1066 1044 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 1067 1045 }, 1068 - { "sne.sn", TILE_OPC_SNE_SN, 0x3, 3, TREG_SN, 1, 1046 + { "sne.sn", TILEPRO_OPC_SNE_SN, 0x3, 3, TREG_SN, 1, 1069 1047 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1070 1048 }, 1071 - { "sneb", TILE_OPC_SNEB, 0x3, 3, TREG_ZERO, 1, 1049 + { "sneb", TILEPRO_OPC_SNEB, 0x3, 3, TREG_ZERO, 1, 1072 1050 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1073 1051 }, 1074 - { "sneb.sn", TILE_OPC_SNEB_SN, 0x3, 3, TREG_SN, 1, 1052 + { "sneb.sn", TILEPRO_OPC_SNEB_SN, 0x3, 3, TREG_SN, 1, 1075 1053 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1076 1054 }, 1077 - { "sneh", TILE_OPC_SNEH, 0x3, 3, TREG_ZERO, 1, 1055 + { "sneh", TILEPRO_OPC_SNEH, 0x3, 3, TREG_ZERO, 1, 1078 1056 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1079 1057 }, 1080 - { "sneh.sn", TILE_OPC_SNEH_SN, 0x3, 3, TREG_SN, 1, 1058 + { "sneh.sn", TILEPRO_OPC_SNEH_SN, 0x3, 3, TREG_SN, 1, 1081 1059 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1082 1060 }, 1083 - { "sra", TILE_OPC_SRA, 0xf, 3, TREG_ZERO, 1, 1061 + { "sra", TILEPRO_OPC_SRA, 0xf, 3, TREG_ZERO, 1, 1084 1062 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 1085 1063 }, 1086 - { "sra.sn", TILE_OPC_SRA_SN, 0x3, 3, TREG_SN, 1, 1064 + { "sra.sn", TILEPRO_OPC_SRA_SN, 0x3, 3, TREG_SN, 1, 1087 1065 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1088 1066 }, 1089 - { "srab", TILE_OPC_SRAB, 0x3, 3, TREG_ZERO, 1, 1067 + { "srab", TILEPRO_OPC_SRAB, 0x3, 3, TREG_ZERO, 1, 1090 1068 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1091 1069 }, 1092 - { "srab.sn", TILE_OPC_SRAB_SN, 0x3, 3, TREG_SN, 1, 1070 + { "srab.sn", TILEPRO_OPC_SRAB_SN, 0x3, 3, TREG_SN, 1, 1093 1071 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1094 1072 }, 1095 - { "srah", TILE_OPC_SRAH, 0x3, 3, TREG_ZERO, 1, 1073 + { "srah", TILEPRO_OPC_SRAH, 0x3, 3, TREG_ZERO, 1, 1096 1074 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1097 1075 }, 1098 - { "srah.sn", TILE_OPC_SRAH_SN, 0x3, 3, TREG_SN, 1, 1076 + { "srah.sn", TILEPRO_OPC_SRAH_SN, 0x3, 3, TREG_SN, 1, 1099 1077 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1100 1078 }, 1101 - { "srai", TILE_OPC_SRAI, 0xf, 3, TREG_ZERO, 1, 1079 + { "srai", TILEPRO_OPC_SRAI, 0xf, 3, TREG_ZERO, 1, 1102 1080 { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } }, 1103 1081 }, 1104 - { "srai.sn", TILE_OPC_SRAI_SN, 0x3, 3, TREG_SN, 1, 1082 + { "srai.sn", TILEPRO_OPC_SRAI_SN, 0x3, 3, TREG_SN, 1, 1105 1083 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 1106 1084 }, 1107 - { "sraib", TILE_OPC_SRAIB, 0x3, 3, TREG_ZERO, 1, 1085 + { "sraib", TILEPRO_OPC_SRAIB, 0x3, 3, TREG_ZERO, 1, 1108 1086 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 1109 1087 }, 1110 - { "sraib.sn", TILE_OPC_SRAIB_SN, 0x3, 3, TREG_SN, 1, 1088 + { "sraib.sn", TILEPRO_OPC_SRAIB_SN, 0x3, 3, TREG_SN, 1, 1111 1089 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 1112 1090 }, 1113 - { "sraih", TILE_OPC_SRAIH, 0x3, 3, TREG_ZERO, 1, 1091 + { "sraih", TILEPRO_OPC_SRAIH, 0x3, 3, TREG_ZERO, 1, 1114 1092 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 1115 1093 }, 1116 - { "sraih.sn", TILE_OPC_SRAIH_SN, 0x3, 3, TREG_SN, 1, 1094 + { "sraih.sn", TILEPRO_OPC_SRAIH_SN, 0x3, 3, TREG_SN, 1, 1117 1095 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, 1118 1096 }, 1119 - { "sub", TILE_OPC_SUB, 0xf, 3, TREG_ZERO, 1, 1097 + { "sub", TILEPRO_OPC_SUB, 0xf, 3, TREG_ZERO, 1, 1120 1098 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 1121 1099 }, 1122 - { "sub.sn", TILE_OPC_SUB_SN, 0x3, 3, TREG_SN, 1, 1100 + { "sub.sn", TILEPRO_OPC_SUB_SN, 0x3, 3, TREG_SN, 1, 1123 1101 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1124 1102 }, 1125 - { "subb", TILE_OPC_SUBB, 0x3, 3, TREG_ZERO, 1, 1103 + { "subb", TILEPRO_OPC_SUBB, 0x3, 3, TREG_ZERO, 1, 1126 1104 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1127 1105 }, 1128 - { "subb.sn", TILE_OPC_SUBB_SN, 0x3, 3, TREG_SN, 1, 1106 + { "subb.sn", TILEPRO_OPC_SUBB_SN, 0x3, 3, TREG_SN, 1, 1129 1107 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1130 1108 }, 1131 - { "subbs_u", TILE_OPC_SUBBS_U, 0x3, 3, TREG_ZERO, 1, 1109 + { "subbs_u", TILEPRO_OPC_SUBBS_U, 0x3, 3, TREG_ZERO, 1, 1132 1110 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1133 1111 }, 1134 - { "subbs_u.sn", TILE_OPC_SUBBS_U_SN, 0x3, 3, TREG_SN, 1, 1112 + { "subbs_u.sn", TILEPRO_OPC_SUBBS_U_SN, 0x3, 3, TREG_SN, 1, 1135 1113 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1136 1114 }, 1137 - { "subh", TILE_OPC_SUBH, 0x3, 3, TREG_ZERO, 1, 1115 + { "subh", TILEPRO_OPC_SUBH, 0x3, 3, TREG_ZERO, 1, 1138 1116 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1139 1117 }, 1140 - { "subh.sn", TILE_OPC_SUBH_SN, 0x3, 3, TREG_SN, 1, 1118 + { "subh.sn", TILEPRO_OPC_SUBH_SN, 0x3, 3, TREG_SN, 1, 1141 1119 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1142 1120 }, 1143 - { "subhs", TILE_OPC_SUBHS, 0x3, 3, TREG_ZERO, 1, 1121 + { "subhs", TILEPRO_OPC_SUBHS, 0x3, 3, TREG_ZERO, 1, 1144 1122 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1145 1123 }, 1146 - { "subhs.sn", TILE_OPC_SUBHS_SN, 0x3, 3, TREG_SN, 1, 1124 + { "subhs.sn", TILEPRO_OPC_SUBHS_SN, 0x3, 3, TREG_SN, 1, 1147 1125 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1148 1126 }, 1149 - { "subs", TILE_OPC_SUBS, 0x3, 3, TREG_ZERO, 1, 1127 + { "subs", TILEPRO_OPC_SUBS, 0x3, 3, TREG_ZERO, 1, 1150 1128 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1151 1129 }, 1152 - { "subs.sn", TILE_OPC_SUBS_SN, 0x3, 3, TREG_SN, 1, 1130 + { "subs.sn", TILEPRO_OPC_SUBS_SN, 0x3, 3, TREG_SN, 1, 1153 1131 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1154 1132 }, 1155 - { "sw", TILE_OPC_SW, 0x12, 2, TREG_ZERO, 1, 1133 + { "sw", TILEPRO_OPC_SW, 0x12, 2, TREG_ZERO, 1, 1156 1134 { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } }, 1157 1135 }, 1158 - { "swadd", TILE_OPC_SWADD, 0x2, 3, TREG_ZERO, 1, 1136 + { "swadd", TILEPRO_OPC_SWADD, 0x2, 3, TREG_ZERO, 1, 1159 1137 { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } }, 1160 1138 }, 1161 - { "swint0", TILE_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0, 1139 + { "swint0", TILEPRO_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0, 1162 1140 { { 0, }, { }, { 0, }, { 0, }, { 0, } }, 1163 1141 }, 1164 - { "swint1", TILE_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0, 1142 + { "swint1", TILEPRO_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0, 1165 1143 { { 0, }, { }, { 0, }, { 0, }, { 0, } }, 1166 1144 }, 1167 - { "swint2", TILE_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0, 1145 + { "swint2", TILEPRO_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0, 1168 1146 { { 0, }, { }, { 0, }, { 0, }, { 0, } }, 1169 1147 }, 1170 - { "swint3", TILE_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0, 1148 + { "swint3", TILEPRO_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0, 1171 1149 { { 0, }, { }, { 0, }, { 0, }, { 0, } }, 1172 1150 }, 1173 - { "tblidxb0", TILE_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1, 1151 + { "tblidxb0", TILEPRO_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1, 1174 1152 { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } }, 1175 1153 }, 1176 - { "tblidxb0.sn", TILE_OPC_TBLIDXB0_SN, 0x1, 2, TREG_SN, 1, 1154 + { "tblidxb0.sn", TILEPRO_OPC_TBLIDXB0_SN, 0x1, 2, TREG_SN, 1, 1177 1155 { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, 1178 1156 }, 1179 - { "tblidxb1", TILE_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1, 1157 + { "tblidxb1", TILEPRO_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1, 1180 1158 { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } }, 1181 1159 }, 1182 - { "tblidxb1.sn", TILE_OPC_TBLIDXB1_SN, 0x1, 2, TREG_SN, 1, 1160 + { "tblidxb1.sn", TILEPRO_OPC_TBLIDXB1_SN, 0x1, 2, TREG_SN, 1, 1183 1161 { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, 1184 1162 }, 1185 - { "tblidxb2", TILE_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1, 1163 + { "tblidxb2", TILEPRO_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1, 1186 1164 { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } }, 1187 1165 }, 1188 - { "tblidxb2.sn", TILE_OPC_TBLIDXB2_SN, 0x1, 2, TREG_SN, 1, 1166 + { "tblidxb2.sn", TILEPRO_OPC_TBLIDXB2_SN, 0x1, 2, TREG_SN, 1, 1189 1167 { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, 1190 1168 }, 1191 - { "tblidxb3", TILE_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1, 1169 + { "tblidxb3", TILEPRO_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1, 1192 1170 { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } }, 1193 1171 }, 1194 - { "tblidxb3.sn", TILE_OPC_TBLIDXB3_SN, 0x1, 2, TREG_SN, 1, 1172 + { "tblidxb3.sn", TILEPRO_OPC_TBLIDXB3_SN, 0x1, 2, TREG_SN, 1, 1195 1173 { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, 1196 1174 }, 1197 - { "tns", TILE_OPC_TNS, 0x2, 2, TREG_ZERO, 1, 1175 + { "tns", TILEPRO_OPC_TNS, 0x2, 2, TREG_ZERO, 1, 1198 1176 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, 1199 1177 }, 1200 - { "tns.sn", TILE_OPC_TNS_SN, 0x2, 2, TREG_SN, 1, 1178 + { "tns.sn", TILEPRO_OPC_TNS_SN, 0x2, 2, TREG_SN, 1, 1201 1179 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, 1202 1180 }, 1203 - { "wh64", TILE_OPC_WH64, 0x2, 1, TREG_ZERO, 1, 1181 + { "wh64", TILEPRO_OPC_WH64, 0x2, 1, TREG_ZERO, 1, 1204 1182 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, 1205 1183 }, 1206 - { "xor", TILE_OPC_XOR, 0xf, 3, TREG_ZERO, 1, 1184 + { "xor", TILEPRO_OPC_XOR, 0xf, 3, TREG_ZERO, 1, 1207 1185 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, 1208 1186 }, 1209 - { "xor.sn", TILE_OPC_XOR_SN, 0x3, 3, TREG_SN, 1, 1187 + { "xor.sn", TILEPRO_OPC_XOR_SN, 0x3, 3, TREG_SN, 1, 1210 1188 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, 1211 1189 }, 1212 - { "xori", TILE_OPC_XORI, 0x3, 3, TREG_ZERO, 1, 1190 + { "xori", TILEPRO_OPC_XORI, 0x3, 3, TREG_ZERO, 1, 1213 1191 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 1214 1192 }, 1215 - { "xori.sn", TILE_OPC_XORI_SN, 0x3, 3, TREG_SN, 1, 1193 + { "xori.sn", TILEPRO_OPC_XORI_SN, 0x3, 3, TREG_SN, 1, 1216 1194 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, 1217 1195 }, 1218 - { NULL, TILE_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } }, 1196 + { NULL, TILEPRO_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } }, 1219 1197 } 1220 1198 }; 1221 1199 #define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6)) 1222 - #define CHILD(array_index) (TILE_OPC_NONE + (array_index)) 1200 + #define CHILD(array_index) (TILEPRO_OPC_NONE + (array_index)) 1223 1201 1224 1202 static const unsigned short decode_X0_fsm[1153] = 1225 1203 { 1226 1204 BITFIELD(22, 9) /* index 0 */, 1227 1205 CHILD(513), CHILD(530), CHILD(547), CHILD(564), CHILD(596), CHILD(613), 1228 - CHILD(630), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1229 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1230 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1231 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1232 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1233 - TILE_OPC_NONE, CHILD(663), CHILD(680), CHILD(697), CHILD(714), CHILD(746), 1234 - CHILD(763), CHILD(780), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1235 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1236 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1237 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1238 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1239 - TILE_OPC_NONE, TILE_OPC_NONE, CHILD(813), CHILD(813), CHILD(813), 1206 + CHILD(630), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1207 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1208 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1209 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1210 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1211 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1212 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(663), CHILD(680), CHILD(697), 1213 + CHILD(714), CHILD(746), CHILD(763), CHILD(780), TILEPRO_OPC_NONE, 1214 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1215 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1216 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1217 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1218 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1219 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1240 1220 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), 1241 1221 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), 1242 1222 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), ··· 1247 1227 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), 1248 1228 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), 1249 1229 CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), 1250 - CHILD(813), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), 1230 + CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(828), CHILD(828), 1251 1231 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), 1252 1232 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), 1253 1233 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), ··· 1257 1237 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), 1258 1238 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), 1259 1239 CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), 1260 - CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(843), 1240 + CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), 1241 + CHILD(828), CHILD(828), CHILD(843), CHILD(843), CHILD(843), CHILD(843), 1261 1242 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), 1262 1243 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), 1263 1244 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), ··· 1269 1248 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), 1270 1249 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), 1271 1250 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), 1272 - CHILD(843), CHILD(843), CHILD(843), CHILD(873), CHILD(878), CHILD(883), 1273 - CHILD(903), CHILD(908), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1274 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1275 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1276 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1277 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1278 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(913), 1279 - CHILD(918), CHILD(923), CHILD(943), CHILD(948), TILE_OPC_NONE, 1280 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1281 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1282 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1283 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1284 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1285 - TILE_OPC_NONE, CHILD(953), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1286 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1287 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1288 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1289 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1290 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1291 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(988), TILE_OPC_NONE, 1292 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1293 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1294 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1295 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1296 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1297 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1298 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1299 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1300 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1301 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1302 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1303 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1304 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1305 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1306 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1307 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1308 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1309 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1310 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, CHILD(993), 1311 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1312 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1313 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1314 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1315 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1316 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1317 - TILE_OPC_NONE, CHILD(1076), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1318 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1319 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1320 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1321 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1322 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1323 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1251 + CHILD(873), CHILD(878), CHILD(883), CHILD(903), CHILD(908), 1252 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1253 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1254 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1255 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1256 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1257 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1258 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(913), 1259 + CHILD(918), CHILD(923), CHILD(943), CHILD(948), TILEPRO_OPC_NONE, 1260 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1261 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1262 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1263 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1264 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1265 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1266 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(953), TILEPRO_OPC_NONE, 1267 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1268 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1269 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1270 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1271 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1272 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1273 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1274 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(988), TILEPRO_OPC_NONE, 1275 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1276 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1277 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1278 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1279 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1280 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1281 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1282 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1283 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1284 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1285 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1286 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1287 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1288 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1289 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1290 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1291 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1292 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1293 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1294 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1295 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1296 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1297 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1298 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, CHILD(993), TILEPRO_OPC_NONE, 1299 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1300 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1301 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1302 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1303 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1304 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1305 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1306 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(1076), TILEPRO_OPC_NONE, 1307 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1308 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1309 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1310 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1311 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1312 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1313 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1314 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1324 1315 BITFIELD(18, 4) /* index 513 */, 1325 - TILE_OPC_NONE, TILE_OPC_ADDB, TILE_OPC_ADDH, TILE_OPC_ADD, 1326 - TILE_OPC_ADIFFB_U, TILE_OPC_ADIFFH, TILE_OPC_AND, TILE_OPC_AVGB_U, 1327 - TILE_OPC_AVGH, TILE_OPC_CRC32_32, TILE_OPC_CRC32_8, TILE_OPC_INTHB, 1328 - TILE_OPC_INTHH, TILE_OPC_INTLB, TILE_OPC_INTLH, TILE_OPC_MAXB_U, 1316 + TILEPRO_OPC_NONE, TILEPRO_OPC_ADDB, TILEPRO_OPC_ADDH, TILEPRO_OPC_ADD, 1317 + TILEPRO_OPC_ADIFFB_U, TILEPRO_OPC_ADIFFH, TILEPRO_OPC_AND, 1318 + TILEPRO_OPC_AVGB_U, TILEPRO_OPC_AVGH, TILEPRO_OPC_CRC32_32, 1319 + TILEPRO_OPC_CRC32_8, TILEPRO_OPC_INTHB, TILEPRO_OPC_INTHH, 1320 + TILEPRO_OPC_INTLB, TILEPRO_OPC_INTLH, TILEPRO_OPC_MAXB_U, 1329 1321 BITFIELD(18, 4) /* index 530 */, 1330 - TILE_OPC_MAXH, TILE_OPC_MINB_U, TILE_OPC_MINH, TILE_OPC_MNZB, TILE_OPC_MNZH, 1331 - TILE_OPC_MNZ, TILE_OPC_MULHHA_SS, TILE_OPC_MULHHA_SU, TILE_OPC_MULHHA_UU, 1332 - TILE_OPC_MULHHSA_UU, TILE_OPC_MULHH_SS, TILE_OPC_MULHH_SU, 1333 - TILE_OPC_MULHH_UU, TILE_OPC_MULHLA_SS, TILE_OPC_MULHLA_SU, 1334 - TILE_OPC_MULHLA_US, 1322 + TILEPRO_OPC_MAXH, TILEPRO_OPC_MINB_U, TILEPRO_OPC_MINH, TILEPRO_OPC_MNZB, 1323 + TILEPRO_OPC_MNZH, TILEPRO_OPC_MNZ, TILEPRO_OPC_MULHHA_SS, 1324 + TILEPRO_OPC_MULHHA_SU, TILEPRO_OPC_MULHHA_UU, TILEPRO_OPC_MULHHSA_UU, 1325 + TILEPRO_OPC_MULHH_SS, TILEPRO_OPC_MULHH_SU, TILEPRO_OPC_MULHH_UU, 1326 + TILEPRO_OPC_MULHLA_SS, TILEPRO_OPC_MULHLA_SU, TILEPRO_OPC_MULHLA_US, 1335 1327 BITFIELD(18, 4) /* index 547 */, 1336 - TILE_OPC_MULHLA_UU, TILE_OPC_MULHLSA_UU, TILE_OPC_MULHL_SS, 1337 - TILE_OPC_MULHL_SU, TILE_OPC_MULHL_US, TILE_OPC_MULHL_UU, TILE_OPC_MULLLA_SS, 1338 - TILE_OPC_MULLLA_SU, TILE_OPC_MULLLA_UU, TILE_OPC_MULLLSA_UU, 1339 - TILE_OPC_MULLL_SS, TILE_OPC_MULLL_SU, TILE_OPC_MULLL_UU, TILE_OPC_MVNZ, 1340 - TILE_OPC_MVZ, TILE_OPC_MZB, 1328 + TILEPRO_OPC_MULHLA_UU, TILEPRO_OPC_MULHLSA_UU, TILEPRO_OPC_MULHL_SS, 1329 + TILEPRO_OPC_MULHL_SU, TILEPRO_OPC_MULHL_US, TILEPRO_OPC_MULHL_UU, 1330 + TILEPRO_OPC_MULLLA_SS, TILEPRO_OPC_MULLLA_SU, TILEPRO_OPC_MULLLA_UU, 1331 + TILEPRO_OPC_MULLLSA_UU, TILEPRO_OPC_MULLL_SS, TILEPRO_OPC_MULLL_SU, 1332 + TILEPRO_OPC_MULLL_UU, TILEPRO_OPC_MVNZ, TILEPRO_OPC_MVZ, TILEPRO_OPC_MZB, 1341 1333 BITFIELD(18, 4) /* index 564 */, 1342 - TILE_OPC_MZH, TILE_OPC_MZ, TILE_OPC_NOR, CHILD(581), TILE_OPC_PACKHB, 1343 - TILE_OPC_PACKLB, TILE_OPC_RL, TILE_OPC_S1A, TILE_OPC_S2A, TILE_OPC_S3A, 1344 - TILE_OPC_SADAB_U, TILE_OPC_SADAH, TILE_OPC_SADAH_U, TILE_OPC_SADB_U, 1345 - TILE_OPC_SADH, TILE_OPC_SADH_U, 1334 + TILEPRO_OPC_MZH, TILEPRO_OPC_MZ, TILEPRO_OPC_NOR, CHILD(581), 1335 + TILEPRO_OPC_PACKHB, TILEPRO_OPC_PACKLB, TILEPRO_OPC_RL, TILEPRO_OPC_S1A, 1336 + TILEPRO_OPC_S2A, TILEPRO_OPC_S3A, TILEPRO_OPC_SADAB_U, TILEPRO_OPC_SADAH, 1337 + TILEPRO_OPC_SADAH_U, TILEPRO_OPC_SADB_U, TILEPRO_OPC_SADH, 1338 + TILEPRO_OPC_SADH_U, 1346 1339 BITFIELD(12, 2) /* index 581 */, 1347 - TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(586), 1340 + TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(586), 1348 1341 BITFIELD(14, 2) /* index 586 */, 1349 - TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(591), 1342 + TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(591), 1350 1343 BITFIELD(16, 2) /* index 591 */, 1351 - TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_MOVE, 1344 + TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_MOVE, 1352 1345 BITFIELD(18, 4) /* index 596 */, 1353 - TILE_OPC_SEQB, TILE_OPC_SEQH, TILE_OPC_SEQ, TILE_OPC_SHLB, TILE_OPC_SHLH, 1354 - TILE_OPC_SHL, TILE_OPC_SHRB, TILE_OPC_SHRH, TILE_OPC_SHR, TILE_OPC_SLTB, 1355 - TILE_OPC_SLTB_U, TILE_OPC_SLTEB, TILE_OPC_SLTEB_U, TILE_OPC_SLTEH, 1356 - TILE_OPC_SLTEH_U, TILE_OPC_SLTE, 1346 + TILEPRO_OPC_SEQB, TILEPRO_OPC_SEQH, TILEPRO_OPC_SEQ, TILEPRO_OPC_SHLB, 1347 + TILEPRO_OPC_SHLH, TILEPRO_OPC_SHL, TILEPRO_OPC_SHRB, TILEPRO_OPC_SHRH, 1348 + TILEPRO_OPC_SHR, TILEPRO_OPC_SLTB, TILEPRO_OPC_SLTB_U, TILEPRO_OPC_SLTEB, 1349 + TILEPRO_OPC_SLTEB_U, TILEPRO_OPC_SLTEH, TILEPRO_OPC_SLTEH_U, 1350 + TILEPRO_OPC_SLTE, 1357 1351 BITFIELD(18, 4) /* index 613 */, 1358 - TILE_OPC_SLTE_U, TILE_OPC_SLTH, TILE_OPC_SLTH_U, TILE_OPC_SLT, 1359 - TILE_OPC_SLT_U, TILE_OPC_SNEB, TILE_OPC_SNEH, TILE_OPC_SNE, TILE_OPC_SRAB, 1360 - TILE_OPC_SRAH, TILE_OPC_SRA, TILE_OPC_SUBB, TILE_OPC_SUBH, TILE_OPC_SUB, 1361 - TILE_OPC_XOR, TILE_OPC_DWORD_ALIGN, 1352 + TILEPRO_OPC_SLTE_U, TILEPRO_OPC_SLTH, TILEPRO_OPC_SLTH_U, TILEPRO_OPC_SLT, 1353 + TILEPRO_OPC_SLT_U, TILEPRO_OPC_SNEB, TILEPRO_OPC_SNEH, TILEPRO_OPC_SNE, 1354 + TILEPRO_OPC_SRAB, TILEPRO_OPC_SRAH, TILEPRO_OPC_SRA, TILEPRO_OPC_SUBB, 1355 + TILEPRO_OPC_SUBH, TILEPRO_OPC_SUB, TILEPRO_OPC_XOR, TILEPRO_OPC_DWORD_ALIGN, 1362 1356 BITFIELD(18, 3) /* index 630 */, 1363 1357 CHILD(639), CHILD(642), CHILD(645), CHILD(648), CHILD(651), CHILD(654), 1364 1358 CHILD(657), CHILD(660), 1365 1359 BITFIELD(21, 1) /* index 639 */, 1366 - TILE_OPC_ADDS, TILE_OPC_NONE, 1360 + TILEPRO_OPC_ADDS, TILEPRO_OPC_NONE, 1367 1361 BITFIELD(21, 1) /* index 642 */, 1368 - TILE_OPC_SUBS, TILE_OPC_NONE, 1362 + TILEPRO_OPC_SUBS, TILEPRO_OPC_NONE, 1369 1363 BITFIELD(21, 1) /* index 645 */, 1370 - TILE_OPC_ADDBS_U, TILE_OPC_NONE, 1364 + TILEPRO_OPC_ADDBS_U, TILEPRO_OPC_NONE, 1371 1365 BITFIELD(21, 1) /* index 648 */, 1372 - TILE_OPC_ADDHS, TILE_OPC_NONE, 1366 + TILEPRO_OPC_ADDHS, TILEPRO_OPC_NONE, 1373 1367 BITFIELD(21, 1) /* index 651 */, 1374 - TILE_OPC_SUBBS_U, TILE_OPC_NONE, 1368 + TILEPRO_OPC_SUBBS_U, TILEPRO_OPC_NONE, 1375 1369 BITFIELD(21, 1) /* index 654 */, 1376 - TILE_OPC_SUBHS, TILE_OPC_NONE, 1370 + TILEPRO_OPC_SUBHS, TILEPRO_OPC_NONE, 1377 1371 BITFIELD(21, 1) /* index 657 */, 1378 - TILE_OPC_PACKHS, TILE_OPC_NONE, 1372 + TILEPRO_OPC_PACKHS, TILEPRO_OPC_NONE, 1379 1373 BITFIELD(21, 1) /* index 660 */, 1380 - TILE_OPC_PACKBS_U, TILE_OPC_NONE, 1374 + TILEPRO_OPC_PACKBS_U, TILEPRO_OPC_NONE, 1381 1375 BITFIELD(18, 4) /* index 663 */, 1382 - TILE_OPC_NONE, TILE_OPC_ADDB_SN, TILE_OPC_ADDH_SN, TILE_OPC_ADD_SN, 1383 - TILE_OPC_ADIFFB_U_SN, TILE_OPC_ADIFFH_SN, TILE_OPC_AND_SN, 1384 - TILE_OPC_AVGB_U_SN, TILE_OPC_AVGH_SN, TILE_OPC_CRC32_32_SN, 1385 - TILE_OPC_CRC32_8_SN, TILE_OPC_INTHB_SN, TILE_OPC_INTHH_SN, 1386 - TILE_OPC_INTLB_SN, TILE_OPC_INTLH_SN, TILE_OPC_MAXB_U_SN, 1376 + TILEPRO_OPC_NONE, TILEPRO_OPC_ADDB_SN, TILEPRO_OPC_ADDH_SN, 1377 + TILEPRO_OPC_ADD_SN, TILEPRO_OPC_ADIFFB_U_SN, TILEPRO_OPC_ADIFFH_SN, 1378 + TILEPRO_OPC_AND_SN, TILEPRO_OPC_AVGB_U_SN, TILEPRO_OPC_AVGH_SN, 1379 + TILEPRO_OPC_CRC32_32_SN, TILEPRO_OPC_CRC32_8_SN, TILEPRO_OPC_INTHB_SN, 1380 + TILEPRO_OPC_INTHH_SN, TILEPRO_OPC_INTLB_SN, TILEPRO_OPC_INTLH_SN, 1381 + TILEPRO_OPC_MAXB_U_SN, 1387 1382 BITFIELD(18, 4) /* index 680 */, 1388 - TILE_OPC_MAXH_SN, TILE_OPC_MINB_U_SN, TILE_OPC_MINH_SN, TILE_OPC_MNZB_SN, 1389 - TILE_OPC_MNZH_SN, TILE_OPC_MNZ_SN, TILE_OPC_MULHHA_SS_SN, 1390 - TILE_OPC_MULHHA_SU_SN, TILE_OPC_MULHHA_UU_SN, TILE_OPC_MULHHSA_UU_SN, 1391 - TILE_OPC_MULHH_SS_SN, TILE_OPC_MULHH_SU_SN, TILE_OPC_MULHH_UU_SN, 1392 - TILE_OPC_MULHLA_SS_SN, TILE_OPC_MULHLA_SU_SN, TILE_OPC_MULHLA_US_SN, 1383 + TILEPRO_OPC_MAXH_SN, TILEPRO_OPC_MINB_U_SN, TILEPRO_OPC_MINH_SN, 1384 + TILEPRO_OPC_MNZB_SN, TILEPRO_OPC_MNZH_SN, TILEPRO_OPC_MNZ_SN, 1385 + TILEPRO_OPC_MULHHA_SS_SN, TILEPRO_OPC_MULHHA_SU_SN, 1386 + TILEPRO_OPC_MULHHA_UU_SN, TILEPRO_OPC_MULHHSA_UU_SN, 1387 + TILEPRO_OPC_MULHH_SS_SN, TILEPRO_OPC_MULHH_SU_SN, TILEPRO_OPC_MULHH_UU_SN, 1388 + TILEPRO_OPC_MULHLA_SS_SN, TILEPRO_OPC_MULHLA_SU_SN, 1389 + TILEPRO_OPC_MULHLA_US_SN, 1393 1390 BITFIELD(18, 4) /* index 697 */, 1394 - TILE_OPC_MULHLA_UU_SN, TILE_OPC_MULHLSA_UU_SN, TILE_OPC_MULHL_SS_SN, 1395 - TILE_OPC_MULHL_SU_SN, TILE_OPC_MULHL_US_SN, TILE_OPC_MULHL_UU_SN, 1396 - TILE_OPC_MULLLA_SS_SN, TILE_OPC_MULLLA_SU_SN, TILE_OPC_MULLLA_UU_SN, 1397 - TILE_OPC_MULLLSA_UU_SN, TILE_OPC_MULLL_SS_SN, TILE_OPC_MULLL_SU_SN, 1398 - TILE_OPC_MULLL_UU_SN, TILE_OPC_MVNZ_SN, TILE_OPC_MVZ_SN, TILE_OPC_MZB_SN, 1391 + TILEPRO_OPC_MULHLA_UU_SN, TILEPRO_OPC_MULHLSA_UU_SN, 1392 + TILEPRO_OPC_MULHL_SS_SN, TILEPRO_OPC_MULHL_SU_SN, TILEPRO_OPC_MULHL_US_SN, 1393 + TILEPRO_OPC_MULHL_UU_SN, TILEPRO_OPC_MULLLA_SS_SN, TILEPRO_OPC_MULLLA_SU_SN, 1394 + TILEPRO_OPC_MULLLA_UU_SN, TILEPRO_OPC_MULLLSA_UU_SN, 1395 + TILEPRO_OPC_MULLL_SS_SN, TILEPRO_OPC_MULLL_SU_SN, TILEPRO_OPC_MULLL_UU_SN, 1396 + TILEPRO_OPC_MVNZ_SN, TILEPRO_OPC_MVZ_SN, TILEPRO_OPC_MZB_SN, 1399 1397 BITFIELD(18, 4) /* index 714 */, 1400 - TILE_OPC_MZH_SN, TILE_OPC_MZ_SN, TILE_OPC_NOR_SN, CHILD(731), 1401 - TILE_OPC_PACKHB_SN, TILE_OPC_PACKLB_SN, TILE_OPC_RL_SN, TILE_OPC_S1A_SN, 1402 - TILE_OPC_S2A_SN, TILE_OPC_S3A_SN, TILE_OPC_SADAB_U_SN, TILE_OPC_SADAH_SN, 1403 - TILE_OPC_SADAH_U_SN, TILE_OPC_SADB_U_SN, TILE_OPC_SADH_SN, 1404 - TILE_OPC_SADH_U_SN, 1398 + TILEPRO_OPC_MZH_SN, TILEPRO_OPC_MZ_SN, TILEPRO_OPC_NOR_SN, CHILD(731), 1399 + TILEPRO_OPC_PACKHB_SN, TILEPRO_OPC_PACKLB_SN, TILEPRO_OPC_RL_SN, 1400 + TILEPRO_OPC_S1A_SN, TILEPRO_OPC_S2A_SN, TILEPRO_OPC_S3A_SN, 1401 + TILEPRO_OPC_SADAB_U_SN, TILEPRO_OPC_SADAH_SN, TILEPRO_OPC_SADAH_U_SN, 1402 + TILEPRO_OPC_SADB_U_SN, TILEPRO_OPC_SADH_SN, TILEPRO_OPC_SADH_U_SN, 1405 1403 BITFIELD(12, 2) /* index 731 */, 1406 - TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, CHILD(736), 1404 + TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, CHILD(736), 1407 1405 BITFIELD(14, 2) /* index 736 */, 1408 - TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, CHILD(741), 1406 + TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, CHILD(741), 1409 1407 BITFIELD(16, 2) /* index 741 */, 1410 - TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_MOVE_SN, 1408 + TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, 1409 + TILEPRO_OPC_MOVE_SN, 1411 1410 BITFIELD(18, 4) /* index 746 */, 1412 - TILE_OPC_SEQB_SN, TILE_OPC_SEQH_SN, TILE_OPC_SEQ_SN, TILE_OPC_SHLB_SN, 1413 - TILE_OPC_SHLH_SN, TILE_OPC_SHL_SN, TILE_OPC_SHRB_SN, TILE_OPC_SHRH_SN, 1414 - TILE_OPC_SHR_SN, TILE_OPC_SLTB_SN, TILE_OPC_SLTB_U_SN, TILE_OPC_SLTEB_SN, 1415 - TILE_OPC_SLTEB_U_SN, TILE_OPC_SLTEH_SN, TILE_OPC_SLTEH_U_SN, 1416 - TILE_OPC_SLTE_SN, 1411 + TILEPRO_OPC_SEQB_SN, TILEPRO_OPC_SEQH_SN, TILEPRO_OPC_SEQ_SN, 1412 + TILEPRO_OPC_SHLB_SN, TILEPRO_OPC_SHLH_SN, TILEPRO_OPC_SHL_SN, 1413 + TILEPRO_OPC_SHRB_SN, TILEPRO_OPC_SHRH_SN, TILEPRO_OPC_SHR_SN, 1414 + TILEPRO_OPC_SLTB_SN, TILEPRO_OPC_SLTB_U_SN, TILEPRO_OPC_SLTEB_SN, 1415 + TILEPRO_OPC_SLTEB_U_SN, TILEPRO_OPC_SLTEH_SN, TILEPRO_OPC_SLTEH_U_SN, 1416 + TILEPRO_OPC_SLTE_SN, 1417 1417 BITFIELD(18, 4) /* index 763 */, 1418 - TILE_OPC_SLTE_U_SN, TILE_OPC_SLTH_SN, TILE_OPC_SLTH_U_SN, TILE_OPC_SLT_SN, 1419 - TILE_OPC_SLT_U_SN, TILE_OPC_SNEB_SN, TILE_OPC_SNEH_SN, TILE_OPC_SNE_SN, 1420 - TILE_OPC_SRAB_SN, TILE_OPC_SRAH_SN, TILE_OPC_SRA_SN, TILE_OPC_SUBB_SN, 1421 - TILE_OPC_SUBH_SN, TILE_OPC_SUB_SN, TILE_OPC_XOR_SN, TILE_OPC_DWORD_ALIGN_SN, 1418 + TILEPRO_OPC_SLTE_U_SN, TILEPRO_OPC_SLTH_SN, TILEPRO_OPC_SLTH_U_SN, 1419 + TILEPRO_OPC_SLT_SN, TILEPRO_OPC_SLT_U_SN, TILEPRO_OPC_SNEB_SN, 1420 + TILEPRO_OPC_SNEH_SN, TILEPRO_OPC_SNE_SN, TILEPRO_OPC_SRAB_SN, 1421 + TILEPRO_OPC_SRAH_SN, TILEPRO_OPC_SRA_SN, TILEPRO_OPC_SUBB_SN, 1422 + TILEPRO_OPC_SUBH_SN, TILEPRO_OPC_SUB_SN, TILEPRO_OPC_XOR_SN, 1423 + TILEPRO_OPC_DWORD_ALIGN_SN, 1422 1424 BITFIELD(18, 3) /* index 780 */, 1423 1425 CHILD(789), CHILD(792), CHILD(795), CHILD(798), CHILD(801), CHILD(804), 1424 1426 CHILD(807), CHILD(810), 1425 1427 BITFIELD(21, 1) /* index 789 */, 1426 - TILE_OPC_ADDS_SN, TILE_OPC_NONE, 1428 + TILEPRO_OPC_ADDS_SN, TILEPRO_OPC_NONE, 1427 1429 BITFIELD(21, 1) /* index 792 */, 1428 - TILE_OPC_SUBS_SN, TILE_OPC_NONE, 1430 + TILEPRO_OPC_SUBS_SN, TILEPRO_OPC_NONE, 1429 1431 BITFIELD(21, 1) /* index 795 */, 1430 - TILE_OPC_ADDBS_U_SN, TILE_OPC_NONE, 1432 + TILEPRO_OPC_ADDBS_U_SN, TILEPRO_OPC_NONE, 1431 1433 BITFIELD(21, 1) /* index 798 */, 1432 - TILE_OPC_ADDHS_SN, TILE_OPC_NONE, 1434 + TILEPRO_OPC_ADDHS_SN, TILEPRO_OPC_NONE, 1433 1435 BITFIELD(21, 1) /* index 801 */, 1434 - TILE_OPC_SUBBS_U_SN, TILE_OPC_NONE, 1436 + TILEPRO_OPC_SUBBS_U_SN, TILEPRO_OPC_NONE, 1435 1437 BITFIELD(21, 1) /* index 804 */, 1436 - TILE_OPC_SUBHS_SN, TILE_OPC_NONE, 1438 + TILEPRO_OPC_SUBHS_SN, TILEPRO_OPC_NONE, 1437 1439 BITFIELD(21, 1) /* index 807 */, 1438 - TILE_OPC_PACKHS_SN, TILE_OPC_NONE, 1440 + TILEPRO_OPC_PACKHS_SN, TILEPRO_OPC_NONE, 1439 1441 BITFIELD(21, 1) /* index 810 */, 1440 - TILE_OPC_PACKBS_U_SN, TILE_OPC_NONE, 1442 + TILEPRO_OPC_PACKBS_U_SN, TILEPRO_OPC_NONE, 1441 1443 BITFIELD(6, 2) /* index 813 */, 1442 - TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, CHILD(818), 1444 + TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, 1445 + CHILD(818), 1443 1446 BITFIELD(8, 2) /* index 818 */, 1444 - TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, CHILD(823), 1447 + TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, 1448 + CHILD(823), 1445 1449 BITFIELD(10, 2) /* index 823 */, 1446 - TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_MOVELI_SN, 1450 + TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, 1451 + TILEPRO_OPC_MOVELI_SN, 1447 1452 BITFIELD(6, 2) /* index 828 */, 1448 - TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, CHILD(833), 1453 + TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, CHILD(833), 1449 1454 BITFIELD(8, 2) /* index 833 */, 1450 - TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, CHILD(838), 1455 + TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, CHILD(838), 1451 1456 BITFIELD(10, 2) /* index 838 */, 1452 - TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_MOVELI, 1457 + TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_MOVELI, 1453 1458 BITFIELD(0, 2) /* index 843 */, 1454 - TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(848), 1459 + TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(848), 1455 1460 BITFIELD(2, 2) /* index 848 */, 1456 - TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(853), 1461 + TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(853), 1457 1462 BITFIELD(4, 2) /* index 853 */, 1458 - TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(858), 1463 + TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(858), 1459 1464 BITFIELD(6, 2) /* index 858 */, 1460 - TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(863), 1465 + TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(863), 1461 1466 BITFIELD(8, 2) /* index 863 */, 1462 - TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(868), 1467 + TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(868), 1463 1468 BITFIELD(10, 2) /* index 868 */, 1464 - TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_INFOL, 1469 + TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_INFOL, 1465 1470 BITFIELD(20, 2) /* index 873 */, 1466 - TILE_OPC_NONE, TILE_OPC_ADDIB, TILE_OPC_ADDIH, TILE_OPC_ADDI, 1471 + TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB, TILEPRO_OPC_ADDIH, TILEPRO_OPC_ADDI, 1467 1472 BITFIELD(20, 2) /* index 878 */, 1468 - TILE_OPC_MAXIB_U, TILE_OPC_MAXIH, TILE_OPC_MINIB_U, TILE_OPC_MINIH, 1473 + TILEPRO_OPC_MAXIB_U, TILEPRO_OPC_MAXIH, TILEPRO_OPC_MINIB_U, 1474 + TILEPRO_OPC_MINIH, 1469 1475 BITFIELD(20, 2) /* index 883 */, 1470 - CHILD(888), TILE_OPC_SEQIB, TILE_OPC_SEQIH, TILE_OPC_SEQI, 1476 + CHILD(888), TILEPRO_OPC_SEQIB, TILEPRO_OPC_SEQIH, TILEPRO_OPC_SEQI, 1471 1477 BITFIELD(6, 2) /* index 888 */, 1472 - TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(893), 1478 + TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(893), 1473 1479 BITFIELD(8, 2) /* index 893 */, 1474 - TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(898), 1480 + TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(898), 1475 1481 BITFIELD(10, 2) /* index 898 */, 1476 - TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_MOVEI, 1482 + TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_MOVEI, 1477 1483 BITFIELD(20, 2) /* index 903 */, 1478 - TILE_OPC_SLTIB, TILE_OPC_SLTIB_U, TILE_OPC_SLTIH, TILE_OPC_SLTIH_U, 1484 + TILEPRO_OPC_SLTIB, TILEPRO_OPC_SLTIB_U, TILEPRO_OPC_SLTIH, 1485 + TILEPRO_OPC_SLTIH_U, 1479 1486 BITFIELD(20, 2) /* index 908 */, 1480 - TILE_OPC_SLTI, TILE_OPC_SLTI_U, TILE_OPC_NONE, TILE_OPC_NONE, 1487 + TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1481 1488 BITFIELD(20, 2) /* index 913 */, 1482 - TILE_OPC_NONE, TILE_OPC_ADDIB_SN, TILE_OPC_ADDIH_SN, TILE_OPC_ADDI_SN, 1489 + TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB_SN, TILEPRO_OPC_ADDIH_SN, 1490 + TILEPRO_OPC_ADDI_SN, 1483 1491 BITFIELD(20, 2) /* index 918 */, 1484 - TILE_OPC_MAXIB_U_SN, TILE_OPC_MAXIH_SN, TILE_OPC_MINIB_U_SN, 1485 - TILE_OPC_MINIH_SN, 1492 + TILEPRO_OPC_MAXIB_U_SN, TILEPRO_OPC_MAXIH_SN, TILEPRO_OPC_MINIB_U_SN, 1493 + TILEPRO_OPC_MINIH_SN, 1486 1494 BITFIELD(20, 2) /* index 923 */, 1487 - CHILD(928), TILE_OPC_SEQIB_SN, TILE_OPC_SEQIH_SN, TILE_OPC_SEQI_SN, 1495 + CHILD(928), TILEPRO_OPC_SEQIB_SN, TILEPRO_OPC_SEQIH_SN, TILEPRO_OPC_SEQI_SN, 1488 1496 BITFIELD(6, 2) /* index 928 */, 1489 - TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, CHILD(933), 1497 + TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(933), 1490 1498 BITFIELD(8, 2) /* index 933 */, 1491 - TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, CHILD(938), 1499 + TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(938), 1492 1500 BITFIELD(10, 2) /* index 938 */, 1493 - TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_MOVEI_SN, 1501 + TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, 1502 + TILEPRO_OPC_MOVEI_SN, 1494 1503 BITFIELD(20, 2) /* index 943 */, 1495 - TILE_OPC_SLTIB_SN, TILE_OPC_SLTIB_U_SN, TILE_OPC_SLTIH_SN, 1496 - TILE_OPC_SLTIH_U_SN, 1504 + TILEPRO_OPC_SLTIB_SN, TILEPRO_OPC_SLTIB_U_SN, TILEPRO_OPC_SLTIH_SN, 1505 + TILEPRO_OPC_SLTIH_U_SN, 1497 1506 BITFIELD(20, 2) /* index 948 */, 1498 - TILE_OPC_SLTI_SN, TILE_OPC_SLTI_U_SN, TILE_OPC_NONE, TILE_OPC_NONE, 1507 + TILEPRO_OPC_SLTI_SN, TILEPRO_OPC_SLTI_U_SN, TILEPRO_OPC_NONE, 1508 + TILEPRO_OPC_NONE, 1499 1509 BITFIELD(20, 2) /* index 953 */, 1500 - TILE_OPC_NONE, CHILD(958), TILE_OPC_XORI, TILE_OPC_NONE, 1510 + TILEPRO_OPC_NONE, CHILD(958), TILEPRO_OPC_XORI, TILEPRO_OPC_NONE, 1501 1511 BITFIELD(0, 2) /* index 958 */, 1502 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(963), 1512 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(963), 1503 1513 BITFIELD(2, 2) /* index 963 */, 1504 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(968), 1514 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(968), 1505 1515 BITFIELD(4, 2) /* index 968 */, 1506 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(973), 1516 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(973), 1507 1517 BITFIELD(6, 2) /* index 973 */, 1508 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(978), 1518 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(978), 1509 1519 BITFIELD(8, 2) /* index 978 */, 1510 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(983), 1520 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(983), 1511 1521 BITFIELD(10, 2) /* index 983 */, 1512 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_INFO, 1522 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_INFO, 1513 1523 BITFIELD(20, 2) /* index 988 */, 1514 - TILE_OPC_NONE, TILE_OPC_ANDI_SN, TILE_OPC_XORI_SN, TILE_OPC_NONE, 1524 + TILEPRO_OPC_NONE, TILEPRO_OPC_ANDI_SN, TILEPRO_OPC_XORI_SN, 1525 + TILEPRO_OPC_NONE, 1515 1526 BITFIELD(17, 5) /* index 993 */, 1516 - TILE_OPC_NONE, TILE_OPC_RLI, TILE_OPC_SHLIB, TILE_OPC_SHLIH, TILE_OPC_SHLI, 1517 - TILE_OPC_SHRIB, TILE_OPC_SHRIH, TILE_OPC_SHRI, TILE_OPC_SRAIB, 1518 - TILE_OPC_SRAIH, TILE_OPC_SRAI, CHILD(1026), TILE_OPC_NONE, TILE_OPC_NONE, 1519 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1520 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1521 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1522 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1527 + TILEPRO_OPC_NONE, TILEPRO_OPC_RLI, TILEPRO_OPC_SHLIB, TILEPRO_OPC_SHLIH, 1528 + TILEPRO_OPC_SHLI, TILEPRO_OPC_SHRIB, TILEPRO_OPC_SHRIH, TILEPRO_OPC_SHRI, 1529 + TILEPRO_OPC_SRAIB, TILEPRO_OPC_SRAIH, TILEPRO_OPC_SRAI, CHILD(1026), 1530 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1531 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1532 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1533 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1534 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1523 1535 BITFIELD(12, 4) /* index 1026 */, 1524 - TILE_OPC_NONE, CHILD(1043), CHILD(1046), CHILD(1049), CHILD(1052), 1536 + TILEPRO_OPC_NONE, CHILD(1043), CHILD(1046), CHILD(1049), CHILD(1052), 1525 1537 CHILD(1055), CHILD(1058), CHILD(1061), CHILD(1064), CHILD(1067), 1526 - CHILD(1070), CHILD(1073), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1527 - TILE_OPC_NONE, 1538 + CHILD(1070), CHILD(1073), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1539 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1528 1540 BITFIELD(16, 1) /* index 1043 */, 1529 - TILE_OPC_BITX, TILE_OPC_NONE, 1541 + TILEPRO_OPC_BITX, TILEPRO_OPC_NONE, 1530 1542 BITFIELD(16, 1) /* index 1046 */, 1531 - TILE_OPC_BYTEX, TILE_OPC_NONE, 1543 + TILEPRO_OPC_BYTEX, TILEPRO_OPC_NONE, 1532 1544 BITFIELD(16, 1) /* index 1049 */, 1533 - TILE_OPC_CLZ, TILE_OPC_NONE, 1545 + TILEPRO_OPC_CLZ, TILEPRO_OPC_NONE, 1534 1546 BITFIELD(16, 1) /* index 1052 */, 1535 - TILE_OPC_CTZ, TILE_OPC_NONE, 1547 + TILEPRO_OPC_CTZ, TILEPRO_OPC_NONE, 1536 1548 BITFIELD(16, 1) /* index 1055 */, 1537 - TILE_OPC_FNOP, TILE_OPC_NONE, 1549 + TILEPRO_OPC_FNOP, TILEPRO_OPC_NONE, 1538 1550 BITFIELD(16, 1) /* index 1058 */, 1539 - TILE_OPC_NOP, TILE_OPC_NONE, 1551 + TILEPRO_OPC_NOP, TILEPRO_OPC_NONE, 1540 1552 BITFIELD(16, 1) /* index 1061 */, 1541 - TILE_OPC_PCNT, TILE_OPC_NONE, 1553 + TILEPRO_OPC_PCNT, TILEPRO_OPC_NONE, 1542 1554 BITFIELD(16, 1) /* index 1064 */, 1543 - TILE_OPC_TBLIDXB0, TILE_OPC_NONE, 1555 + TILEPRO_OPC_TBLIDXB0, TILEPRO_OPC_NONE, 1544 1556 BITFIELD(16, 1) /* index 1067 */, 1545 - TILE_OPC_TBLIDXB1, TILE_OPC_NONE, 1557 + TILEPRO_OPC_TBLIDXB1, TILEPRO_OPC_NONE, 1546 1558 BITFIELD(16, 1) /* index 1070 */, 1547 - TILE_OPC_TBLIDXB2, TILE_OPC_NONE, 1559 + TILEPRO_OPC_TBLIDXB2, TILEPRO_OPC_NONE, 1548 1560 BITFIELD(16, 1) /* index 1073 */, 1549 - TILE_OPC_TBLIDXB3, TILE_OPC_NONE, 1561 + TILEPRO_OPC_TBLIDXB3, TILEPRO_OPC_NONE, 1550 1562 BITFIELD(17, 5) /* index 1076 */, 1551 - TILE_OPC_NONE, TILE_OPC_RLI_SN, TILE_OPC_SHLIB_SN, TILE_OPC_SHLIH_SN, 1552 - TILE_OPC_SHLI_SN, TILE_OPC_SHRIB_SN, TILE_OPC_SHRIH_SN, TILE_OPC_SHRI_SN, 1553 - TILE_OPC_SRAIB_SN, TILE_OPC_SRAIH_SN, TILE_OPC_SRAI_SN, CHILD(1109), 1554 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1555 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1556 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1557 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1563 + TILEPRO_OPC_NONE, TILEPRO_OPC_RLI_SN, TILEPRO_OPC_SHLIB_SN, 1564 + TILEPRO_OPC_SHLIH_SN, TILEPRO_OPC_SHLI_SN, TILEPRO_OPC_SHRIB_SN, 1565 + TILEPRO_OPC_SHRIH_SN, TILEPRO_OPC_SHRI_SN, TILEPRO_OPC_SRAIB_SN, 1566 + TILEPRO_OPC_SRAIH_SN, TILEPRO_OPC_SRAI_SN, CHILD(1109), TILEPRO_OPC_NONE, 1567 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1568 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1569 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1570 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1571 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1558 1572 BITFIELD(12, 4) /* index 1109 */, 1559 - TILE_OPC_NONE, CHILD(1126), CHILD(1129), CHILD(1132), CHILD(1135), 1573 + TILEPRO_OPC_NONE, CHILD(1126), CHILD(1129), CHILD(1132), CHILD(1135), 1560 1574 CHILD(1055), CHILD(1058), CHILD(1138), CHILD(1141), CHILD(1144), 1561 - CHILD(1147), CHILD(1150), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1562 - TILE_OPC_NONE, 1575 + CHILD(1147), CHILD(1150), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1576 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1563 1577 BITFIELD(16, 1) /* index 1126 */, 1564 - TILE_OPC_BITX_SN, TILE_OPC_NONE, 1578 + TILEPRO_OPC_BITX_SN, TILEPRO_OPC_NONE, 1565 1579 BITFIELD(16, 1) /* index 1129 */, 1566 - TILE_OPC_BYTEX_SN, TILE_OPC_NONE, 1580 + TILEPRO_OPC_BYTEX_SN, TILEPRO_OPC_NONE, 1567 1581 BITFIELD(16, 1) /* index 1132 */, 1568 - TILE_OPC_CLZ_SN, TILE_OPC_NONE, 1582 + TILEPRO_OPC_CLZ_SN, TILEPRO_OPC_NONE, 1569 1583 BITFIELD(16, 1) /* index 1135 */, 1570 - TILE_OPC_CTZ_SN, TILE_OPC_NONE, 1584 + TILEPRO_OPC_CTZ_SN, TILEPRO_OPC_NONE, 1571 1585 BITFIELD(16, 1) /* index 1138 */, 1572 - TILE_OPC_PCNT_SN, TILE_OPC_NONE, 1586 + TILEPRO_OPC_PCNT_SN, TILEPRO_OPC_NONE, 1573 1587 BITFIELD(16, 1) /* index 1141 */, 1574 - TILE_OPC_TBLIDXB0_SN, TILE_OPC_NONE, 1588 + TILEPRO_OPC_TBLIDXB0_SN, TILEPRO_OPC_NONE, 1575 1589 BITFIELD(16, 1) /* index 1144 */, 1576 - TILE_OPC_TBLIDXB1_SN, TILE_OPC_NONE, 1590 + TILEPRO_OPC_TBLIDXB1_SN, TILEPRO_OPC_NONE, 1577 1591 BITFIELD(16, 1) /* index 1147 */, 1578 - TILE_OPC_TBLIDXB2_SN, TILE_OPC_NONE, 1592 + TILEPRO_OPC_TBLIDXB2_SN, TILEPRO_OPC_NONE, 1579 1593 BITFIELD(16, 1) /* index 1150 */, 1580 - TILE_OPC_TBLIDXB3_SN, TILE_OPC_NONE, 1594 + TILEPRO_OPC_TBLIDXB3_SN, TILEPRO_OPC_NONE, 1581 1595 }; 1582 1596 1583 1597 static const unsigned short decode_X1_fsm[1540] = 1584 1598 { 1585 1599 BITFIELD(54, 9) /* index 0 */, 1586 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1587 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1588 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1589 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1590 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1591 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1592 - TILE_OPC_NONE, TILE_OPC_NONE, CHILD(513), CHILD(561), CHILD(594), 1593 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1594 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1595 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(641), CHILD(689), 1596 - CHILD(722), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1597 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1598 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(766), 1600 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1601 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1602 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1603 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1604 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1605 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1606 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1607 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1608 + CHILD(513), CHILD(561), CHILD(594), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1609 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1610 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1611 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(641), 1612 + CHILD(689), CHILD(722), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1613 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1614 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1615 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(766), 1599 1616 CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), 1600 1617 CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), 1601 1618 CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), ··· 1655 1596 CHILD(826), CHILD(826), CHILD(826), CHILD(843), CHILD(843), CHILD(843), 1656 1597 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), 1657 1598 CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), 1658 - CHILD(843), CHILD(860), CHILD(899), CHILD(923), CHILD(932), TILE_OPC_NONE, 1659 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1660 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1661 - TILE_OPC_NONE, CHILD(941), CHILD(950), CHILD(974), CHILD(983), 1662 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1663 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1664 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1665 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1666 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1667 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1668 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1669 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, 1670 - TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, CHILD(992), 1671 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1672 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1673 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1674 - CHILD(1334), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1675 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1676 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1677 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1678 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1679 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1680 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1681 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1682 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1683 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_J, TILE_OPC_J, 1684 - TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, 1685 - TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, 1686 - TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, 1687 - TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, 1688 - TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, 1689 - TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, 1690 - TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, 1691 - TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, 1692 - TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, 1693 - TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, 1694 - TILE_OPC_J, TILE_OPC_J, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, 1695 - TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, 1696 - TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, 1697 - TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, 1698 - TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, 1699 - TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, 1700 - TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, 1701 - TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, 1702 - TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, 1703 - TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, 1704 - TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, 1705 - TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, 1706 - TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, 1707 - TILE_OPC_JAL, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1708 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1709 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1710 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1711 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1712 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1713 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1714 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1715 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1716 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1717 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1718 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1719 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1599 + CHILD(843), CHILD(860), CHILD(899), CHILD(923), CHILD(932), 1600 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1601 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1602 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1603 + CHILD(941), CHILD(950), CHILD(974), CHILD(983), TILEPRO_OPC_NONE, 1604 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1605 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1606 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_MM, 1607 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1608 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1609 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1610 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1611 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1612 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1613 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, 1614 + TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, CHILD(992), 1615 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1616 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1617 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1618 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(1334), 1619 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1620 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1621 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1622 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1623 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1624 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1625 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1626 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1627 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1628 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1629 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1630 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_J, 1631 + TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, 1632 + TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, 1633 + TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, 1634 + TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, 1635 + TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, 1636 + TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, 1637 + TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, 1638 + TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, 1639 + TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, 1640 + TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, 1641 + TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, 1642 + TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, 1643 + TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_JAL, 1644 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1645 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1646 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1647 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1648 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1649 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1650 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1651 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1652 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1653 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1654 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1655 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1656 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1657 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1658 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, 1659 + TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_NONE, 1660 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1661 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1662 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1663 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1664 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1665 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1666 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1667 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1668 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1669 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1670 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1671 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1672 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1673 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1674 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1675 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1720 1676 BITFIELD(49, 5) /* index 513 */, 1721 - TILE_OPC_NONE, TILE_OPC_ADDB, TILE_OPC_ADDH, TILE_OPC_ADD, TILE_OPC_AND, 1722 - TILE_OPC_INTHB, TILE_OPC_INTHH, TILE_OPC_INTLB, TILE_OPC_INTLH, 1723 - TILE_OPC_JALRP, TILE_OPC_JALR, TILE_OPC_JRP, TILE_OPC_JR, TILE_OPC_LNK, 1724 - TILE_OPC_MAXB_U, TILE_OPC_MAXH, TILE_OPC_MINB_U, TILE_OPC_MINH, 1725 - TILE_OPC_MNZB, TILE_OPC_MNZH, TILE_OPC_MNZ, TILE_OPC_MZB, TILE_OPC_MZH, 1726 - TILE_OPC_MZ, TILE_OPC_NOR, CHILD(546), TILE_OPC_PACKHB, TILE_OPC_PACKLB, 1727 - TILE_OPC_RL, TILE_OPC_S1A, TILE_OPC_S2A, TILE_OPC_S3A, 1677 + TILEPRO_OPC_NONE, TILEPRO_OPC_ADDB, TILEPRO_OPC_ADDH, TILEPRO_OPC_ADD, 1678 + TILEPRO_OPC_AND, TILEPRO_OPC_INTHB, TILEPRO_OPC_INTHH, TILEPRO_OPC_INTLB, 1679 + TILEPRO_OPC_INTLH, TILEPRO_OPC_JALRP, TILEPRO_OPC_JALR, TILEPRO_OPC_JRP, 1680 + TILEPRO_OPC_JR, TILEPRO_OPC_LNK, TILEPRO_OPC_MAXB_U, TILEPRO_OPC_MAXH, 1681 + TILEPRO_OPC_MINB_U, TILEPRO_OPC_MINH, TILEPRO_OPC_MNZB, TILEPRO_OPC_MNZH, 1682 + TILEPRO_OPC_MNZ, TILEPRO_OPC_MZB, TILEPRO_OPC_MZH, TILEPRO_OPC_MZ, 1683 + TILEPRO_OPC_NOR, CHILD(546), TILEPRO_OPC_PACKHB, TILEPRO_OPC_PACKLB, 1684 + TILEPRO_OPC_RL, TILEPRO_OPC_S1A, TILEPRO_OPC_S2A, TILEPRO_OPC_S3A, 1728 1685 BITFIELD(43, 2) /* index 546 */, 1729 - TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(551), 1686 + TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(551), 1730 1687 BITFIELD(45, 2) /* index 551 */, 1731 - TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(556), 1688 + TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(556), 1732 1689 BITFIELD(47, 2) /* index 556 */, 1733 - TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_MOVE, 1690 + TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_MOVE, 1734 1691 BITFIELD(49, 5) /* index 561 */, 1735 - TILE_OPC_SB, TILE_OPC_SEQB, TILE_OPC_SEQH, TILE_OPC_SEQ, TILE_OPC_SHLB, 1736 - TILE_OPC_SHLH, TILE_OPC_SHL, TILE_OPC_SHRB, TILE_OPC_SHRH, TILE_OPC_SHR, 1737 - TILE_OPC_SH, TILE_OPC_SLTB, TILE_OPC_SLTB_U, TILE_OPC_SLTEB, 1738 - TILE_OPC_SLTEB_U, TILE_OPC_SLTEH, TILE_OPC_SLTEH_U, TILE_OPC_SLTE, 1739 - TILE_OPC_SLTE_U, TILE_OPC_SLTH, TILE_OPC_SLTH_U, TILE_OPC_SLT, 1740 - TILE_OPC_SLT_U, TILE_OPC_SNEB, TILE_OPC_SNEH, TILE_OPC_SNE, TILE_OPC_SRAB, 1741 - TILE_OPC_SRAH, TILE_OPC_SRA, TILE_OPC_SUBB, TILE_OPC_SUBH, TILE_OPC_SUB, 1692 + TILEPRO_OPC_SB, TILEPRO_OPC_SEQB, TILEPRO_OPC_SEQH, TILEPRO_OPC_SEQ, 1693 + TILEPRO_OPC_SHLB, TILEPRO_OPC_SHLH, TILEPRO_OPC_SHL, TILEPRO_OPC_SHRB, 1694 + TILEPRO_OPC_SHRH, TILEPRO_OPC_SHR, TILEPRO_OPC_SH, TILEPRO_OPC_SLTB, 1695 + TILEPRO_OPC_SLTB_U, TILEPRO_OPC_SLTEB, TILEPRO_OPC_SLTEB_U, 1696 + TILEPRO_OPC_SLTEH, TILEPRO_OPC_SLTEH_U, TILEPRO_OPC_SLTE, 1697 + TILEPRO_OPC_SLTE_U, TILEPRO_OPC_SLTH, TILEPRO_OPC_SLTH_U, TILEPRO_OPC_SLT, 1698 + TILEPRO_OPC_SLT_U, TILEPRO_OPC_SNEB, TILEPRO_OPC_SNEH, TILEPRO_OPC_SNE, 1699 + TILEPRO_OPC_SRAB, TILEPRO_OPC_SRAH, TILEPRO_OPC_SRA, TILEPRO_OPC_SUBB, 1700 + TILEPRO_OPC_SUBH, TILEPRO_OPC_SUB, 1742 1701 BITFIELD(49, 4) /* index 594 */, 1743 1702 CHILD(611), CHILD(614), CHILD(617), CHILD(620), CHILD(623), CHILD(626), 1744 - CHILD(629), CHILD(632), CHILD(635), CHILD(638), TILE_OPC_NONE, 1745 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1703 + CHILD(629), CHILD(632), CHILD(635), CHILD(638), TILEPRO_OPC_NONE, 1704 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1705 + TILEPRO_OPC_NONE, 1746 1706 BITFIELD(53, 1) /* index 611 */, 1747 - TILE_OPC_SW, TILE_OPC_NONE, 1707 + TILEPRO_OPC_SW, TILEPRO_OPC_NONE, 1748 1708 BITFIELD(53, 1) /* index 614 */, 1749 - TILE_OPC_XOR, TILE_OPC_NONE, 1709 + TILEPRO_OPC_XOR, TILEPRO_OPC_NONE, 1750 1710 BITFIELD(53, 1) /* index 617 */, 1751 - TILE_OPC_ADDS, TILE_OPC_NONE, 1711 + TILEPRO_OPC_ADDS, TILEPRO_OPC_NONE, 1752 1712 BITFIELD(53, 1) /* index 620 */, 1753 - TILE_OPC_SUBS, TILE_OPC_NONE, 1713 + TILEPRO_OPC_SUBS, TILEPRO_OPC_NONE, 1754 1714 BITFIELD(53, 1) /* index 623 */, 1755 - TILE_OPC_ADDBS_U, TILE_OPC_NONE, 1715 + TILEPRO_OPC_ADDBS_U, TILEPRO_OPC_NONE, 1756 1716 BITFIELD(53, 1) /* index 626 */, 1757 - TILE_OPC_ADDHS, TILE_OPC_NONE, 1717 + TILEPRO_OPC_ADDHS, TILEPRO_OPC_NONE, 1758 1718 BITFIELD(53, 1) /* index 629 */, 1759 - TILE_OPC_SUBBS_U, TILE_OPC_NONE, 1719 + TILEPRO_OPC_SUBBS_U, TILEPRO_OPC_NONE, 1760 1720 BITFIELD(53, 1) /* index 632 */, 1761 - TILE_OPC_SUBHS, TILE_OPC_NONE, 1721 + TILEPRO_OPC_SUBHS, TILEPRO_OPC_NONE, 1762 1722 BITFIELD(53, 1) /* index 635 */, 1763 - TILE_OPC_PACKHS, TILE_OPC_NONE, 1723 + TILEPRO_OPC_PACKHS, TILEPRO_OPC_NONE, 1764 1724 BITFIELD(53, 1) /* index 638 */, 1765 - TILE_OPC_PACKBS_U, TILE_OPC_NONE, 1725 + TILEPRO_OPC_PACKBS_U, TILEPRO_OPC_NONE, 1766 1726 BITFIELD(49, 5) /* index 641 */, 1767 - TILE_OPC_NONE, TILE_OPC_ADDB_SN, TILE_OPC_ADDH_SN, TILE_OPC_ADD_SN, 1768 - TILE_OPC_AND_SN, TILE_OPC_INTHB_SN, TILE_OPC_INTHH_SN, TILE_OPC_INTLB_SN, 1769 - TILE_OPC_INTLH_SN, TILE_OPC_JALRP, TILE_OPC_JALR, TILE_OPC_JRP, TILE_OPC_JR, 1770 - TILE_OPC_LNK_SN, TILE_OPC_MAXB_U_SN, TILE_OPC_MAXH_SN, TILE_OPC_MINB_U_SN, 1771 - TILE_OPC_MINH_SN, TILE_OPC_MNZB_SN, TILE_OPC_MNZH_SN, TILE_OPC_MNZ_SN, 1772 - TILE_OPC_MZB_SN, TILE_OPC_MZH_SN, TILE_OPC_MZ_SN, TILE_OPC_NOR_SN, 1773 - CHILD(674), TILE_OPC_PACKHB_SN, TILE_OPC_PACKLB_SN, TILE_OPC_RL_SN, 1774 - TILE_OPC_S1A_SN, TILE_OPC_S2A_SN, TILE_OPC_S3A_SN, 1727 + TILEPRO_OPC_NONE, TILEPRO_OPC_ADDB_SN, TILEPRO_OPC_ADDH_SN, 1728 + TILEPRO_OPC_ADD_SN, TILEPRO_OPC_AND_SN, TILEPRO_OPC_INTHB_SN, 1729 + TILEPRO_OPC_INTHH_SN, TILEPRO_OPC_INTLB_SN, TILEPRO_OPC_INTLH_SN, 1730 + TILEPRO_OPC_JALRP, TILEPRO_OPC_JALR, TILEPRO_OPC_JRP, TILEPRO_OPC_JR, 1731 + TILEPRO_OPC_LNK_SN, TILEPRO_OPC_MAXB_U_SN, TILEPRO_OPC_MAXH_SN, 1732 + TILEPRO_OPC_MINB_U_SN, TILEPRO_OPC_MINH_SN, TILEPRO_OPC_MNZB_SN, 1733 + TILEPRO_OPC_MNZH_SN, TILEPRO_OPC_MNZ_SN, TILEPRO_OPC_MZB_SN, 1734 + TILEPRO_OPC_MZH_SN, TILEPRO_OPC_MZ_SN, TILEPRO_OPC_NOR_SN, CHILD(674), 1735 + TILEPRO_OPC_PACKHB_SN, TILEPRO_OPC_PACKLB_SN, TILEPRO_OPC_RL_SN, 1736 + TILEPRO_OPC_S1A_SN, TILEPRO_OPC_S2A_SN, TILEPRO_OPC_S3A_SN, 1775 1737 BITFIELD(43, 2) /* index 674 */, 1776 - TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, CHILD(679), 1738 + TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, CHILD(679), 1777 1739 BITFIELD(45, 2) /* index 679 */, 1778 - TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, CHILD(684), 1740 + TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, CHILD(684), 1779 1741 BITFIELD(47, 2) /* index 684 */, 1780 - TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_MOVE_SN, 1742 + TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, 1743 + TILEPRO_OPC_MOVE_SN, 1781 1744 BITFIELD(49, 5) /* index 689 */, 1782 - TILE_OPC_SB, TILE_OPC_SEQB_SN, TILE_OPC_SEQH_SN, TILE_OPC_SEQ_SN, 1783 - TILE_OPC_SHLB_SN, TILE_OPC_SHLH_SN, TILE_OPC_SHL_SN, TILE_OPC_SHRB_SN, 1784 - TILE_OPC_SHRH_SN, TILE_OPC_SHR_SN, TILE_OPC_SH, TILE_OPC_SLTB_SN, 1785 - TILE_OPC_SLTB_U_SN, TILE_OPC_SLTEB_SN, TILE_OPC_SLTEB_U_SN, 1786 - TILE_OPC_SLTEH_SN, TILE_OPC_SLTEH_U_SN, TILE_OPC_SLTE_SN, 1787 - TILE_OPC_SLTE_U_SN, TILE_OPC_SLTH_SN, TILE_OPC_SLTH_U_SN, TILE_OPC_SLT_SN, 1788 - TILE_OPC_SLT_U_SN, TILE_OPC_SNEB_SN, TILE_OPC_SNEH_SN, TILE_OPC_SNE_SN, 1789 - TILE_OPC_SRAB_SN, TILE_OPC_SRAH_SN, TILE_OPC_SRA_SN, TILE_OPC_SUBB_SN, 1790 - TILE_OPC_SUBH_SN, TILE_OPC_SUB_SN, 1745 + TILEPRO_OPC_SB, TILEPRO_OPC_SEQB_SN, TILEPRO_OPC_SEQH_SN, 1746 + TILEPRO_OPC_SEQ_SN, TILEPRO_OPC_SHLB_SN, TILEPRO_OPC_SHLH_SN, 1747 + TILEPRO_OPC_SHL_SN, TILEPRO_OPC_SHRB_SN, TILEPRO_OPC_SHRH_SN, 1748 + TILEPRO_OPC_SHR_SN, TILEPRO_OPC_SH, TILEPRO_OPC_SLTB_SN, 1749 + TILEPRO_OPC_SLTB_U_SN, TILEPRO_OPC_SLTEB_SN, TILEPRO_OPC_SLTEB_U_SN, 1750 + TILEPRO_OPC_SLTEH_SN, TILEPRO_OPC_SLTEH_U_SN, TILEPRO_OPC_SLTE_SN, 1751 + TILEPRO_OPC_SLTE_U_SN, TILEPRO_OPC_SLTH_SN, TILEPRO_OPC_SLTH_U_SN, 1752 + TILEPRO_OPC_SLT_SN, TILEPRO_OPC_SLT_U_SN, TILEPRO_OPC_SNEB_SN, 1753 + TILEPRO_OPC_SNEH_SN, TILEPRO_OPC_SNE_SN, TILEPRO_OPC_SRAB_SN, 1754 + TILEPRO_OPC_SRAH_SN, TILEPRO_OPC_SRA_SN, TILEPRO_OPC_SUBB_SN, 1755 + TILEPRO_OPC_SUBH_SN, TILEPRO_OPC_SUB_SN, 1791 1756 BITFIELD(49, 4) /* index 722 */, 1792 1757 CHILD(611), CHILD(739), CHILD(742), CHILD(745), CHILD(748), CHILD(751), 1793 - CHILD(754), CHILD(757), CHILD(760), CHILD(763), TILE_OPC_NONE, 1794 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1758 + CHILD(754), CHILD(757), CHILD(760), CHILD(763), TILEPRO_OPC_NONE, 1759 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1760 + TILEPRO_OPC_NONE, 1795 1761 BITFIELD(53, 1) /* index 739 */, 1796 - TILE_OPC_XOR_SN, TILE_OPC_NONE, 1762 + TILEPRO_OPC_XOR_SN, TILEPRO_OPC_NONE, 1797 1763 BITFIELD(53, 1) /* index 742 */, 1798 - TILE_OPC_ADDS_SN, TILE_OPC_NONE, 1764 + TILEPRO_OPC_ADDS_SN, TILEPRO_OPC_NONE, 1799 1765 BITFIELD(53, 1) /* index 745 */, 1800 - TILE_OPC_SUBS_SN, TILE_OPC_NONE, 1766 + TILEPRO_OPC_SUBS_SN, TILEPRO_OPC_NONE, 1801 1767 BITFIELD(53, 1) /* index 748 */, 1802 - TILE_OPC_ADDBS_U_SN, TILE_OPC_NONE, 1768 + TILEPRO_OPC_ADDBS_U_SN, TILEPRO_OPC_NONE, 1803 1769 BITFIELD(53, 1) /* index 751 */, 1804 - TILE_OPC_ADDHS_SN, TILE_OPC_NONE, 1770 + TILEPRO_OPC_ADDHS_SN, TILEPRO_OPC_NONE, 1805 1771 BITFIELD(53, 1) /* index 754 */, 1806 - TILE_OPC_SUBBS_U_SN, TILE_OPC_NONE, 1772 + TILEPRO_OPC_SUBBS_U_SN, TILEPRO_OPC_NONE, 1807 1773 BITFIELD(53, 1) /* index 757 */, 1808 - TILE_OPC_SUBHS_SN, TILE_OPC_NONE, 1774 + TILEPRO_OPC_SUBHS_SN, TILEPRO_OPC_NONE, 1809 1775 BITFIELD(53, 1) /* index 760 */, 1810 - TILE_OPC_PACKHS_SN, TILE_OPC_NONE, 1776 + TILEPRO_OPC_PACKHS_SN, TILEPRO_OPC_NONE, 1811 1777 BITFIELD(53, 1) /* index 763 */, 1812 - TILE_OPC_PACKBS_U_SN, TILE_OPC_NONE, 1778 + TILEPRO_OPC_PACKBS_U_SN, TILEPRO_OPC_NONE, 1813 1779 BITFIELD(37, 2) /* index 766 */, 1814 - TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, CHILD(771), 1780 + TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, 1781 + CHILD(771), 1815 1782 BITFIELD(39, 2) /* index 771 */, 1816 - TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, CHILD(776), 1783 + TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, 1784 + CHILD(776), 1817 1785 BITFIELD(41, 2) /* index 776 */, 1818 - TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_MOVELI_SN, 1786 + TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, 1787 + TILEPRO_OPC_MOVELI_SN, 1819 1788 BITFIELD(37, 2) /* index 781 */, 1820 - TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, CHILD(786), 1789 + TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, CHILD(786), 1821 1790 BITFIELD(39, 2) /* index 786 */, 1822 - TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, CHILD(791), 1791 + TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, CHILD(791), 1823 1792 BITFIELD(41, 2) /* index 791 */, 1824 - TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_MOVELI, 1793 + TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_MOVELI, 1825 1794 BITFIELD(31, 2) /* index 796 */, 1826 - TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(801), 1795 + TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(801), 1827 1796 BITFIELD(33, 2) /* index 801 */, 1828 - TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(806), 1797 + TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(806), 1829 1798 BITFIELD(35, 2) /* index 806 */, 1830 - TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(811), 1799 + TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(811), 1831 1800 BITFIELD(37, 2) /* index 811 */, 1832 - TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(816), 1801 + TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(816), 1833 1802 BITFIELD(39, 2) /* index 816 */, 1834 - TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(821), 1803 + TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(821), 1835 1804 BITFIELD(41, 2) /* index 821 */, 1836 - TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_INFOL, 1805 + TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_INFOL, 1837 1806 BITFIELD(31, 4) /* index 826 */, 1838 - TILE_OPC_BZ, TILE_OPC_BZT, TILE_OPC_BNZ, TILE_OPC_BNZT, TILE_OPC_BGZ, 1839 - TILE_OPC_BGZT, TILE_OPC_BGEZ, TILE_OPC_BGEZT, TILE_OPC_BLZ, TILE_OPC_BLZT, 1840 - TILE_OPC_BLEZ, TILE_OPC_BLEZT, TILE_OPC_BBS, TILE_OPC_BBST, TILE_OPC_BBNS, 1841 - TILE_OPC_BBNST, 1807 + TILEPRO_OPC_BZ, TILEPRO_OPC_BZT, TILEPRO_OPC_BNZ, TILEPRO_OPC_BNZT, 1808 + TILEPRO_OPC_BGZ, TILEPRO_OPC_BGZT, TILEPRO_OPC_BGEZ, TILEPRO_OPC_BGEZT, 1809 + TILEPRO_OPC_BLZ, TILEPRO_OPC_BLZT, TILEPRO_OPC_BLEZ, TILEPRO_OPC_BLEZT, 1810 + TILEPRO_OPC_BBS, TILEPRO_OPC_BBST, TILEPRO_OPC_BBNS, TILEPRO_OPC_BBNST, 1842 1811 BITFIELD(31, 4) /* index 843 */, 1843 - TILE_OPC_BZ_SN, TILE_OPC_BZT_SN, TILE_OPC_BNZ_SN, TILE_OPC_BNZT_SN, 1844 - TILE_OPC_BGZ_SN, TILE_OPC_BGZT_SN, TILE_OPC_BGEZ_SN, TILE_OPC_BGEZT_SN, 1845 - TILE_OPC_BLZ_SN, TILE_OPC_BLZT_SN, TILE_OPC_BLEZ_SN, TILE_OPC_BLEZT_SN, 1846 - TILE_OPC_BBS_SN, TILE_OPC_BBST_SN, TILE_OPC_BBNS_SN, TILE_OPC_BBNST_SN, 1812 + TILEPRO_OPC_BZ_SN, TILEPRO_OPC_BZT_SN, TILEPRO_OPC_BNZ_SN, 1813 + TILEPRO_OPC_BNZT_SN, TILEPRO_OPC_BGZ_SN, TILEPRO_OPC_BGZT_SN, 1814 + TILEPRO_OPC_BGEZ_SN, TILEPRO_OPC_BGEZT_SN, TILEPRO_OPC_BLZ_SN, 1815 + TILEPRO_OPC_BLZT_SN, TILEPRO_OPC_BLEZ_SN, TILEPRO_OPC_BLEZT_SN, 1816 + TILEPRO_OPC_BBS_SN, TILEPRO_OPC_BBST_SN, TILEPRO_OPC_BBNS_SN, 1817 + TILEPRO_OPC_BBNST_SN, 1847 1818 BITFIELD(51, 3) /* index 860 */, 1848 - TILE_OPC_NONE, TILE_OPC_ADDIB, TILE_OPC_ADDIH, TILE_OPC_ADDI, CHILD(869), 1849 - TILE_OPC_MAXIB_U, TILE_OPC_MAXIH, TILE_OPC_MFSPR, 1819 + TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB, TILEPRO_OPC_ADDIH, TILEPRO_OPC_ADDI, 1820 + CHILD(869), TILEPRO_OPC_MAXIB_U, TILEPRO_OPC_MAXIH, TILEPRO_OPC_MFSPR, 1850 1821 BITFIELD(31, 2) /* index 869 */, 1851 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(874), 1822 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(874), 1852 1823 BITFIELD(33, 2) /* index 874 */, 1853 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(879), 1824 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(879), 1854 1825 BITFIELD(35, 2) /* index 879 */, 1855 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(884), 1826 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(884), 1856 1827 BITFIELD(37, 2) /* index 884 */, 1857 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(889), 1828 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(889), 1858 1829 BITFIELD(39, 2) /* index 889 */, 1859 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(894), 1830 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(894), 1860 1831 BITFIELD(41, 2) /* index 894 */, 1861 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_INFO, 1832 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_INFO, 1862 1833 BITFIELD(51, 3) /* index 899 */, 1863 - TILE_OPC_MINIB_U, TILE_OPC_MINIH, TILE_OPC_MTSPR, CHILD(908), 1864 - TILE_OPC_SEQIB, TILE_OPC_SEQIH, TILE_OPC_SEQI, TILE_OPC_SLTIB, 1834 + TILEPRO_OPC_MINIB_U, TILEPRO_OPC_MINIH, TILEPRO_OPC_MTSPR, CHILD(908), 1835 + TILEPRO_OPC_SEQIB, TILEPRO_OPC_SEQIH, TILEPRO_OPC_SEQI, TILEPRO_OPC_SLTIB, 1865 1836 BITFIELD(37, 2) /* index 908 */, 1866 - TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(913), 1837 + TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(913), 1867 1838 BITFIELD(39, 2) /* index 913 */, 1868 - TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(918), 1839 + TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(918), 1869 1840 BITFIELD(41, 2) /* index 918 */, 1870 - TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_MOVEI, 1841 + TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_MOVEI, 1871 1842 BITFIELD(51, 3) /* index 923 */, 1872 - TILE_OPC_SLTIB_U, TILE_OPC_SLTIH, TILE_OPC_SLTIH_U, TILE_OPC_SLTI, 1873 - TILE_OPC_SLTI_U, TILE_OPC_XORI, TILE_OPC_LBADD, TILE_OPC_LBADD_U, 1843 + TILEPRO_OPC_SLTIB_U, TILEPRO_OPC_SLTIH, TILEPRO_OPC_SLTIH_U, 1844 + TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U, TILEPRO_OPC_XORI, TILEPRO_OPC_LBADD, 1845 + TILEPRO_OPC_LBADD_U, 1874 1846 BITFIELD(51, 3) /* index 932 */, 1875 - TILE_OPC_LHADD, TILE_OPC_LHADD_U, TILE_OPC_LWADD, TILE_OPC_LWADD_NA, 1876 - TILE_OPC_SBADD, TILE_OPC_SHADD, TILE_OPC_SWADD, TILE_OPC_NONE, 1847 + TILEPRO_OPC_LHADD, TILEPRO_OPC_LHADD_U, TILEPRO_OPC_LWADD, 1848 + TILEPRO_OPC_LWADD_NA, TILEPRO_OPC_SBADD, TILEPRO_OPC_SHADD, 1849 + TILEPRO_OPC_SWADD, TILEPRO_OPC_NONE, 1877 1850 BITFIELD(51, 3) /* index 941 */, 1878 - TILE_OPC_NONE, TILE_OPC_ADDIB_SN, TILE_OPC_ADDIH_SN, TILE_OPC_ADDI_SN, 1879 - TILE_OPC_ANDI_SN, TILE_OPC_MAXIB_U_SN, TILE_OPC_MAXIH_SN, TILE_OPC_MFSPR, 1851 + TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB_SN, TILEPRO_OPC_ADDIH_SN, 1852 + TILEPRO_OPC_ADDI_SN, TILEPRO_OPC_ANDI_SN, TILEPRO_OPC_MAXIB_U_SN, 1853 + TILEPRO_OPC_MAXIH_SN, TILEPRO_OPC_MFSPR, 1880 1854 BITFIELD(51, 3) /* index 950 */, 1881 - TILE_OPC_MINIB_U_SN, TILE_OPC_MINIH_SN, TILE_OPC_MTSPR, CHILD(959), 1882 - TILE_OPC_SEQIB_SN, TILE_OPC_SEQIH_SN, TILE_OPC_SEQI_SN, TILE_OPC_SLTIB_SN, 1855 + TILEPRO_OPC_MINIB_U_SN, TILEPRO_OPC_MINIH_SN, TILEPRO_OPC_MTSPR, CHILD(959), 1856 + TILEPRO_OPC_SEQIB_SN, TILEPRO_OPC_SEQIH_SN, TILEPRO_OPC_SEQI_SN, 1857 + TILEPRO_OPC_SLTIB_SN, 1883 1858 BITFIELD(37, 2) /* index 959 */, 1884 - TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, CHILD(964), 1859 + TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(964), 1885 1860 BITFIELD(39, 2) /* index 964 */, 1886 - TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, CHILD(969), 1861 + TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(969), 1887 1862 BITFIELD(41, 2) /* index 969 */, 1888 - TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_MOVEI_SN, 1863 + TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, 1864 + TILEPRO_OPC_MOVEI_SN, 1889 1865 BITFIELD(51, 3) /* index 974 */, 1890 - TILE_OPC_SLTIB_U_SN, TILE_OPC_SLTIH_SN, TILE_OPC_SLTIH_U_SN, 1891 - TILE_OPC_SLTI_SN, TILE_OPC_SLTI_U_SN, TILE_OPC_XORI_SN, TILE_OPC_LBADD_SN, 1892 - TILE_OPC_LBADD_U_SN, 1866 + TILEPRO_OPC_SLTIB_U_SN, TILEPRO_OPC_SLTIH_SN, TILEPRO_OPC_SLTIH_U_SN, 1867 + TILEPRO_OPC_SLTI_SN, TILEPRO_OPC_SLTI_U_SN, TILEPRO_OPC_XORI_SN, 1868 + TILEPRO_OPC_LBADD_SN, TILEPRO_OPC_LBADD_U_SN, 1893 1869 BITFIELD(51, 3) /* index 983 */, 1894 - TILE_OPC_LHADD_SN, TILE_OPC_LHADD_U_SN, TILE_OPC_LWADD_SN, 1895 - TILE_OPC_LWADD_NA_SN, TILE_OPC_SBADD, TILE_OPC_SHADD, TILE_OPC_SWADD, 1896 - TILE_OPC_NONE, 1870 + TILEPRO_OPC_LHADD_SN, TILEPRO_OPC_LHADD_U_SN, TILEPRO_OPC_LWADD_SN, 1871 + TILEPRO_OPC_LWADD_NA_SN, TILEPRO_OPC_SBADD, TILEPRO_OPC_SHADD, 1872 + TILEPRO_OPC_SWADD, TILEPRO_OPC_NONE, 1897 1873 BITFIELD(46, 7) /* index 992 */, 1898 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(1121), 1899 - CHILD(1121), CHILD(1121), CHILD(1121), CHILD(1124), CHILD(1124), 1900 - CHILD(1124), CHILD(1124), CHILD(1127), CHILD(1127), CHILD(1127), 1901 - CHILD(1127), CHILD(1130), CHILD(1130), CHILD(1130), CHILD(1130), 1902 - CHILD(1133), CHILD(1133), CHILD(1133), CHILD(1133), CHILD(1136), 1903 - CHILD(1136), CHILD(1136), CHILD(1136), CHILD(1139), CHILD(1139), 1904 - CHILD(1139), CHILD(1139), CHILD(1142), CHILD(1142), CHILD(1142), 1905 - CHILD(1142), CHILD(1145), CHILD(1145), CHILD(1145), CHILD(1145), 1906 - CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1151), 1907 - CHILD(1242), CHILD(1290), CHILD(1323), TILE_OPC_NONE, TILE_OPC_NONE, 1908 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1909 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1910 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1911 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1912 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1913 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1914 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1915 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1916 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1917 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1918 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1919 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1920 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1921 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1922 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1923 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1874 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1875 + CHILD(1121), CHILD(1121), CHILD(1121), CHILD(1121), CHILD(1124), 1876 + CHILD(1124), CHILD(1124), CHILD(1124), CHILD(1127), CHILD(1127), 1877 + CHILD(1127), CHILD(1127), CHILD(1130), CHILD(1130), CHILD(1130), 1878 + CHILD(1130), CHILD(1133), CHILD(1133), CHILD(1133), CHILD(1133), 1879 + CHILD(1136), CHILD(1136), CHILD(1136), CHILD(1136), CHILD(1139), 1880 + CHILD(1139), CHILD(1139), CHILD(1139), CHILD(1142), CHILD(1142), 1881 + CHILD(1142), CHILD(1142), CHILD(1145), CHILD(1145), CHILD(1145), 1882 + CHILD(1145), CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1148), 1883 + CHILD(1151), CHILD(1242), CHILD(1290), CHILD(1323), TILEPRO_OPC_NONE, 1884 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1885 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1886 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1887 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1888 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1889 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1890 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1891 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1892 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1893 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1894 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1895 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1896 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1897 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1898 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1899 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1900 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1901 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1902 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1903 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 1924 1904 BITFIELD(53, 1) /* index 1121 */, 1925 - TILE_OPC_RLI, TILE_OPC_NONE, 1905 + TILEPRO_OPC_RLI, TILEPRO_OPC_NONE, 1926 1906 BITFIELD(53, 1) /* index 1124 */, 1927 - TILE_OPC_SHLIB, TILE_OPC_NONE, 1907 + TILEPRO_OPC_SHLIB, TILEPRO_OPC_NONE, 1928 1908 BITFIELD(53, 1) /* index 1127 */, 1929 - TILE_OPC_SHLIH, TILE_OPC_NONE, 1909 + TILEPRO_OPC_SHLIH, TILEPRO_OPC_NONE, 1930 1910 BITFIELD(53, 1) /* index 1130 */, 1931 - TILE_OPC_SHLI, TILE_OPC_NONE, 1911 + TILEPRO_OPC_SHLI, TILEPRO_OPC_NONE, 1932 1912 BITFIELD(53, 1) /* index 1133 */, 1933 - TILE_OPC_SHRIB, TILE_OPC_NONE, 1913 + TILEPRO_OPC_SHRIB, TILEPRO_OPC_NONE, 1934 1914 BITFIELD(53, 1) /* index 1136 */, 1935 - TILE_OPC_SHRIH, TILE_OPC_NONE, 1915 + TILEPRO_OPC_SHRIH, TILEPRO_OPC_NONE, 1936 1916 BITFIELD(53, 1) /* index 1139 */, 1937 - TILE_OPC_SHRI, TILE_OPC_NONE, 1917 + TILEPRO_OPC_SHRI, TILEPRO_OPC_NONE, 1938 1918 BITFIELD(53, 1) /* index 1142 */, 1939 - TILE_OPC_SRAIB, TILE_OPC_NONE, 1919 + TILEPRO_OPC_SRAIB, TILEPRO_OPC_NONE, 1940 1920 BITFIELD(53, 1) /* index 1145 */, 1941 - TILE_OPC_SRAIH, TILE_OPC_NONE, 1921 + TILEPRO_OPC_SRAIH, TILEPRO_OPC_NONE, 1942 1922 BITFIELD(53, 1) /* index 1148 */, 1943 - TILE_OPC_SRAI, TILE_OPC_NONE, 1923 + TILEPRO_OPC_SRAI, TILEPRO_OPC_NONE, 1944 1924 BITFIELD(43, 3) /* index 1151 */, 1945 - TILE_OPC_NONE, CHILD(1160), CHILD(1163), CHILD(1166), CHILD(1169), 1925 + TILEPRO_OPC_NONE, CHILD(1160), CHILD(1163), CHILD(1166), CHILD(1169), 1946 1926 CHILD(1172), CHILD(1175), CHILD(1178), 1947 1927 BITFIELD(53, 1) /* index 1160 */, 1948 - TILE_OPC_DRAIN, TILE_OPC_NONE, 1928 + TILEPRO_OPC_DRAIN, TILEPRO_OPC_NONE, 1949 1929 BITFIELD(53, 1) /* index 1163 */, 1950 - TILE_OPC_DTLBPR, TILE_OPC_NONE, 1930 + TILEPRO_OPC_DTLBPR, TILEPRO_OPC_NONE, 1951 1931 BITFIELD(53, 1) /* index 1166 */, 1952 - TILE_OPC_FINV, TILE_OPC_NONE, 1932 + TILEPRO_OPC_FINV, TILEPRO_OPC_NONE, 1953 1933 BITFIELD(53, 1) /* index 1169 */, 1954 - TILE_OPC_FLUSH, TILE_OPC_NONE, 1934 + TILEPRO_OPC_FLUSH, TILEPRO_OPC_NONE, 1955 1935 BITFIELD(53, 1) /* index 1172 */, 1956 - TILE_OPC_FNOP, TILE_OPC_NONE, 1936 + TILEPRO_OPC_FNOP, TILEPRO_OPC_NONE, 1957 1937 BITFIELD(53, 1) /* index 1175 */, 1958 - TILE_OPC_ICOH, TILE_OPC_NONE, 1938 + TILEPRO_OPC_ICOH, TILEPRO_OPC_NONE, 1959 1939 BITFIELD(31, 2) /* index 1178 */, 1960 1940 CHILD(1183), CHILD(1211), CHILD(1239), CHILD(1239), 1961 1941 BITFIELD(53, 1) /* index 1183 */, 1962 - CHILD(1186), TILE_OPC_NONE, 1942 + CHILD(1186), TILEPRO_OPC_NONE, 1963 1943 BITFIELD(33, 2) /* index 1186 */, 1964 - TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_ILL, CHILD(1191), 1944 + TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, CHILD(1191), 1965 1945 BITFIELD(35, 2) /* index 1191 */, 1966 - TILE_OPC_ILL, CHILD(1196), TILE_OPC_ILL, TILE_OPC_ILL, 1946 + TILEPRO_OPC_ILL, CHILD(1196), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, 1967 1947 BITFIELD(37, 2) /* index 1196 */, 1968 - TILE_OPC_ILL, CHILD(1201), TILE_OPC_ILL, TILE_OPC_ILL, 1948 + TILEPRO_OPC_ILL, CHILD(1201), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, 1969 1949 BITFIELD(39, 2) /* index 1201 */, 1970 - TILE_OPC_ILL, CHILD(1206), TILE_OPC_ILL, TILE_OPC_ILL, 1950 + TILEPRO_OPC_ILL, CHILD(1206), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, 1971 1951 BITFIELD(41, 2) /* index 1206 */, 1972 - TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_BPT, TILE_OPC_ILL, 1952 + TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_BPT, TILEPRO_OPC_ILL, 1973 1953 BITFIELD(53, 1) /* index 1211 */, 1974 - CHILD(1214), TILE_OPC_NONE, 1954 + CHILD(1214), TILEPRO_OPC_NONE, 1975 1955 BITFIELD(33, 2) /* index 1214 */, 1976 - TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_ILL, CHILD(1219), 1956 + TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, CHILD(1219), 1977 1957 BITFIELD(35, 2) /* index 1219 */, 1978 - TILE_OPC_ILL, CHILD(1224), TILE_OPC_ILL, TILE_OPC_ILL, 1958 + TILEPRO_OPC_ILL, CHILD(1224), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, 1979 1959 BITFIELD(37, 2) /* index 1224 */, 1980 - TILE_OPC_ILL, CHILD(1229), TILE_OPC_ILL, TILE_OPC_ILL, 1960 + TILEPRO_OPC_ILL, CHILD(1229), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, 1981 1961 BITFIELD(39, 2) /* index 1229 */, 1982 - TILE_OPC_ILL, CHILD(1234), TILE_OPC_ILL, TILE_OPC_ILL, 1962 + TILEPRO_OPC_ILL, CHILD(1234), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, 1983 1963 BITFIELD(41, 2) /* index 1234 */, 1984 - TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_RAISE, TILE_OPC_ILL, 1964 + TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_RAISE, TILEPRO_OPC_ILL, 1985 1965 BITFIELD(53, 1) /* index 1239 */, 1986 - TILE_OPC_ILL, TILE_OPC_NONE, 1966 + TILEPRO_OPC_ILL, TILEPRO_OPC_NONE, 1987 1967 BITFIELD(43, 3) /* index 1242 */, 1988 1968 CHILD(1251), CHILD(1254), CHILD(1257), CHILD(1275), CHILD(1278), 1989 1969 CHILD(1281), CHILD(1284), CHILD(1287), 1990 1970 BITFIELD(53, 1) /* index 1251 */, 1991 - TILE_OPC_INV, TILE_OPC_NONE, 1971 + TILEPRO_OPC_INV, TILEPRO_OPC_NONE, 1992 1972 BITFIELD(53, 1) /* index 1254 */, 1993 - TILE_OPC_IRET, TILE_OPC_NONE, 1973 + TILEPRO_OPC_IRET, TILEPRO_OPC_NONE, 1994 1974 BITFIELD(53, 1) /* index 1257 */, 1995 - CHILD(1260), TILE_OPC_NONE, 1975 + CHILD(1260), TILEPRO_OPC_NONE, 1996 1976 BITFIELD(31, 2) /* index 1260 */, 1997 - TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(1265), 1977 + TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(1265), 1998 1978 BITFIELD(33, 2) /* index 1265 */, 1999 - TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(1270), 1979 + TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(1270), 2000 1980 BITFIELD(35, 2) /* index 1270 */, 2001 - TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_PREFETCH, 1981 + TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_PREFETCH, 2002 1982 BITFIELD(53, 1) /* index 1275 */, 2003 - TILE_OPC_LB_U, TILE_OPC_NONE, 1983 + TILEPRO_OPC_LB_U, TILEPRO_OPC_NONE, 2004 1984 BITFIELD(53, 1) /* index 1278 */, 2005 - TILE_OPC_LH, TILE_OPC_NONE, 1985 + TILEPRO_OPC_LH, TILEPRO_OPC_NONE, 2006 1986 BITFIELD(53, 1) /* index 1281 */, 2007 - TILE_OPC_LH_U, TILE_OPC_NONE, 1987 + TILEPRO_OPC_LH_U, TILEPRO_OPC_NONE, 2008 1988 BITFIELD(53, 1) /* index 1284 */, 2009 - TILE_OPC_LW, TILE_OPC_NONE, 1989 + TILEPRO_OPC_LW, TILEPRO_OPC_NONE, 2010 1990 BITFIELD(53, 1) /* index 1287 */, 2011 - TILE_OPC_MF, TILE_OPC_NONE, 1991 + TILEPRO_OPC_MF, TILEPRO_OPC_NONE, 2012 1992 BITFIELD(43, 3) /* index 1290 */, 2013 1993 CHILD(1299), CHILD(1302), CHILD(1305), CHILD(1308), CHILD(1311), 2014 1994 CHILD(1314), CHILD(1317), CHILD(1320), 2015 1995 BITFIELD(53, 1) /* index 1299 */, 2016 - TILE_OPC_NAP, TILE_OPC_NONE, 1996 + TILEPRO_OPC_NAP, TILEPRO_OPC_NONE, 2017 1997 BITFIELD(53, 1) /* index 1302 */, 2018 - TILE_OPC_NOP, TILE_OPC_NONE, 1998 + TILEPRO_OPC_NOP, TILEPRO_OPC_NONE, 2019 1999 BITFIELD(53, 1) /* index 1305 */, 2020 - TILE_OPC_SWINT0, TILE_OPC_NONE, 2000 + TILEPRO_OPC_SWINT0, TILEPRO_OPC_NONE, 2021 2001 BITFIELD(53, 1) /* index 1308 */, 2022 - TILE_OPC_SWINT1, TILE_OPC_NONE, 2002 + TILEPRO_OPC_SWINT1, TILEPRO_OPC_NONE, 2023 2003 BITFIELD(53, 1) /* index 1311 */, 2024 - TILE_OPC_SWINT2, TILE_OPC_NONE, 2004 + TILEPRO_OPC_SWINT2, TILEPRO_OPC_NONE, 2025 2005 BITFIELD(53, 1) /* index 1314 */, 2026 - TILE_OPC_SWINT3, TILE_OPC_NONE, 2006 + TILEPRO_OPC_SWINT3, TILEPRO_OPC_NONE, 2027 2007 BITFIELD(53, 1) /* index 1317 */, 2028 - TILE_OPC_TNS, TILE_OPC_NONE, 2008 + TILEPRO_OPC_TNS, TILEPRO_OPC_NONE, 2029 2009 BITFIELD(53, 1) /* index 1320 */, 2030 - TILE_OPC_WH64, TILE_OPC_NONE, 2010 + TILEPRO_OPC_WH64, TILEPRO_OPC_NONE, 2031 2011 BITFIELD(43, 2) /* index 1323 */, 2032 - CHILD(1328), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2012 + CHILD(1328), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2033 2013 BITFIELD(45, 1) /* index 1328 */, 2034 - CHILD(1331), TILE_OPC_NONE, 2014 + CHILD(1331), TILEPRO_OPC_NONE, 2035 2015 BITFIELD(53, 1) /* index 1331 */, 2036 - TILE_OPC_LW_NA, TILE_OPC_NONE, 2016 + TILEPRO_OPC_LW_NA, TILEPRO_OPC_NONE, 2037 2017 BITFIELD(46, 7) /* index 1334 */, 2038 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(1463), 2039 - CHILD(1463), CHILD(1463), CHILD(1463), CHILD(1466), CHILD(1466), 2040 - CHILD(1466), CHILD(1466), CHILD(1469), CHILD(1469), CHILD(1469), 2041 - CHILD(1469), CHILD(1472), CHILD(1472), CHILD(1472), CHILD(1472), 2042 - CHILD(1475), CHILD(1475), CHILD(1475), CHILD(1475), CHILD(1478), 2043 - CHILD(1478), CHILD(1478), CHILD(1478), CHILD(1481), CHILD(1481), 2044 - CHILD(1481), CHILD(1481), CHILD(1484), CHILD(1484), CHILD(1484), 2045 - CHILD(1484), CHILD(1487), CHILD(1487), CHILD(1487), CHILD(1487), 2046 - CHILD(1490), CHILD(1490), CHILD(1490), CHILD(1490), CHILD(1151), 2047 - CHILD(1493), CHILD(1517), CHILD(1529), TILE_OPC_NONE, TILE_OPC_NONE, 2048 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2049 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2050 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2051 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2052 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2053 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2054 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2055 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2056 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2057 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2058 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2059 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2060 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2061 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2062 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2063 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2018 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2019 + CHILD(1463), CHILD(1463), CHILD(1463), CHILD(1463), CHILD(1466), 2020 + CHILD(1466), CHILD(1466), CHILD(1466), CHILD(1469), CHILD(1469), 2021 + CHILD(1469), CHILD(1469), CHILD(1472), CHILD(1472), CHILD(1472), 2022 + CHILD(1472), CHILD(1475), CHILD(1475), CHILD(1475), CHILD(1475), 2023 + CHILD(1478), CHILD(1478), CHILD(1478), CHILD(1478), CHILD(1481), 2024 + CHILD(1481), CHILD(1481), CHILD(1481), CHILD(1484), CHILD(1484), 2025 + CHILD(1484), CHILD(1484), CHILD(1487), CHILD(1487), CHILD(1487), 2026 + CHILD(1487), CHILD(1490), CHILD(1490), CHILD(1490), CHILD(1490), 2027 + CHILD(1151), CHILD(1493), CHILD(1517), CHILD(1529), TILEPRO_OPC_NONE, 2028 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2029 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2030 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2031 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2032 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2033 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2034 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2035 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2036 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2037 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2038 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2039 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2040 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2041 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2042 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2043 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2044 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2045 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2046 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2047 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2064 2048 BITFIELD(53, 1) /* index 1463 */, 2065 - TILE_OPC_RLI_SN, TILE_OPC_NONE, 2049 + TILEPRO_OPC_RLI_SN, TILEPRO_OPC_NONE, 2066 2050 BITFIELD(53, 1) /* index 1466 */, 2067 - TILE_OPC_SHLIB_SN, TILE_OPC_NONE, 2051 + TILEPRO_OPC_SHLIB_SN, TILEPRO_OPC_NONE, 2068 2052 BITFIELD(53, 1) /* index 1469 */, 2069 - TILE_OPC_SHLIH_SN, TILE_OPC_NONE, 2053 + TILEPRO_OPC_SHLIH_SN, TILEPRO_OPC_NONE, 2070 2054 BITFIELD(53, 1) /* index 1472 */, 2071 - TILE_OPC_SHLI_SN, TILE_OPC_NONE, 2055 + TILEPRO_OPC_SHLI_SN, TILEPRO_OPC_NONE, 2072 2056 BITFIELD(53, 1) /* index 1475 */, 2073 - TILE_OPC_SHRIB_SN, TILE_OPC_NONE, 2057 + TILEPRO_OPC_SHRIB_SN, TILEPRO_OPC_NONE, 2074 2058 BITFIELD(53, 1) /* index 1478 */, 2075 - TILE_OPC_SHRIH_SN, TILE_OPC_NONE, 2059 + TILEPRO_OPC_SHRIH_SN, TILEPRO_OPC_NONE, 2076 2060 BITFIELD(53, 1) /* index 1481 */, 2077 - TILE_OPC_SHRI_SN, TILE_OPC_NONE, 2061 + TILEPRO_OPC_SHRI_SN, TILEPRO_OPC_NONE, 2078 2062 BITFIELD(53, 1) /* index 1484 */, 2079 - TILE_OPC_SRAIB_SN, TILE_OPC_NONE, 2063 + TILEPRO_OPC_SRAIB_SN, TILEPRO_OPC_NONE, 2080 2064 BITFIELD(53, 1) /* index 1487 */, 2081 - TILE_OPC_SRAIH_SN, TILE_OPC_NONE, 2065 + TILEPRO_OPC_SRAIH_SN, TILEPRO_OPC_NONE, 2082 2066 BITFIELD(53, 1) /* index 1490 */, 2083 - TILE_OPC_SRAI_SN, TILE_OPC_NONE, 2067 + TILEPRO_OPC_SRAI_SN, TILEPRO_OPC_NONE, 2084 2068 BITFIELD(43, 3) /* index 1493 */, 2085 2069 CHILD(1251), CHILD(1254), CHILD(1502), CHILD(1505), CHILD(1508), 2086 2070 CHILD(1511), CHILD(1514), CHILD(1287), 2087 2071 BITFIELD(53, 1) /* index 1502 */, 2088 - TILE_OPC_LB_SN, TILE_OPC_NONE, 2072 + TILEPRO_OPC_LB_SN, TILEPRO_OPC_NONE, 2089 2073 BITFIELD(53, 1) /* index 1505 */, 2090 - TILE_OPC_LB_U_SN, TILE_OPC_NONE, 2074 + TILEPRO_OPC_LB_U_SN, TILEPRO_OPC_NONE, 2091 2075 BITFIELD(53, 1) /* index 1508 */, 2092 - TILE_OPC_LH_SN, TILE_OPC_NONE, 2076 + TILEPRO_OPC_LH_SN, TILEPRO_OPC_NONE, 2093 2077 BITFIELD(53, 1) /* index 1511 */, 2094 - TILE_OPC_LH_U_SN, TILE_OPC_NONE, 2078 + TILEPRO_OPC_LH_U_SN, TILEPRO_OPC_NONE, 2095 2079 BITFIELD(53, 1) /* index 1514 */, 2096 - TILE_OPC_LW_SN, TILE_OPC_NONE, 2080 + TILEPRO_OPC_LW_SN, TILEPRO_OPC_NONE, 2097 2081 BITFIELD(43, 3) /* index 1517 */, 2098 2082 CHILD(1299), CHILD(1302), CHILD(1305), CHILD(1308), CHILD(1311), 2099 2083 CHILD(1314), CHILD(1526), CHILD(1320), 2100 2084 BITFIELD(53, 1) /* index 1526 */, 2101 - TILE_OPC_TNS_SN, TILE_OPC_NONE, 2085 + TILEPRO_OPC_TNS_SN, TILEPRO_OPC_NONE, 2102 2086 BITFIELD(43, 2) /* index 1529 */, 2103 - CHILD(1534), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2087 + CHILD(1534), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2104 2088 BITFIELD(45, 1) /* index 1534 */, 2105 - CHILD(1537), TILE_OPC_NONE, 2089 + CHILD(1537), TILEPRO_OPC_NONE, 2106 2090 BITFIELD(53, 1) /* index 1537 */, 2107 - TILE_OPC_LW_NA_SN, TILE_OPC_NONE, 2091 + TILEPRO_OPC_LW_NA_SN, TILEPRO_OPC_NONE, 2108 2092 }; 2109 2093 2110 2094 static const unsigned short decode_Y0_fsm[168] = 2111 2095 { 2112 2096 BITFIELD(27, 4) /* index 0 */, 2113 - TILE_OPC_NONE, CHILD(17), CHILD(22), CHILD(27), CHILD(47), CHILD(52), 2114 - CHILD(57), CHILD(62), CHILD(67), TILE_OPC_ADDI, CHILD(72), CHILD(102), 2115 - TILE_OPC_SEQI, CHILD(117), TILE_OPC_SLTI, TILE_OPC_SLTI_U, 2097 + TILEPRO_OPC_NONE, CHILD(17), CHILD(22), CHILD(27), CHILD(47), CHILD(52), 2098 + CHILD(57), CHILD(62), CHILD(67), TILEPRO_OPC_ADDI, CHILD(72), CHILD(102), 2099 + TILEPRO_OPC_SEQI, CHILD(117), TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U, 2116 2100 BITFIELD(18, 2) /* index 17 */, 2117 - TILE_OPC_ADD, TILE_OPC_S1A, TILE_OPC_S2A, TILE_OPC_SUB, 2101 + TILEPRO_OPC_ADD, TILEPRO_OPC_S1A, TILEPRO_OPC_S2A, TILEPRO_OPC_SUB, 2118 2102 BITFIELD(18, 2) /* index 22 */, 2119 - TILE_OPC_MNZ, TILE_OPC_MVNZ, TILE_OPC_MVZ, TILE_OPC_MZ, 2103 + TILEPRO_OPC_MNZ, TILEPRO_OPC_MVNZ, TILEPRO_OPC_MVZ, TILEPRO_OPC_MZ, 2120 2104 BITFIELD(18, 2) /* index 27 */, 2121 - TILE_OPC_AND, TILE_OPC_NOR, CHILD(32), TILE_OPC_XOR, 2105 + TILEPRO_OPC_AND, TILEPRO_OPC_NOR, CHILD(32), TILEPRO_OPC_XOR, 2122 2106 BITFIELD(12, 2) /* index 32 */, 2123 - TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(37), 2107 + TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(37), 2124 2108 BITFIELD(14, 2) /* index 37 */, 2125 - TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(42), 2109 + TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(42), 2126 2110 BITFIELD(16, 2) /* index 42 */, 2127 - TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_MOVE, 2111 + TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_MOVE, 2128 2112 BITFIELD(18, 2) /* index 47 */, 2129 - TILE_OPC_RL, TILE_OPC_SHL, TILE_OPC_SHR, TILE_OPC_SRA, 2113 + TILEPRO_OPC_RL, TILEPRO_OPC_SHL, TILEPRO_OPC_SHR, TILEPRO_OPC_SRA, 2130 2114 BITFIELD(18, 2) /* index 52 */, 2131 - TILE_OPC_SLTE, TILE_OPC_SLTE_U, TILE_OPC_SLT, TILE_OPC_SLT_U, 2115 + TILEPRO_OPC_SLTE, TILEPRO_OPC_SLTE_U, TILEPRO_OPC_SLT, TILEPRO_OPC_SLT_U, 2132 2116 BITFIELD(18, 2) /* index 57 */, 2133 - TILE_OPC_MULHLSA_UU, TILE_OPC_S3A, TILE_OPC_SEQ, TILE_OPC_SNE, 2117 + TILEPRO_OPC_MULHLSA_UU, TILEPRO_OPC_S3A, TILEPRO_OPC_SEQ, TILEPRO_OPC_SNE, 2134 2118 BITFIELD(18, 2) /* index 62 */, 2135 - TILE_OPC_MULHH_SS, TILE_OPC_MULHH_UU, TILE_OPC_MULLL_SS, TILE_OPC_MULLL_UU, 2119 + TILEPRO_OPC_MULHH_SS, TILEPRO_OPC_MULHH_UU, TILEPRO_OPC_MULLL_SS, 2120 + TILEPRO_OPC_MULLL_UU, 2136 2121 BITFIELD(18, 2) /* index 67 */, 2137 - TILE_OPC_MULHHA_SS, TILE_OPC_MULHHA_UU, TILE_OPC_MULLLA_SS, 2138 - TILE_OPC_MULLLA_UU, 2122 + TILEPRO_OPC_MULHHA_SS, TILEPRO_OPC_MULHHA_UU, TILEPRO_OPC_MULLLA_SS, 2123 + TILEPRO_OPC_MULLLA_UU, 2139 2124 BITFIELD(0, 2) /* index 72 */, 2140 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(77), 2125 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(77), 2141 2126 BITFIELD(2, 2) /* index 77 */, 2142 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(82), 2127 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(82), 2143 2128 BITFIELD(4, 2) /* index 82 */, 2144 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(87), 2129 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(87), 2145 2130 BITFIELD(6, 2) /* index 87 */, 2146 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(92), 2131 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(92), 2147 2132 BITFIELD(8, 2) /* index 92 */, 2148 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(97), 2133 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(97), 2149 2134 BITFIELD(10, 2) /* index 97 */, 2150 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_INFO, 2135 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_INFO, 2151 2136 BITFIELD(6, 2) /* index 102 */, 2152 - TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(107), 2137 + TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(107), 2153 2138 BITFIELD(8, 2) /* index 107 */, 2154 - TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(112), 2139 + TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(112), 2155 2140 BITFIELD(10, 2) /* index 112 */, 2156 - TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_MOVEI, 2141 + TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_MOVEI, 2157 2142 BITFIELD(15, 5) /* index 117 */, 2158 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_RLI, 2159 - TILE_OPC_RLI, TILE_OPC_RLI, TILE_OPC_RLI, TILE_OPC_SHLI, TILE_OPC_SHLI, 2160 - TILE_OPC_SHLI, TILE_OPC_SHLI, TILE_OPC_SHRI, TILE_OPC_SHRI, TILE_OPC_SHRI, 2161 - TILE_OPC_SHRI, TILE_OPC_SRAI, TILE_OPC_SRAI, TILE_OPC_SRAI, TILE_OPC_SRAI, 2162 - CHILD(150), CHILD(159), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2163 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2164 - TILE_OPC_NONE, TILE_OPC_NONE, 2143 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2144 + TILEPRO_OPC_RLI, TILEPRO_OPC_RLI, TILEPRO_OPC_RLI, TILEPRO_OPC_RLI, 2145 + TILEPRO_OPC_SHLI, TILEPRO_OPC_SHLI, TILEPRO_OPC_SHLI, TILEPRO_OPC_SHLI, 2146 + TILEPRO_OPC_SHRI, TILEPRO_OPC_SHRI, TILEPRO_OPC_SHRI, TILEPRO_OPC_SHRI, 2147 + TILEPRO_OPC_SRAI, TILEPRO_OPC_SRAI, TILEPRO_OPC_SRAI, TILEPRO_OPC_SRAI, 2148 + CHILD(150), CHILD(159), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2149 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2150 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2165 2151 BITFIELD(12, 3) /* index 150 */, 2166 - TILE_OPC_NONE, TILE_OPC_BITX, TILE_OPC_BYTEX, TILE_OPC_CLZ, TILE_OPC_CTZ, 2167 - TILE_OPC_FNOP, TILE_OPC_NOP, TILE_OPC_PCNT, 2152 + TILEPRO_OPC_NONE, TILEPRO_OPC_BITX, TILEPRO_OPC_BYTEX, TILEPRO_OPC_CLZ, 2153 + TILEPRO_OPC_CTZ, TILEPRO_OPC_FNOP, TILEPRO_OPC_NOP, TILEPRO_OPC_PCNT, 2168 2154 BITFIELD(12, 3) /* index 159 */, 2169 - TILE_OPC_TBLIDXB0, TILE_OPC_TBLIDXB1, TILE_OPC_TBLIDXB2, TILE_OPC_TBLIDXB3, 2170 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2155 + TILEPRO_OPC_TBLIDXB0, TILEPRO_OPC_TBLIDXB1, TILEPRO_OPC_TBLIDXB2, 2156 + TILEPRO_OPC_TBLIDXB3, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2157 + TILEPRO_OPC_NONE, 2171 2158 }; 2172 2159 2173 2160 static const unsigned short decode_Y1_fsm[140] = 2174 2161 { 2175 2162 BITFIELD(59, 4) /* index 0 */, 2176 - TILE_OPC_NONE, CHILD(17), CHILD(22), CHILD(27), CHILD(47), CHILD(52), 2177 - CHILD(57), TILE_OPC_ADDI, CHILD(62), CHILD(92), TILE_OPC_SEQI, CHILD(107), 2178 - TILE_OPC_SLTI, TILE_OPC_SLTI_U, TILE_OPC_NONE, TILE_OPC_NONE, 2163 + TILEPRO_OPC_NONE, CHILD(17), CHILD(22), CHILD(27), CHILD(47), CHILD(52), 2164 + CHILD(57), TILEPRO_OPC_ADDI, CHILD(62), CHILD(92), TILEPRO_OPC_SEQI, 2165 + CHILD(107), TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U, TILEPRO_OPC_NONE, 2166 + TILEPRO_OPC_NONE, 2179 2167 BITFIELD(49, 2) /* index 17 */, 2180 - TILE_OPC_ADD, TILE_OPC_S1A, TILE_OPC_S2A, TILE_OPC_SUB, 2168 + TILEPRO_OPC_ADD, TILEPRO_OPC_S1A, TILEPRO_OPC_S2A, TILEPRO_OPC_SUB, 2181 2169 BITFIELD(49, 2) /* index 22 */, 2182 - TILE_OPC_NONE, TILE_OPC_MNZ, TILE_OPC_MZ, TILE_OPC_NONE, 2170 + TILEPRO_OPC_NONE, TILEPRO_OPC_MNZ, TILEPRO_OPC_MZ, TILEPRO_OPC_NONE, 2183 2171 BITFIELD(49, 2) /* index 27 */, 2184 - TILE_OPC_AND, TILE_OPC_NOR, CHILD(32), TILE_OPC_XOR, 2172 + TILEPRO_OPC_AND, TILEPRO_OPC_NOR, CHILD(32), TILEPRO_OPC_XOR, 2185 2173 BITFIELD(43, 2) /* index 32 */, 2186 - TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(37), 2174 + TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(37), 2187 2175 BITFIELD(45, 2) /* index 37 */, 2188 - TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(42), 2176 + TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(42), 2189 2177 BITFIELD(47, 2) /* index 42 */, 2190 - TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_MOVE, 2178 + TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_MOVE, 2191 2179 BITFIELD(49, 2) /* index 47 */, 2192 - TILE_OPC_RL, TILE_OPC_SHL, TILE_OPC_SHR, TILE_OPC_SRA, 2180 + TILEPRO_OPC_RL, TILEPRO_OPC_SHL, TILEPRO_OPC_SHR, TILEPRO_OPC_SRA, 2193 2181 BITFIELD(49, 2) /* index 52 */, 2194 - TILE_OPC_SLTE, TILE_OPC_SLTE_U, TILE_OPC_SLT, TILE_OPC_SLT_U, 2182 + TILEPRO_OPC_SLTE, TILEPRO_OPC_SLTE_U, TILEPRO_OPC_SLT, TILEPRO_OPC_SLT_U, 2195 2183 BITFIELD(49, 2) /* index 57 */, 2196 - TILE_OPC_NONE, TILE_OPC_S3A, TILE_OPC_SEQ, TILE_OPC_SNE, 2184 + TILEPRO_OPC_NONE, TILEPRO_OPC_S3A, TILEPRO_OPC_SEQ, TILEPRO_OPC_SNE, 2197 2185 BITFIELD(31, 2) /* index 62 */, 2198 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(67), 2186 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(67), 2199 2187 BITFIELD(33, 2) /* index 67 */, 2200 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(72), 2188 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(72), 2201 2189 BITFIELD(35, 2) /* index 72 */, 2202 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(77), 2190 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(77), 2203 2191 BITFIELD(37, 2) /* index 77 */, 2204 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(82), 2192 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(82), 2205 2193 BITFIELD(39, 2) /* index 82 */, 2206 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(87), 2194 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(87), 2207 2195 BITFIELD(41, 2) /* index 87 */, 2208 - TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_INFO, 2196 + TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_INFO, 2209 2197 BITFIELD(37, 2) /* index 92 */, 2210 - TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(97), 2198 + TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(97), 2211 2199 BITFIELD(39, 2) /* index 97 */, 2212 - TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(102), 2200 + TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(102), 2213 2201 BITFIELD(41, 2) /* index 102 */, 2214 - TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_MOVEI, 2202 + TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_MOVEI, 2215 2203 BITFIELD(48, 3) /* index 107 */, 2216 - TILE_OPC_NONE, TILE_OPC_RLI, TILE_OPC_SHLI, TILE_OPC_SHRI, TILE_OPC_SRAI, 2217 - CHILD(116), TILE_OPC_NONE, TILE_OPC_NONE, 2204 + TILEPRO_OPC_NONE, TILEPRO_OPC_RLI, TILEPRO_OPC_SHLI, TILEPRO_OPC_SHRI, 2205 + TILEPRO_OPC_SRAI, CHILD(116), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2218 2206 BITFIELD(43, 3) /* index 116 */, 2219 - TILE_OPC_NONE, CHILD(125), CHILD(130), CHILD(135), TILE_OPC_NONE, 2220 - TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2207 + TILEPRO_OPC_NONE, CHILD(125), CHILD(130), CHILD(135), TILEPRO_OPC_NONE, 2208 + TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2221 2209 BITFIELD(46, 2) /* index 125 */, 2222 - TILE_OPC_FNOP, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2210 + TILEPRO_OPC_FNOP, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2223 2211 BITFIELD(46, 2) /* index 130 */, 2224 - TILE_OPC_ILL, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2212 + TILEPRO_OPC_ILL, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2225 2213 BITFIELD(46, 2) /* index 135 */, 2226 - TILE_OPC_NOP, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2214 + TILEPRO_OPC_NOP, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, 2227 2215 }; 2228 2216 2229 2217 static const unsigned short decode_Y2_fsm[24] = 2230 2218 { 2231 2219 BITFIELD(56, 3) /* index 0 */, 2232 - CHILD(9), TILE_OPC_LB_U, TILE_OPC_LH, TILE_OPC_LH_U, TILE_OPC_LW, 2233 - TILE_OPC_SB, TILE_OPC_SH, TILE_OPC_SW, 2220 + CHILD(9), TILEPRO_OPC_LB_U, TILEPRO_OPC_LH, TILEPRO_OPC_LH_U, 2221 + TILEPRO_OPC_LW, TILEPRO_OPC_SB, TILEPRO_OPC_SH, TILEPRO_OPC_SW, 2234 2222 BITFIELD(20, 2) /* index 9 */, 2235 - TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(14), 2223 + TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(14), 2236 2224 BITFIELD(22, 2) /* index 14 */, 2237 - TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(19), 2225 + TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(19), 2238 2226 BITFIELD(24, 2) /* index 19 */, 2239 - TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_PREFETCH, 2227 + TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_PREFETCH, 2240 2228 }; 2241 2229 2242 2230 #undef BITFIELD 2243 2231 #undef CHILD 2244 2232 const unsigned short * const 2245 - tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS] = 2233 + tilepro_bundle_decoder_fsms[TILEPRO_NUM_PIPELINE_ENCODINGS] = 2246 2234 { 2247 2235 decode_X0_fsm, 2248 2236 decode_X1_fsm, ··· 2297 2191 decode_Y1_fsm, 2298 2192 decode_Y2_fsm 2299 2193 }; 2300 - const struct tile_operand tile_operands[43] = 2194 + const struct tilepro_operand tilepro_operands[43] = 2301 2195 { 2302 2196 { 2303 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM8_X0), 2197 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM8_X0), 2304 2198 8, 1, 0, 0, 0, 0, 2305 2199 create_Imm8_X0, get_Imm8_X0 2306 2200 }, 2307 2201 { 2308 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM8_X1), 2202 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM8_X1), 2309 2203 8, 1, 0, 0, 0, 0, 2310 2204 create_Imm8_X1, get_Imm8_X1 2311 2205 }, 2312 2206 { 2313 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM8_Y0), 2207 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM8_Y0), 2314 2208 8, 1, 0, 0, 0, 0, 2315 2209 create_Imm8_Y0, get_Imm8_Y0 2316 2210 }, 2317 2211 { 2318 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM8_Y1), 2212 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM8_Y1), 2319 2213 8, 1, 0, 0, 0, 0, 2320 2214 create_Imm8_Y1, get_Imm8_Y1 2321 2215 }, 2322 2216 { 2323 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM16_X0), 2217 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM16_X0), 2324 2218 16, 1, 0, 0, 0, 0, 2325 2219 create_Imm16_X0, get_Imm16_X0 2326 2220 }, 2327 2221 { 2328 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM16_X1), 2222 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM16_X1), 2329 2223 16, 1, 0, 0, 0, 0, 2330 2224 create_Imm16_X1, get_Imm16_X1 2331 2225 }, 2332 2226 { 2333 - TILE_OP_TYPE_ADDRESS, BFD_RELOC(TILE_JOFFLONG_X1), 2334 - 29, 1, 0, 0, 1, TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, 2227 + TILEPRO_OP_TYPE_ADDRESS, BFD_RELOC(TILEPRO_JOFFLONG_X1), 2228 + 29, 1, 0, 0, 1, TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, 2335 2229 create_JOffLong_X1, get_JOffLong_X1 2336 2230 }, 2337 2231 { 2338 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2232 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2339 2233 6, 0, 0, 1, 0, 0, 2340 2234 create_Dest_X0, get_Dest_X0 2341 2235 }, 2342 2236 { 2343 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2237 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2344 2238 6, 0, 1, 0, 0, 0, 2345 2239 create_SrcA_X0, get_SrcA_X0 2346 2240 }, 2347 2241 { 2348 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2242 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2349 2243 6, 0, 0, 1, 0, 0, 2350 2244 create_Dest_X1, get_Dest_X1 2351 2245 }, 2352 2246 { 2353 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2247 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2354 2248 6, 0, 1, 0, 0, 0, 2355 2249 create_SrcA_X1, get_SrcA_X1 2356 2250 }, 2357 2251 { 2358 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2252 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2359 2253 6, 0, 0, 1, 0, 0, 2360 2254 create_Dest_Y0, get_Dest_Y0 2361 2255 }, 2362 2256 { 2363 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2257 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2364 2258 6, 0, 1, 0, 0, 0, 2365 2259 create_SrcA_Y0, get_SrcA_Y0 2366 2260 }, 2367 2261 { 2368 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2262 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2369 2263 6, 0, 0, 1, 0, 0, 2370 2264 create_Dest_Y1, get_Dest_Y1 2371 2265 }, 2372 2266 { 2373 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2267 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2374 2268 6, 0, 1, 0, 0, 0, 2375 2269 create_SrcA_Y1, get_SrcA_Y1 2376 2270 }, 2377 2271 { 2378 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2272 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2379 2273 6, 0, 1, 0, 0, 0, 2380 2274 create_SrcA_Y2, get_SrcA_Y2 2381 2275 }, 2382 2276 { 2383 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2277 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2384 2278 6, 0, 1, 0, 0, 0, 2385 2279 create_SrcB_X0, get_SrcB_X0 2386 2280 }, 2387 2281 { 2388 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2282 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2389 2283 6, 0, 1, 0, 0, 0, 2390 2284 create_SrcB_X1, get_SrcB_X1 2391 2285 }, 2392 2286 { 2393 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2287 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2394 2288 6, 0, 1, 0, 0, 0, 2395 2289 create_SrcB_Y0, get_SrcB_Y0 2396 2290 }, 2397 2291 { 2398 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2292 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2399 2293 6, 0, 1, 0, 0, 0, 2400 2294 create_SrcB_Y1, get_SrcB_Y1 2401 2295 }, 2402 2296 { 2403 - TILE_OP_TYPE_ADDRESS, BFD_RELOC(TILE_BROFF_X1), 2404 - 17, 1, 0, 0, 1, TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, 2297 + TILEPRO_OP_TYPE_ADDRESS, BFD_RELOC(TILEPRO_BROFF_X1), 2298 + 17, 1, 0, 0, 1, TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, 2405 2299 create_BrOff_X1, get_BrOff_X1 2406 2300 }, 2407 2301 { 2408 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2302 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2409 2303 6, 0, 1, 1, 0, 0, 2410 2304 create_Dest_X0, get_Dest_X0 2411 2305 }, 2412 2306 { 2413 - TILE_OP_TYPE_ADDRESS, BFD_RELOC(NONE), 2414 - 28, 1, 0, 0, 1, TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, 2307 + TILEPRO_OP_TYPE_ADDRESS, BFD_RELOC(NONE), 2308 + 28, 1, 0, 0, 1, TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, 2415 2309 create_JOff_X1, get_JOff_X1 2416 2310 }, 2417 2311 { 2418 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2312 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2419 2313 6, 0, 0, 1, 0, 0, 2420 2314 create_SrcBDest_Y2, get_SrcBDest_Y2 2421 2315 }, 2422 2316 { 2423 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2317 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2424 2318 6, 0, 1, 1, 0, 0, 2425 2319 create_SrcA_X1, get_SrcA_X1 2426 2320 }, 2427 2321 { 2428 - TILE_OP_TYPE_SPR, BFD_RELOC(TILE_MF_IMM15_X1), 2322 + TILEPRO_OP_TYPE_SPR, BFD_RELOC(TILEPRO_MF_IMM15_X1), 2429 2323 15, 0, 0, 0, 0, 0, 2430 2324 create_MF_Imm15_X1, get_MF_Imm15_X1 2431 2325 }, 2432 2326 { 2433 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_MMSTART_X0), 2327 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_MMSTART_X0), 2434 2328 5, 0, 0, 0, 0, 0, 2435 2329 create_MMStart_X0, get_MMStart_X0 2436 2330 }, 2437 2331 { 2438 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_MMEND_X0), 2332 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_MMEND_X0), 2439 2333 5, 0, 0, 0, 0, 0, 2440 2334 create_MMEnd_X0, get_MMEnd_X0 2441 2335 }, 2442 2336 { 2443 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_MMSTART_X1), 2337 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_MMSTART_X1), 2444 2338 5, 0, 0, 0, 0, 0, 2445 2339 create_MMStart_X1, get_MMStart_X1 2446 2340 }, 2447 2341 { 2448 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_MMEND_X1), 2342 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_MMEND_X1), 2449 2343 5, 0, 0, 0, 0, 0, 2450 2344 create_MMEnd_X1, get_MMEnd_X1 2451 2345 }, 2452 2346 { 2453 - TILE_OP_TYPE_SPR, BFD_RELOC(TILE_MT_IMM15_X1), 2347 + TILEPRO_OP_TYPE_SPR, BFD_RELOC(TILEPRO_MT_IMM15_X1), 2454 2348 15, 0, 0, 0, 0, 0, 2455 2349 create_MT_Imm15_X1, get_MT_Imm15_X1 2456 2350 }, 2457 2351 { 2458 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2352 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2459 2353 6, 0, 1, 1, 0, 0, 2460 2354 create_Dest_Y0, get_Dest_Y0 2461 2355 }, 2462 2356 { 2463 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SHAMT_X0), 2357 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_SHAMT_X0), 2464 2358 5, 0, 0, 0, 0, 0, 2465 2359 create_ShAmt_X0, get_ShAmt_X0 2466 2360 }, 2467 2361 { 2468 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SHAMT_X1), 2362 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_SHAMT_X1), 2469 2363 5, 0, 0, 0, 0, 0, 2470 2364 create_ShAmt_X1, get_ShAmt_X1 2471 2365 }, 2472 2366 { 2473 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SHAMT_Y0), 2367 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_SHAMT_Y0), 2474 2368 5, 0, 0, 0, 0, 0, 2475 2369 create_ShAmt_Y0, get_ShAmt_Y0 2476 2370 }, 2477 2371 { 2478 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SHAMT_Y1), 2372 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_SHAMT_Y1), 2479 2373 5, 0, 0, 0, 0, 0, 2480 2374 create_ShAmt_Y1, get_ShAmt_Y1 2481 2375 }, 2482 2376 { 2483 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2377 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2484 2378 6, 0, 1, 0, 0, 0, 2485 2379 create_SrcBDest_Y2, get_SrcBDest_Y2 2486 2380 }, 2487 2381 { 2488 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE), 2382 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_DEST_IMM8_X1), 2489 2383 8, 1, 0, 0, 0, 0, 2490 2384 create_Dest_Imm8_X1, get_Dest_Imm8_X1 2491 2385 }, 2492 2386 { 2493 - TILE_OP_TYPE_ADDRESS, BFD_RELOC(TILE_SN_BROFF), 2494 - 10, 1, 0, 0, 1, TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES, 2387 + TILEPRO_OP_TYPE_ADDRESS, BFD_RELOC(NONE), 2388 + 10, 1, 0, 0, 1, TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES, 2495 2389 create_BrOff_SN, get_BrOff_SN 2496 2390 }, 2497 2391 { 2498 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SN_UIMM8), 2392 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE), 2499 2393 8, 0, 0, 0, 0, 0, 2500 2394 create_Imm8_SN, get_Imm8_SN 2501 2395 }, 2502 2396 { 2503 - TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SN_IMM8), 2397 + TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE), 2504 2398 8, 1, 0, 0, 0, 0, 2505 2399 create_Imm8_SN, get_Imm8_SN 2506 2400 }, 2507 2401 { 2508 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2402 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2509 2403 2, 0, 0, 1, 0, 0, 2510 2404 create_Dest_SN, get_Dest_SN 2511 2405 }, 2512 2406 { 2513 - TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2407 + TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), 2514 2408 2, 0, 1, 0, 0, 0, 2515 2409 create_Src_SN, get_Src_SN 2516 2410 } ··· 2522 2416 /* Given a set of bundle bits and a specific pipe, returns which 2523 2417 * instruction the bundle contains in that pipe. 2524 2418 */ 2525 - const struct tile_opcode * 2526 - find_opcode(tile_bundle_bits bits, tile_pipeline pipe) 2419 + const struct tilepro_opcode * 2420 + find_opcode(tilepro_bundle_bits bits, tilepro_pipeline pipe) 2527 2421 { 2528 - const unsigned short *table = tile_bundle_decoder_fsms[pipe]; 2422 + const unsigned short *table = tilepro_bundle_decoder_fsms[pipe]; 2529 2423 int index = 0; 2530 2424 2531 2425 while (1) ··· 2535 2429 ((unsigned int)(bits >> (bitspec & 63))) & (bitspec >> 6); 2536 2430 2537 2431 unsigned short next = table[index + 1 + bitfield]; 2538 - if (next <= TILE_OPC_NONE) 2539 - return &tile_opcodes[next]; 2432 + if (next <= TILEPRO_OPC_NONE) 2433 + return &tilepro_opcodes[next]; 2540 2434 2541 - index = next - TILE_OPC_NONE; 2435 + index = next - TILEPRO_OPC_NONE; 2542 2436 } 2543 2437 } 2544 2438 2545 2439 2546 2440 int 2547 - parse_insn_tile(tile_bundle_bits bits, 2548 - unsigned int pc, 2549 - struct tile_decoded_instruction 2550 - decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]) 2441 + parse_insn_tilepro(tilepro_bundle_bits bits, 2442 + unsigned int pc, 2443 + struct tilepro_decoded_instruction 2444 + decoded[TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE]) 2551 2445 { 2552 2446 int num_instructions = 0; 2553 2447 int pipe; 2554 2448 2555 2449 int min_pipe, max_pipe; 2556 - if ((bits & TILE_BUNDLE_Y_ENCODING_MASK) == 0) 2450 + if ((bits & TILEPRO_BUNDLE_Y_ENCODING_MASK) == 0) 2557 2451 { 2558 - min_pipe = TILE_PIPELINE_X0; 2559 - max_pipe = TILE_PIPELINE_X1; 2452 + min_pipe = TILEPRO_PIPELINE_X0; 2453 + max_pipe = TILEPRO_PIPELINE_X1; 2560 2454 } 2561 2455 else 2562 2456 { 2563 - min_pipe = TILE_PIPELINE_Y0; 2564 - max_pipe = TILE_PIPELINE_Y2; 2457 + min_pipe = TILEPRO_PIPELINE_Y0; 2458 + max_pipe = TILEPRO_PIPELINE_Y2; 2565 2459 } 2566 2460 2567 2461 /* For each pipe, find an instruction that fits. */ 2568 2462 for (pipe = min_pipe; pipe <= max_pipe; pipe++) 2569 2463 { 2570 - const struct tile_opcode *opc; 2571 - struct tile_decoded_instruction *d; 2464 + const struct tilepro_opcode *opc; 2465 + struct tilepro_decoded_instruction *d; 2572 2466 int i; 2573 2467 2574 2468 d = &decoded[num_instructions++]; 2575 - opc = find_opcode (bits, (tile_pipeline)pipe); 2469 + opc = find_opcode (bits, (tilepro_pipeline)pipe); 2576 2470 d->opcode = opc; 2577 2471 2578 2472 /* Decode each operand, sign extending, etc. as appropriate. */ 2579 2473 for (i = 0; i < opc->num_operands; i++) 2580 2474 { 2581 - const struct tile_operand *op = 2582 - &tile_operands[opc->operands[pipe][i]]; 2475 + const struct tilepro_operand *op = 2476 + &tilepro_operands[opc->operands[pipe][i]]; 2583 2477 int opval = op->extract (bits); 2584 2478 if (op->is_signed) 2585 2479 { ··· 2589 2483 } 2590 2484 2591 2485 /* Adjust PC-relative scaled branch offsets. */ 2592 - if (op->type == TILE_OP_TYPE_ADDRESS) 2486 + if (op->type == TILEPRO_OP_TYPE_ADDRESS) 2593 2487 { 2594 - opval *= TILE_BUNDLE_SIZE_IN_BYTES; 2488 + opval *= TILEPRO_BUNDLE_SIZE_IN_BYTES; 2595 2489 opval += (int)pc; 2596 2490 } 2597 2491
+23 -5
arch/tile/kernel/tile-desc_64.c
··· 1 + /* TILE-Gx opcode information. 2 + * 3 + * Copyright 2011 Tilera Corporation. All Rights Reserved. 4 + * 5 + * This program is free software; you can redistribute it and/or 6 + * modify it under the terms of the GNU General Public License 7 + * as published by the Free Software Foundation, version 2. 8 + * 9 + * This program is distributed in the hope that it will be useful, but 10 + * WITHOUT ANY WARRANTY; without even the implied warranty of 11 + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 + * NON INFRINGEMENT. See the GNU General Public License for 13 + * more details. 14 + * 15 + * 16 + * 17 + * 18 + * 19 + */ 20 + 1 21 /* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */ 2 22 #define BFD_RELOC(x) -1 3 23 ··· 26 6 #define TREG_SN 56 27 7 #define TREG_ZERO 63 28 8 29 - /* FIXME: Rename this. */ 30 - #include <asm/opcode-tile_64.h> 31 - 32 9 #include <linux/stddef.h> 10 + #include <asm/tile-desc.h> 33 11 34 12 const struct tilegx_opcode tilegx_opcodes[334] = 35 13 { ··· 2058 2040 create_BrOff_X1, get_BrOff_X1 2059 2041 }, 2060 2042 { 2061 - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE), 2043 + TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMSTART_X0), 2062 2044 6, 0, 0, 0, 0, 0, 2063 2045 create_BFStart_X0, get_BFStart_X0 2064 2046 }, 2065 2047 { 2066 - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE), 2048 + TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMEND_X0), 2067 2049 6, 0, 0, 0, 0, 0, 2068 2050 create_BFEnd_X0, get_BFEnd_X0 2069 2051 },
+2 -3
arch/tile/kernel/traps.c
··· 19 19 #include <linux/reboot.h> 20 20 #include <linux/uaccess.h> 21 21 #include <linux/ptrace.h> 22 - #include <asm/opcode-tile.h> 23 - #include <asm/opcode_constants.h> 24 22 #include <asm/stack.h> 25 23 #include <asm/traps.h> 26 24 27 25 #include <arch/interrupts.h> 28 26 #include <arch/spr_def.h> 27 + #include <arch/opcode.h> 29 28 30 29 void __init trap_init(void) 31 30 { ··· 134 135 if (get_UnaryOpcodeExtension_X1(bundle) != ILL_UNARY_OPCODE_X1) 135 136 return 0; 136 137 #else 137 - if (bundle & TILE_BUNDLE_Y_ENCODING_MASK) 138 + if (bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK) 138 139 return 0; 139 140 if (get_Opcode_X1(bundle) != SHUN_0_OPCODE_X1) 140 141 return 0;
-2
arch/tile/lib/exports.c
··· 79 79 int64_t __moddi3(int64_t dividend, int64_t divisor); 80 80 EXPORT_SYMBOL(__moddi3); 81 81 #ifndef __tilegx__ 82 - uint64_t __ll_mul(uint64_t n0, uint64_t n1); 83 - EXPORT_SYMBOL(__ll_mul); 84 82 int64_t __muldi3(int64_t, int64_t); 85 83 EXPORT_SYMBOL(__muldi3); 86 84 uint64_t __lshrdi3(uint64_t, unsigned int);