tjh.dev / kernel
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kernel os linux
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drm/amdgpu: Clear RAS interrupt status on aldebaran

Resolve incorrect register address

Reviewed-by: Candice Li <candice.li@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

John Clements and committed by
Alex Deucher 156872b0 e5b310f9

+25 -5
+25 -5
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
··· 85 85 #define mmRCC_DEV0_EPF0_STRAP0_ALDE 0x0015 86 86 #define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX 2 87 87 88 - #define mmBIF_DOORBELL_INT_CNTL_ALDE 0x3878 88 + #define mmBIF_DOORBELL_INT_CNTL_ALDE 0x00fe 89 89 #define mmBIF_DOORBELL_INT_CNTL_ALDE_BASE_IDX 2 90 90 #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 91 91 #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L 92 + 93 + #define mmBIF_INTR_CNTL_ALDE 0x0101 94 + #define mmBIF_INTR_CNTL_ALDE_BASE_IDX 2 92 95 93 96 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, 94 97 void *ras_error_status); ··· 443 440 */ 444 441 uint32_t bif_intr_cntl; 445 442 446 - bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 443 + if (adev->asic_type == CHIP_ALDEBARAN) 444 + bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE); 445 + else 446 + bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 447 + 447 448 if (state == AMDGPU_IRQ_STATE_ENABLE) { 448 449 /* set interrupt vector select bit to 0 to select 449 450 * vetcor 1 for bare metal case */ 450 451 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 451 452 BIF_INTR_CNTL, 452 453 RAS_INTR_VEC_SEL, 0); 453 - WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 454 + 455 + if (adev->asic_type == CHIP_ALDEBARAN) 456 + WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl); 457 + else 458 + WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 459 + 454 460 } 455 461 456 462 return 0; ··· 488 476 */ 489 477 uint32_t bif_intr_cntl; 490 478 491 - bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 479 + if (adev->asic_type == CHIP_ALDEBARAN) 480 + bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE); 481 + else 482 + bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 483 + 492 484 if (state == AMDGPU_IRQ_STATE_ENABLE) { 493 485 /* set interrupt vector select bit to 0 to select 494 486 * vetcor 1 for bare metal case */ 495 487 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 496 488 BIF_INTR_CNTL, 497 489 RAS_INTR_VEC_SEL, 0); 498 - WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 490 + 491 + if (adev->asic_type == CHIP_ALDEBARAN) 492 + WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl); 493 + else 494 + WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 499 495 } 500 496 501 497 return 0;