tjh.dev / kernel
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ata: sata_fsl: convert VPRINTK() calls to ata_port_dbg()

Signed-off-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>

authored by

Hannes Reinecke and committed by
Damien Le Moal 14d36306 47013c58

+33 -47
+33 -47
drivers/ata/sata_fsl.c
··· 406 406 return tag; 407 407 } 408 408 409 - static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, 409 + static void sata_fsl_setup_cmd_hdr_entry(struct ata_port *ap, 410 + struct sata_fsl_port_priv *pp, 410 411 unsigned int tag, u32 desc_info, 411 412 u32 data_xfer_len, u8 num_prde, 412 413 u8 fis_len) ··· 425 424 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); 426 425 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); 427 426 428 - VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 427 + ata_port_dbg(ap, "cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 429 428 pp->cmdslot[tag].cda, 430 429 pp->cmdslot[tag].prde_fis_len, 431 430 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); ··· 451 450 dma_addr_t indirect_ext_segment_paddr; 452 451 unsigned int si; 453 452 454 - VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd); 455 - 456 453 indirect_ext_segment_paddr = cmd_desc_paddr + 457 454 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; 458 455 459 456 for_each_sg(qc->sg, sg, qc->n_elem, si) { 460 457 dma_addr_t sg_addr = sg_dma_address(sg); 461 458 u32 sg_len = sg_dma_len(sg); 462 - 463 - VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n", 464 - (unsigned long long)sg_addr, sg_len); 465 459 466 460 /* warn if each s/g element is not dword aligned */ 467 461 if (unlikely(sg_addr & 0x03)) ··· 468 472 469 473 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && 470 474 sg_next(sg) != NULL) { 471 - VPRINTK("setting indirect prde\n"); 472 475 prd_ptr_to_indirect_ext = prd; 473 476 prd->dba = cpu_to_le32(indirect_ext_segment_paddr); 474 477 indirect_ext_segment_sz = 0; ··· 478 483 ttl_dwords += sg_len; 479 484 prd->dba = cpu_to_le32(sg_addr); 480 485 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03)); 481 - 482 - VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", 483 - ttl_dwords, prd->dba, prd->ddc_and_ext); 484 486 485 487 ++num_prde; 486 488 ++prd; ··· 515 523 516 524 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); 517 525 518 - VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", 519 - cd->cfis[0], cd->cfis[1], cd->cfis[2]); 520 - 521 - if (qc->tf.protocol == ATA_PROT_NCQ) { 522 - VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", 523 - cd->cfis[3], cd->cfis[11]); 524 - } 525 - 526 526 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ 527 527 if (ata_is_atapi(qc->tf.protocol)) { 528 528 desc_info |= ATAPI_CMD; ··· 530 546 if (qc->tf.protocol == ATA_PROT_NCQ) 531 547 desc_info |= FPDMA_QUEUED_CMD; 532 548 533 - sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, 549 + sata_fsl_setup_cmd_hdr_entry(ap, pp, tag, desc_info, ttl_dwords, 534 550 num_prde, 5); 535 551 536 - VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", 552 + ata_port_dbg(ap, "SATA FSL : di = 0x%x, ttl = %d, num_prde = %d\n", 537 553 desc_info, ttl_dwords, num_prde); 538 554 539 555 return AC_ERR_OK; ··· 546 562 void __iomem *hcr_base = host_priv->hcr_base; 547 563 unsigned int tag = sata_fsl_tag(ap, qc->hw_tag, hcr_base); 548 564 549 - VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 565 + ata_port_dbg(ap, "CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 550 566 ioread32(CQ + hcr_base), 551 567 ioread32(CA + hcr_base), 552 568 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); ··· 556 572 /* Simply queue command to the controller/device */ 557 573 iowrite32(1 << tag, CQ + hcr_base); 558 574 559 - VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", 575 + ata_port_dbg(ap, "tag=%d, CQ=0x%x, CA=0x%x\n", 560 576 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); 561 577 562 - VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 578 + ata_port_dbg(ap, "CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 563 579 ioread32(CE + hcr_base), 564 580 ioread32(DE + hcr_base), 565 581 ioread32(CC + hcr_base), ··· 600 616 return -EINVAL; 601 617 } 602 618 603 - VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); 619 + ata_link_dbg(link, "reg_in = %d\n", sc_reg); 604 620 605 621 iowrite32(val, ssr_base + (sc_reg * 4)); 606 622 return 0; ··· 624 640 return -EINVAL; 625 641 } 626 642 627 - VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); 643 + ata_link_dbg(link, "reg_in = %d\n", sc_reg); 628 644 629 645 *val = ioread32(ssr_base + (sc_reg * 4)); 630 646 return 0; ··· 636 652 void __iomem *hcr_base = host_priv->hcr_base; 637 653 u32 temp; 638 654 639 - VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 655 + ata_port_dbg(ap, "CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 640 656 ioread32(CQ + hcr_base), 641 657 ioread32(CA + hcr_base), 642 658 ioread32(CE + hcr_base), ioread32(DE + hcr_base)); 643 - VPRINTK("CmdStat = 0x%x\n", 659 + ata_port_dbg(ap, "CmdStat = 0x%x\n", 644 660 ioread32(host_priv->csr_base + COMMANDSTAT)); 645 661 646 662 /* disable interrupts on the controller/port */ 647 663 temp = ioread32(hcr_base + HCONTROL); 648 664 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 649 665 650 - VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", 666 + ata_port_dbg(ap, "HControl = 0x%x, HStatus = 0x%x\n", 651 667 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 652 668 } 653 669 ··· 660 676 /* ack. any pending IRQs for this controller/port */ 661 677 temp = ioread32(hcr_base + HSTATUS); 662 678 663 - VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); 679 + ata_port_dbg(ap, "pending IRQs = 0x%x\n", (temp & 0x3F)); 664 680 665 681 if (temp & 0x3F) 666 682 iowrite32((temp & 0x3F), hcr_base + HSTATUS); ··· 669 685 temp = ioread32(hcr_base + HCONTROL); 670 686 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 671 687 672 - VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", 688 + ata_port_dbg(ap, "HControl = 0x%x, HStatus = 0x%x\n", 673 689 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 674 690 } 675 691 ··· 731 747 732 748 ap->private_data = pp; 733 749 734 - VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", 735 - pp->cmdslot_paddr, pp->cmdentry_paddr); 750 + ata_port_dbg(ap, "CHBA = 0x%lx, cmdentry_phys = 0x%lx\n", 751 + (unsigned long)pp->cmdslot_paddr, 752 + (unsigned long)pp->cmdentry_paddr); 736 753 737 754 /* Now, update the CHBA register in host controller cmd register set */ 738 755 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); ··· 749 764 temp = ioread32(hcr_base + HCONTROL); 750 765 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); 751 766 752 - VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 753 - VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 754 - VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 767 + ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 768 + ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 769 + ata_port_dbg(ap, "CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 755 770 756 771 return 0; 757 772 } ··· 791 806 792 807 temp = ioread32(hcr_base + SIGNATURE); 793 808 794 - VPRINTK("raw sig = 0x%x\n", temp); 795 - VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 796 - VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 809 + ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 810 + ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 797 811 798 812 tf.lbah = (temp >> 24) & 0xff; 799 813 tf.lbam = (temp >> 16) & 0xff; ··· 945 961 cfis = (u8 *) &pp->cmdentry->cfis; 946 962 947 963 /* device reset/SRST is a control register update FIS, uses tag0 */ 948 - sata_fsl_setup_cmd_hdr_entry(pp, 0, 964 + sata_fsl_setup_cmd_hdr_entry(ap, pp, 0, 949 965 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 950 966 951 967 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ ··· 995 1011 * using ATA signature D2H register FIS to the host controller. 996 1012 */ 997 1013 998 - sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 999 - 0, 0, 5); 1014 + sata_fsl_setup_cmd_hdr_entry(ap, pp, 0, 1015 + CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 1016 + 0, 0, 5); 1000 1017 1001 1018 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 1002 1019 ata_tf_to_fis(&tf, pmp, 0, cfis); ··· 1027 1042 1028 1043 *class = sata_fsl_dev_classify(ap); 1029 1044 1030 - VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); 1031 - VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); 1045 + ata_port_dbg(ap, "ccreg = 0x%x\n", ioread32(hcr_base + CC)); 1046 + ata_port_dbg(ap, "cereg = 0x%x\n", ioread32(hcr_base + CE)); 1032 1047 } 1033 1048 1034 1049 return 0; ··· 1233 1248 return; 1234 1249 } 1235 1250 1236 - VPRINTK("Status of all queues :\n"); 1237 - VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n", 1251 + ata_port_dbg(ap, "Status of all queues :\n"); 1252 + ata_port_dbg(ap, "done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n", 1238 1253 done_mask, 1239 1254 ioread32(hcr_base + CA), 1240 1255 ioread32(hcr_base + CE), ··· 1452 1467 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG); 1453 1468 } 1454 1469 1455 - ata_port_dbg(ap, "@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); 1470 + dev_dbg(&ofdev->dev, "@reset i/o = 0x%x\n", 1471 + ioread32(csr_base + TRANSCFG)); 1456 1472 1457 1473 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); 1458 1474 if (!host_priv)