tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

mxser: convert large macros to functions

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Jiri Slaby <jirislaby@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

authored by

Christoph Hellwig and committed by
Linus Torvalds 148ff86b 12a3de0a

+214 -152
+214 -15
drivers/char/mxser.c
··· 307 307 static struct mxser_mon_ext mon_data_ext; 308 308 static int mxser_set_baud_method[MXSER_PORTS + 1]; 309 309 310 + static void mxser_enable_must_enchance_mode(unsigned long baseio) 311 + { 312 + u8 oldlcr; 313 + u8 efr; 314 + 315 + oldlcr = inb(baseio + UART_LCR); 316 + outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); 317 + 318 + efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 319 + efr |= MOXA_MUST_EFR_EFRB_ENABLE; 320 + 321 + outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 322 + outb(oldlcr, baseio + UART_LCR); 323 + } 324 + 325 + static void mxser_disable_must_enchance_mode(unsigned long baseio) 326 + { 327 + u8 oldlcr; 328 + u8 efr; 329 + 330 + oldlcr = inb(baseio + UART_LCR); 331 + outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); 332 + 333 + efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 334 + efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; 335 + 336 + outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 337 + outb(oldlcr, baseio + UART_LCR); 338 + } 339 + 340 + static void mxser_set_must_xon1_value(unsigned long baseio, u8 value) 341 + { 342 + u8 oldlcr; 343 + u8 efr; 344 + 345 + oldlcr = inb(baseio + UART_LCR); 346 + outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); 347 + 348 + efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 349 + efr &= ~MOXA_MUST_EFR_BANK_MASK; 350 + efr |= MOXA_MUST_EFR_BANK0; 351 + 352 + outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 353 + outb(value, baseio + MOXA_MUST_XON1_REGISTER); 354 + outb(oldlcr, baseio + UART_LCR); 355 + } 356 + 357 + static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value) 358 + { 359 + u8 oldlcr; 360 + u8 efr; 361 + 362 + oldlcr = inb(baseio + UART_LCR); 363 + outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); 364 + 365 + efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 366 + efr &= ~MOXA_MUST_EFR_BANK_MASK; 367 + efr |= MOXA_MUST_EFR_BANK0; 368 + 369 + outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 370 + outb(value, baseio + MOXA_MUST_XOFF1_REGISTER); 371 + outb(oldlcr, baseio + UART_LCR); 372 + } 373 + 374 + static void mxser_set_must_fifo_value(struct mxser_port *info) 375 + { 376 + u8 oldlcr; 377 + u8 efr; 378 + 379 + oldlcr = inb(info->ioaddr + UART_LCR); 380 + outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR); 381 + 382 + efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER); 383 + efr &= ~MOXA_MUST_EFR_BANK_MASK; 384 + efr |= MOXA_MUST_EFR_BANK1; 385 + 386 + outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER); 387 + outb((u8)info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER); 388 + outb((u8)info->rx_trigger, info->ioaddr + MOXA_MUST_RBRTI_REGISTER); 389 + outb((u8)info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER); 390 + outb(oldlcr, info->ioaddr + UART_LCR); 391 + } 392 + 393 + static void mxser_set_must_enum_value(unsigned long baseio, u8 value) 394 + { 395 + u8 oldlcr; 396 + u8 efr; 397 + 398 + oldlcr = inb(baseio + UART_LCR); 399 + outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); 400 + 401 + efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 402 + efr &= ~MOXA_MUST_EFR_BANK_MASK; 403 + efr |= MOXA_MUST_EFR_BANK2; 404 + 405 + outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 406 + outb(value, baseio + MOXA_MUST_ENUM_REGISTER); 407 + outb(oldlcr, baseio + UART_LCR); 408 + } 409 + 410 + static void mxser_get_must_hardware_id(unsigned long baseio, u8 *pId) 411 + { 412 + u8 oldlcr; 413 + u8 efr; 414 + 415 + oldlcr = inb(baseio + UART_LCR); 416 + outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); 417 + 418 + efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 419 + efr &= ~MOXA_MUST_EFR_BANK_MASK; 420 + efr |= MOXA_MUST_EFR_BANK2; 421 + 422 + outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 423 + *pId = inb(baseio + MOXA_MUST_HWID_REGISTER); 424 + outb(oldlcr, baseio + UART_LCR); 425 + } 426 + 427 + static void SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(unsigned long baseio) 428 + { 429 + u8 oldlcr; 430 + u8 efr; 431 + 432 + oldlcr = inb(baseio + UART_LCR); 433 + outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); 434 + 435 + efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 436 + efr &= ~MOXA_MUST_EFR_SF_MASK; 437 + 438 + outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 439 + outb(oldlcr, baseio + UART_LCR); 440 + } 441 + 442 + static void mxser_enable_must_tx_software_flow_control(unsigned long baseio) 443 + { 444 + u8 oldlcr; 445 + u8 efr; 446 + 447 + oldlcr = inb(baseio + UART_LCR); 448 + outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); 449 + 450 + efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 451 + efr &= ~MOXA_MUST_EFR_SF_TX_MASK; 452 + efr |= MOXA_MUST_EFR_SF_TX1; 453 + 454 + outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 455 + outb(oldlcr, baseio + UART_LCR); 456 + } 457 + 458 + static void mxser_disable_must_tx_software_flow_control(unsigned long baseio) 459 + { 460 + u8 oldlcr; 461 + u8 efr; 462 + 463 + oldlcr = inb(baseio + UART_LCR); 464 + outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); 465 + 466 + efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 467 + efr &= ~MOXA_MUST_EFR_SF_TX_MASK; 468 + 469 + outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 470 + outb(oldlcr, baseio + UART_LCR); 471 + } 472 + 473 + static void mxser_enable_must_rx_software_flow_control(unsigned long baseio) 474 + { 475 + u8 oldlcr; 476 + u8 efr; 477 + 478 + oldlcr = inb(baseio + UART_LCR); 479 + outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); 480 + 481 + efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 482 + efr &= ~MOXA_MUST_EFR_SF_RX_MASK; 483 + efr |= MOXA_MUST_EFR_SF_RX1; 484 + 485 + outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 486 + outb(oldlcr, baseio + UART_LCR); 487 + } 488 + 489 + static void mxser_disable_must_rx_software_flow_control(unsigned long baseio) 490 + { 491 + u8 oldlcr; 492 + u8 efr; 493 + 494 + oldlcr = inb(baseio + UART_LCR); 495 + outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR); 496 + 497 + efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 498 + efr &= ~MOXA_MUST_EFR_SF_RX_MASK; 499 + 500 + outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 501 + outb(oldlcr, baseio + UART_LCR); 502 + } 503 + 310 504 #ifdef CONFIG_PCI 311 505 static int __devinit CheckIsMoxaMust(unsigned long io) 312 506 { ··· 508 314 int i; 509 315 510 316 outb(0, io + UART_LCR); 511 - DISABLE_MOXA_MUST_ENCHANCE_MODE(io); 317 + mxser_disable_must_enchance_mode(io); 512 318 oldmcr = inb(io + UART_MCR); 513 319 outb(0, io + UART_MCR); 514 - SET_MOXA_MUST_XON1_VALUE(io, 0x11); 320 + mxser_set_must_xon1_value(io, 0x11); 515 321 if ((hwid = inb(io + UART_MCR)) != 0) { 516 322 outb(oldmcr, io + UART_MCR); 517 323 return MOXA_OTHER_UART; 518 324 } 519 325 520 - GET_MOXA_MUST_HARDWARE_ID(io, &hwid); 326 + mxser_get_must_hardware_id(io, &hwid); 521 327 for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */ 522 328 if (hwid == Gpci_uart_info[i].type) 523 329 return (int)hwid; ··· 688 494 } else 689 495 quot /= newspd; 690 496 691 - SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, quot); 497 + mxser_set_must_enum_value(info->ioaddr, quot); 692 498 } else 693 499 #endif 694 - SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, 0); 500 + mxser_set_must_enum_value(info->ioaddr, 0); 695 501 696 502 return 0; 697 503 } ··· 747 553 if (info->board->chip_flag) { 748 554 fcr = UART_FCR_ENABLE_FIFO; 749 555 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; 750 - SET_MOXA_MUST_FIFO_VALUE(info); 556 + mxser_set_must_fifo_value(info); 751 557 } else 752 558 fcr = 0; 753 559 } else { 754 560 fcr = UART_FCR_ENABLE_FIFO; 755 561 if (info->board->chip_flag) { 756 562 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; 757 - SET_MOXA_MUST_FIFO_VALUE(info); 563 + mxser_set_must_fifo_value(info); 758 564 } else { 759 565 switch (info->rx_trigger) { 760 566 case 1: ··· 851 657 } 852 658 } 853 659 if (info->board->chip_flag) { 854 - SET_MOXA_MUST_XON1_VALUE(info->ioaddr, START_CHAR(info->tty)); 855 - SET_MOXA_MUST_XOFF1_VALUE(info->ioaddr, STOP_CHAR(info->tty)); 660 + mxser_set_must_xon1_value(info->ioaddr, START_CHAR(info->tty)); 661 + mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(info->tty)); 856 662 if (I_IXON(info->tty)) { 857 - ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr); 663 + mxser_enable_must_rx_software_flow_control( 664 + info->ioaddr); 858 665 } else { 859 - DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr); 666 + mxser_disable_must_rx_software_flow_control( 667 + info->ioaddr); 860 668 } 861 669 if (I_IXOFF(info->tty)) { 862 - ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr); 670 + mxser_enable_must_tx_software_flow_control( 671 + info->ioaddr); 863 672 } else { 864 - DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr); 673 + mxser_disable_must_tx_software_flow_control( 674 + info->ioaddr); 865 675 } 866 676 } 867 677 ··· 2136 1938 2137 1939 if (info->board->chip_flag) { 2138 1940 spin_lock_irqsave(&info->slock, flags); 2139 - DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr); 1941 + mxser_disable_must_rx_software_flow_control( 1942 + info->ioaddr); 2140 1943 spin_unlock_irqrestore(&info->slock, flags); 2141 1944 } 2142 1945 ··· 2556 2357 2557 2358 /* Enhance mode enabled here */ 2558 2359 if (brd->chip_flag != MOXA_OTHER_UART) 2559 - ENABLE_MOXA_MUST_ENCHANCE_MODE(info->ioaddr); 2360 + mxser_enable_must_enchance_mode(info->ioaddr); 2560 2361 2561 2362 info->flags = ASYNC_SHARE_IRQ; 2562 2363 info->type = brd->uart_type;
-137
drivers/char/mxser.h
··· 147 147 /* Rx software flow control mask */ 148 148 #define MOXA_MUST_EFR_SF_RX_MASK 0x03 149 149 150 - #define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \ 151 - u8 __oldlcr, __efr; \ 152 - __oldlcr = inb((baseio)+UART_LCR); \ 153 - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 154 - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 155 - __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \ 156 - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 157 - outb(__oldlcr, (baseio)+UART_LCR); \ 158 - } while (0) 159 - 160 - #define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \ 161 - u8 __oldlcr, __efr; \ 162 - __oldlcr = inb((baseio)+UART_LCR); \ 163 - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 164 - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 165 - __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \ 166 - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 167 - outb(__oldlcr, (baseio)+UART_LCR); \ 168 - } while (0) 169 - 170 - #define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \ 171 - u8 __oldlcr, __efr; \ 172 - __oldlcr = inb((baseio)+UART_LCR); \ 173 - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 174 - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 175 - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 176 - __efr |= MOXA_MUST_EFR_BANK0; \ 177 - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 178 - outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \ 179 - outb(__oldlcr, (baseio)+UART_LCR); \ 180 - } while (0) 181 - 182 - #define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \ 183 - u8 __oldlcr, __efr; \ 184 - __oldlcr = inb((baseio)+UART_LCR); \ 185 - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 186 - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 187 - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 188 - __efr |= MOXA_MUST_EFR_BANK0; \ 189 - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 190 - outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \ 191 - outb(__oldlcr, (baseio)+UART_LCR); \ 192 - } while (0) 193 - 194 - #define SET_MOXA_MUST_FIFO_VALUE(info) do { \ 195 - u8 __oldlcr, __efr; \ 196 - __oldlcr = inb((info)->ioaddr+UART_LCR); \ 197 - outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\ 198 - __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \ 199 - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 200 - __efr |= MOXA_MUST_EFR_BANK1; \ 201 - outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \ 202 - outb((u8)((info)->rx_high_water), (info)->ioaddr+ \ 203 - MOXA_MUST_RBRTH_REGISTER); \ 204 - outb((u8)((info)->rx_trigger), (info)->ioaddr+ \ 205 - MOXA_MUST_RBRTI_REGISTER); \ 206 - outb((u8)((info)->rx_low_water), (info)->ioaddr+ \ 207 - MOXA_MUST_RBRTL_REGISTER); \ 208 - outb(__oldlcr, (info)->ioaddr+UART_LCR); \ 209 - } while (0) 210 - 211 - #define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do { \ 212 - u8 __oldlcr, __efr; \ 213 - __oldlcr = inb((baseio)+UART_LCR); \ 214 - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 215 - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 216 - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 217 - __efr |= MOXA_MUST_EFR_BANK2; \ 218 - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 219 - outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \ 220 - outb(__oldlcr, (baseio)+UART_LCR); \ 221 - } while (0) 222 - 223 - #define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \ 224 - u8 __oldlcr, __efr; \ 225 - __oldlcr = inb((baseio)+UART_LCR); \ 226 - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 227 - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 228 - __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 229 - __efr |= MOXA_MUST_EFR_BANK2; \ 230 - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 231 - *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \ 232 - outb(__oldlcr, (baseio)+UART_LCR); \ 233 - } while (0) 234 - 235 - #define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \ 236 - u8 __oldlcr, __efr; \ 237 - __oldlcr = inb((baseio)+UART_LCR); \ 238 - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 239 - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 240 - __efr &= ~MOXA_MUST_EFR_SF_MASK; \ 241 - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 242 - outb(__oldlcr, (baseio)+UART_LCR); \ 243 - } while (0) 244 - 245 - #define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \ 246 - u8 __oldlcr, __efr; \ 247 - __oldlcr = inb((baseio)+UART_LCR); \ 248 - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 249 - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 250 - __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ 251 - __efr |= MOXA_MUST_EFR_SF_TX1; \ 252 - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 253 - outb(__oldlcr, (baseio)+UART_LCR); \ 254 - } while (0) 255 - 256 - #define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \ 257 - u8 __oldlcr, __efr; \ 258 - __oldlcr = inb((baseio)+UART_LCR); \ 259 - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 260 - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 261 - __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ 262 - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 263 - outb(__oldlcr, (baseio)+UART_LCR); \ 264 - } while (0) 265 - 266 - #define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \ 267 - u8 __oldlcr, __efr; \ 268 - __oldlcr = inb((baseio)+UART_LCR); \ 269 - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 270 - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 271 - __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ 272 - __efr |= MOXA_MUST_EFR_SF_RX1; \ 273 - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 274 - outb(__oldlcr, (baseio)+UART_LCR); \ 275 - } while (0) 276 - 277 - #define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \ 278 - u8 __oldlcr, __efr; \ 279 - __oldlcr = inb((baseio)+UART_LCR); \ 280 - outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 281 - __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 282 - __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ 283 - outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 284 - outb(__oldlcr, (baseio)+UART_LCR); \ 285 - } while (0) 286 - 287 150 #endif