tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: starfive: Rename "jh7100" to "jh71x0" for the common code
Rename some variables from "jh7100" or "JH7100" to "jh71x0"
or "JH71X0".
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
authored by
Emil Renner Berthing
and committed by
Conor Dooley
147455ed
e19aa786
+418
-406
+36
-36
drivers/clk/starfive/clk-starfive-jh7100-audio.c
+36
-36
drivers/clk/starfive/clk-starfive-jh7100-audio.c
···
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28
#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6)
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#define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7)
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31
-
static const struct jh7100_clk_data jh7100_audclk_data[] = {
32
-
JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
31
+
static const struct jh71x0_clk_data jh7100_audclk_data[] = {
32
+
JH71X0__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
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JH7100_AUDCLK_AUDIO_SRC,
34
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JH7100_AUDCLK_AUDIO_12288),
35
-
JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
35
+
JH71X0__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
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JH7100_AUDCLK_AUDIO_SRC,
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JH7100_AUDCLK_AUDIO_12288),
38
-
JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
39
-
JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
38
+
JH71X0_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
39
+
JH71X0_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
40
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JH7100_AUDCLK_ADC_MCLK,
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JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
42
-
JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
43
-
JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
42
+
JH71X0__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
43
+
JH71X0_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
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JH7100_AUDCLK_I2SADC_BCLK_N,
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JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
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JH7100_AUDCLK_I2SADC_BCLK),
47
-
JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
48
-
JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
47
+
JH71X0_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
48
+
JH71X0__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
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JH7100_AUDCLK_AUDIO_SRC,
50
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JH7100_AUDCLK_AUDIO_12288),
51
-
JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
52
-
JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
51
+
JH71X0_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
52
+
JH71X0__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
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JH7100_AUDCLK_AUDIO_SRC,
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JH7100_AUDCLK_AUDIO_12288),
55
-
JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
56
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JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
57
-
JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
55
+
JH71X0_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
56
+
JH71X0_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
57
+
JH71X0__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
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JH7100_AUDCLK_AUDIO_SRC,
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JH7100_AUDCLK_AUDIO_12288),
60
-
JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
61
-
JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
60
+
JH71X0_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
61
+
JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
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JH7100_AUDCLK_DAC_MCLK,
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JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
64
-
JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
65
-
JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
64
+
JH71X0__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
65
+
JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
66
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JH7100_AUDCLK_I2S1_MCLK,
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JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
68
-
JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
69
-
JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
68
+
JH71X0_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
69
+
JH71X0_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
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JH7100_AUDCLK_I2S1_MCLK,
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JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
72
-
JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
73
-
JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
72
+
JH71X0__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
73
+
JH71X0_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
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JH7100_AUDCLK_I2S1_BCLK_N,
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JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
76
-
JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
77
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JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
78
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JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
79
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JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
80
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JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
81
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JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
82
-
JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
83
-
JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
76
+
JH71X0_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
77
+
JH71X0__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
78
+
JH71X0_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
79
+
JH71X0_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
80
+
JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
81
+
JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
82
+
JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
83
+
JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
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JH7100_AUDCLK_VAD_INTMEM,
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JH7100_AUDCLK_AUDIO_12288),
86
86
};
87
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static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
89
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{
90
-
struct jh7100_clk_priv *priv = data;
90
+
struct jh71x0_clk_priv *priv = data;
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unsigned int idx = clkspec->args[0];
92
92
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if (idx < JH7100_AUDCLK_END)
···
98
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static int jh7100_audclk_probe(struct platform_device *pdev)
100
100
{
101
-
struct jh7100_clk_priv *priv;
101
+
struct jh71x0_clk_priv *priv;
102
102
unsigned int idx;
103
103
int ret;
104
104
···
117
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struct clk_parent_data parents[4] = {};
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struct clk_init_data init = {
119
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.name = jh7100_audclk_data[idx].name,
120
-
.ops = starfive_jh7100_clk_ops(max),
120
+
.ops = starfive_jh71x0_clk_ops(max),
121
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.parent_data = parents,
122
-
.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
122
+
.num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
123
123
.flags = jh7100_audclk_data[idx].flags,
124
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};
125
-
struct jh7100_clk *clk = &priv->reg[idx];
125
+
struct jh71x0_clk *clk = &priv->reg[idx];
126
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unsigned int i;
127
127
128
128
for (i = 0; i < init.num_parents; i++) {
···
140
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141
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clk->hw.init = &init;
142
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clk->idx = idx;
143
-
clk->max_div = max & JH7100_CLK_DIV_MASK;
143
+
clk->max_div = max & JH71X0_CLK_DIV_MASK;
144
144
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ret = devm_clk_hw_register(priv->dev, &clk->hw);
146
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if (ret)
+196
-193
drivers/clk/starfive/clk-starfive-jh7100.c
+196
-193
drivers/clk/starfive/clk-starfive-jh7100.c
···
23
23
#define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2)
24
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#define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3)
25
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26
-
static const struct jh7100_clk_data jh7100_clk_data[] __initconst = {
27
-
JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
26
+
static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
27
+
JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
28
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JH7100_CLK_OSC_SYS,
29
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JH7100_CLK_PLL0_OUT,
30
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JH7100_CLK_PLL1_OUT,
31
31
JH7100_CLK_PLL2_OUT),
32
-
JH7100__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
32
+
JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
33
33
JH7100_CLK_OSC_SYS,
34
34
JH7100_CLK_PLL1_OUT,
35
35
JH7100_CLK_PLL2_OUT),
36
-
JH7100__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
36
+
JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
37
37
JH7100_CLK_OSC_SYS,
38
38
JH7100_CLK_PLL0_OUT,
39
39
JH7100_CLK_PLL1_OUT,
40
40
JH7100_CLK_PLL2_OUT),
41
-
JH7100__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
41
+
JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
42
42
JH7100_CLK_OSC_SYS,
43
43
JH7100_CLK_PLL0_OUT,
44
44
JH7100_CLK_PLL2_OUT),
45
-
JH7100__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
45
+
JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
46
46
JH7100_CLK_OSC_SYS,
47
47
JH7100_CLK_PLL0_OUT),
48
-
JH7100__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
48
+
JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
49
49
JH7100_CLK_OSC_SYS,
50
50
JH7100_CLK_PLL2_OUT),
51
-
JH7100__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
51
+
JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
52
52
JH7100_CLK_OSC_SYS,
53
53
JH7100_CLK_PLL1_OUT,
54
54
JH7100_CLK_PLL2_OUT),
55
-
JH7100__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
55
+
JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
56
56
JH7100_CLK_OSC_AUD,
57
57
JH7100_CLK_PLL0_OUT,
58
58
JH7100_CLK_PLL2_OUT),
59
-
JH7100_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
60
-
JH7100__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
59
+
JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
60
+
JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
61
61
JH7100_CLK_OSC_SYS,
62
62
JH7100_CLK_PLL1_OUT,
63
63
JH7100_CLK_PLL2_OUT),
64
-
JH7100__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
64
+
JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
65
65
JH7100_CLK_OSC_SYS,
66
66
JH7100_CLK_PLL0_OUT,
67
67
JH7100_CLK_PLL1_OUT),
68
-
JH7100__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
68
+
JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
69
69
JH7100_CLK_OSC_AUD,
70
70
JH7100_CLK_PLL0_OUT,
71
71
JH7100_CLK_PLL2_OUT),
72
-
JH7100__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
73
-
JH7100__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
74
-
JH7100__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
75
-
JH7100__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
76
-
JH7100_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
77
-
JH7100_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
78
-
JH7100_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
79
-
JH7100__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
72
+
JH71X0__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
73
+
JH71X0__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
74
+
JH71X0__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
75
+
JH71X0__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
76
+
JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
77
+
JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
78
+
JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
79
+
JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
80
80
JH7100_CLK_OSC_SYS,
81
81
JH7100_CLK_OSC_AUD),
82
-
JH7100__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
83
-
JH7100__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
84
-
JH7100__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
85
-
JH7100__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
86
-
JH7100__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
87
-
JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
88
-
JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
89
-
JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
90
-
JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
91
-
JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
92
-
JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
93
-
JH7100_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
94
-
JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
95
-
JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
96
-
JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
97
-
JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
98
-
JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
99
-
JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
100
-
JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
101
-
JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
102
-
JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
103
-
JH7100__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
104
-
JH7100__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
105
-
JH7100_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
106
-
JH7100_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
107
-
JH7100_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
108
-
JH7100_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
109
-
JH7100_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
110
-
JH7100_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
111
-
JH7100_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
112
-
JH7100_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
113
-
JH7100_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
114
-
JH7100_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
115
-
JH7100__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
116
-
JH7100_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
117
-
JH7100_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
118
-
JH7100__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
119
-
JH7100_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
120
-
JH7100_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
121
-
JH7100_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
122
-
JH7100_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
123
-
JH7100_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
124
-
JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
125
-
JH7100_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2),
126
-
JH7100_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4),
127
-
JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
128
-
JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
82
+
JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
83
+
JH71X0__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
84
+
JH71X0__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
85
+
JH71X0__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
86
+
JH71X0__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
87
+
JH71X0_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
88
+
JH71X0_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
89
+
JH71X0_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
90
+
JH71X0_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
91
+
JH71X0_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
92
+
JH71X0_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
93
+
JH71X0_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
94
+
JH71X0_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
95
+
JH71X0_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
96
+
JH71X0__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
97
+
JH71X0_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
98
+
JH71X0_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
99
+
JH71X0_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
100
+
JH71X0_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
101
+
JH71X0__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
102
+
JH71X0_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
103
+
JH71X0__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
104
+
JH71X0__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
105
+
JH71X0_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
106
+
JH71X0_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
107
+
JH71X0_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
108
+
JH71X0_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
109
+
JH71X0_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
110
+
JH71X0_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
111
+
JH71X0_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
112
+
JH71X0_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
113
+
JH71X0_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
114
+
JH71X0_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
115
+
JH71X0__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
116
+
JH71X0_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
117
+
JH71X0_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
118
+
JH71X0__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
119
+
JH71X0_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
120
+
JH71X0_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
121
+
JH71X0_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
122
+
JH71X0_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
123
+
JH71X0_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
124
+
JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
125
+
JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2,
126
+
JH7100_CLK_DDRPLL_DIV2),
127
+
JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2,
128
+
JH7100_CLK_DDRPLL_DIV4),
129
+
JH71X0_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
130
+
JH71X0_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
129
131
JH7100_CLK_DDROSC_DIV2,
130
132
JH7100_CLK_DDRPLL_DIV2,
131
133
JH7100_CLK_DDRPLL_DIV4,
132
134
JH7100_CLK_DDRPLL_DIV8),
133
-
JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
135
+
JH71X0_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
134
136
JH7100_CLK_DDROSC_DIV2,
135
137
JH7100_CLK_DDRPLL_DIV2,
136
138
JH7100_CLK_DDRPLL_DIV4,
137
139
JH7100_CLK_DDRPLL_DIV8),
138
-
JH7100_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
139
-
JH7100__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
140
-
JH7100__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
141
-
JH7100_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
142
-
JH7100__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
143
-
JH7100__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
140
+
JH71X0_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
141
+
JH71X0__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
142
+
JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
143
+
JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
144
+
JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
145
+
JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
144
146
JH7100_CLK_CPU_AXI,
145
147
JH7100_CLK_NNEBUS_SRC1),
146
-
JH7100_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
147
-
JH7100_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
148
-
JH7100_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
149
-
JH7100_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
150
-
JH7100__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
151
-
JH7100__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
152
-
JH7100_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
153
-
JH7100__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
154
-
JH7100_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
155
-
JH7100_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
156
-
JH7100__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
157
-
JH7100_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
158
-
JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
159
-
JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
160
-
JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
161
-
JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
162
-
JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
163
-
JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
164
-
JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
165
-
JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV),
166
-
JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
148
+
JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
149
+
JH71X0_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
150
+
JH71X0_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
151
+
JH71X0_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
152
+
JH71X0__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
153
+
JH71X0__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
154
+
JH71X0_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
155
+
JH71X0__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
156
+
JH71X0_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
157
+
JH71X0_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
158
+
JH71X0__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
159
+
JH71X0_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
160
+
JH71X0_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
161
+
JH71X0_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
162
+
JH71X0__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
163
+
JH71X0_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
164
+
JH71X0_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
165
+
JH71X0__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
166
+
JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
167
+
JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
168
+
JH7100_CLK_USBPHY_ROOTDIV),
169
+
JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
167
170
JH7100_CLK_OSC_SYS,
168
171
JH7100_CLK_USBPHY_PLLDIV25M),
169
-
JH7100_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
170
-
JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
171
-
JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
172
-
JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
173
-
JH7100__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
174
-
JH7100_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
175
-
JH7100_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
176
-
JH7100_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
177
-
JH7100__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
178
-
JH7100_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
179
-
JH7100_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
180
-
JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
181
-
JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
182
-
JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
183
-
JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
184
-
JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
185
-
JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
186
-
JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
187
-
JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
188
-
JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
189
-
JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
190
-
JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
191
-
JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
192
-
JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
193
-
JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
194
-
JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
195
-
JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
196
-
JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
197
-
JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
198
-
JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
199
-
JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
200
-
JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
172
+
JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
173
+
JH71X0_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
174
+
JH71X0_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
175
+
JH71X0_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
176
+
JH71X0__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
177
+
JH71X0_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
178
+
JH71X0_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
179
+
JH71X0_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
180
+
JH71X0__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
181
+
JH71X0_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
182
+
JH71X0_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
183
+
JH71X0__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
184
+
JH71X0_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
185
+
JH71X0_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
186
+
JH71X0_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
187
+
JH71X0__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
188
+
JH71X0__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
189
+
JH71X0_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
190
+
JH71X0_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
191
+
JH71X0_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
192
+
JH71X0_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
193
+
JH71X0__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
194
+
JH71X0_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
195
+
JH71X0_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
196
+
JH71X0__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
197
+
JH71X0_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
198
+
JH71X0__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
199
+
JH71X0_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
200
+
JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
201
+
JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
202
+
JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
203
+
JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
201
204
JH7100_CLK_GMAC_GTX,
202
205
JH7100_CLK_GMAC_TX_INV,
203
206
JH7100_CLK_GMAC_RMII_TX),
204
-
JH7100__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
205
-
JH7100__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
207
+
JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
208
+
JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
206
209
JH7100_CLK_GMAC_GR_MII_RX,
207
210
JH7100_CLK_GMAC_RMII_RX),
208
-
JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
209
-
JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
210
-
JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
211
-
JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
212
-
JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
213
-
JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
214
-
JH7100_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
215
-
JH7100_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
216
-
JH7100_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
217
-
JH7100_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
218
-
JH7100_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
219
-
JH7100_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
220
-
JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
221
-
JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
222
-
JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
223
-
JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
224
-
JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
225
-
JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
226
-
JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
227
-
JH7100_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
228
-
JH7100_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
229
-
JH7100_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
230
-
JH7100_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
231
-
JH7100_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
232
-
JH7100_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
233
-
JH7100_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
234
-
JH7100_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
235
-
JH7100_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
236
-
JH7100_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
237
-
JH7100_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
238
-
JH7100_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
239
-
JH7100_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
240
-
JH7100_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
241
-
JH7100_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
242
-
JH7100_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
243
-
JH7100_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
244
-
JH7100_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
245
-
JH7100_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
246
-
JH7100_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
247
-
JH7100_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
248
-
JH7100_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
249
-
JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
250
-
JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
251
-
JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
252
-
JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
253
-
JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
254
-
JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
255
-
JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
256
-
JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
257
-
JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
258
-
JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
259
-
JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
260
-
JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
261
-
JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
262
-
JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
263
-
JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
264
-
JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
211
+
JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
212
+
JH71X0_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
213
+
JH71X0_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
214
+
JH71X0_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
215
+
JH71X0_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
216
+
JH71X0_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
217
+
JH71X0_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
218
+
JH71X0_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
219
+
JH71X0_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
220
+
JH71X0_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
221
+
JH71X0_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
222
+
JH71X0_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
223
+
JH71X0_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
224
+
JH71X0_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
225
+
JH71X0_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
226
+
JH71X0_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
227
+
JH71X0_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
228
+
JH71X0_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
229
+
JH71X0_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
230
+
JH71X0_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
231
+
JH71X0_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
232
+
JH71X0_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
233
+
JH71X0_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
234
+
JH71X0_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
235
+
JH71X0_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
236
+
JH71X0_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
237
+
JH71X0_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
238
+
JH71X0_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
239
+
JH71X0_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
240
+
JH71X0_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
241
+
JH71X0_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
242
+
JH71X0_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
243
+
JH71X0_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
244
+
JH71X0_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
245
+
JH71X0_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
246
+
JH71X0_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
247
+
JH71X0_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
248
+
JH71X0_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
249
+
JH71X0_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
250
+
JH71X0_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
251
+
JH71X0_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
252
+
JH71X0_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
253
+
JH71X0_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
254
+
JH71X0_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
255
+
JH71X0_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
256
+
JH71X0_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
257
+
JH71X0_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
258
+
JH71X0_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
259
+
JH71X0_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
260
+
JH71X0_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
261
+
JH71X0_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
262
+
JH71X0_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
263
+
JH71X0_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
264
+
JH71X0_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
265
+
JH71X0_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
266
+
JH71X0_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
267
+
JH71X0_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
265
268
};
266
269
267
270
static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
268
271
{
269
-
struct jh7100_clk_priv *priv = data;
272
+
struct jh71x0_clk_priv *priv = data;
270
273
unsigned int idx = clkspec->args[0];
271
274
272
275
if (idx < JH7100_CLK_PLL0_OUT)
···
283
280
284
281
static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
285
282
{
286
-
struct jh7100_clk_priv *priv;
283
+
struct jh71x0_clk_priv *priv;
287
284
unsigned int idx;
288
285
int ret;
289
286
···
317
314
struct clk_parent_data parents[4] = {};
318
315
struct clk_init_data init = {
319
316
.name = jh7100_clk_data[idx].name,
320
-
.ops = starfive_jh7100_clk_ops(max),
317
+
.ops = starfive_jh71x0_clk_ops(max),
321
318
.parent_data = parents,
322
-
.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
319
+
.num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
323
320
.flags = jh7100_clk_data[idx].flags,
324
321
};
325
-
struct jh7100_clk *clk = &priv->reg[idx];
322
+
struct jh71x0_clk *clk = &priv->reg[idx];
326
323
unsigned int i;
327
324
328
325
for (i = 0; i < init.num_parents; i++) {
···
344
341
345
342
clk->hw.init = &init;
346
343
clk->idx = idx;
347
-
clk->max_div = max & JH7100_CLK_DIV_MASK;
344
+
clk->max_div = max & JH71X0_CLK_DIV_MASK;
348
345
349
346
ret = devm_clk_hw_register(priv->dev, &clk->hw);
350
347
if (ret)
+141
-141
drivers/clk/starfive/clk-starfive-jh71x0.c
+141
-141
drivers/clk/starfive/clk-starfive-jh71x0.c
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
/*
3
-
* StarFive JH7100 Clock Generator Driver
3
+
* StarFive JH71X0 Clock Generator Driver
4
4
*
5
5
* Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
6
6
*/
···
12
12
13
13
#include "clk-starfive-jh71x0.h"
14
14
15
-
static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
15
+
static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)
16
16
{
17
-
return container_of(hw, struct jh7100_clk, hw);
17
+
return container_of(hw, struct jh71x0_clk, hw);
18
18
}
19
19
20
-
static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)
20
+
static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk)
21
21
{
22
-
return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);
22
+
return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]);
23
23
}
24
24
25
-
static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)
25
+
static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk)
26
26
{
27
-
struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
27
+
struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
28
28
void __iomem *reg = priv->base + 4 * clk->idx;
29
29
30
30
return readl_relaxed(reg);
31
31
}
32
32
33
-
static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
33
+
static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value)
34
34
{
35
-
struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
35
+
struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
36
36
void __iomem *reg = priv->base + 4 * clk->idx;
37
37
unsigned long flags;
38
38
···
42
42
spin_unlock_irqrestore(&priv->rmw_lock, flags);
43
43
}
44
44
45
-
static int jh7100_clk_enable(struct clk_hw *hw)
45
+
static int jh71x0_clk_enable(struct clk_hw *hw)
46
46
{
47
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
47
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
48
48
49
-
jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);
49
+
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, JH71X0_CLK_ENABLE);
50
50
return 0;
51
51
}
52
52
53
-
static void jh7100_clk_disable(struct clk_hw *hw)
53
+
static void jh71x0_clk_disable(struct clk_hw *hw)
54
54
{
55
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
55
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
56
56
57
-
jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);
57
+
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, 0);
58
58
}
59
59
60
-
static int jh7100_clk_is_enabled(struct clk_hw *hw)
60
+
static int jh71x0_clk_is_enabled(struct clk_hw *hw)
61
61
{
62
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
62
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
63
63
64
-
return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);
64
+
return !!(jh71x0_clk_reg_get(clk) & JH71X0_CLK_ENABLE);
65
65
}
66
66
67
-
static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
67
+
static unsigned long jh71x0_clk_recalc_rate(struct clk_hw *hw,
68
68
unsigned long parent_rate)
69
69
{
70
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
71
-
u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;
70
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
71
+
u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK;
72
72
73
73
return div ? parent_rate / div : 0;
74
74
}
75
75
76
-
static int jh7100_clk_determine_rate(struct clk_hw *hw,
76
+
static int jh71x0_clk_determine_rate(struct clk_hw *hw,
77
77
struct clk_rate_request *req)
78
78
{
79
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
79
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
80
80
unsigned long parent = req->best_parent_rate;
81
81
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
82
82
unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
···
102
102
return 0;
103
103
}
104
104
105
-
static int jh7100_clk_set_rate(struct clk_hw *hw,
105
+
static int jh71x0_clk_set_rate(struct clk_hw *hw,
106
106
unsigned long rate,
107
107
unsigned long parent_rate)
108
108
{
109
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
109
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
110
110
unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
111
111
1UL, (unsigned long)clk->max_div);
112
112
113
-
jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
113
+
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div);
114
114
return 0;
115
115
}
116
116
117
-
static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw,
117
+
static unsigned long jh71x0_clk_frac_recalc_rate(struct clk_hw *hw,
118
118
unsigned long parent_rate)
119
119
{
120
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
121
-
u32 reg = jh7100_clk_reg_get(clk);
122
-
unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) +
123
-
((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT);
120
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
121
+
u32 reg = jh71x0_clk_reg_get(clk);
122
+
unsigned long div100 = 100 * (reg & JH71X0_CLK_INT_MASK) +
123
+
((reg & JH71X0_CLK_FRAC_MASK) >> JH71X0_CLK_FRAC_SHIFT);
124
124
125
-
return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
125
+
return (div100 >= JH71X0_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
126
126
}
127
127
128
-
static int jh7100_clk_frac_determine_rate(struct clk_hw *hw,
128
+
static int jh71x0_clk_frac_determine_rate(struct clk_hw *hw,
129
129
struct clk_rate_request *req)
130
130
{
131
131
unsigned long parent100 = 100 * req->best_parent_rate;
132
132
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
133
133
unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
134
-
JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
134
+
JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
135
135
unsigned long result = parent100 / div100;
136
136
137
-
/* clamp the result as in jh7100_clk_determine_rate() above */
138
-
if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX)
137
+
/* clamp the result as in jh71x0_clk_determine_rate() above */
138
+
if (result > req->max_rate && div100 < JH71X0_CLK_FRAC_MAX)
139
139
result = parent100 / (div100 + 1);
140
-
if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN)
140
+
if (result < req->min_rate && div100 > JH71X0_CLK_FRAC_MIN)
141
141
result = parent100 / (div100 - 1);
142
142
143
143
req->rate = result;
144
144
return 0;
145
145
}
146
146
147
-
static int jh7100_clk_frac_set_rate(struct clk_hw *hw,
147
+
static int jh71x0_clk_frac_set_rate(struct clk_hw *hw,
148
148
unsigned long rate,
149
149
unsigned long parent_rate)
150
150
{
151
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
151
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
152
152
unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
153
-
JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
154
-
u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100);
153
+
JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
154
+
u32 value = ((div100 % 100) << JH71X0_CLK_FRAC_SHIFT) | (div100 / 100);
155
155
156
-
jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value);
156
+
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value);
157
157
return 0;
158
158
}
159
159
160
-
static u8 jh7100_clk_get_parent(struct clk_hw *hw)
160
+
static u8 jh71x0_clk_get_parent(struct clk_hw *hw)
161
161
{
162
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
163
-
u32 value = jh7100_clk_reg_get(clk);
162
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
163
+
u32 value = jh71x0_clk_reg_get(clk);
164
164
165
-
return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;
165
+
return (value & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT;
166
166
}
167
167
168
-
static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)
168
+
static int jh71x0_clk_set_parent(struct clk_hw *hw, u8 index)
169
169
{
170
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
171
-
u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;
170
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
171
+
u32 value = (u32)index << JH71X0_CLK_MUX_SHIFT;
172
172
173
-
jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);
173
+
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, value);
174
174
return 0;
175
175
}
176
176
177
-
static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,
177
+
static int jh71x0_clk_mux_determine_rate(struct clk_hw *hw,
178
178
struct clk_rate_request *req)
179
179
{
180
180
return clk_mux_determine_rate_flags(hw, req, 0);
181
181
}
182
182
183
-
static int jh7100_clk_get_phase(struct clk_hw *hw)
183
+
static int jh71x0_clk_get_phase(struct clk_hw *hw)
184
184
{
185
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
186
-
u32 value = jh7100_clk_reg_get(clk);
185
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
186
+
u32 value = jh71x0_clk_reg_get(clk);
187
187
188
-
return (value & JH7100_CLK_INVERT) ? 180 : 0;
188
+
return (value & JH71X0_CLK_INVERT) ? 180 : 0;
189
189
}
190
190
191
-
static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)
191
+
static int jh71x0_clk_set_phase(struct clk_hw *hw, int degrees)
192
192
{
193
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
193
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
194
194
u32 value;
195
195
196
196
if (degrees == 0)
197
197
value = 0;
198
198
else if (degrees == 180)
199
-
value = JH7100_CLK_INVERT;
199
+
value = JH71X0_CLK_INVERT;
200
200
else
201
201
return -EINVAL;
202
202
203
-
jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);
203
+
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, value);
204
204
return 0;
205
205
}
206
206
207
207
#ifdef CONFIG_DEBUG_FS
208
-
static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
208
+
static void jh71x0_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
209
209
{
210
-
static const struct debugfs_reg32 jh7100_clk_reg = {
210
+
static const struct debugfs_reg32 jh71x0_clk_reg = {
211
211
.name = "CTRL",
212
212
.offset = 0,
213
213
};
214
-
struct jh7100_clk *clk = jh7100_clk_from(hw);
215
-
struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
214
+
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
215
+
struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
216
216
struct debugfs_regset32 *regset;
217
217
218
218
regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
219
219
if (!regset)
220
220
return;
221
221
222
-
regset->regs = &jh7100_clk_reg;
222
+
regset->regs = &jh71x0_clk_reg;
223
223
regset->nregs = 1;
224
224
regset->base = priv->base + 4 * clk->idx;
225
225
226
226
debugfs_create_regset32("registers", 0400, dentry, regset);
227
227
}
228
228
#else
229
-
#define jh7100_clk_debug_init NULL
229
+
#define jh71x0_clk_debug_init NULL
230
230
#endif
231
231
232
-
static const struct clk_ops jh7100_clk_gate_ops = {
233
-
.enable = jh7100_clk_enable,
234
-
.disable = jh7100_clk_disable,
235
-
.is_enabled = jh7100_clk_is_enabled,
236
-
.debug_init = jh7100_clk_debug_init,
232
+
static const struct clk_ops jh71x0_clk_gate_ops = {
233
+
.enable = jh71x0_clk_enable,
234
+
.disable = jh71x0_clk_disable,
235
+
.is_enabled = jh71x0_clk_is_enabled,
236
+
.debug_init = jh71x0_clk_debug_init,
237
237
};
238
238
239
-
static const struct clk_ops jh7100_clk_div_ops = {
240
-
.recalc_rate = jh7100_clk_recalc_rate,
241
-
.determine_rate = jh7100_clk_determine_rate,
242
-
.set_rate = jh7100_clk_set_rate,
243
-
.debug_init = jh7100_clk_debug_init,
239
+
static const struct clk_ops jh71x0_clk_div_ops = {
240
+
.recalc_rate = jh71x0_clk_recalc_rate,
241
+
.determine_rate = jh71x0_clk_determine_rate,
242
+
.set_rate = jh71x0_clk_set_rate,
243
+
.debug_init = jh71x0_clk_debug_init,
244
244
};
245
245
246
-
static const struct clk_ops jh7100_clk_fdiv_ops = {
247
-
.recalc_rate = jh7100_clk_frac_recalc_rate,
248
-
.determine_rate = jh7100_clk_frac_determine_rate,
249
-
.set_rate = jh7100_clk_frac_set_rate,
250
-
.debug_init = jh7100_clk_debug_init,
246
+
static const struct clk_ops jh71x0_clk_fdiv_ops = {
247
+
.recalc_rate = jh71x0_clk_frac_recalc_rate,
248
+
.determine_rate = jh71x0_clk_frac_determine_rate,
249
+
.set_rate = jh71x0_clk_frac_set_rate,
250
+
.debug_init = jh71x0_clk_debug_init,
251
251
};
252
252
253
-
static const struct clk_ops jh7100_clk_gdiv_ops = {
254
-
.enable = jh7100_clk_enable,
255
-
.disable = jh7100_clk_disable,
256
-
.is_enabled = jh7100_clk_is_enabled,
257
-
.recalc_rate = jh7100_clk_recalc_rate,
258
-
.determine_rate = jh7100_clk_determine_rate,
259
-
.set_rate = jh7100_clk_set_rate,
260
-
.debug_init = jh7100_clk_debug_init,
253
+
static const struct clk_ops jh71x0_clk_gdiv_ops = {
254
+
.enable = jh71x0_clk_enable,
255
+
.disable = jh71x0_clk_disable,
256
+
.is_enabled = jh71x0_clk_is_enabled,
257
+
.recalc_rate = jh71x0_clk_recalc_rate,
258
+
.determine_rate = jh71x0_clk_determine_rate,
259
+
.set_rate = jh71x0_clk_set_rate,
260
+
.debug_init = jh71x0_clk_debug_init,
261
261
};
262
262
263
-
static const struct clk_ops jh7100_clk_mux_ops = {
264
-
.determine_rate = jh7100_clk_mux_determine_rate,
265
-
.set_parent = jh7100_clk_set_parent,
266
-
.get_parent = jh7100_clk_get_parent,
267
-
.debug_init = jh7100_clk_debug_init,
263
+
static const struct clk_ops jh71x0_clk_mux_ops = {
264
+
.determine_rate = jh71x0_clk_mux_determine_rate,
265
+
.set_parent = jh71x0_clk_set_parent,
266
+
.get_parent = jh71x0_clk_get_parent,
267
+
.debug_init = jh71x0_clk_debug_init,
268
268
};
269
269
270
-
static const struct clk_ops jh7100_clk_gmux_ops = {
271
-
.enable = jh7100_clk_enable,
272
-
.disable = jh7100_clk_disable,
273
-
.is_enabled = jh7100_clk_is_enabled,
274
-
.determine_rate = jh7100_clk_mux_determine_rate,
275
-
.set_parent = jh7100_clk_set_parent,
276
-
.get_parent = jh7100_clk_get_parent,
277
-
.debug_init = jh7100_clk_debug_init,
270
+
static const struct clk_ops jh71x0_clk_gmux_ops = {
271
+
.enable = jh71x0_clk_enable,
272
+
.disable = jh71x0_clk_disable,
273
+
.is_enabled = jh71x0_clk_is_enabled,
274
+
.determine_rate = jh71x0_clk_mux_determine_rate,
275
+
.set_parent = jh71x0_clk_set_parent,
276
+
.get_parent = jh71x0_clk_get_parent,
277
+
.debug_init = jh71x0_clk_debug_init,
278
278
};
279
279
280
-
static const struct clk_ops jh7100_clk_mdiv_ops = {
281
-
.recalc_rate = jh7100_clk_recalc_rate,
282
-
.determine_rate = jh7100_clk_determine_rate,
283
-
.get_parent = jh7100_clk_get_parent,
284
-
.set_parent = jh7100_clk_set_parent,
285
-
.set_rate = jh7100_clk_set_rate,
286
-
.debug_init = jh7100_clk_debug_init,
280
+
static const struct clk_ops jh71x0_clk_mdiv_ops = {
281
+
.recalc_rate = jh71x0_clk_recalc_rate,
282
+
.determine_rate = jh71x0_clk_determine_rate,
283
+
.get_parent = jh71x0_clk_get_parent,
284
+
.set_parent = jh71x0_clk_set_parent,
285
+
.set_rate = jh71x0_clk_set_rate,
286
+
.debug_init = jh71x0_clk_debug_init,
287
287
};
288
288
289
-
static const struct clk_ops jh7100_clk_gmd_ops = {
290
-
.enable = jh7100_clk_enable,
291
-
.disable = jh7100_clk_disable,
292
-
.is_enabled = jh7100_clk_is_enabled,
293
-
.recalc_rate = jh7100_clk_recalc_rate,
294
-
.determine_rate = jh7100_clk_determine_rate,
295
-
.get_parent = jh7100_clk_get_parent,
296
-
.set_parent = jh7100_clk_set_parent,
297
-
.set_rate = jh7100_clk_set_rate,
298
-
.debug_init = jh7100_clk_debug_init,
289
+
static const struct clk_ops jh71x0_clk_gmd_ops = {
290
+
.enable = jh71x0_clk_enable,
291
+
.disable = jh71x0_clk_disable,
292
+
.is_enabled = jh71x0_clk_is_enabled,
293
+
.recalc_rate = jh71x0_clk_recalc_rate,
294
+
.determine_rate = jh71x0_clk_determine_rate,
295
+
.get_parent = jh71x0_clk_get_parent,
296
+
.set_parent = jh71x0_clk_set_parent,
297
+
.set_rate = jh71x0_clk_set_rate,
298
+
.debug_init = jh71x0_clk_debug_init,
299
299
};
300
300
301
-
static const struct clk_ops jh7100_clk_inv_ops = {
302
-
.get_phase = jh7100_clk_get_phase,
303
-
.set_phase = jh7100_clk_set_phase,
304
-
.debug_init = jh7100_clk_debug_init,
301
+
static const struct clk_ops jh71x0_clk_inv_ops = {
302
+
.get_phase = jh71x0_clk_get_phase,
303
+
.set_phase = jh71x0_clk_set_phase,
304
+
.debug_init = jh71x0_clk_debug_init,
305
305
};
306
306
307
-
const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
307
+
const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)
308
308
{
309
-
if (max & JH7100_CLK_DIV_MASK) {
310
-
if (max & JH7100_CLK_MUX_MASK) {
311
-
if (max & JH7100_CLK_ENABLE)
312
-
return &jh7100_clk_gmd_ops;
313
-
return &jh7100_clk_mdiv_ops;
309
+
if (max & JH71X0_CLK_DIV_MASK) {
310
+
if (max & JH71X0_CLK_MUX_MASK) {
311
+
if (max & JH71X0_CLK_ENABLE)
312
+
return &jh71x0_clk_gmd_ops;
313
+
return &jh71x0_clk_mdiv_ops;
314
314
}
315
-
if (max & JH7100_CLK_ENABLE)
316
-
return &jh7100_clk_gdiv_ops;
317
-
if (max == JH7100_CLK_FRAC_MAX)
318
-
return &jh7100_clk_fdiv_ops;
319
-
return &jh7100_clk_div_ops;
315
+
if (max & JH71X0_CLK_ENABLE)
316
+
return &jh71x0_clk_gdiv_ops;
317
+
if (max == JH71X0_CLK_FRAC_MAX)
318
+
return &jh71x0_clk_fdiv_ops;
319
+
return &jh71x0_clk_div_ops;
320
320
}
321
321
322
-
if (max & JH7100_CLK_MUX_MASK) {
323
-
if (max & JH7100_CLK_ENABLE)
324
-
return &jh7100_clk_gmux_ops;
325
-
return &jh7100_clk_mux_ops;
322
+
if (max & JH71X0_CLK_MUX_MASK) {
323
+
if (max & JH71X0_CLK_ENABLE)
324
+
return &jh71x0_clk_gmux_ops;
325
+
return &jh71x0_clk_mux_ops;
326
326
}
327
327
328
-
if (max & JH7100_CLK_ENABLE)
329
-
return &jh7100_clk_gate_ops;
328
+
if (max & JH71X0_CLK_ENABLE)
329
+
return &jh71x0_clk_gate_ops;
330
330
331
-
return &jh7100_clk_inv_ops;
331
+
return &jh71x0_clk_inv_ops;
332
332
}
333
-
EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops);
333
+
EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops);
+45
-36
drivers/clk/starfive/clk-starfive-jh71x0.h
+45
-36
drivers/clk/starfive/clk-starfive-jh71x0.h
···
1
1
/* SPDX-License-Identifier: GPL-2.0 */
2
-
#ifndef __CLK_STARFIVE_JH7100_H
3
-
#define __CLK_STARFIVE_JH7100_H
2
+
#ifndef __CLK_STARFIVE_JH71X0_H
3
+
#define __CLK_STARFIVE_JH71X0_H
4
4
5
5
#include <linux/bits.h>
6
6
#include <linux/clk-provider.h>
···
8
8
#include <linux/spinlock.h>
9
9
10
10
/* register fields */
11
-
#define JH7100_CLK_ENABLE BIT(31)
12
-
#define JH7100_CLK_INVERT BIT(30)
13
-
#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
14
-
#define JH7100_CLK_MUX_SHIFT 24
15
-
#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
16
-
#define JH7100_CLK_FRAC_MASK GENMASK(15, 8)
17
-
#define JH7100_CLK_FRAC_SHIFT 8
18
-
#define JH7100_CLK_INT_MASK GENMASK(7, 0)
11
+
#define JH71X0_CLK_ENABLE BIT(31)
12
+
#define JH71X0_CLK_INVERT BIT(30)
13
+
#define JH71X0_CLK_MUX_MASK GENMASK(27, 24)
14
+
#define JH71X0_CLK_MUX_SHIFT 24
15
+
#define JH71X0_CLK_DIV_MASK GENMASK(23, 0)
16
+
#define JH71X0_CLK_FRAC_MASK GENMASK(15, 8)
17
+
#define JH71X0_CLK_FRAC_SHIFT 8
18
+
#define JH71X0_CLK_INT_MASK GENMASK(7, 0)
19
19
20
20
/* fractional divider min/max */
21
-
#define JH7100_CLK_FRAC_MIN 100UL
22
-
#define JH7100_CLK_FRAC_MAX 25599UL
21
+
#define JH71X0_CLK_FRAC_MIN 100UL
22
+
#define JH71X0_CLK_FRAC_MAX 25599UL
23
23
24
24
/* clock data */
25
-
struct jh7100_clk_data {
25
+
struct jh71x0_clk_data {
26
26
const char *name;
27
27
unsigned long flags;
28
28
u32 max;
29
29
u8 parents[4];
30
30
};
31
31
32
-
#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
32
+
#define JH71X0_GATE(_idx, _name, _flags, _parent) \
33
+
[_idx] = { \
33
34
.name = _name, \
34
35
.flags = CLK_SET_RATE_PARENT | (_flags), \
35
-
.max = JH7100_CLK_ENABLE, \
36
+
.max = JH71X0_CLK_ENABLE, \
36
37
.parents = { [0] = _parent }, \
37
38
}
38
39
39
-
#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
40
+
#define JH71X0__DIV(_idx, _name, _max, _parent) \
41
+
[_idx] = { \
40
42
.name = _name, \
41
43
.flags = 0, \
42
44
.max = _max, \
43
45
.parents = { [0] = _parent }, \
44
46
}
45
47
46
-
#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
48
+
#define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \
49
+
[_idx] = { \
47
50
.name = _name, \
48
51
.flags = _flags, \
49
-
.max = JH7100_CLK_ENABLE | (_max), \
52
+
.max = JH71X0_CLK_ENABLE | (_max), \
50
53
.parents = { [0] = _parent }, \
51
54
}
52
55
53
-
#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \
56
+
#define JH71X0_FDIV(_idx, _name, _parent) \
57
+
[_idx] = { \
54
58
.name = _name, \
55
59
.flags = 0, \
56
-
.max = JH7100_CLK_FRAC_MAX, \
60
+
.max = JH71X0_CLK_FRAC_MAX, \
57
61
.parents = { [0] = _parent }, \
58
62
}
59
63
60
-
#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
64
+
#define JH71X0__MUX(_idx, _name, _nparents, ...) \
65
+
[_idx] = { \
61
66
.name = _name, \
62
67
.flags = 0, \
63
-
.max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
68
+
.max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT, \
64
69
.parents = { __VA_ARGS__ }, \
65
70
}
66
71
67
-
#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
72
+
#define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) \
73
+
[_idx] = { \
68
74
.name = _name, \
69
75
.flags = _flags, \
70
-
.max = JH7100_CLK_ENABLE | \
71
-
(((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
76
+
.max = JH71X0_CLK_ENABLE | \
77
+
(((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT), \
72
78
.parents = { __VA_ARGS__ }, \
73
79
}
74
80
75
-
#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
81
+
#define JH71X0_MDIV(_idx, _name, _max, _nparents, ...) \
82
+
[_idx] = { \
76
83
.name = _name, \
77
84
.flags = 0, \
78
-
.max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
85
+
.max = (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
79
86
.parents = { __VA_ARGS__ }, \
80
87
}
81
88
82
-
#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
89
+
#define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) \
90
+
[_idx] = { \
83
91
.name = _name, \
84
92
.flags = _flags, \
85
-
.max = JH7100_CLK_ENABLE | \
86
-
(((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
93
+
.max = JH71X0_CLK_ENABLE | \
94
+
(((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
87
95
.parents = { __VA_ARGS__ }, \
88
96
}
89
97
90
-
#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
98
+
#define JH71X0__INV(_idx, _name, _parent) \
99
+
[_idx] = { \
91
100
.name = _name, \
92
101
.flags = CLK_SET_RATE_PARENT, \
93
-
.max = JH7100_CLK_INVERT, \
102
+
.max = JH71X0_CLK_INVERT, \
94
103
.parents = { [0] = _parent }, \
95
104
}
96
105
97
-
struct jh7100_clk {
106
+
struct jh71x0_clk {
98
107
struct clk_hw hw;
99
108
unsigned int idx;
100
109
unsigned int max_div;
101
110
};
102
111
103
-
struct jh7100_clk_priv {
112
+
struct jh71x0_clk_priv {
104
113
/* protect clk enable and set rate/parent from happening at the same time */
105
114
spinlock_t rmw_lock;
106
115
struct device *dev;
107
116
void __iomem *base;
108
117
struct clk_hw *pll[3];
109
-
struct jh7100_clk reg[];
118
+
struct jh71x0_clk reg[];
110
119
};
111
120
112
-
const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
121
+
const struct clk_ops *starfive_jh71x0_clk_ops(u32 max);
113
122
114
123
#endif