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dt-bindings: Convert Arm Mali Utgard GPU to DT schema
Convert the Arm Utgard GPU binding to DT schema format.
'allwinner,sun8i-a23-mali' compatible was not documented, so add it.
The 'clocks' property is now required. This simplifies the schema as
effectively all the users require 'clocks' already and the upstream
driver requires clocks.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Rob Herring <robh@kernel.org>
+168
-129
-129
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
-129
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
···
1
-
ARM Mali Utgard GPU
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-
===================
3
-
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-
Required properties:
5
-
- compatible
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* Must be one of the following:
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+ "arm,mali-300"
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+ "arm,mali-400"
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+ "arm,mali-450"
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* And, optionally, one of the vendor specific compatible:
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+ allwinner,sun4i-a10-mali
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-
+ allwinner,sun7i-a20-mali
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-
+ allwinner,sun8i-h3-mali
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-
+ allwinner,sun50i-a64-mali
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-
+ allwinner,sun50i-h5-mali
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-
+ amlogic,meson8-mali
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-
+ amlogic,meson8b-mali
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-
+ amlogic,meson-gxbb-mali
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+ amlogic,meson-gxl-mali
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+ samsung,exynos4210-mali
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-
+ rockchip,rk3036-mali
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-
+ rockchip,rk3066-mali
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-
+ rockchip,rk3188-mali
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-
+ rockchip,rk3228-mali
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+ rockchip,rk3328-mali
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+ stericsson,db8500-mali
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+ hisilicon,hi6220-mali
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-
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- reg: Physical base address and length of the GPU registers
30
-
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- interrupts: an entry for each entry in interrupt-names.
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See ../interrupt-controller/interrupts.txt for details.
33
-
34
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- interrupt-names:
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* ppX: Pixel Processor X interrupt (X from 0 to 7)
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* ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
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* pp: Pixel Processor broadcast interrupt (mali-450 only)
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* gp: Geometry Processor interrupt
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* gpmmu: Geometry Processor MMU interrupt
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-
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- clocks: an entry for each entry in clock-names
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- clock-names:
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* bus: bus clock for the GPU
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* core: clock driving the GPU itself
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-
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Optional properties:
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- interrupt-names and interrupts:
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* pmu: Power Management Unit interrupt, if implemented in hardware
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-
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- memory-region:
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Memory region to allocate from, as defined in
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Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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-
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- mali-supply:
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Phandle to regulator for the Mali device, as defined in
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Documentation/devicetree/bindings/regulator/regulator.txt for details.
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-
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- operating-points-v2:
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Operating Points for the GPU, as defined in
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Documentation/devicetree/bindings/opp/opp.txt
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-
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- power-domains:
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A power domain consumer specifier as defined in
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Documentation/devicetree/bindings/power/power_domain.txt
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-
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Vendor-specific bindings
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------------------------
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-
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The Mali GPU is integrated very differently from one SoC to
70
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another. In order to accomodate those differences, you have the option
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to specify one more vendor-specific compatible, among:
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-
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- allwinner,sun4i-a10-mali
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Required properties:
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* resets: phandle to the reset line for the GPU
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-
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- allwinner,sun7i-a20-mali
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Required properties:
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* resets: phandle to the reset line for the GPU
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-
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- allwinner,sun50i-a64-mali
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Required properties:
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* resets: phandle to the reset line for the GPU
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-
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- allwinner,sun50i-h5-mali
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Required properties:
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* resets: phandle to the reset line for the GPU
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-
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- amlogic,meson8-mali and amlogic,meson8b-mali
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Required properties:
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* resets: phandle to the reset line for the GPU
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-
93
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- Rockchip variants:
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Required properties:
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* resets: phandle to the reset line for the GPU
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-
97
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- stericsson,db8500-mali
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-
Required properties:
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* interrupt-names and interrupts:
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+ combined: combined interrupt of all of the above lines
101
-
102
-
- hisilicon,hi6220-mali
103
-
Required properties:
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* resets: phandles to the reset lines for the GPU
105
-
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Example:
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-
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mali: gpu@1c40000 {
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compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
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reg = <0x01c40000 0x10000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
113
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
115
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
116
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp",
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"gpmmu",
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"pp0",
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"ppmmu0",
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"pp1",
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"ppmmu1",
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"pmu";
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clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
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clock-names = "bus", "core";
127
-
resets = <&ccu RST_BUS_GPU>;
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-
};
129
-
+168
Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
+168
Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
···
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+
# SPDX-License-Identifier: GPL-2.0-only
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+
%YAML 1.2
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+
---
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$id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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title: ARM Mali Utgard GPU
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+
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maintainers:
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- Rob Herring <robh@kernel.org>
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- Maxime Ripard <maxime.ripard@free-electrons.com>
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+
- Heiko Stuebner <heiko@sntech.de>
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+
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+
properties:
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+
$nodename:
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+
pattern: '^gpu@[a-f0-9]+$'
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+
compatible:
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+
oneOf:
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- items:
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+
- const: allwinner,sun8i-a23-mali
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+
- const: allwinner,sun7i-a20-mali
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+
- const: arm,mali-400
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+
- items:
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+
- enum:
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+
- allwinner,sun4i-a10-mali
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+
- allwinner,sun7i-a20-mali
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+
- allwinner,sun8i-h3-mali
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+
- allwinner,sun50i-a64-mali
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+
- rockchip,rk3036-mali
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+
- rockchip,rk3066-mali
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+
- rockchip,rk3188-mali
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+
- rockchip,rk3228-mali
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+
- samsung,exynos4210-mali
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+
- stericsson,db8500-mali
35
+
- const: arm,mali-400
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+
- items:
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+
- enum:
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+
- allwinner,sun50i-h5-mali
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+
- amlogic,meson8-mali
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+
- amlogic,meson8b-mali
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+
- amlogic,meson-gxbb-mali
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+
- amlogic,meson-gxl-mali
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+
- hisilicon,hi6220-mali
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+
- rockchip,rk3328-mali
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+
- const: arm,mali-450
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+
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# "arm,mali-300"
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+
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+
reg:
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+
maxItems: 1
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+
52
+
interrupts:
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minItems: 4
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+
maxItems: 20
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+
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+
interrupt-names:
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+
allOf:
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- additionalItems: true
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+
minItems: 4
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+
maxItems: 20
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items:
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# At least enforce the first 2 interrupts
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- const: gp
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+
- const: gpmmu
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- items:
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# Not ideal as any order and combination are allowed
67
+
enum:
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- gp # Geometry Processor interrupt
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- gpmmu # Geometry Processor MMU interrupt
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- pp # Pixel Processor broadcast interrupt (mali-450 only)
71
+
- pp0 # Pixel Processor X interrupt (X from 0 to 7)
72
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- ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7)
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+
- pp1
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+
- ppmmu1
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+
- pp2
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+
- ppmmu2
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+
- pp3
78
+
- ppmmu3
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+
- pp4
80
+
- ppmmu4
81
+
- pp5
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+
- ppmmu5
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+
- pp6
84
+
- ppmmu6
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+
- pp7
86
+
- ppmmu7
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+
- pmu # Power Management Unit interrupt (optional)
88
+
- combined # stericsson,db8500-mali only
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+
90
+
clocks:
91
+
maxItems: 2
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+
93
+
clock-names:
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+
items:
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+
- const: bus
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+
- const: core
97
+
98
+
memory-region: true
99
+
100
+
mali-supply:
101
+
maxItems: 1
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+
103
+
power-domains:
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+
maxItems: 1
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+
106
+
resets:
107
+
maxItems: 1
108
+
109
+
operating-points-v2: true
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+
111
+
required:
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+
- compatible
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+
- reg
114
+
- interrupts
115
+
- interrupt-names
116
+
- clocks
117
+
- clock-names
118
+
119
+
allOf:
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+
- if:
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+
properties:
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+
compatible:
123
+
contains:
124
+
enum:
125
+
- allwinner,sun4i-a10-mali
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+
- allwinner,sun7i-a20-mali
127
+
- allwinner,sun50i-a64-mali
128
+
- allwinner,sun50i-h5-mali
129
+
- amlogic,meson8-mali
130
+
- amlogic,meson8b-mali
131
+
- hisilicon,hi6220-mali
132
+
- rockchip,rk3036-mali
133
+
- rockchip,rk3066-mali
134
+
- rockchip,rk3188-mali
135
+
- rockchip,rk3228-mali
136
+
- rockchip,rk3328-mali
137
+
then:
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+
required:
139
+
- resets
140
+
141
+
examples:
142
+
- |
143
+
#include <dt-bindings/interrupt-controller/irq.h>
144
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
145
+
146
+
mali: gpu@1c40000 {
147
+
compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
148
+
reg = <0x01c40000 0x10000>;
149
+
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
150
+
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
151
+
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
152
+
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
153
+
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
154
+
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
155
+
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
156
+
interrupt-names = "gp",
157
+
"gpmmu",
158
+
"pp0",
159
+
"ppmmu0",
160
+
"pp1",
161
+
"ppmmu1",
162
+
"pmu";
163
+
clocks = <&ccu 1>, <&ccu 2>;
164
+
clock-names = "bus", "core";
165
+
resets = <&ccu 1>;
166
+
};
167
+
168
+
...