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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
drm/i915/dmc: Define flip queue related PIPEDMC registers
Add the register definitions for a bunch of flip queue related
PIPEDMC registers.
v2: The layout of flip queue entries changed on PTL
Bump the DMC_FQ_W2_PTS_CFG_SEL bitfields sizes (Uma)
Reduce the scanlines to 21 bits for now (Uma)
v3: Also define some undocumented DMC variables we need on PTL
v3: Drop PIPEDMC_FQ_CTRL_BUSY as it seems to no longer exist
on LNL+
Fix up some typos
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250624170049.27284-4-ville.syrjala@linux.intel.com
+190
+190
drivers/gpu/drm/i915/display/intel_dmc_regs.h
+190
drivers/gpu/drm/i915/display/intel_dmc_regs.h
···
287
287
#define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
288
288
#define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
289
289
290
+
#define _PIPEDMC_LOAD_HTP_A 0x5f000
291
+
#define _PIPEDMC_LOAD_HTP_B 0x5f400
292
+
#define PIPEDMC_LOAD_HTP(pipe) _MMIO_PIPE((pipe), _PIPEDMC_LOAD_HTP_A, _PIPEDMC_LOAD_HTP_B)
293
+
294
+
#define _PIPEDMC_CTL_A 0x5f064
295
+
#define _PIPEDMC_CTL_B 0x5f464
296
+
#define PIPEDMC_CTL(pipe) _MMIO_PIPE((pipe), _PIPEDMC_CTL_A, _PIPEDMC_CTL_B)
297
+
#define PIPEDMC_HALT REG_BIT(31)
298
+
#define PIPEDMC_STEP REG_BIT(27)
299
+
#define PIPEDMC_CLOCKGATE REG_BIT(23)
300
+
290
301
#define _PIPEDMC_STATUS_A 0x5f06c
291
302
#define _PIPEDMC_STATUS_B 0x5f46c
292
303
#define PIPEDMC_STATUS(pipe) _MMIO_PIPE((pipe), _PIPEDMC_STATUS_A, _PIPEDMC_STATUS_B)
···
308
297
#define PIPEDMC_INT_VECTOR_DC6V_FLIPQ_OVERLAP_ERROR REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0x2)
309
298
#define PIPEDMC_INT_VECTOR_FLIPQ_PROG_DONE REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0xff) /* Wa_16018781658:lnl[a0] */
310
299
#define PIPEDMC_EVT_PENDING REG_GENMASK(7, 0)
300
+
301
+
#define _PIPEDMC_FQ_CTRL_A 0x5f078
302
+
#define _PIPEDMC_FQ_CTRL_B 0x5f478
303
+
#define PIPEDMC_FQ_CTRL(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FQ_CTRL_A, _PIPEDMC_FQ_CTRL_B)
304
+
#define PIPEDMC_FQ_CTRL_ENABLE REG_BIT(31)
305
+
#define PIPEDMC_FQ_CTRL_ASYNC REG_BIT(29)
306
+
#define PIPEDMC_FQ_CTRL_PREEMPT REG_BIT(0)
307
+
308
+
#define _PIPEDMC_FQ_STATUS_A 0x5f098
309
+
#define _PIPEDMC_FQ_STATUS_B 0x5f498
310
+
#define PIPEDMC_FQ_STATUS(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FQ_STATUS_A, _PIPEDMC_FQ_STATUS_B)
311
+
#define PIPEDMC_FQ_STATUS_BUSY REG_BIT(31)
312
+
#define PIPEDMC_FQ_STATUS_W2_LIVE_STATUS REG_BIT(1)
313
+
#define PIPEDMC_FQ_STATUS_W1_LIVE_STATUS REG_BIT(0)
314
+
315
+
#define _PIPEDMC_FPQ_ATOMIC_TP_A 0x5f0a0
316
+
#define _PIPEDMC_FPQ_ATOMIC_TP_B 0x5f4a0
317
+
#define PIPEDMC_FPQ_ATOMIC_TP(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FPQ_ATOMIC_TP_A, _PIPEDMC_FPQ_ATOMIC_TP_B)
318
+
#define PIPEDMC_FPQ_PLANEQ_3_TP_MASK REG_GENMASK(31, 26)
319
+
#define PIPEDMC_FPQ_PLANEQ_3_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, (tail))
320
+
#define PIPEDMC_FPQ_PLANEQ_2_TP_MASK REG_GENMASK(24, 19)
321
+
#define PIPEDMC_FPQ_PLANEQ_2_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, (tail))
322
+
#define PIPEDMC_FPQ_PLANEQ_1_TP_MASK REG_GENMASK(17, 12)
323
+
#define PIPEDMC_FPQ_PLANEQ_1_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, (tail))
324
+
#define PIPEDMC_FPQ_FASTQ_TP_MASK REG_GENMASK(10, 6)
325
+
#define PIPEDMC_FPQ_FASTQ_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_FASTQ_TP_MASK, (tail))
326
+
#define PIPEDMC_FPQ_GENERALQ_TP_MASK REG_GENMASK(4, 0)
327
+
#define PIPEDMC_FPQ_GENERALQ_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_GENERALQ_TP_MASK, (tail))
328
+
329
+
#define _PIPEDMC_FPQ_LINES_TO_W1_A 0x5f0a4
330
+
#define _PIPEDMC_FPQ_LINES_TO_W1_B 0x5f4a4
331
+
#define PIPEDMC_FPQ_LINES_TO_W1 _MMIO_PIPE((pipe), _PIPEDMC_FPQ_LINES_TO_W1_A, _PIPEDMC_FPQ_LINES_TO_W1_B)
332
+
333
+
#define _PIPEDMC_FPQ_LINES_TO_W2_A 0x5f0a8
334
+
#define _PIPEDMC_FPQ_LINES_TO_W2_B 0x5f4a8
335
+
#define PIPEDMC_FPQ_LINES_TO_W2 _MMIO_PIPE((pipe), _PIPEDMC_FPQ_LINES_TO_W2_A, _PIPEDMC_FPQ_LINES_TO_W2_B)
336
+
337
+
#define _PIPEDMC_SCANLINECMP_A 0x5f11c
338
+
#define _PIPEDMC_SCANLINECMP_B 0x5f51c
339
+
#define PIPEDMC_SCANLINECMP(pipe) _MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMP_A, _PIPEDMC_SCANLINECMP_B)
340
+
#define PIPEDMC_SCANLINECMP_EN REG_BIT(31)
341
+
#define PIPEDMC_SCANLINE_NUMBER REG_GENMASK(20, 0)
342
+
343
+
#define _PIPEDMC_SCANLINECMPLOWER_A 0x5f120
344
+
#define _PIPEDMC_SCANLINECMPLOWER_B 0x5f520
345
+
#define PIPEDMC_SCANLINECMPLOWER(pipe) _MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMPLOWER_A, _PIPEDMC_SCANLINECMPLOWER_B)
346
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#define PIPEDMC_SCANLINEINRANGECMP_EN REG_BIT(31)
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#define PIPEDMC_SCANLINEOUTRANGECMP_EN REG_BIT(30)
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+
#define PIPEDMC_SCANLINE_LOWER_MASK REG_GENMASK(20, 0)
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+
#define PIPEDMC_SCANLINE_LOWER(scanline) REG_FIELD_PREP(PIPEDMC_SCANLINE_LOWER_MASK, (scanline))
350
+
351
+
#define _PIPEDMC_SCANLINECMPUPPER_A 0x5f124
352
+
#define _PIPEDMC_SCANLINECMPUPPER_B 0x5f524
353
+
#define PIPEDMC_SCANLINECMPUPPER(pipe) _MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMPUPPER_A, _PIPEDMC_SCANLINECMPUPPER_B)
354
+
#define PIPEDMC_SCANLINE_UPPER_MASK REG_GENMASK(20, 0)
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+
#define PIPEDMC_SCANLINE_UPPER(scanline) REG_FIELD_PREP(PIPEDMC_SCANLINE_UPPER_MASK, (scanline))
356
+
357
+
#define _MMIO_PIPEDMC_FPQ(pipe, fq_id, \
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reg_fpq1_a, reg_fpq2_a, reg_fpq3_a, reg_fpq4_a, \
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reg_fpq1_b, reg_fpq2_b, reg_fpq3_b, reg_fpq4_b) \
360
+
_MMIO(_PICK_EVEN_2RANGES((fq_id), INTEL_FLIPQ_PLANE_3, \
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_PIPE((pipe), (reg_fpq1_a), (reg_fpq1_b)), \
362
+
_PIPE((pipe), (reg_fpq2_a), (reg_fpq2_b)), \
363
+
_PIPE((pipe), (reg_fpq3_a), (reg_fpq3_b)), \
364
+
_PIPE((pipe), (reg_fpq4_a), (reg_fpq4_b))))
365
+
366
+
#define _PIPEDMC_FPQ1_HP_A 0x5f128
367
+
#define _PIPEDMC_FPQ2_HP_A 0x5f138
368
+
#define _PIPEDMC_FPQ3_HP_A 0x5f168
369
+
#define _PIPEDMC_FPQ4_HP_A 0x5f174
370
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#define _PIPEDMC_FPQ5_HP_A 0x5f180
371
+
#define _PIPEDMC_FPQ1_HP_B 0x5f528
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+
#define _PIPEDMC_FPQ2_HP_B 0x5f538
373
+
#define _PIPEDMC_FPQ3_HP_B 0x5f568
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+
#define _PIPEDMC_FPQ4_HP_B 0x5f574
375
+
#define _PIPEDMC_FPQ5_HP_B 0x5f580
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+
#define PIPEDMC_FPQ_HP(pipe, fq_id) _MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
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+
_PIPEDMC_FPQ1_HP_A, _PIPEDMC_FPQ2_HP_A, \
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_PIPEDMC_FPQ3_HP_A, _PIPEDMC_FPQ4_HP_A, \
379
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_PIPEDMC_FPQ1_HP_B, _PIPEDMC_FPQ2_HP_B, \
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_PIPEDMC_FPQ3_HP_B, _PIPEDMC_FPQ4_HP_B)
381
+
382
+
#define _PIPEDMC_FPQ1_TP_A 0x5f12c
383
+
#define _PIPEDMC_FPQ2_TP_A 0x5f13c
384
+
#define _PIPEDMC_FPQ3_TP_A 0x5f16c
385
+
#define _PIPEDMC_FPQ4_TP_A 0x5f178
386
+
#define _PIPEDMC_FPQ5_TP_A 0x5f184
387
+
#define _PIPEDMC_FPQ1_TP_B 0x5f52c
388
+
#define _PIPEDMC_FPQ2_TP_B 0x5f53c
389
+
#define _PIPEDMC_FPQ3_TP_B 0x5f56c
390
+
#define _PIPEDMC_FPQ4_TP_B 0x5f578
391
+
#define _PIPEDMC_FPQ5_TP_B 0x5f584
392
+
#define PIPEDMC_FPQ_TP(pipe, fq_id) _MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
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_PIPEDMC_FPQ1_TP_A, _PIPEDMC_FPQ2_TP_A, \
394
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_PIPEDMC_FPQ3_TP_A, _PIPEDMC_FPQ4_TP_A, \
395
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_PIPEDMC_FPQ1_TP_B, _PIPEDMC_FPQ2_TP_B, \
396
+
_PIPEDMC_FPQ3_TP_B, _PIPEDMC_FPQ4_TP_B)
397
+
398
+
#define _PIPEDMC_FPQ1_CHP_A 0x5f130
399
+
#define _PIPEDMC_FPQ2_CHP_A 0x5f140
400
+
#define _PIPEDMC_FPQ3_CHP_A 0x5f170
401
+
#define _PIPEDMC_FPQ4_CHP_A 0x5f17c
402
+
#define _PIPEDMC_FPQ5_CHP_A 0x5f188
403
+
#define _PIPEDMC_FPQ1_CHP_B 0x5f530
404
+
#define _PIPEDMC_FPQ2_CHP_B 0x5f540
405
+
#define _PIPEDMC_FPQ3_CHP_B 0x5f570
406
+
#define _PIPEDMC_FPQ4_CHP_B 0x5f57c
407
+
#define _PIPEDMC_FPQ5_CHP_B 0x5f588
408
+
#define PIPEDMC_FPQ_CHP(pipe, fq_id) _MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
409
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_PIPEDMC_FPQ1_CHP_A, _PIPEDMC_FPQ2_CHP_A, \
410
+
_PIPEDMC_FPQ3_CHP_A, _PIPEDMC_FPQ4_CHP_A, \
411
+
_PIPEDMC_FPQ1_CHP_B, _PIPEDMC_FPQ2_CHP_B, \
412
+
_PIPEDMC_FPQ3_CHP_B, _PIPEDMC_FPQ4_CHP_B)
413
+
414
+
#define _PIPEDMC_FPQ_TS_A 0x5f134
415
+
#define _PIPEDMC_FPQ_TS_B 0x5f534
416
+
#define PIPEDMC_FPQ_TS(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FPQ_TS_A, _PIPEDMC_FPQ_TS_B)
417
+
418
+
#define _PIPEDMC_SCANLINE_RO_A 0x5f144
419
+
#define _PIPEDMC_SCANLINE_RO_B 0x5f544
420
+
#define PIPEDMC_SCANLINE_RO(pipe) _MMIO_PIPE((pipe), _PIPEDMC_SCANLINE_RO_A, _PIPEDMC_SCANLINE_RO_B)
421
+
422
+
#define _PIPEDMC_FPQ_CTL1_A 0x5f160
423
+
#define _PIPEDMC_FPQ_CTL1_B 0x5f560
424
+
#define PIPEDMC_FPQ_CTL1(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FPQ_CTL1_A, _PIPEDMC_FPQ_CTL1_B)
425
+
#define PIPEDMC_SW_DMC_WAKE REG_BIT(0)
426
+
427
+
#define _PIPEDMC_FPQ_CTL2_A 0x5f164
428
+
#define _PIPEDMC_FPQ_CTL2_B 0x5f564
429
+
#define PIPEDMC_FPQ_CTL2(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FPQ_CTL2_A, _PIPEDMC_FPQ_CTL2_B)
430
+
#define PIPEDMC_DMC_INT_AT_DELAYED_VBLANK REG_BIT(1)
431
+
#define PIPEDMC_W1_DMC_WAKE REG_BIT(0)
311
432
312
433
#define _PIPEDMC_INTERRUPT_A 0x5f190 /* lnl+ */
313
434
#define _PIPEDMC_INTERRUPT_B 0x5f590 /* lnl+ */
···
536
393
#define DMC_WAKELOCK1_CTL _MMIO(0x8F140)
537
394
#define DMC_WAKELOCK_CTL_REQ REG_BIT(31)
538
395
#define DMC_WAKELOCK_CTL_ACK REG_BIT(15)
396
+
397
+
#define DMC_FQ_W2_PTS_CFG_SEL _MMIO(0x8f240)
398
+
#define PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK REG_GENMASK(26, 24)
399
+
#define PIPE_D_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))
400
+
#define PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK REG_GENMASK(18, 16)
401
+
#define PIPE_C_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))
402
+
#define PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK REG_GENMASK(10, 8)
403
+
#define PIPE_B_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))
404
+
#define PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK REG_GENMASK(2, 0)
405
+
#define PIPE_A_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))
406
+
407
+
/* plane/general flip queue entries */
408
+
#define PIPEDMC_FQ_RAM(start_mmioaddr, i) _MMIO((start_mmioaddr) + (i) * 4)
409
+
/* LNL */
410
+
/* DW0 pts */
411
+
/* DW1 head */
412
+
/* DW2 size/etc. */
413
+
#define LNL_FQ_INTERRUPT REG_BIT(31)
414
+
#define LNL_FQ_DSB_ID_MASK REG_GENMASK(30, 29)
415
+
#define LNL_FQ_DSB_ID(dsb_id) REG_FIELD_PREP(LNL_FQ_DSB_ID_MASK, (dsb_id))
416
+
#define LNL_FQ_EXECUTED REG_BIT(28)
417
+
#define LNL_FQ_DSB_SIZE_MASK REG_GENMASK(15, 0)
418
+
#define LNL_FQ_DSB_SIZE(size) REG_FIELD_PREP(LNL_FQ_DSB_SIZE_MASK, (size))
419
+
/* DW3 reserved (plane queues) */
420
+
/* DW3 second DSB head (general queue) */
421
+
/* DW4 second DSB size/etc. (general queue) */
422
+
/* DW5 reserved (general queue) */
423
+
424
+
/* PTL+ */
425
+
/* DW0 pts */
426
+
/* DW1 reserved */
427
+
/* DW2 size/etc. */
428
+
#define PTL_FQ_INTERRUPT REG_BIT(31)
429
+
#define PTL_FQ_NEED_PUSH REG_BIT(30)
430
+
#define PTL_FQ_BLOCK_PUSH REG_BIT(29)
431
+
#define PTL_FQ_EXECUTED REG_BIT(28)
432
+
#define PTL_FQ_DSB_ID_MASK REG_GENMASK(25, 24)
433
+
#define PTL_FQ_DSB_ID(dsb_id) REG_FIELD_PREP(PTL_FQ_DSB_ID_MASK, (dsb_id))
434
+
#define PTL_FQ_DSB_SIZE_MASK REG_GENMASK(15, 0)
435
+
#define PTL_FQ_DSB_SIZE(size) REG_FIELD_PREP(PTL_FQ_DSB_SIZE_MASK, (size))
436
+
/* DW3 head */
437
+
/* DW4 second DSB size/etc. (general queue) */
438
+
/* DW5 second DSB head (general queue) */
439
+
440
+
/* undocumented magic DMC variables */
441
+
#define PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6b8)
442
+
#define PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6c0)
539
443
540
444
#endif /* __INTEL_DMC_REGS_H__ */