tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: properly enable VM fault interrupts
This fixes not printing VM faults.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Christian König
and committed by
Alex Deucher
140b519f
5134e999
+18
-15
+9
-7
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+9
-7
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
···
523
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tmp = RREG32(mmVM_CONTEXT1_CNTL);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
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-
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
528
-
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
530
-
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
531
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
532
-
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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-
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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-
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
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531
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
539
533
amdgpu_vm_block_size - 9);
···
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return 0;
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}
848
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+
static int gmc_v7_0_late_init(void *handle)
856
+
{
857
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
858
+
859
+
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
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+
}
861
+
849
862
static int gmc_v7_0_sw_init(void *handle)
850
863
{
851
864
int r;
···
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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+
amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
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gmc_v7_0_gart_disable(adev);
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return 0;
···
1303
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const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
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.early_init = gmc_v7_0_early_init,
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-
.late_init = NULL,
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+
.late_init = gmc_v7_0_late_init,
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1305
.sw_init = gmc_v7_0_sw_init,
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.sw_fini = gmc_v7_0_sw_fini,
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.hw_init = gmc_v7_0_hw_init,
+9
-8
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+9
-8
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
···
653
653
tmp = RREG32(mmVM_CONTEXT1_CNTL);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
656
-
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
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656
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
658
-
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
660
-
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
662
-
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
663
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
664
-
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
666
-
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
667
661
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
668
-
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
671
664
amdgpu_vm_block_size - 9);
···
845
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return 0;
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}
847
854
855
+
static int gmc_v8_0_late_init(void *handle)
856
+
{
857
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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+
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+
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
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+
}
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+
848
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static int gmc_v8_0_sw_init(void *handle)
849
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{
850
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int r;
···
978
978
{
979
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
980
980
981
+
amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
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gmc_v8_0_gart_disable(adev);
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return 0;
···
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const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
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.early_init = gmc_v8_0_early_init,
1292
-
.late_init = NULL,
1291
+
.late_init = gmc_v8_0_late_init,
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.sw_init = gmc_v8_0_sw_init,
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.sw_fini = gmc_v8_0_sw_fini,
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.hw_init = gmc_v8_0_hw_init,