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kernel
os
linux
drm/msm/dsi: correct programming sequence for SM8350 / SM8450
According to the display-drivers, 5nm DSI PLL (v4.2, v4.3) have
different boundaries for pll_clock_inverters programming. Follow the
vendor code and use correct values.
Fixes: 2f9ae4e395ed ("drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/606947/
Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-3-1149dd8399fe@linaro.org
+11
-1
+11
-1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+11
-1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
···
135
135
config->pll_clock_inverters = 0x00;
136
136
else
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config->pll_clock_inverters = 0x40;
138
-
} else {
138
+
} else if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
139
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if (pll_freq <= 1000000000ULL)
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140
config->pll_clock_inverters = 0xa0;
141
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else if (pll_freq <= 2500000000ULL)
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142
config->pll_clock_inverters = 0x20;
143
143
else if (pll_freq <= 3020000000ULL)
144
+
config->pll_clock_inverters = 0x00;
145
+
else
146
+
config->pll_clock_inverters = 0x40;
147
+
} else {
148
+
/* 4.2, 4.3 */
149
+
if (pll_freq <= 1000000000ULL)
150
+
config->pll_clock_inverters = 0xa0;
151
+
else if (pll_freq <= 2500000000ULL)
152
+
config->pll_clock_inverters = 0x20;
153
+
else if (pll_freq <= 3500000000ULL)
144
154
config->pll_clock_inverters = 0x00;
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else
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config->pll_clock_inverters = 0x40;