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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
viafb: complete support for VX800/VX855 accelerated framebuffer
This patch is a painful merge of change
a90bab567ece3e915d0ccd55ab00c9bb333fa8c0 (viafb: Add support for 2D
accelerated framebuffer on VX800/VX855) in the OLPC tree, originally by
Harald Welte. Harald's changelog read:
The VX800/VX820 and the VX855/VX875 chipsets have a different 2D
acceleration engine called "M1". The M1 engine has some subtle
(and some not-so-subtle) differences to the previous engines, so
support for accelerated framebuffer on those chipsets was disabled
so far.
This merge tries to preserve Harald's changes in the framework of the
much-changed 2.6.34 viafb code.
Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: ScottFang@viatech.com.cn
Cc: JosephChan@via.com.tw
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
+73
-9
+33
-9
drivers/video/via/accel.c
+33
-9
drivers/video/via/accel.c
···
317
317
{
318
318
struct viafb_par *viapar = info->par;
319
319
void __iomem *engine;
320
+
int highest_reg, i;
320
321
u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
321
322
vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;
322
323
···
328
327
"hardware acceleration disabled\n");
329
328
return -ENOMEM;
330
329
}
330
+
331
+
/* Initialize registers to reset the 2D engine */
332
+
switch (viapar->shared->chip_info.twod_engine) {
333
+
case VIA_2D_ENG_M1:
334
+
highest_reg = 0x5c;
335
+
break;
336
+
default:
337
+
highest_reg = 0x40;
338
+
break;
339
+
}
340
+
for (i = 0; i <= highest_reg; i += 4)
341
+
writel(0x0, engine + i);
331
342
332
343
switch (chip_name) {
333
344
case UNICHROME_CLE266:
···
370
357
viapar->shared->vq_vram_addr = viapar->fbmem_free;
371
358
viapar->fbmem_used += VQ_SIZE;
372
359
373
-
/* Init 2D engine reg to reset 2D engine */
374
-
writel(0x0, engine + VIA_REG_KEYCONTROL);
375
-
376
360
/* Init AGP and VQ regs */
377
361
switch (chip_name) {
378
362
case UNICHROME_K8M890:
379
363
case UNICHROME_P4M900:
364
+
case UNICHROME_VX800:
365
+
case UNICHROME_VX855:
380
366
writel(0x00100000, engine + VIA_REG_CR_TRANSET);
381
367
writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
382
368
writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
···
410
398
switch (chip_name) {
411
399
case UNICHROME_K8M890:
412
400
case UNICHROME_P4M900:
401
+
case UNICHROME_VX800:
402
+
case UNICHROME_VX855:
413
403
vq_start_low |= 0x20000000;
414
404
vq_end_low |= 0x20000000;
415
405
vq_high |= 0x20000000;
···
489
475
{
490
476
struct viafb_par *viapar = info->par;
491
477
int loop = 0;
478
+
u32 mask;
492
479
493
-
while (!(readl(viapar->shared->engine_mmio + VIA_REG_STATUS) &
494
-
VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
495
-
loop++;
496
-
cpu_relax();
480
+
switch (viapar->shared->chip_info.twod_engine) {
481
+
case VIA_2D_ENG_H5:
482
+
case VIA_2D_ENG_M1:
483
+
mask = VIA_CMD_RGTR_BUSY_M1 | VIA_2D_ENG_BUSY_M1 |
484
+
VIA_3D_ENG_BUSY_M1;
485
+
break;
486
+
default:
487
+
while (!(readl(viapar->shared->engine_mmio + VIA_REG_STATUS) &
488
+
VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
489
+
loop++;
490
+
cpu_relax();
491
+
}
492
+
mask = VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY;
493
+
break;
497
494
}
498
495
499
-
while ((readl(viapar->shared->engine_mmio + VIA_REG_STATUS) &
500
-
(VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) &&
496
+
while ((readl(viapar->shared->engine_mmio + VIA_REG_STATUS) & mask) &&
501
497
(loop < MAXLOOP)) {
502
498
loop++;
503
499
cpu_relax();
+40
drivers/video/via/accel.h
+40
drivers/video/via/accel.h
···
67
67
/* from 0x100 to 0x1ff */
68
68
#define VIA_REG_COLORPAT 0x100
69
69
70
+
/* defines for VIA 2D registers for vt3353/3409 (M1 engine)*/
71
+
#define VIA_REG_GECMD_M1 0x000
72
+
#define VIA_REG_GEMODE_M1 0x004
73
+
#define VIA_REG_GESTATUS_M1 0x004 /* as same as VIA_REG_GEMODE */
74
+
#define VIA_REG_PITCH_M1 0x008 /* pitch of src and dst */
75
+
#define VIA_REG_DIMENSION_M1 0x00C /* width and height */
76
+
#define VIA_REG_DSTPOS_M1 0x010
77
+
#define VIA_REG_LINE_XY_M1 0x010
78
+
#define VIA_REG_DSTBASE_M1 0x014
79
+
#define VIA_REG_SRCPOS_M1 0x018
80
+
#define VIA_REG_LINE_K1K2_M1 0x018
81
+
#define VIA_REG_SRCBASE_M1 0x01C
82
+
#define VIA_REG_PATADDR_M1 0x020
83
+
#define VIA_REG_MONOPAT0_M1 0x024
84
+
#define VIA_REG_MONOPAT1_M1 0x028
85
+
#define VIA_REG_OFFSET_M1 0x02C
86
+
#define VIA_REG_LINE_ERROR_M1 0x02C
87
+
#define VIA_REG_CLIPTL_M1 0x040 /* top and left of clipping */
88
+
#define VIA_REG_CLIPBR_M1 0x044 /* bottom and right of clipping */
89
+
#define VIA_REG_KEYCONTROL_M1 0x048 /* color key control */
90
+
#define VIA_REG_FGCOLOR_M1 0x04C
91
+
#define VIA_REG_DSTCOLORKEY_M1 0x04C /* as same as VIA_REG_FG */
92
+
#define VIA_REG_BGCOLOR_M1 0x050
93
+
#define VIA_REG_SRCCOLORKEY_M1 0x050 /* as same as VIA_REG_BG */
94
+
#define VIA_REG_MONOPATFGC_M1 0x058 /* Add BG color of Pattern. */
95
+
#define VIA_REG_MONOPATBGC_M1 0x05C /* Add FG color of Pattern. */
96
+
#define VIA_REG_COLORPAT_M1 0x100 /* from 0x100 to 0x1ff */
97
+
70
98
/* VIA_REG_PITCH(0x38): Pitch Setting */
71
99
#define VIA_PITCH_ENABLE 0x80000000
72
100
···
184
156
#define VIA_3D_ENG_BUSY 0x00000001
185
157
/* Virtual Queue is busy */
186
158
#define VIA_VR_QUEUE_BUSY 0x00020000
159
+
160
+
/* VIA_REG_STATUS(0x400): Engine Status for H5 */
161
+
#define VIA_CMD_RGTR_BUSY_H5 0x00000010 /* Command Regulator is busy */
162
+
#define VIA_2D_ENG_BUSY_H5 0x00000002 /* 2D Engine is busy */
163
+
#define VIA_3D_ENG_BUSY_H5 0x00001FE1 /* 3D Engine is busy */
164
+
#define VIA_VR_QUEUE_BUSY_H5 0x00000004 /* Virtual Queue is busy */
165
+
166
+
/* VIA_REG_STATUS(0x400): Engine Status for VT3353/3409 */
167
+
#define VIA_CMD_RGTR_BUSY_M1 0x00000010 /* Command Regulator is busy */
168
+
#define VIA_2D_ENG_BUSY_M1 0x00000002 /* 2D Engine is busy */
169
+
#define VIA_3D_ENG_BUSY_M1 0x00001FE1 /* 3D Engine is busy */
170
+
#define VIA_VR_QUEUE_BUSY_M1 0x00000004 /* Virtual Queue is busy */
187
171
188
172
#define MAXLOOP 0xFFFFFF
189
173