tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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Merge branch '20251014-qcom_ipq5424_nsscc-v7-2-081f4956be02@quicinc.com' into HEAD

Merge IPQ5424 DeviceTree bindings for the Network Subsystem clock
controller from topic branch, to gain access to binding constants.

Bjorn Andersson 12fe71e7 74c2c1e0

+201 -9
+55 -8
Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
··· 4 4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 - title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 7 + title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424 8 8 9 9 maintainers: 10 10 - Bjorn Andersson <andersson@kernel.org> ··· 12 12 13 13 description: | 14 14 Qualcomm networking sub system clock control module provides the clocks, 15 - resets on IPQ9574 15 + resets on IPQ9574 and IPQ5424 16 16 17 - See also:: 17 + See also: 18 + include/dt-bindings/clock/qcom,ipq5424-nsscc.h 18 19 include/dt-bindings/clock/qcom,ipq9574-nsscc.h 20 + include/dt-bindings/reset/qcom,ipq5424-nsscc.h 19 21 include/dt-bindings/reset/qcom,ipq9574-nsscc.h 20 22 21 23 properties: 22 24 compatible: 23 - const: qcom,ipq9574-nsscc 25 + enum: 26 + - qcom,ipq5424-nsscc 27 + - qcom,ipq9574-nsscc 24 28 25 29 clocks: 26 30 items: 27 31 - description: Board XO source 28 - - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source 29 - - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source 32 + - description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate 33 + can vary for different IPQ SoCs. For example, it is 1200 MHz on the 34 + IPQ9574 and 300 MHz on the IPQ5424. 35 + - description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock 36 + rate can vary for different IPQ SoCs. For example, it is 353 MHz 37 + on the IPQ9574 and 375 MHz on the IPQ5424. 30 38 - description: GCC GPLL0 OUT AUX clock source 31 39 - description: Uniphy0 NSS Rx clock source 32 40 - description: Uniphy0 NSS Tx clock source ··· 50 42 clock-names: 51 43 items: 52 44 - const: xo 53 - - const: nss_1200 54 - - const: ppe_353 45 + - enum: 46 + - nss_1200 47 + - nss 48 + - enum: 49 + - ppe_353 50 + - ppe 55 51 - const: gpll0_out 56 52 - const: uniphy0_rx 57 53 - const: uniphy0_tx ··· 72 60 73 61 allOf: 74 62 - $ref: qcom,gcc.yaml# 63 + - if: 64 + properties: 65 + compatible: 66 + const: qcom,ipq9574-nsscc 67 + then: 68 + properties: 69 + clock-names: 70 + items: 71 + - const: xo 72 + - const: nss_1200 73 + - const: ppe_353 74 + - const: gpll0_out 75 + - const: uniphy0_rx 76 + - const: uniphy0_tx 77 + - const: uniphy1_rx 78 + - const: uniphy1_tx 79 + - const: uniphy2_rx 80 + - const: uniphy2_tx 81 + - const: bus 82 + else: 83 + properties: 84 + clock-names: 85 + items: 86 + - const: xo 87 + - const: nss 88 + - const: ppe 89 + - const: gpll0_out 90 + - const: uniphy0_rx 91 + - const: uniphy0_tx 92 + - const: uniphy1_rx 93 + - const: uniphy1_tx 94 + - const: uniphy2_rx 95 + - const: uniphy2_tx 96 + - const: bus 75 97 76 98 unevaluatedProperties: false 77 99 ··· 140 94 "bus"; 141 95 #clock-cells = <1>; 142 96 #reset-cells = <1>; 97 + #interconnect-cells = <1>; 143 98 }; 144 99 ...
+2 -1
include/dt-bindings/clock/qcom,ipq5424-gcc.h
··· 1 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 2 /* 3 3 * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved. 4 - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 5 */ 6 6 7 7 #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H ··· 152 152 #define GCC_PCIE3_RCHNG_CLK 143 153 153 #define GCC_IM_SLEEP_CLK 144 154 154 #define GCC_XO_CLK 145 155 + #define GPLL0_OUT_AUX 146 155 156 156 157 #endif
+65
include/dt-bindings/clock/qcom,ipq5424-nsscc.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H 7 + #define _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H 8 + 9 + /* NSS_CC clocks */ 10 + #define NSS_CC_CE_APB_CLK 0 11 + #define NSS_CC_CE_AXI_CLK 1 12 + #define NSS_CC_CE_CLK_SRC 2 13 + #define NSS_CC_CFG_CLK_SRC 3 14 + #define NSS_CC_DEBUG_CLK 4 15 + #define NSS_CC_EIP_BFDCD_CLK_SRC 5 16 + #define NSS_CC_EIP_CLK 6 17 + #define NSS_CC_NSS_CSR_CLK 7 18 + #define NSS_CC_NSSNOC_CE_APB_CLK 8 19 + #define NSS_CC_NSSNOC_CE_AXI_CLK 9 20 + #define NSS_CC_NSSNOC_EIP_CLK 10 21 + #define NSS_CC_NSSNOC_NSS_CSR_CLK 11 22 + #define NSS_CC_NSSNOC_PPE_CFG_CLK 12 23 + #define NSS_CC_NSSNOC_PPE_CLK 13 24 + #define NSS_CC_PORT1_MAC_CLK 14 25 + #define NSS_CC_PORT1_RX_CLK 15 26 + #define NSS_CC_PORT1_RX_CLK_SRC 16 27 + #define NSS_CC_PORT1_RX_DIV_CLK_SRC 17 28 + #define NSS_CC_PORT1_TX_CLK 18 29 + #define NSS_CC_PORT1_TX_CLK_SRC 19 30 + #define NSS_CC_PORT1_TX_DIV_CLK_SRC 20 31 + #define NSS_CC_PORT2_MAC_CLK 21 32 + #define NSS_CC_PORT2_RX_CLK 22 33 + #define NSS_CC_PORT2_RX_CLK_SRC 23 34 + #define NSS_CC_PORT2_RX_DIV_CLK_SRC 24 35 + #define NSS_CC_PORT2_TX_CLK 25 36 + #define NSS_CC_PORT2_TX_CLK_SRC 26 37 + #define NSS_CC_PORT2_TX_DIV_CLK_SRC 27 38 + #define NSS_CC_PORT3_MAC_CLK 28 39 + #define NSS_CC_PORT3_RX_CLK 29 40 + #define NSS_CC_PORT3_RX_CLK_SRC 30 41 + #define NSS_CC_PORT3_RX_DIV_CLK_SRC 31 42 + #define NSS_CC_PORT3_TX_CLK 32 43 + #define NSS_CC_PORT3_TX_CLK_SRC 33 44 + #define NSS_CC_PORT3_TX_DIV_CLK_SRC 34 45 + #define NSS_CC_PPE_CLK_SRC 35 46 + #define NSS_CC_PPE_EDMA_CFG_CLK 36 47 + #define NSS_CC_PPE_EDMA_CLK 37 48 + #define NSS_CC_PPE_SWITCH_BTQ_CLK 38 49 + #define NSS_CC_PPE_SWITCH_CFG_CLK 39 50 + #define NSS_CC_PPE_SWITCH_CLK 40 51 + #define NSS_CC_PPE_SWITCH_IPE_CLK 41 52 + #define NSS_CC_UNIPHY_PORT1_RX_CLK 42 53 + #define NSS_CC_UNIPHY_PORT1_TX_CLK 43 54 + #define NSS_CC_UNIPHY_PORT2_RX_CLK 44 55 + #define NSS_CC_UNIPHY_PORT2_TX_CLK 45 56 + #define NSS_CC_UNIPHY_PORT3_RX_CLK 46 57 + #define NSS_CC_UNIPHY_PORT3_TX_CLK 47 58 + #define NSS_CC_XGMAC0_PTP_REF_CLK 48 59 + #define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 49 60 + #define NSS_CC_XGMAC1_PTP_REF_CLK 50 61 + #define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 51 62 + #define NSS_CC_XGMAC2_PTP_REF_CLK 52 63 + #define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 53 64 + 65 + #endif
+33
include/dt-bindings/interconnect/qcom,ipq5424.h
··· 20 20 #define SLAVE_CNOC_PCIE3 15 21 21 #define MASTER_CNOC_USB 16 22 22 #define SLAVE_CNOC_USB 17 23 + #define MASTER_NSSNOC_NSSCC 18 24 + #define SLAVE_NSSNOC_NSSCC 19 25 + #define MASTER_NSSNOC_SNOC_0 20 26 + #define SLAVE_NSSNOC_SNOC_0 21 27 + #define MASTER_NSSNOC_SNOC_1 22 28 + #define SLAVE_NSSNOC_SNOC_1 23 29 + #define MASTER_NSSNOC_PCNOC_1 24 30 + #define SLAVE_NSSNOC_PCNOC_1 25 31 + #define MASTER_NSSNOC_QOSGEN_REF 26 32 + #define SLAVE_NSSNOC_QOSGEN_REF 27 33 + #define MASTER_NSSNOC_TIMEOUT_REF 28 34 + #define SLAVE_NSSNOC_TIMEOUT_REF 29 35 + #define MASTER_NSSNOC_XO_DCD 30 36 + #define SLAVE_NSSNOC_XO_DCD 31 37 + #define MASTER_NSSNOC_ATB 32 38 + #define SLAVE_NSSNOC_ATB 33 39 + #define MASTER_CNOC_LPASS_CFG 34 40 + #define SLAVE_CNOC_LPASS_CFG 35 41 + #define MASTER_SNOC_LPASS 36 42 + #define SLAVE_SNOC_LPASS 37 23 43 24 44 #define MASTER_CPU 0 25 45 #define SLAVE_L3 1 46 + 47 + #define MASTER_NSSNOC_PPE 0 48 + #define SLAVE_NSSNOC_PPE 1 49 + #define MASTER_NSSNOC_PPE_CFG 2 50 + #define SLAVE_NSSNOC_PPE_CFG 3 51 + #define MASTER_NSSNOC_NSS_CSR 4 52 + #define SLAVE_NSSNOC_NSS_CSR 5 53 + #define MASTER_NSSNOC_CE_AXI 6 54 + #define SLAVE_NSSNOC_CE_AXI 7 55 + #define MASTER_NSSNOC_CE_APB 8 56 + #define SLAVE_NSSNOC_CE_APB 9 57 + #define MASTER_NSSNOC_EIP 10 58 + #define SLAVE_NSSNOC_EIP 11 26 59 27 60 #endif /* INTERCONNECT_QCOM_IPQ5424_H */
+46
include/dt-bindings/reset/qcom,ipq5424-nsscc.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H 7 + #define _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H 8 + 9 + #define NSS_CC_CE_APB_CLK_ARES 0 10 + #define NSS_CC_CE_AXI_CLK_ARES 1 11 + #define NSS_CC_DEBUG_CLK_ARES 2 12 + #define NSS_CC_EIP_CLK_ARES 3 13 + #define NSS_CC_NSS_CSR_CLK_ARES 4 14 + #define NSS_CC_NSSNOC_CE_APB_CLK_ARES 5 15 + #define NSS_CC_NSSNOC_CE_AXI_CLK_ARES 6 16 + #define NSS_CC_NSSNOC_EIP_CLK_ARES 7 17 + #define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES 8 18 + #define NSS_CC_NSSNOC_PPE_CLK_ARES 9 19 + #define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES 10 20 + #define NSS_CC_PORT1_MAC_CLK_ARES 11 21 + #define NSS_CC_PORT1_RX_CLK_ARES 12 22 + #define NSS_CC_PORT1_TX_CLK_ARES 13 23 + #define NSS_CC_PORT2_MAC_CLK_ARES 14 24 + #define NSS_CC_PORT2_RX_CLK_ARES 15 25 + #define NSS_CC_PORT2_TX_CLK_ARES 16 26 + #define NSS_CC_PORT3_MAC_CLK_ARES 17 27 + #define NSS_CC_PORT3_RX_CLK_ARES 18 28 + #define NSS_CC_PORT3_TX_CLK_ARES 19 29 + #define NSS_CC_PPE_BCR 20 30 + #define NSS_CC_PPE_EDMA_CLK_ARES 21 31 + #define NSS_CC_PPE_EDMA_CFG_CLK_ARES 22 32 + #define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES 23 33 + #define NSS_CC_PPE_SWITCH_CLK_ARES 24 34 + #define NSS_CC_PPE_SWITCH_CFG_CLK_ARES 25 35 + #define NSS_CC_PPE_SWITCH_IPE_CLK_ARES 26 36 + #define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES 27 37 + #define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES 28 38 + #define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES 29 39 + #define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES 30 40 + #define NSS_CC_UNIPHY_PORT3_RX_CLK_ARES 31 41 + #define NSS_CC_UNIPHY_PORT3_TX_CLK_ARES 32 42 + #define NSS_CC_XGMAC0_PTP_REF_CLK_ARES 33 43 + #define NSS_CC_XGMAC1_PTP_REF_CLK_ARES 34 44 + #define NSS_CC_XGMAC2_PTP_REF_CLK_ARES 35 45 + 46 + #endif