[MIPS] No need to write c0_compare in plat_timer_setup

If R4k counter was used for hpt_timer and interrupt source,
c0_hpt_timer_init() initializes the c0_compare register.

Signed-off-by: Atsushi Nemoto <[e-mail]>
Signed-off-by: Ralf Baechle <[e-mail]>

arch/mips/lasat/setup.c

···
 
 void __init plat_timer_setup(struct irqaction *irq)
 {
-	write_c0_compare( read_c0_count() + mips_hpt_frequency / HZ);
 	change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5);
 }
 

arch/mips/mips-boards/generic/time.c

···
 	irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
 	set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
 #endif
-
-        /* to generate the first timer interrupt */
-	write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
 }

arch/mips/mips-boards/sim/sim_time.c

···
 	irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU;
 	set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
 #endif
-
-	/* to generate the first timer interrupt */
-	write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
 }

arch/mips/tx4927/common/tx4927_setup.c

···
 
 void __init plat_timer_setup(struct irqaction *irq)
 {
-	u32 count;
-	u32 c1;
-	u32 c2;
-
 	setup_irq(TX4927_IRQ_CPU_TIMER, irq);
-
-	/* to generate the first timer interrupt */
-	c1 = read_c0_count();
-	count = c1 + (mips_hpt_frequency / HZ);
-	write_c0_compare(count);
-	c2 = read_c0_count();
 
 #ifdef CONFIG_TOSHIBA_RBTX4927
 	{

arch/mips/tx4938/common/setup.c

···
 
 void __init plat_timer_setup(struct irqaction *irq)
 {
-	u32 count;
-	u32 c1;
-	u32 c2;
-
 	setup_irq(TX4938_IRQ_CPU_TIMER, irq);
-
-	c1 = read_c0_count();
-	count = c1 + (mips_hpt_frequency / HZ);
-	write_c0_compare(count);
-	c2 = read_c0_count();
 }