tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: samsung: Fix the width of PINCFG_TYPE_DRV bitfields for Exynos5433
This patch fixes the wrong width of PINCFG_TYPE_DRV bitfields for Exynos5433
because PINCFG_TYPE_DRV of Exynos5433 has 4bit fields in the *_DRV
registers. Usually, other Exynos have 2bit field for PINCFG_TYPE_DRV.
Fixes: 3c5ecc9ed353 ("pinctrl: exynos: Add support for Exynos5433")
Cc: stable@vger.kernel.org
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
authored by
Chanwoo Choi
and committed by
Linus Walleij
1259fedd
f24d311f
+82
-40
+51
-40
drivers/pinctrl/samsung/pinctrl-exynos.c
+51
-40
drivers/pinctrl/samsung/pinctrl-exynos.c
···
56
56
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
57
57
};
58
58
59
+
/* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */
60
+
static const struct samsung_pin_bank_type exynos5433_bank_type_off = {
61
+
.fld_width = { 4, 1, 2, 4, 2, 2, },
62
+
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
63
+
};
64
+
65
+
static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
66
+
.fld_width = { 4, 1, 2, 4, },
67
+
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
68
+
};
69
+
59
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static void exynos_irq_mask(struct irq_data *irqd)
60
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{
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struct irq_chip *chip = irq_data_get_irq_chip(irqd);
···
1346
1335
1347
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/* pin banks of exynos5433 pin-controller - ALIVE */
1348
1337
static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {
1349
-
EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1350
-
EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1351
-
EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1352
-
EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1353
-
EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
1354
-
EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
1355
-
EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
1356
-
EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
1357
-
EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
1338
+
EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1339
+
EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1340
+
EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1341
+
EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1342
+
EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
1343
+
EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
1344
+
EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
1345
+
EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
1346
+
EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
1358
1347
};
1359
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1349
/* pin banks of exynos5433 pin-controller - AUD */
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static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = {
1362
-
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1363
-
EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1351
+
EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1352
+
EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1364
1353
};
1365
1354
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1355
/* pin banks of exynos5433 pin-controller - CPIF */
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static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = {
1368
-
EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
1357
+
EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
1369
1358
};
1370
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1371
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/* pin banks of exynos5433 pin-controller - eSE */
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static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = {
1373
-
EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
1362
+
EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
1374
1363
};
1375
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/* pin banks of exynos5433 pin-controller - FINGER */
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static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = {
1378
-
EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
1367
+
EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
1379
1368
};
1380
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1370
/* pin banks of exynos5433 pin-controller - FSYS */
1382
1371
static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = {
1383
-
EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
1384
-
EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
1385
-
EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
1386
-
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
1387
-
EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
1388
-
EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
1372
+
EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
1373
+
EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
1374
+
EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
1375
+
EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
1376
+
EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
1377
+
EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
1389
1378
};
1390
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/* pin banks of exynos5433 pin-controller - IMEM */
1392
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static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = {
1393
-
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
1382
+
EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
1394
1383
};
1395
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/* pin banks of exynos5433 pin-controller - NFC */
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static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = {
1398
-
EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1387
+
EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1399
1388
};
1400
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1401
1390
/* pin banks of exynos5433 pin-controller - PERIC */
1402
1391
static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = {
1403
-
EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
1404
-
EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
1405
-
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
1406
-
EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
1407
-
EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
1408
-
EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
1409
-
EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
1410
-
EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
1411
-
EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
1412
-
EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
1413
-
EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
1414
-
EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
1415
-
EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
1416
-
EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
1417
-
EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
1418
-
EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
1419
-
EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
1392
+
EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
1393
+
EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
1394
+
EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
1395
+
EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
1396
+
EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
1397
+
EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
1398
+
EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
1399
+
EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
1400
+
EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
1401
+
EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
1402
+
EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
1403
+
EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
1404
+
EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
1405
+
EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
1406
+
EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
1407
+
EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
1408
+
EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
1420
1409
};
1421
1410
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1411
/* pin banks of exynos5433 pin-controller - TOUCH */
1423
1412
static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = {
1424
-
EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1413
+
EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1425
1414
};
1426
1415
1427
1416
/*
+31
drivers/pinctrl/samsung/pinctrl-exynos.h
+31
drivers/pinctrl/samsung/pinctrl-exynos.h
···
90
90
.pctl_res_idx = pctl_idx, \
91
91
} \
92
92
93
+
#define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \
94
+
{ \
95
+
.type = &exynos5433_bank_type_off, \
96
+
.pctl_offset = reg, \
97
+
.nr_pins = pins, \
98
+
.eint_type = EINT_TYPE_GPIO, \
99
+
.eint_offset = offs, \
100
+
.name = id \
101
+
}
102
+
103
+
#define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \
104
+
{ \
105
+
.type = &exynos5433_bank_type_alive, \
106
+
.pctl_offset = reg, \
107
+
.nr_pins = pins, \
108
+
.eint_type = EINT_TYPE_WKUP, \
109
+
.eint_offset = offs, \
110
+
.name = id \
111
+
}
112
+
113
+
#define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
114
+
{ \
115
+
.type = &exynos5433_bank_type_alive, \
116
+
.pctl_offset = reg, \
117
+
.nr_pins = pins, \
118
+
.eint_type = EINT_TYPE_WKUP, \
119
+
.eint_offset = offs, \
120
+
.name = id, \
121
+
.pctl_res_idx = pctl_idx, \
122
+
} \
123
+
93
124
/**
94
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* struct exynos_weint_data: irq specific data for all the wakeup interrupts
95
126
* generated by the external wakeup interrupt controller.