tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: mediatek: mt8192: Move apmixedsys clock driver to its own file
This is the last man standing in clk-mt8192.c that won't allow us to
use the module_platform_driver() macro, and for *no* good reason.
Move it to clk-mt8192-apmixedsys.c and while at it, also add a
.remove() callback for it.
Also, since the need for "clk-mt8192-simple" and "clk-mt8192" was
just due to them being in the same file and probing different clocks,
and since now there's just one platform_driver struct per file, it
seemed natural to rename the `-simple` variant to just "clk-mt8192".
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-48-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
AngeloGioacchino Del Regno
and committed by
Stephen Boyd
124294ff
5baf38e0
+219
-218
+1
-1
drivers/clk/mediatek/Makefile
+1
-1
drivers/clk/mediatek/Makefile
···
100
100
obj-$(CONFIG_COMMON_CLK_MT8186_VDECSYS) += clk-mt8186-vdec.o
101
101
obj-$(CONFIG_COMMON_CLK_MT8186_VENCSYS) += clk-mt8186-venc.o
102
102
obj-$(CONFIG_COMMON_CLK_MT8186_WPESYS) += clk-mt8186-wpe.o
103
-
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
103
+
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
104
104
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
105
105
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
106
106
obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS) += clk-mt8192-img.o
+214
drivers/clk/mediatek/clk-mt8192-apmixedsys.c
+214
drivers/clk/mediatek/clk-mt8192-apmixedsys.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
* Chun-Jie Chen <chun-jie.chen@mediatek.com>
5
+
* Copyright (c) 2023 Collabora Ltd.
6
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
7
+
*/
8
+
9
+
#include <dt-bindings/clock/mt8192-clk.h>
10
+
#include <linux/module.h>
11
+
#include <linux/platform_device.h>
12
+
#include "clk-fhctl.h"
13
+
#include "clk-gate.h"
14
+
#include "clk-mtk.h"
15
+
#include "clk-pll.h"
16
+
#include "clk-pllfh.h"
17
+
18
+
static const struct mtk_gate_regs apmixed_cg_regs = {
19
+
.set_ofs = 0x14,
20
+
.clr_ofs = 0x14,
21
+
.sta_ofs = 0x14,
22
+
};
23
+
24
+
#define GATE_APMIXED(_id, _name, _parent, _shift) \
25
+
GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
26
+
27
+
static const struct mtk_gate apmixed_clks[] = {
28
+
GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16),
29
+
};
30
+
31
+
#define MT8192_PLL_FMAX (3800UL * MHZ)
32
+
#define MT8192_PLL_FMIN (1500UL * MHZ)
33
+
#define MT8192_INTEGER_BITS 8
34
+
35
+
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
36
+
_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
37
+
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
38
+
_pcw_reg, _pcw_shift, _pcw_chg_reg, \
39
+
_en_reg, _pll_en_bit) { \
40
+
.id = _id, \
41
+
.name = _name, \
42
+
.reg = _reg, \
43
+
.pwr_reg = _pwr_reg, \
44
+
.en_mask = _en_mask, \
45
+
.flags = _flags, \
46
+
.rst_bar_mask = _rst_bar_mask, \
47
+
.fmax = MT8192_PLL_FMAX, \
48
+
.fmin = MT8192_PLL_FMIN, \
49
+
.pcwbits = _pcwbits, \
50
+
.pcwibits = MT8192_INTEGER_BITS, \
51
+
.pd_reg = _pd_reg, \
52
+
.pd_shift = _pd_shift, \
53
+
.tuner_reg = _tuner_reg, \
54
+
.tuner_en_reg = _tuner_en_reg, \
55
+
.tuner_en_bit = _tuner_en_bit, \
56
+
.pcw_reg = _pcw_reg, \
57
+
.pcw_shift = _pcw_shift, \
58
+
.pcw_chg_reg = _pcw_chg_reg, \
59
+
.en_reg = _en_reg, \
60
+
.pll_en_bit = _pll_en_bit, \
61
+
}
62
+
63
+
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
64
+
_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
65
+
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
66
+
_pcw_reg, _pcw_shift) \
67
+
PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
68
+
_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
69
+
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
70
+
_pcw_reg, _pcw_shift, 0, 0, 0)
71
+
72
+
static const struct mtk_pll_data plls[] = {
73
+
PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000,
74
+
HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0),
75
+
PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000,
76
+
HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0),
77
+
PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000,
78
+
0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2),
79
+
PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000,
80
+
0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0),
81
+
PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000,
82
+
HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0),
83
+
PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000,
84
+
HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0),
85
+
PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000,
86
+
0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0),
87
+
PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000,
88
+
0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0),
89
+
PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000,
90
+
0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0),
91
+
PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000,
92
+
0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0),
93
+
};
94
+
95
+
enum fh_pll_id {
96
+
FH_ARMPLL_LL,
97
+
FH_ARMPLL_BL0,
98
+
FH_ARMPLL_BL1,
99
+
FH_ARMPLL_BL2,
100
+
FH_ARMPLL_BL3,
101
+
FH_CCIPLL,
102
+
FH_MFGPLL,
103
+
FH_MEMPLL,
104
+
FH_MPLL,
105
+
FH_MMPLL,
106
+
FH_MAINPLL,
107
+
FH_MSDCPLL,
108
+
FH_ADSPPLL,
109
+
FH_APUPLL,
110
+
FH_TVDPLL,
111
+
FH_NR_FH,
112
+
};
113
+
114
+
#define FH(_pllid, _fhid, _offset) { \
115
+
.data = { \
116
+
.pll_id = _pllid, \
117
+
.fh_id = _fhid, \
118
+
.fh_ver = FHCTL_PLLFH_V2, \
119
+
.fhx_offset = _offset, \
120
+
.dds_mask = GENMASK(21, 0), \
121
+
.slope0_value = 0x6003c97, \
122
+
.slope1_value = 0x6003c97, \
123
+
.sfstrx_en = BIT(2), \
124
+
.frddsx_en = BIT(1), \
125
+
.fhctlx_en = BIT(0), \
126
+
.tgl_org = BIT(31), \
127
+
.dvfs_tri = BIT(31), \
128
+
.pcwchg = BIT(31), \
129
+
.dt_val = 0x0, \
130
+
.df_val = 0x9, \
131
+
.updnlmt_shft = 16, \
132
+
.msk_frddsx_dys = GENMASK(23, 20), \
133
+
.msk_frddsx_dts = GENMASK(19, 16), \
134
+
}, \
135
+
}
136
+
137
+
static struct mtk_pllfh_data pllfhs[] = {
138
+
FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4),
139
+
FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
140
+
FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
141
+
FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
142
+
FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x12c),
143
+
FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154),
144
+
};
145
+
146
+
static const struct of_device_id of_match_clk_mt8192_apmixed[] = {
147
+
{ .compatible = "mediatek,mt8192-apmixedsys" },
148
+
{ /* sentinel */ }
149
+
};
150
+
151
+
static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
152
+
{
153
+
struct clk_hw_onecell_data *clk_data;
154
+
struct device_node *node = pdev->dev.of_node;
155
+
const u8 *fhctl_node = "mediatek,mt8192-fhctl";
156
+
int r;
157
+
158
+
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
159
+
if (!clk_data)
160
+
return -ENOMEM;
161
+
162
+
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
163
+
164
+
r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
165
+
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
166
+
if (r)
167
+
goto free_clk_data;
168
+
169
+
r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
170
+
ARRAY_SIZE(apmixed_clks), clk_data);
171
+
if (r)
172
+
goto unregister_plls;
173
+
174
+
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
175
+
if (r)
176
+
goto unregister_gates;
177
+
178
+
return r;
179
+
180
+
unregister_gates:
181
+
mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
182
+
unregister_plls:
183
+
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
184
+
ARRAY_SIZE(pllfhs), clk_data);
185
+
free_clk_data:
186
+
mtk_free_clk_data(clk_data);
187
+
return r;
188
+
}
189
+
190
+
static int clk_mt8192_apmixed_remove(struct platform_device *pdev)
191
+
{
192
+
struct device_node *node = pdev->dev.of_node;
193
+
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
194
+
195
+
of_clk_del_provider(node);
196
+
mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
197
+
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
198
+
ARRAY_SIZE(pllfhs), clk_data);
199
+
mtk_free_clk_data(clk_data);
200
+
201
+
return 0;
202
+
}
203
+
204
+
static struct platform_driver clk_mt8192_apmixed_drv = {
205
+
.driver = {
206
+
.name = "clk-mt8192-apmixed",
207
+
.of_match_table = of_match_clk_mt8192_apmixed,
208
+
},
209
+
.probe = clk_mt8192_apmixed_probe,
210
+
.remove = clk_mt8192_apmixed_remove,
211
+
};
212
+
module_platform_driver(clk_mt8192_apmixed_drv);
213
+
MODULE_DESCRIPTION("MediaTek MT8192 apmixed clocks driver");
214
+
MODULE_LICENSE("GPL");
+4
-217
drivers/clk/mediatek/clk-mt8192.c
+4
-217
drivers/clk/mediatek/clk-mt8192.c
···
12
12
#include <linux/platform_device.h>
13
13
#include <linux/slab.h>
14
14
15
-
#include "clk-fhctl.h"
16
15
#include "clk-gate.h"
17
16
#include "clk-mtk.h"
18
17
#include "clk-mux.h"
19
-
#include "clk-pll.h"
20
-
#include "clk-pllfh.h"
21
18
22
19
#include <dt-bindings/clock/mt8192-clk.h>
23
20
#include <dt-bindings/reset/mt8192-resets.h>
···
711
714
DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16),
712
715
};
713
716
714
-
static const struct mtk_gate_regs apmixed_cg_regs = {
715
-
.set_ofs = 0x14,
716
-
.clr_ofs = 0x14,
717
-
.sta_ofs = 0x14,
718
-
};
719
-
720
-
#define GATE_APMIXED(_id, _name, _parent, _shift) \
721
-
GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
722
-
723
-
static const struct mtk_gate apmixed_clks[] = {
724
-
GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16),
725
-
};
726
-
727
717
static const struct mtk_gate_regs infra0_cg_regs = {
728
718
.set_ofs = 0x80,
729
719
.clr_ofs = 0x84,
···
964
980
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
965
981
};
966
982
967
-
#define MT8192_PLL_FMAX (3800UL * MHZ)
968
-
#define MT8192_PLL_FMIN (1500UL * MHZ)
969
-
#define MT8192_INTEGER_BITS 8
970
-
971
-
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
972
-
_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
973
-
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
974
-
_pcw_reg, _pcw_shift, _pcw_chg_reg, \
975
-
_en_reg, _pll_en_bit) { \
976
-
.id = _id, \
977
-
.name = _name, \
978
-
.reg = _reg, \
979
-
.pwr_reg = _pwr_reg, \
980
-
.en_mask = _en_mask, \
981
-
.flags = _flags, \
982
-
.rst_bar_mask = _rst_bar_mask, \
983
-
.fmax = MT8192_PLL_FMAX, \
984
-
.fmin = MT8192_PLL_FMIN, \
985
-
.pcwbits = _pcwbits, \
986
-
.pcwibits = MT8192_INTEGER_BITS, \
987
-
.pd_reg = _pd_reg, \
988
-
.pd_shift = _pd_shift, \
989
-
.tuner_reg = _tuner_reg, \
990
-
.tuner_en_reg = _tuner_en_reg, \
991
-
.tuner_en_bit = _tuner_en_bit, \
992
-
.pcw_reg = _pcw_reg, \
993
-
.pcw_shift = _pcw_shift, \
994
-
.pcw_chg_reg = _pcw_chg_reg, \
995
-
.en_reg = _en_reg, \
996
-
.pll_en_bit = _pll_en_bit, \
997
-
}
998
-
999
-
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1000
-
_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
1001
-
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
1002
-
_pcw_reg, _pcw_shift) \
1003
-
PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1004
-
_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
1005
-
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
1006
-
_pcw_reg, _pcw_shift, 0, 0, 0)
1007
-
1008
-
static const struct mtk_pll_data plls[] = {
1009
-
PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000,
1010
-
HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0),
1011
-
PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000,
1012
-
HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0),
1013
-
PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000,
1014
-
0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2),
1015
-
PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000,
1016
-
0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0),
1017
-
PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000,
1018
-
HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0),
1019
-
PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000,
1020
-
HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0),
1021
-
PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000,
1022
-
0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0),
1023
-
PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000,
1024
-
0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0),
1025
-
PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000,
1026
-
0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0),
1027
-
PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000,
1028
-
0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0),
1029
-
};
1030
-
1031
-
enum fh_pll_id {
1032
-
FH_ARMPLL_LL,
1033
-
FH_ARMPLL_BL0,
1034
-
FH_ARMPLL_BL1,
1035
-
FH_ARMPLL_BL2,
1036
-
FH_ARMPLL_BL3,
1037
-
FH_CCIPLL,
1038
-
FH_MFGPLL,
1039
-
FH_MEMPLL,
1040
-
FH_MPLL,
1041
-
FH_MMPLL,
1042
-
FH_MAINPLL,
1043
-
FH_MSDCPLL,
1044
-
FH_ADSPPLL,
1045
-
FH_APUPLL,
1046
-
FH_TVDPLL,
1047
-
FH_NR_FH,
1048
-
};
1049
-
1050
-
#define FH(_pllid, _fhid, _offset) { \
1051
-
.data = { \
1052
-
.pll_id = _pllid, \
1053
-
.fh_id = _fhid, \
1054
-
.fh_ver = FHCTL_PLLFH_V2, \
1055
-
.fhx_offset = _offset, \
1056
-
.dds_mask = GENMASK(21, 0), \
1057
-
.slope0_value = 0x6003c97, \
1058
-
.slope1_value = 0x6003c97, \
1059
-
.sfstrx_en = BIT(2), \
1060
-
.frddsx_en = BIT(1), \
1061
-
.fhctlx_en = BIT(0), \
1062
-
.tgl_org = BIT(31), \
1063
-
.dvfs_tri = BIT(31), \
1064
-
.pcwchg = BIT(31), \
1065
-
.dt_val = 0x0, \
1066
-
.df_val = 0x9, \
1067
-
.updnlmt_shft = 16, \
1068
-
.msk_frddsx_dys = GENMASK(23, 20), \
1069
-
.msk_frddsx_dts = GENMASK(19, 16), \
1070
-
}, \
1071
-
}
1072
-
1073
-
static struct mtk_pllfh_data pllfhs[] = {
1074
-
FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4),
1075
-
FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
1076
-
FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
1077
-
FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
1078
-
FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x12c),
1079
-
FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154),
1080
-
};
1081
-
1082
983
/* Register mux notifier for MFG mux */
1083
984
static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
1084
985
{
···
984
1115
mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
985
1116
986
1117
return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
987
-
}
988
-
989
-
static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
990
-
{
991
-
struct clk_hw_onecell_data *clk_data;
992
-
struct device_node *node = pdev->dev.of_node;
993
-
const u8 *fhctl_node = "mediatek,mt8192-fhctl";
994
-
int r;
995
-
996
-
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
997
-
if (!clk_data)
998
-
return -ENOMEM;
999
-
1000
-
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
1001
-
1002
-
r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
1003
-
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
1004
-
if (r)
1005
-
goto free_clk_data;
1006
-
1007
-
r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
1008
-
ARRAY_SIZE(apmixed_clks), clk_data);
1009
-
if (r)
1010
-
goto unregister_plls;
1011
-
1012
-
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1013
-
if (r)
1014
-
goto unregister_gates;
1015
-
1016
-
return r;
1017
-
1018
-
unregister_gates:
1019
-
mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
1020
-
unregister_plls:
1021
-
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
1022
-
ARRAY_SIZE(pllfhs), clk_data);
1023
-
free_clk_data:
1024
-
mtk_free_clk_data(clk_data);
1025
-
return r;
1026
-
}
1027
-
1028
-
static const struct of_device_id of_match_clk_mt8192[] = {
1029
-
{
1030
-
.compatible = "mediatek,mt8192-apmixedsys",
1031
-
.data = clk_mt8192_apmixed_probe,
1032
-
}, {
1033
-
/* sentinel */
1034
-
}
1035
-
};
1036
-
1037
-
static int clk_mt8192_probe(struct platform_device *pdev)
1038
-
{
1039
-
int (*clk_probe)(struct platform_device *pdev);
1040
-
int r;
1041
-
1042
-
clk_probe = of_device_get_match_data(&pdev->dev);
1043
-
if (!clk_probe)
1044
-
return -EINVAL;
1045
-
1046
-
r = clk_probe(pdev);
1047
-
if (r)
1048
-
dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r);
1049
-
1050
-
return r;
1051
1118
}
1052
1119
1053
1120
static const struct mtk_clk_desc infra_desc = {
···
1013
1208
.mfg_clk_idx = CLK_TOP_MFG_PLL_SEL,
1014
1209
};
1015
1210
1016
-
static const struct of_device_id of_match_clk_mt8192_simple[] = {
1211
+
static const struct of_device_id of_match_clk_mt8192[] = {
1017
1212
{ .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc },
1018
1213
{ .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc },
1019
1214
{ .compatible = "mediatek,mt8192-topckgen", .data = &topck_desc },
1020
1215
{ /* sentinel */ }
1021
1216
};
1022
1217
1023
-
static struct platform_driver clk_mt8192_simple_drv = {
1024
-
.probe = mtk_clk_simple_probe,
1025
-
.remove = mtk_clk_simple_remove,
1026
-
.driver = {
1027
-
.name = "clk-mt8192-simple",
1028
-
.of_match_table = of_match_clk_mt8192_simple,
1029
-
},
1030
-
};
1031
-
1032
1218
static struct platform_driver clk_mt8192_drv = {
1033
-
.probe = clk_mt8192_probe,
1034
1219
.driver = {
1035
1220
.name = "clk-mt8192",
1036
1221
.of_match_table = of_match_clk_mt8192,
1037
1222
},
1223
+
.probe = mtk_clk_simple_probe,
1224
+
.remove = mtk_clk_simple_remove,
1038
1225
};
1039
-
1040
-
static int __init clk_mt8192_init(void)
1041
-
{
1042
-
int ret = platform_driver_register(&clk_mt8192_drv);
1043
-
1044
-
if (ret)
1045
-
return ret;
1046
-
return platform_driver_register(&clk_mt8192_simple_drv);
1047
-
}
1048
-
1049
-
arch_initcall(clk_mt8192_init);
1226
+
module_platform_driver(clk_mt8192_drv);
1050
1227
MODULE_LICENSE("GPL");