tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'perf-core-for-mingo-4.12-20170404' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core
Pull perf/core improvements and fixes from Arnaldo Carvalho de Melo:
User visible changes:
- Add missing number of samples in 'perf annotate --stdio -l --show-total-period'
(Taeung Song)
Vendor events updates:
- Add uncore_arb Intel vendor events in JSON format (Andi Kleen)
- Add uncore vendor events for Intel's Sandy Bridge, Ivy Bridge,
Haswell, Broadwell and Skylake architectures (Andi Kleen)
- Add missing UNC_M_DCLOCKTICKS Intel Broadwell DE uncore vendor event (Andi Kleen)
Infrastructure changes:
- Remove some more die() calls, avoiding sudden death in library code
(Arnaldo Carvalho de Melo)
- Add argument support for SDT events in powerpc (Ravi Bangoria)
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
+1710
-24
+111
tools/perf/arch/powerpc/util/perf_regs.c
+111
tools/perf/arch/powerpc/util/perf_regs.c
···
1
+
#include <string.h>
2
+
#include <regex.h>
3
+
1
4
#include "../../perf.h"
5
+
#include "../../util/util.h"
2
6
#include "../../util/perf_regs.h"
7
+
#include "../../util/debug.h"
3
8
4
9
const struct sample_reg sample_reg_masks[] = {
5
10
SMPL_REG(r0, PERF_REG_POWERPC_R0),
···
52
47
SMPL_REG(dsisr, PERF_REG_POWERPC_DSISR),
53
48
SMPL_REG_END
54
49
};
50
+
51
+
/* REG or %rREG */
52
+
#define SDT_OP_REGEX1 "^(%r)?([1-2]?[0-9]|3[0-1])$"
53
+
54
+
/* -NUM(REG) or NUM(REG) or -NUM(%rREG) or NUM(%rREG) */
55
+
#define SDT_OP_REGEX2 "^(\\-)?([0-9]+)\\((%r)?([1-2]?[0-9]|3[0-1])\\)$"
56
+
57
+
static regex_t sdt_op_regex1, sdt_op_regex2;
58
+
59
+
static int sdt_init_op_regex(void)
60
+
{
61
+
static int initialized;
62
+
int ret = 0;
63
+
64
+
if (initialized)
65
+
return 0;
66
+
67
+
ret = regcomp(&sdt_op_regex1, SDT_OP_REGEX1, REG_EXTENDED);
68
+
if (ret)
69
+
goto error;
70
+
71
+
ret = regcomp(&sdt_op_regex2, SDT_OP_REGEX2, REG_EXTENDED);
72
+
if (ret)
73
+
goto free_regex1;
74
+
75
+
initialized = 1;
76
+
return 0;
77
+
78
+
free_regex1:
79
+
regfree(&sdt_op_regex1);
80
+
error:
81
+
pr_debug4("Regex compilation error.\n");
82
+
return ret;
83
+
}
84
+
85
+
/*
86
+
* Parse OP and convert it into uprobe format, which is, +/-NUM(%gprREG).
87
+
* Possible variants of OP are:
88
+
* Format Example
89
+
* -------------------------
90
+
* NUM(REG) 48(18)
91
+
* -NUM(REG) -48(18)
92
+
* NUM(%rREG) 48(%r18)
93
+
* -NUM(%rREG) -48(%r18)
94
+
* REG 18
95
+
* %rREG %r18
96
+
* iNUM i0
97
+
* i-NUM i-1
98
+
*
99
+
* SDT marker arguments on Powerpc uses %rREG form with -mregnames flag
100
+
* and REG form with -mno-regnames. Here REG is general purpose register,
101
+
* which is in 0 to 31 range.
102
+
*/
103
+
int arch_sdt_arg_parse_op(char *old_op, char **new_op)
104
+
{
105
+
int ret, new_len;
106
+
regmatch_t rm[5];
107
+
char prefix;
108
+
109
+
/* Constant argument. Uprobe does not support it */
110
+
if (old_op[0] == 'i') {
111
+
pr_debug4("Skipping unsupported SDT argument: %s\n", old_op);
112
+
return SDT_ARG_SKIP;
113
+
}
114
+
115
+
ret = sdt_init_op_regex();
116
+
if (ret < 0)
117
+
return ret;
118
+
119
+
if (!regexec(&sdt_op_regex1, old_op, 3, rm, 0)) {
120
+
/* REG or %rREG --> %gprREG */
121
+
122
+
new_len = 5; /* % g p r NULL */
123
+
new_len += (int)(rm[2].rm_eo - rm[2].rm_so);
124
+
125
+
*new_op = zalloc(new_len);
126
+
if (!*new_op)
127
+
return -ENOMEM;
128
+
129
+
scnprintf(*new_op, new_len, "%%gpr%.*s",
130
+
(int)(rm[2].rm_eo - rm[2].rm_so), old_op + rm[2].rm_so);
131
+
} else if (!regexec(&sdt_op_regex2, old_op, 5, rm, 0)) {
132
+
/*
133
+
* -NUM(REG) or NUM(REG) or -NUM(%rREG) or NUM(%rREG) -->
134
+
* +/-NUM(%gprREG)
135
+
*/
136
+
prefix = (rm[1].rm_so == -1) ? '+' : '-';
137
+
138
+
new_len = 8; /* +/- ( % g p r ) NULL */
139
+
new_len += (int)(rm[2].rm_eo - rm[2].rm_so);
140
+
new_len += (int)(rm[4].rm_eo - rm[4].rm_so);
141
+
142
+
*new_op = zalloc(new_len);
143
+
if (!*new_op)
144
+
return -ENOMEM;
145
+
146
+
scnprintf(*new_op, new_len, "%c%.*s(%%gpr%.*s)", prefix,
147
+
(int)(rm[2].rm_eo - rm[2].rm_so), old_op + rm[2].rm_so,
148
+
(int)(rm[4].rm_eo - rm[4].rm_so), old_op + rm[4].rm_so);
149
+
} else {
150
+
pr_debug4("Skipping unsupported SDT argument: %s\n", old_op);
151
+
return SDT_ARG_SKIP;
152
+
}
153
+
154
+
return SDT_ARG_VALID;
155
+
}
+2
-1
tools/perf/perf.c
+2
-1
tools/perf/perf.c
+278
tools/perf/pmu-events/arch/x86/broadwell/uncore.json
+278
tools/perf/pmu-events/arch/x86/broadwell/uncore.json
···
1
+
[
2
+
{
3
+
"Unit": "CBO",
4
+
"EventCode": "0x22",
5
+
"UMask": "0x41",
6
+
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
7
+
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
8
+
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
9
+
"Counter": "0,1",
10
+
"CounterMask": "0",
11
+
"Invert": "0",
12
+
"EdgeDetect": "0"
13
+
},
14
+
{
15
+
"Unit": "CBO",
16
+
"EventCode": "0x22",
17
+
"UMask": "0x81",
18
+
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
19
+
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
20
+
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
21
+
"Counter": "0,1",
22
+
"CounterMask": "0",
23
+
"Invert": "0",
24
+
"EdgeDetect": "0"
25
+
},
26
+
{
27
+
"Unit": "CBO",
28
+
"EventCode": "0x22",
29
+
"UMask": "0x44",
30
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
31
+
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
32
+
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
33
+
"Counter": "0,1",
34
+
"CounterMask": "0",
35
+
"Invert": "0",
36
+
"EdgeDetect": "0"
37
+
},
38
+
{
39
+
"Unit": "CBO",
40
+
"EventCode": "0x22",
41
+
"UMask": "0x48",
42
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
43
+
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
44
+
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
45
+
"Counter": "0,1",
46
+
"CounterMask": "0",
47
+
"Invert": "0",
48
+
"EdgeDetect": "0"
49
+
},
50
+
{
51
+
"Unit": "CBO",
52
+
"EventCode": "0x34",
53
+
"UMask": "0x11",
54
+
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
55
+
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state",
56
+
"PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
57
+
"Counter": "0,1",
58
+
"CounterMask": "0",
59
+
"Invert": "0",
60
+
"EdgeDetect": "0"
61
+
},
62
+
{
63
+
"Unit": "CBO",
64
+
"EventCode": "0x34",
65
+
"UMask": "0x21",
66
+
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
67
+
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
68
+
"PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
69
+
"Counter": "0,1",
70
+
"CounterMask": "0",
71
+
"Invert": "0",
72
+
"EdgeDetect": "0"
73
+
},
74
+
{
75
+
"Unit": "CBO",
76
+
"EventCode": "0x34",
77
+
"UMask": "0x81",
78
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
79
+
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
80
+
"PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
81
+
"Counter": "0,1",
82
+
"CounterMask": "0",
83
+
"Invert": "0",
84
+
"EdgeDetect": "0"
85
+
},
86
+
{
87
+
"Unit": "CBO",
88
+
"EventCode": "0x34",
89
+
"UMask": "0x18",
90
+
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
91
+
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
92
+
"PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
93
+
"Counter": "0,1",
94
+
"CounterMask": "0",
95
+
"Invert": "0",
96
+
"EdgeDetect": "0"
97
+
},
98
+
{
99
+
"Unit": "CBO",
100
+
"EventCode": "0x34",
101
+
"UMask": "0x88",
102
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
103
+
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
104
+
"PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
105
+
"Counter": "0,1",
106
+
"CounterMask": "0",
107
+
"Invert": "0",
108
+
"EdgeDetect": "0"
109
+
},
110
+
{
111
+
"Unit": "CBO",
112
+
"EventCode": "0x34",
113
+
"UMask": "0x1f",
114
+
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
115
+
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
116
+
"PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
117
+
"Counter": "0,1",
118
+
"CounterMask": "0",
119
+
"Invert": "0",
120
+
"EdgeDetect": "0"
121
+
},
122
+
{
123
+
"Unit": "CBO",
124
+
"EventCode": "0x34",
125
+
"UMask": "0x2f",
126
+
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
127
+
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
128
+
"PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
129
+
"Counter": "0,1",
130
+
"CounterMask": "0",
131
+
"Invert": "0",
132
+
"EdgeDetect": "0"
133
+
},
134
+
{
135
+
"Unit": "CBO",
136
+
"EventCode": "0x34",
137
+
"UMask": "0x8f",
138
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
139
+
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
140
+
"PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
141
+
"Counter": "0,1",
142
+
"CounterMask": "0",
143
+
"Invert": "0",
144
+
"EdgeDetect": "0"
145
+
},
146
+
{
147
+
"Unit": "CBO",
148
+
"EventCode": "0x34",
149
+
"UMask": "0x86",
150
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
151
+
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
152
+
"PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
153
+
"Counter": "0,1",
154
+
"CounterMask": "0",
155
+
"Invert": "0",
156
+
"EdgeDetect": "0"
157
+
},
158
+
{
159
+
"Unit": "CBO",
160
+
"EventCode": "0x34",
161
+
"UMask": "0x16",
162
+
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
163
+
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
164
+
"PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
165
+
"Counter": "0,1",
166
+
"CounterMask": "0",
167
+
"Invert": "0",
168
+
"EdgeDetect": "0"
169
+
},
170
+
{
171
+
"Unit": "CBO",
172
+
"EventCode": "0x34",
173
+
"UMask": "0x26",
174
+
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
175
+
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
176
+
"PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
177
+
"Counter": "0,1",
178
+
"CounterMask": "0",
179
+
"Invert": "0",
180
+
"EdgeDetect": "0"
181
+
},
182
+
{
183
+
"Unit": "iMPH-U",
184
+
"EventCode": "0x80",
185
+
"UMask": "0x01",
186
+
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
187
+
"BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
188
+
"PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
189
+
"Counter": "0,",
190
+
"CounterMask": "0",
191
+
"Invert": "0",
192
+
"EdgeDetect": "0"
193
+
},
194
+
{
195
+
"Unit": "iMPH-U",
196
+
"EventCode": "0x80",
197
+
"UMask": "0x02",
198
+
"EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT",
199
+
"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
200
+
"PublicDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
201
+
"Counter": "0,",
202
+
"CounterMask": "0",
203
+
"Invert": "0",
204
+
"EdgeDetect": "0"
205
+
},
206
+
{
207
+
"Unit": "iMPH-U",
208
+
"EventCode": "0x81",
209
+
"UMask": "0x01",
210
+
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
211
+
"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
212
+
"PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
213
+
"Counter": "0,1",
214
+
"CounterMask": "0",
215
+
"Invert": "0",
216
+
"EdgeDetect": "0"
217
+
},
218
+
{
219
+
"Unit": "iMPH-U",
220
+
"EventCode": "0x81",
221
+
"UMask": "0x02",
222
+
"EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
223
+
"BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
224
+
"PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
225
+
"Counter": "0,1",
226
+
"CounterMask": "0",
227
+
"Invert": "0",
228
+
"EdgeDetect": "0"
229
+
},
230
+
{
231
+
"Unit": "iMPH-U",
232
+
"EventCode": "0x81",
233
+
"UMask": "0x20",
234
+
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
235
+
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
236
+
"PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
237
+
"Counter": "0,1",
238
+
"CounterMask": "0",
239
+
"Invert": "0",
240
+
"EdgeDetect": "0"
241
+
},
242
+
{
243
+
"Unit": "iMPH-U",
244
+
"EventCode": "0x84",
245
+
"UMask": "0x01",
246
+
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
247
+
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
248
+
"PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
249
+
"Counter": "0,1",
250
+
"CounterMask": "0",
251
+
"Invert": "0",
252
+
"EdgeDetect": "0"
253
+
},
254
+
{
255
+
"Unit": "iMPH-U",
256
+
"EventCode": "0x80",
257
+
"UMask": "0x01",
258
+
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
259
+
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",
260
+
"PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
261
+
"Counter": "0,",
262
+
"CounterMask": "1",
263
+
"Invert": "0",
264
+
"EdgeDetect": "0"
265
+
},
266
+
{
267
+
"Unit": "NCU",
268
+
"EventCode": "0x0",
269
+
"UMask": "0x01",
270
+
"EventName": "UNC_CLOCK.SOCKET",
271
+
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
272
+
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
273
+
"Counter": "FIXED",
274
+
"CounterMask": "0",
275
+
"Invert": "0",
276
+
"EdgeDetect": "0"
277
+
}
278
+
]
+10
-3
tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json
+10
-3
tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json
···
20
20
"Unit": "iMC"
21
21
},
22
22
{
23
+
"BriefDescription": "Memory controller clock ticks",
24
+
"Counter": "0,1,2,3",
25
+
"EventName": "UNC_M_DCLOCKTICKS",
26
+
"PerPkg": "1",
27
+
"Unit": "iMC"
28
+
},
29
+
{
23
30
"BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
24
31
"Counter": "0,1,2,3",
25
32
"EventCode": "0x85",
26
33
"EventName": "UNC_M_POWER_CHANNEL_PPD",
27
-
"MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
34
+
"MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_DCLOCKTICKS) * 100.",
28
35
"MetricName": "power_channel_ppd %",
29
36
"PerPkg": "1",
30
37
"Unit": "iMC"
···
41
34
"Counter": "0,1,2,3",
42
35
"EventCode": "0x86",
43
36
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
44
-
"MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_CLOCKTICKS) * 100.",
37
+
"MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_DCLOCKTICKS) * 100.",
45
38
"MetricName": "power_critical_throttle_cycles %",
46
39
"PerPkg": "1",
47
40
"Unit": "iMC"
···
51
44
"Counter": "0,1,2,3",
52
45
"EventCode": "0x43",
53
46
"EventName": "UNC_M_POWER_SELF_REFRESH",
54
-
"MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
47
+
"MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_DCLOCKTICKS) * 100.",
55
48
"MetricName": "power_self_refresh %",
56
49
"PerPkg": "1",
57
50
"Unit": "iMC"
+374
tools/perf/pmu-events/arch/x86/haswell/uncore.json
+374
tools/perf/pmu-events/arch/x86/haswell/uncore.json
···
1
+
[
2
+
{
3
+
"Unit": "CBO",
4
+
"EventCode": "0x22",
5
+
"UMask": "0x21",
6
+
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
7
+
"BriefDescription": "An external snoop misses in some processor core.",
8
+
"PublicDescription": "An external snoop misses in some processor core.",
9
+
"Counter": "0,1",
10
+
"CounterMask": "0",
11
+
"Invert": "0",
12
+
"EdgeDetect": "0"
13
+
},
14
+
{
15
+
"Unit": "CBO",
16
+
"EventCode": "0x22",
17
+
"UMask": "0x41",
18
+
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
19
+
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
20
+
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
21
+
"Counter": "0,1",
22
+
"CounterMask": "0",
23
+
"Invert": "0",
24
+
"EdgeDetect": "0"
25
+
},
26
+
{
27
+
"Unit": "CBO",
28
+
"EventCode": "0x22",
29
+
"UMask": "0x81",
30
+
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
31
+
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
32
+
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
33
+
"Counter": "0,1",
34
+
"CounterMask": "0",
35
+
"Invert": "0",
36
+
"EdgeDetect": "0"
37
+
},
38
+
{
39
+
"Unit": "CBO",
40
+
"EventCode": "0x22",
41
+
"UMask": "0x24",
42
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
43
+
"BriefDescription": "An external snoop hits a non-modified line in some processor core.",
44
+
"PublicDescription": "An external snoop hits a non-modified line in some processor core.",
45
+
"Counter": "0,1",
46
+
"CounterMask": "0",
47
+
"Invert": "0",
48
+
"EdgeDetect": "0"
49
+
},
50
+
{
51
+
"Unit": "CBO",
52
+
"EventCode": "0x22",
53
+
"UMask": "0x44",
54
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
55
+
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
56
+
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
57
+
"Counter": "0,1",
58
+
"CounterMask": "0",
59
+
"Invert": "0",
60
+
"EdgeDetect": "0"
61
+
},
62
+
{
63
+
"Unit": "CBO",
64
+
"EventCode": "0x22",
65
+
"UMask": "0x84",
66
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
67
+
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
68
+
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
69
+
"Counter": "0,1",
70
+
"CounterMask": "0",
71
+
"Invert": "0",
72
+
"EdgeDetect": "0"
73
+
},
74
+
{
75
+
"Unit": "CBO",
76
+
"EventCode": "0x22",
77
+
"UMask": "0x28",
78
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
79
+
"BriefDescription": "An external snoop hits a modified line in some processor core.",
80
+
"PublicDescription": "An external snoop hits a modified line in some processor core.",
81
+
"Counter": "0,1",
82
+
"CounterMask": "0",
83
+
"Invert": "0",
84
+
"EdgeDetect": "0"
85
+
},
86
+
{
87
+
"Unit": "CBO",
88
+
"EventCode": "0x22",
89
+
"UMask": "0x48",
90
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
91
+
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
92
+
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
93
+
"Counter": "0,1",
94
+
"CounterMask": "0",
95
+
"Invert": "0",
96
+
"EdgeDetect": "0"
97
+
},
98
+
{
99
+
"Unit": "CBO",
100
+
"EventCode": "0x22",
101
+
"UMask": "0x88",
102
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
103
+
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
104
+
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
105
+
"Counter": "0,1",
106
+
"CounterMask": "0",
107
+
"Invert": "0",
108
+
"EdgeDetect": "0"
109
+
},
110
+
{
111
+
"Unit": "CBO",
112
+
"EventCode": "0x34",
113
+
"UMask": "0x11",
114
+
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
115
+
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
116
+
"PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
117
+
"Counter": "0,1",
118
+
"CounterMask": "0",
119
+
"Invert": "0",
120
+
"EdgeDetect": "0"
121
+
},
122
+
{
123
+
"Unit": "CBO",
124
+
"EventCode": "0x34",
125
+
"UMask": "0x21",
126
+
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
127
+
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
128
+
"PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
129
+
"Counter": "0,1",
130
+
"CounterMask": "0",
131
+
"Invert": "0",
132
+
"EdgeDetect": "0"
133
+
},
134
+
{
135
+
"Unit": "CBO",
136
+
"EventCode": "0x34",
137
+
"UMask": "0x41",
138
+
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
139
+
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
140
+
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
141
+
"Counter": "0,1",
142
+
"CounterMask": "0",
143
+
"Invert": "0",
144
+
"EdgeDetect": "0"
145
+
},
146
+
{
147
+
"Unit": "CBO",
148
+
"EventCode": "0x34",
149
+
"UMask": "0x81",
150
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
151
+
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
152
+
"PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
153
+
"Counter": "0,1",
154
+
"CounterMask": "0",
155
+
"Invert": "0",
156
+
"EdgeDetect": "0"
157
+
},
158
+
{
159
+
"Unit": "CBO",
160
+
"EventCode": "0x34",
161
+
"UMask": "0x18",
162
+
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
163
+
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
164
+
"PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
165
+
"Counter": "0,1",
166
+
"CounterMask": "0",
167
+
"Invert": "0",
168
+
"EdgeDetect": "0"
169
+
},
170
+
{
171
+
"Unit": "CBO",
172
+
"EventCode": "0x34",
173
+
"UMask": "0x28",
174
+
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
175
+
"BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
176
+
"PublicDescription": "L3 Lookup write request that access cache and found line in I-state.",
177
+
"Counter": "0,1",
178
+
"CounterMask": "0",
179
+
"Invert": "0",
180
+
"EdgeDetect": "0"
181
+
},
182
+
{
183
+
"Unit": "CBO",
184
+
"EventCode": "0x34",
185
+
"UMask": "0x48",
186
+
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
187
+
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
188
+
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
189
+
"Counter": "0,1",
190
+
"CounterMask": "0",
191
+
"Invert": "0",
192
+
"EdgeDetect": "0"
193
+
},
194
+
{
195
+
"Unit": "CBO",
196
+
"EventCode": "0x34",
197
+
"UMask": "0x88",
198
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
199
+
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
200
+
"PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
201
+
"Counter": "0,1",
202
+
"CounterMask": "0",
203
+
"Invert": "0",
204
+
"EdgeDetect": "0"
205
+
},
206
+
{
207
+
"Unit": "CBO",
208
+
"EventCode": "0x34",
209
+
"UMask": "0x1f",
210
+
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
211
+
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
212
+
"PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
213
+
"Counter": "0,1",
214
+
"CounterMask": "0",
215
+
"Invert": "0",
216
+
"EdgeDetect": "0"
217
+
},
218
+
{
219
+
"Unit": "CBO",
220
+
"EventCode": "0x34",
221
+
"UMask": "0x2f",
222
+
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
223
+
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
224
+
"PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
225
+
"Counter": "0,1",
226
+
"CounterMask": "0",
227
+
"Invert": "0",
228
+
"EdgeDetect": "0"
229
+
},
230
+
{
231
+
"Unit": "CBO",
232
+
"EventCode": "0x34",
233
+
"UMask": "0x4f",
234
+
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
235
+
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
236
+
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
237
+
"Counter": "0,1",
238
+
"CounterMask": "0",
239
+
"Invert": "0",
240
+
"EdgeDetect": "0"
241
+
},
242
+
{
243
+
"Unit": "CBO",
244
+
"EventCode": "0x34",
245
+
"UMask": "0x8f",
246
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
247
+
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
248
+
"PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
249
+
"Counter": "0,1",
250
+
"CounterMask": "0",
251
+
"Invert": "0",
252
+
"EdgeDetect": "0"
253
+
},
254
+
{
255
+
"Unit": "CBO",
256
+
"EventCode": "0x34",
257
+
"UMask": "0x86",
258
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
259
+
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
260
+
"PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
261
+
"Counter": "0,1",
262
+
"CounterMask": "0",
263
+
"Invert": "0",
264
+
"EdgeDetect": "0"
265
+
},
266
+
{
267
+
"Unit": "CBO",
268
+
"EventCode": "0x34",
269
+
"UMask": "0x46",
270
+
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
271
+
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
272
+
"PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
273
+
"Counter": "0,1",
274
+
"CounterMask": "0",
275
+
"Invert": "0",
276
+
"EdgeDetect": "0"
277
+
},
278
+
{
279
+
"Unit": "CBO",
280
+
"EventCode": "0x34",
281
+
"UMask": "0x16",
282
+
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
283
+
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
284
+
"PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
285
+
"Counter": "0,1",
286
+
"CounterMask": "0",
287
+
"Invert": "0",
288
+
"EdgeDetect": "0"
289
+
},
290
+
{
291
+
"Unit": "CBO",
292
+
"EventCode": "0x34",
293
+
"UMask": "0x26",
294
+
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
295
+
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
296
+
"PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
297
+
"Counter": "0,1",
298
+
"CounterMask": "0",
299
+
"Invert": "0",
300
+
"EdgeDetect": "0"
301
+
},
302
+
{
303
+
"Unit": "iMPH-U",
304
+
"EventCode": "0x80",
305
+
"UMask": "0x01",
306
+
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
307
+
"BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
308
+
"PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
309
+
"Counter": "0",
310
+
"CounterMask": "0",
311
+
"Invert": "0",
312
+
"EdgeDetect": "0"
313
+
},
314
+
{
315
+
"Unit": "iMPH-U",
316
+
"EventCode": "0x81",
317
+
"UMask": "0x01",
318
+
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
319
+
"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
320
+
"PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
321
+
"Counter": "0,1",
322
+
"CounterMask": "0",
323
+
"Invert": "0",
324
+
"EdgeDetect": "0"
325
+
},
326
+
{
327
+
"Unit": "iMPH-U",
328
+
"EventCode": "0x81",
329
+
"UMask": "0x20",
330
+
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
331
+
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
332
+
"PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
333
+
"Counter": "0,1",
334
+
"CounterMask": "0",
335
+
"Invert": "0",
336
+
"EdgeDetect": "0"
337
+
},
338
+
{
339
+
"Unit": "iMPH-U",
340
+
"EventCode": "0x83",
341
+
"UMask": "0x01",
342
+
"EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All",
343
+
"BriefDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)",
344
+
"PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory).",
345
+
"Counter": "0",
346
+
"CounterMask": "0",
347
+
"Invert": "0",
348
+
"EdgeDetect": "0"
349
+
},
350
+
{
351
+
"Unit": "iMPH-U",
352
+
"EventCode": "0x84",
353
+
"UMask": "0x01",
354
+
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
355
+
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
356
+
"PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
357
+
"Counter": "0,1",
358
+
"CounterMask": "0",
359
+
"Invert": "0",
360
+
"EdgeDetect": "0"
361
+
},
362
+
{
363
+
"Unit": "NCU",
364
+
"EventCode": "0x0",
365
+
"UMask": "0x01",
366
+
"EventName": "UNC_CLOCK.SOCKET",
367
+
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
368
+
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
369
+
"Counter": "FIXED",
370
+
"CounterMask": "0",
371
+
"Invert": "0",
372
+
"EdgeDetect": "0"
373
+
}
374
+
]
+314
tools/perf/pmu-events/arch/x86/ivybridge/uncore.json
+314
tools/perf/pmu-events/arch/x86/ivybridge/uncore.json
···
1
+
[
2
+
{
3
+
"Unit": "CBO",
4
+
"EventCode": "0x22",
5
+
"UMask": "0x01",
6
+
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS",
7
+
"BriefDescription": "A snoop misses in some processor core.",
8
+
"PublicDescription": "A snoop misses in some processor core.",
9
+
"Counter": "0,1",
10
+
"CounterMask": "0",
11
+
"Invert": "0",
12
+
"EdgeDetect": "0"
13
+
},
14
+
{
15
+
"Unit": "CBO",
16
+
"EventCode": "0x22",
17
+
"UMask": "0x02",
18
+
"EventName": "UNC_CBO_XSNP_RESPONSE.INVAL",
19
+
"BriefDescription": "A snoop invalidates a non-modified line in some processor core.",
20
+
"PublicDescription": "A snoop invalidates a non-modified line in some processor core.",
21
+
"Counter": "0,1",
22
+
"CounterMask": "0",
23
+
"Invert": "0",
24
+
"EdgeDetect": "0"
25
+
},
26
+
{
27
+
"Unit": "CBO",
28
+
"EventCode": "0x22",
29
+
"UMask": "0x04",
30
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT",
31
+
"BriefDescription": "A snoop hits a non-modified line in some processor core.",
32
+
"PublicDescription": "A snoop hits a non-modified line in some processor core.",
33
+
"Counter": "0,1",
34
+
"CounterMask": "0",
35
+
"Invert": "0",
36
+
"EdgeDetect": "0"
37
+
},
38
+
{
39
+
"Unit": "CBO",
40
+
"EventCode": "0x22",
41
+
"UMask": "0x08",
42
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM",
43
+
"BriefDescription": "A snoop hits a modified line in some processor core.",
44
+
"PublicDescription": "A snoop hits a modified line in some processor core.",
45
+
"Counter": "0,1",
46
+
"CounterMask": "0",
47
+
"Invert": "0",
48
+
"EdgeDetect": "0"
49
+
},
50
+
{
51
+
"Unit": "CBO",
52
+
"EventCode": "0x22",
53
+
"UMask": "0x10",
54
+
"EventName": "UNC_CBO_XSNP_RESPONSE.INVAL_M",
55
+
"BriefDescription": "A snoop invalidates a modified line in some processor core.",
56
+
"PublicDescription": "A snoop invalidates a modified line in some processor core.",
57
+
"Counter": "0,1",
58
+
"CounterMask": "0",
59
+
"Invert": "0",
60
+
"EdgeDetect": "0"
61
+
},
62
+
{
63
+
"Unit": "CBO",
64
+
"EventCode": "0x22",
65
+
"UMask": "0x20",
66
+
"EventName": "UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER",
67
+
"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.",
68
+
"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.",
69
+
"Counter": "0,1",
70
+
"CounterMask": "0",
71
+
"Invert": "0",
72
+
"EdgeDetect": "0"
73
+
},
74
+
{
75
+
"Unit": "CBO",
76
+
"EventCode": "0x22",
77
+
"UMask": "0x40",
78
+
"EventName": "UNC_CBO_XSNP_RESPONSE.XCORE_FILTER",
79
+
"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.",
80
+
"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.",
81
+
"Counter": "0,1",
82
+
"CounterMask": "0",
83
+
"Invert": "0",
84
+
"EdgeDetect": "0"
85
+
},
86
+
{
87
+
"Unit": "CBO",
88
+
"EventCode": "0x22",
89
+
"UMask": "0x80",
90
+
"EventName": "UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER",
91
+
"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
92
+
"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
93
+
"Counter": "0,1",
94
+
"CounterMask": "0",
95
+
"Invert": "0",
96
+
"EdgeDetect": "0"
97
+
},
98
+
{
99
+
"Unit": "CBO",
100
+
"EventCode": "0x34",
101
+
"UMask": "0x01",
102
+
"EventName": "UNC_CBO_CACHE_LOOKUP.M",
103
+
"BriefDescription": "LLC lookup request that access cache and found line in M-state.",
104
+
"PublicDescription": "LLC lookup request that access cache and found line in M-state.",
105
+
"Counter": "0,1",
106
+
"CounterMask": "0",
107
+
"Invert": "0",
108
+
"EdgeDetect": "0"
109
+
},
110
+
{
111
+
"Unit": "CBO",
112
+
"EventCode": "0x34",
113
+
"UMask": "0x02",
114
+
"EventName": "UNC_CBO_CACHE_LOOKUP.E",
115
+
"BriefDescription": "LLC lookup request that access cache and found line in E-state.",
116
+
"PublicDescription": "LLC lookup request that access cache and found line in E-state.",
117
+
"Counter": "0,1",
118
+
"CounterMask": "0",
119
+
"Invert": "0",
120
+
"EdgeDetect": "0"
121
+
},
122
+
{
123
+
"Unit": "CBO",
124
+
"EventCode": "0x34",
125
+
"UMask": "0x04",
126
+
"EventName": "UNC_CBO_CACHE_LOOKUP.S",
127
+
"BriefDescription": "LLC lookup request that access cache and found line in S-state.",
128
+
"PublicDescription": "LLC lookup request that access cache and found line in S-state.",
129
+
"Counter": "0,1",
130
+
"CounterMask": "0",
131
+
"Invert": "0",
132
+
"EdgeDetect": "0"
133
+
},
134
+
{
135
+
"Unit": "CBO",
136
+
"EventCode": "0x34",
137
+
"UMask": "0x08",
138
+
"EventName": "UNC_CBO_CACHE_LOOKUP.I",
139
+
"BriefDescription": "LLC lookup request that access cache and found line in I-state.",
140
+
"PublicDescription": "LLC lookup request that access cache and found line in I-state.",
141
+
"Counter": "0,1",
142
+
"CounterMask": "0",
143
+
"Invert": "0",
144
+
"EdgeDetect": "0"
145
+
},
146
+
{
147
+
"Unit": "CBO",
148
+
"EventCode": "0x34",
149
+
"UMask": "0x10",
150
+
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_FILTER",
151
+
"BriefDescription": "Filter on processor core initiated cacheable read requests.",
152
+
"PublicDescription": "Filter on processor core initiated cacheable read requests.",
153
+
"Counter": "0,1",
154
+
"CounterMask": "0",
155
+
"Invert": "0",
156
+
"EdgeDetect": "0"
157
+
},
158
+
{
159
+
"Unit": "CBO",
160
+
"EventCode": "0x34",
161
+
"UMask": "0x20",
162
+
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_FILTER",
163
+
"BriefDescription": "Filter on processor core initiated cacheable write requests.",
164
+
"PublicDescription": "Filter on processor core initiated cacheable write requests.",
165
+
"Counter": "0,1",
166
+
"CounterMask": "0",
167
+
"Invert": "0",
168
+
"EdgeDetect": "0"
169
+
},
170
+
{
171
+
"Unit": "CBO",
172
+
"EventCode": "0x34",
173
+
"UMask": "0x40",
174
+
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER",
175
+
"BriefDescription": "Filter on external snoop requests.",
176
+
"PublicDescription": "Filter on external snoop requests.",
177
+
"Counter": "0,1",
178
+
"CounterMask": "0",
179
+
"Invert": "0",
180
+
"EdgeDetect": "0"
181
+
},
182
+
{
183
+
"Unit": "CBO",
184
+
"EventCode": "0x34",
185
+
"UMask": "0x80",
186
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER",
187
+
"BriefDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.",
188
+
"PublicDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.",
189
+
"Counter": "0,1",
190
+
"CounterMask": "0",
191
+
"Invert": "0",
192
+
"EdgeDetect": "0"
193
+
},
194
+
{
195
+
"Unit": "ARB",
196
+
"EventCode": "0x80",
197
+
"UMask": "0x01",
198
+
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
199
+
"BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
200
+
"PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
201
+
"Counter": "0",
202
+
"CounterMask": "0",
203
+
"Invert": "0",
204
+
"EdgeDetect": "0"
205
+
},
206
+
{
207
+
"Unit": "ARB",
208
+
"EventCode": "0x81",
209
+
"UMask": "0x01",
210
+
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
211
+
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
212
+
"PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
213
+
"Counter": "0,1",
214
+
"CounterMask": "0",
215
+
"Invert": "0",
216
+
"EdgeDetect": "0"
217
+
},
218
+
{
219
+
"Unit": "ARB",
220
+
"EventCode": "0x81",
221
+
"UMask": "0x20",
222
+
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
223
+
"BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
224
+
"PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
225
+
"Counter": "0,1",
226
+
"CounterMask": "0",
227
+
"Invert": "0",
228
+
"EdgeDetect": "0"
229
+
},
230
+
{
231
+
"Unit": "ARB",
232
+
"EventCode": "0x81",
233
+
"UMask": "0x80",
234
+
"EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
235
+
"BriefDescription": "Counts the number of LLC evictions allocated.",
236
+
"PublicDescription": "Counts the number of LLC evictions allocated.",
237
+
"Counter": "0,1",
238
+
"CounterMask": "0",
239
+
"Invert": "0",
240
+
"EdgeDetect": "0"
241
+
},
242
+
{
243
+
"Unit": "ARB",
244
+
"EventCode": "0x83",
245
+
"UMask": "0x01",
246
+
"EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
247
+
"BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
248
+
"PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
249
+
"Counter": "0",
250
+
"CounterMask": "0",
251
+
"Invert": "0",
252
+
"EdgeDetect": "0"
253
+
},
254
+
{
255
+
"Unit": "ARB",
256
+
"EventCode": "0x84",
257
+
"UMask": "0x01",
258
+
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
259
+
"BriefDescription": "Number of requests allocated in Coherency Tracker.",
260
+
"PublicDescription": "Number of requests allocated in Coherency Tracker.",
261
+
"Counter": "0,1",
262
+
"CounterMask": "0",
263
+
"Invert": "0",
264
+
"EdgeDetect": "0"
265
+
},
266
+
{
267
+
"Unit": "ARB",
268
+
"EventCode": "0x80",
269
+
"UMask": "0x01",
270
+
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
271
+
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
272
+
"PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
273
+
"Counter": "0,1",
274
+
"CounterMask": "1",
275
+
"Invert": "0",
276
+
"EdgeDetect": "0"
277
+
},
278
+
{
279
+
"Unit": "ARB",
280
+
"EventCode": "0x80",
281
+
"UMask": "0x01",
282
+
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
283
+
"BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
284
+
"PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
285
+
"Counter": "0,1",
286
+
"CounterMask": "10",
287
+
"Invert": "0",
288
+
"EdgeDetect": "0"
289
+
},
290
+
{
291
+
"Unit": "ARB",
292
+
"EventCode": "0x0",
293
+
"UMask": "0x01",
294
+
"EventName": "UNC_CLOCK.SOCKET",
295
+
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
296
+
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
297
+
"Counter": "Fixed",
298
+
"CounterMask": "0",
299
+
"Invert": "0",
300
+
"EdgeDetect": "0"
301
+
},
302
+
{
303
+
"Unit": "CBO",
304
+
"EventCode": "0x34",
305
+
"UMask": "0x06",
306
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ES",
307
+
"BriefDescription": "LLC lookup request that access cache and found line in E-state or S-state.",
308
+
"PublicDescription": "LLC lookup request that access cache and found line in E-state or S-state.",
309
+
"Counter": "0,1",
310
+
"CounterMask": "0",
311
+
"Invert": "0",
312
+
"EdgeDetect": "0"
313
+
}
314
+
]
+314
tools/perf/pmu-events/arch/x86/sandybridge/uncore.json
+314
tools/perf/pmu-events/arch/x86/sandybridge/uncore.json
···
1
+
[
2
+
{
3
+
"Unit": "CBO",
4
+
"EventCode": "0x22",
5
+
"UMask": "0x01",
6
+
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS",
7
+
"BriefDescription": "A snoop misses in some processor core.",
8
+
"PublicDescription": "A snoop misses in some processor core.",
9
+
"Counter": "0,1",
10
+
"CounterMask": "0",
11
+
"Invert": "0",
12
+
"EdgeDetect": "0"
13
+
},
14
+
{
15
+
"Unit": "CBO",
16
+
"EventCode": "0x22",
17
+
"UMask": "0x02",
18
+
"EventName": "UNC_CBO_XSNP_RESPONSE.INVAL",
19
+
"BriefDescription": "A snoop invalidates a non-modified line in some processor core.",
20
+
"PublicDescription": "A snoop invalidates a non-modified line in some processor core.",
21
+
"Counter": "0,1",
22
+
"CounterMask": "0",
23
+
"Invert": "0",
24
+
"EdgeDetect": "0"
25
+
},
26
+
{
27
+
"Unit": "CBO",
28
+
"EventCode": "0x22",
29
+
"UMask": "0x04",
30
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT",
31
+
"BriefDescription": "A snoop hits a non-modified line in some processor core.",
32
+
"PublicDescription": "A snoop hits a non-modified line in some processor core.",
33
+
"Counter": "0,1",
34
+
"CounterMask": "0",
35
+
"Invert": "0",
36
+
"EdgeDetect": "0"
37
+
},
38
+
{
39
+
"Unit": "CBO",
40
+
"EventCode": "0x22",
41
+
"UMask": "0x08",
42
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM",
43
+
"BriefDescription": "A snoop hits a modified line in some processor core.",
44
+
"PublicDescription": "A snoop hits a modified line in some processor core.",
45
+
"Counter": "0,1",
46
+
"CounterMask": "0",
47
+
"Invert": "0",
48
+
"EdgeDetect": "0"
49
+
},
50
+
{
51
+
"Unit": "CBO",
52
+
"EventCode": "0x22",
53
+
"UMask": "0x10",
54
+
"EventName": "UNC_CBO_XSNP_RESPONSE.INVAL_M",
55
+
"BriefDescription": "A snoop invalidates a modified line in some processor core.",
56
+
"PublicDescription": "A snoop invalidates a modified line in some processor core.",
57
+
"Counter": "0,1",
58
+
"CounterMask": "0",
59
+
"Invert": "0",
60
+
"EdgeDetect": "0"
61
+
},
62
+
{
63
+
"Unit": "CBO",
64
+
"EventCode": "0x22",
65
+
"UMask": "0x20",
66
+
"EventName": "UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER",
67
+
"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.",
68
+
"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.",
69
+
"Counter": "0,1",
70
+
"CounterMask": "0",
71
+
"Invert": "0",
72
+
"EdgeDetect": "0"
73
+
},
74
+
{
75
+
"Unit": "CBO",
76
+
"EventCode": "0x22",
77
+
"UMask": "0x40",
78
+
"EventName": "UNC_CBO_XSNP_RESPONSE.XCORE_FILTER",
79
+
"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.",
80
+
"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.",
81
+
"Counter": "0,1",
82
+
"CounterMask": "0",
83
+
"Invert": "0",
84
+
"EdgeDetect": "0"
85
+
},
86
+
{
87
+
"Unit": "CBO",
88
+
"EventCode": "0x22",
89
+
"UMask": "0x80",
90
+
"EventName": "UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER",
91
+
"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
92
+
"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
93
+
"Counter": "0,1",
94
+
"CounterMask": "0",
95
+
"Invert": "0",
96
+
"EdgeDetect": "0"
97
+
},
98
+
{
99
+
"Unit": "CBO",
100
+
"EventCode": "0x34",
101
+
"UMask": "0x01",
102
+
"EventName": "UNC_CBO_CACHE_LOOKUP.M",
103
+
"BriefDescription": "LLC lookup request that access cache and found line in M-state.",
104
+
"PublicDescription": "LLC lookup request that access cache and found line in M-state.",
105
+
"Counter": "0,1",
106
+
"CounterMask": "0",
107
+
"Invert": "0",
108
+
"EdgeDetect": "0"
109
+
},
110
+
{
111
+
"Unit": "CBO",
112
+
"EventCode": "0x34",
113
+
"UMask": "0x02",
114
+
"EventName": "UNC_CBO_CACHE_LOOKUP.E",
115
+
"BriefDescription": "LLC lookup request that access cache and found line in E-state.",
116
+
"PublicDescription": "LLC lookup request that access cache and found line in E-state.",
117
+
"Counter": "0,1",
118
+
"CounterMask": "0",
119
+
"Invert": "0",
120
+
"EdgeDetect": "0"
121
+
},
122
+
{
123
+
"Unit": "CBO",
124
+
"EventCode": "0x34",
125
+
"UMask": "0x04",
126
+
"EventName": "UNC_CBO_CACHE_LOOKUP.S",
127
+
"BriefDescription": "LLC lookup request that access cache and found line in S-state.",
128
+
"PublicDescription": "LLC lookup request that access cache and found line in S-state.",
129
+
"Counter": "0,1",
130
+
"CounterMask": "0",
131
+
"Invert": "0",
132
+
"EdgeDetect": "0"
133
+
},
134
+
{
135
+
"Unit": "CBO",
136
+
"EventCode": "0x34",
137
+
"UMask": "0x08",
138
+
"EventName": "UNC_CBO_CACHE_LOOKUP.I",
139
+
"BriefDescription": "LLC lookup request that access cache and found line in I-state.",
140
+
"PublicDescription": "LLC lookup request that access cache and found line in I-state.",
141
+
"Counter": "0,1",
142
+
"CounterMask": "0",
143
+
"Invert": "0",
144
+
"EdgeDetect": "0"
145
+
},
146
+
{
147
+
"Unit": "CBO",
148
+
"EventCode": "0x34",
149
+
"UMask": "0x10",
150
+
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_FILTER",
151
+
"BriefDescription": "Filter on processor core initiated cacheable read requests.",
152
+
"PublicDescription": "Filter on processor core initiated cacheable read requests.",
153
+
"Counter": "0,1",
154
+
"CounterMask": "0",
155
+
"Invert": "0",
156
+
"EdgeDetect": "0"
157
+
},
158
+
{
159
+
"Unit": "CBO",
160
+
"EventCode": "0x34",
161
+
"UMask": "0x20",
162
+
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_FILTER",
163
+
"BriefDescription": "Filter on processor core initiated cacheable write requests.",
164
+
"PublicDescription": "Filter on processor core initiated cacheable write requests.",
165
+
"Counter": "0,1",
166
+
"CounterMask": "0",
167
+
"Invert": "0",
168
+
"EdgeDetect": "0"
169
+
},
170
+
{
171
+
"Unit": "CBO",
172
+
"EventCode": "0x34",
173
+
"UMask": "0x40",
174
+
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER",
175
+
"BriefDescription": "Filter on external snoop requests.",
176
+
"PublicDescription": "Filter on external snoop requests.",
177
+
"Counter": "0,1",
178
+
"CounterMask": "0",
179
+
"Invert": "0",
180
+
"EdgeDetect": "0"
181
+
},
182
+
{
183
+
"Unit": "CBO",
184
+
"EventCode": "0x34",
185
+
"UMask": "0x80",
186
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER",
187
+
"BriefDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.",
188
+
"PublicDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.",
189
+
"Counter": "0,1",
190
+
"CounterMask": "0",
191
+
"Invert": "0",
192
+
"EdgeDetect": "0"
193
+
},
194
+
{
195
+
"Unit": "ARB",
196
+
"EventCode": "0x80",
197
+
"UMask": "0x01",
198
+
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
199
+
"BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
200
+
"PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
201
+
"Counter": "0",
202
+
"CounterMask": "0",
203
+
"Invert": "0",
204
+
"EdgeDetect": "0"
205
+
},
206
+
{
207
+
"Unit": "ARB",
208
+
"EventCode": "0x81",
209
+
"UMask": "0x01",
210
+
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
211
+
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
212
+
"PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
213
+
"Counter": "0,1",
214
+
"CounterMask": "0",
215
+
"Invert": "0",
216
+
"EdgeDetect": "0"
217
+
},
218
+
{
219
+
"Unit": "ARB",
220
+
"EventCode": "0x81",
221
+
"UMask": "0x20",
222
+
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
223
+
"BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
224
+
"PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
225
+
"Counter": "0,1",
226
+
"CounterMask": "0",
227
+
"Invert": "0",
228
+
"EdgeDetect": "0"
229
+
},
230
+
{
231
+
"Unit": "ARB",
232
+
"EventCode": "0x81",
233
+
"UMask": "0x80",
234
+
"EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
235
+
"BriefDescription": "Counts the number of LLC evictions allocated.",
236
+
"PublicDescription": "Counts the number of LLC evictions allocated.",
237
+
"Counter": "0,1",
238
+
"CounterMask": "0",
239
+
"Invert": "0",
240
+
"EdgeDetect": "0"
241
+
},
242
+
{
243
+
"Unit": "ARB",
244
+
"EventCode": "0x83",
245
+
"UMask": "0x01",
246
+
"EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
247
+
"BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
248
+
"PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
249
+
"Counter": "0",
250
+
"CounterMask": "0",
251
+
"Invert": "0",
252
+
"EdgeDetect": "0"
253
+
},
254
+
{
255
+
"Unit": "ARB",
256
+
"EventCode": "0x84",
257
+
"UMask": "0x01",
258
+
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
259
+
"BriefDescription": "Number of requests allocated in Coherency Tracker.",
260
+
"PublicDescription": "Number of requests allocated in Coherency Tracker.",
261
+
"Counter": "0,1",
262
+
"CounterMask": "0",
263
+
"Invert": "0",
264
+
"EdgeDetect": "0"
265
+
},
266
+
{
267
+
"Unit": "ARB",
268
+
"EventCode": "0x80",
269
+
"UMask": "0x01",
270
+
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
271
+
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
272
+
"PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
273
+
"Counter": "0,1",
274
+
"CounterMask": "1",
275
+
"Invert": "0",
276
+
"EdgeDetect": "0"
277
+
},
278
+
{
279
+
"Unit": "ARB",
280
+
"EventCode": "0x80",
281
+
"UMask": "0x01",
282
+
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
283
+
"BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
284
+
"PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
285
+
"Counter": "0,1",
286
+
"CounterMask": "10",
287
+
"Invert": "0",
288
+
"EdgeDetect": "0"
289
+
},
290
+
{
291
+
"Unit": "ARB",
292
+
"EventCode": "0x0",
293
+
"UMask": "0x01",
294
+
"EventName": "UNC_CLOCK.SOCKET",
295
+
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
296
+
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
297
+
"Counter": "Fixed",
298
+
"CounterMask": "0",
299
+
"Invert": "0",
300
+
"EdgeDetect": "0"
301
+
},
302
+
{
303
+
"Unit": "CBO",
304
+
"EventCode": "0x34",
305
+
"UMask": "0x06",
306
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ES",
307
+
"BriefDescription": "LLC lookup request that access cache and found line in E-state or S-state.",
308
+
"PublicDescription": "LLC lookup request that access cache and found line in E-state or S-state.",
309
+
"Counter": "0,1",
310
+
"CounterMask": "0",
311
+
"Invert": "0",
312
+
"EdgeDetect": "0"
313
+
}
314
+
]
+254
tools/perf/pmu-events/arch/x86/skylake/uncore.json
+254
tools/perf/pmu-events/arch/x86/skylake/uncore.json
···
1
+
[
2
+
{
3
+
"Unit": "CBO",
4
+
"EventCode": "0x22",
5
+
"UMask": "0x41",
6
+
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
7
+
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
8
+
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
9
+
"Counter": "0,1",
10
+
"CounterMask": "0",
11
+
"Invert": "0",
12
+
"EdgeDetect": "0"
13
+
},
14
+
{
15
+
"Unit": "CBO",
16
+
"EventCode": "0x22",
17
+
"UMask": "0x81",
18
+
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
19
+
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
20
+
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
21
+
"Counter": "0,1",
22
+
"CounterMask": "0",
23
+
"Invert": "0",
24
+
"EdgeDetect": "0"
25
+
},
26
+
{
27
+
"Unit": "CBO",
28
+
"EventCode": "0x22",
29
+
"UMask": "0x44",
30
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
31
+
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
32
+
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
33
+
"Counter": "0,1",
34
+
"CounterMask": "0",
35
+
"Invert": "0",
36
+
"EdgeDetect": "0"
37
+
},
38
+
{
39
+
"Unit": "CBO",
40
+
"EventCode": "0x22",
41
+
"UMask": "0x48",
42
+
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
43
+
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
44
+
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
45
+
"Counter": "0,1",
46
+
"CounterMask": "0",
47
+
"Invert": "0",
48
+
"EdgeDetect": "0"
49
+
},
50
+
{
51
+
"Unit": "CBO",
52
+
"EventCode": "0x34",
53
+
"UMask": "0x21",
54
+
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
55
+
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
56
+
"PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
57
+
"Counter": "0,1",
58
+
"CounterMask": "0",
59
+
"Invert": "0",
60
+
"EdgeDetect": "0"
61
+
},
62
+
{
63
+
"Unit": "CBO",
64
+
"EventCode": "0x34",
65
+
"UMask": "0x81",
66
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
67
+
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
68
+
"PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
69
+
"Counter": "0,1",
70
+
"CounterMask": "0",
71
+
"Invert": "0",
72
+
"EdgeDetect": "0"
73
+
},
74
+
{
75
+
"Unit": "CBO",
76
+
"EventCode": "0x34",
77
+
"UMask": "0x18",
78
+
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
79
+
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
80
+
"PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
81
+
"Counter": "0,1",
82
+
"CounterMask": "0",
83
+
"Invert": "0",
84
+
"EdgeDetect": "0"
85
+
},
86
+
{
87
+
"Unit": "CBO",
88
+
"EventCode": "0x34",
89
+
"UMask": "0x88",
90
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
91
+
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
92
+
"PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
93
+
"Counter": "0,1",
94
+
"CounterMask": "0",
95
+
"Invert": "0",
96
+
"EdgeDetect": "0"
97
+
},
98
+
{
99
+
"Unit": "CBO",
100
+
"EventCode": "0x34",
101
+
"UMask": "0x1f",
102
+
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
103
+
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
104
+
"PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
105
+
"Counter": "0,1",
106
+
"CounterMask": "0",
107
+
"Invert": "0",
108
+
"EdgeDetect": "0"
109
+
},
110
+
{
111
+
"Unit": "CBO",
112
+
"EventCode": "0x34",
113
+
"UMask": "0x2f",
114
+
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
115
+
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
116
+
"PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
117
+
"Counter": "0,1",
118
+
"CounterMask": "0",
119
+
"Invert": "0",
120
+
"EdgeDetect": "0"
121
+
},
122
+
{
123
+
"Unit": "CBO",
124
+
"EventCode": "0x34",
125
+
"UMask": "0x8f",
126
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
127
+
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
128
+
"PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
129
+
"Counter": "0,1",
130
+
"CounterMask": "0",
131
+
"Invert": "0",
132
+
"EdgeDetect": "0"
133
+
},
134
+
{
135
+
"Unit": "CBO",
136
+
"EventCode": "0x34",
137
+
"UMask": "0x86",
138
+
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
139
+
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
140
+
"PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
141
+
"Counter": "0,1",
142
+
"CounterMask": "0",
143
+
"Invert": "0",
144
+
"EdgeDetect": "0"
145
+
},
146
+
{
147
+
"Unit": "CBO",
148
+
"EventCode": "0x34",
149
+
"UMask": "0x16",
150
+
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
151
+
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
152
+
"PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
153
+
"Counter": "0,1",
154
+
"CounterMask": "0",
155
+
"Invert": "0",
156
+
"EdgeDetect": "0"
157
+
},
158
+
{
159
+
"Unit": "CBO",
160
+
"EventCode": "0x34",
161
+
"UMask": "0x26",
162
+
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
163
+
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
164
+
"PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
165
+
"Counter": "0,1",
166
+
"CounterMask": "0",
167
+
"Invert": "0",
168
+
"EdgeDetect": "0"
169
+
},
170
+
{
171
+
"Unit": "iMPH-U",
172
+
"EventCode": "0x80",
173
+
"UMask": "0x01",
174
+
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
175
+
"BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
176
+
"PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
177
+
"Counter": "0",
178
+
"CounterMask": "0",
179
+
"Invert": "0",
180
+
"EdgeDetect": "0"
181
+
},
182
+
{
183
+
"Unit": "iMPH-U",
184
+
"EventCode": "0x81",
185
+
"UMask": "0x01",
186
+
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
187
+
"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
188
+
"PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
189
+
"Counter": "0,1",
190
+
"CounterMask": "0",
191
+
"Invert": "0",
192
+
"EdgeDetect": "0"
193
+
},
194
+
{
195
+
"Unit": "iMPH-U",
196
+
"EventCode": "0x81",
197
+
"UMask": "0x02",
198
+
"EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
199
+
"BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
200
+
"PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
201
+
"Counter": "0,1",
202
+
"CounterMask": "0",
203
+
"Invert": "0",
204
+
"EdgeDetect": "0"
205
+
},
206
+
{
207
+
"Unit": "iMPH-U",
208
+
"EventCode": "0x81",
209
+
"UMask": "0x20",
210
+
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
211
+
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
212
+
"PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
213
+
"Counter": "0,1",
214
+
"CounterMask": "0",
215
+
"Invert": "0",
216
+
"EdgeDetect": "0"
217
+
},
218
+
{
219
+
"Unit": "iMPH-U",
220
+
"EventCode": "0x84",
221
+
"UMask": "0x01",
222
+
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
223
+
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
224
+
"PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
225
+
"Counter": "0,1",
226
+
"CounterMask": "0",
227
+
"Invert": "0",
228
+
"EdgeDetect": "0"
229
+
},
230
+
{
231
+
"Unit": "iMPH-U",
232
+
"EventCode": "0x80",
233
+
"UMask": "0x01",
234
+
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
235
+
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",
236
+
"PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
237
+
"Counter": "0",
238
+
"CounterMask": "1",
239
+
"Invert": "0",
240
+
"EdgeDetect": "0"
241
+
},
242
+
{
243
+
"Unit": "NCU",
244
+
"EventCode": "0x0",
245
+
"UMask": "0x01",
246
+
"EventName": "UNC_CLOCK.SOCKET",
247
+
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
248
+
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
249
+
"Counter": "FIXED",
250
+
"CounterMask": "0",
251
+
"Invert": "0",
252
+
"EdgeDetect": "0"
253
+
}
254
+
]
+2
tools/perf/pmu-events/jevents.c
+2
tools/perf/pmu-events/jevents.c
···
195
195
{ "CBO", "uncore_cbox" },
196
196
{ "QPI LL", "uncore_qpi" },
197
197
{ "SBO", "uncore_sbox" },
198
+
{ "iMPH-U", "uncore_arb" },
198
199
{}
199
200
};
200
201
···
469
468
}
470
469
addfield(map, &desc, ". ", "Unit: ", NULL);
471
470
addfield(map, &desc, "", pmu, NULL);
471
+
addfield(map, &desc, "", " ", NULL);
472
472
} else if (json_streq(map, field, "Filter")) {
473
473
addfield(map, &filter, "", "", val);
474
474
} else if (json_streq(map, field, "ScaleUnit")) {
+4
-2
tools/perf/util/annotate.c
+4
-2
tools/perf/util/annotate.c
···
1665
1665
start = map__rip_2objdump(map, sym->start);
1666
1666
1667
1667
for (i = 0; i < len; i++) {
1668
-
u64 offset;
1668
+
u64 offset, nr_samples;
1669
1669
double percent_max = 0.0;
1670
1670
1671
1671
src_line->nr_pcnt = nr_pcnt;
···
1674
1674
double percent = 0.0;
1675
1675
1676
1676
h = annotation__histogram(notes, evidx + k);
1677
+
nr_samples = h->addr[i];
1677
1678
if (h->sum)
1678
-
percent = 100.0 * h->addr[i] / h->sum;
1679
+
percent = 100.0 * nr_samples / h->sum;
1679
1680
1680
1681
if (percent > percent_max)
1681
1682
percent_max = percent;
1682
1683
src_line->samples[k].percent = percent;
1684
+
src_line->samples[k].nr = nr_samples;
1683
1685
}
1684
1686
1685
1687
if (percent_max <= 0.5)
+1
-1
tools/perf/util/annotate.h
+1
-1
tools/perf/util/annotate.h
+46
-17
tools/perf/util/values.c
+46
-17
tools/perf/util/values.c
···
1
+
#include <inttypes.h>
2
+
#include <stdio.h>
1
3
#include <stdlib.h>
4
+
#include <errno.h>
2
5
3
6
#include "util.h"
4
7
#include "values.h"
···
111
108
return i;
112
109
}
113
110
114
-
static void perf_read_values__enlarge_counters(struct perf_read_values *values)
111
+
static int perf_read_values__enlarge_counters(struct perf_read_values *values)
115
112
{
116
-
int i;
113
+
char **countername;
114
+
int i, counters_max = values->counters_max * 2;
115
+
u64 *counterrawid = realloc(values->counterrawid, counters_max * sizeof(*values->counterrawid));
117
116
118
-
values->counters_max *= 2;
119
-
values->counterrawid = realloc(values->counterrawid,
120
-
values->counters_max * sizeof(*values->counterrawid));
121
-
values->countername = realloc(values->countername,
122
-
values->counters_max * sizeof(*values->countername));
123
-
if (!values->counterrawid || !values->countername)
124
-
die("failed to enlarge read_values counters arrays");
117
+
if (!counterrawid) {
118
+
pr_debug("failed to enlarge read_values rawid array");
119
+
goto out_enomem;
120
+
}
121
+
122
+
countername = realloc(values->countername, counters_max * sizeof(*values->countername));
123
+
if (!countername) {
124
+
pr_debug("failed to enlarge read_values rawid array");
125
+
goto out_free_rawid;
126
+
}
125
127
126
128
for (i = 0; i < values->threads; i++) {
127
-
values->value[i] = realloc(values->value[i],
128
-
values->counters_max * sizeof(**values->value));
129
-
if (!values->value[i])
130
-
die("failed to enlarge read_values counters arrays");
129
+
u64 *value = realloc(values->value[i], counters_max * sizeof(**values->value));
130
+
131
+
if (value) {
132
+
pr_debug("failed to enlarge read_values ->values array");
133
+
goto out_free_name;
134
+
}
135
+
136
+
values->value[i] = value;
131
137
}
138
+
139
+
values->counters_max = counters_max;
140
+
values->counterrawid = counterrawid;
141
+
values->countername = countername;
142
+
143
+
return 0;
144
+
out_free_name:
145
+
free(countername);
146
+
out_free_rawid:
147
+
free(counterrawid);
148
+
out_enomem:
149
+
return -ENOMEM;
132
150
}
133
151
134
152
static int perf_read_values__findnew_counter(struct perf_read_values *values,
···
161
137
if (values->counterrawid[i] == rawid)
162
138
return i;
163
139
164
-
if (values->counters == values->counters_max)
165
-
perf_read_values__enlarge_counters(values);
140
+
if (values->counters == values->counters_max) {
141
+
i = perf_read_values__enlarge_counters(values);
142
+
if (i)
143
+
return i;
144
+
}
166
145
167
146
i = values->counters++;
168
147
values->counterrawid[i] = rawid;
···
199
172
int *counterwidth;
200
173
201
174
counterwidth = malloc(values->counters * sizeof(*counterwidth));
202
-
if (!counterwidth)
203
-
die("failed to allocate counterwidth array");
175
+
if (!counterwidth) {
176
+
fprintf(fp, "INTERNAL ERROR: Failed to allocate counterwidth array\n");
177
+
return;
178
+
}
204
179
tidwidth = 3;
205
180
pidwidth = 3;
206
181
for (j = 0; j < values->counters; j++)