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linux
staging: rtl8188eu: remove cut_mask field from wl_pwr_cfg
We're no longer matching power transitions and commands against a
power cut version mask.
The cut_mask field from struct wl_pwr_cfg can be removed. It was set to
PWR_CUT_ALL_MSK for all remaining commands.
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Link: https://lore.kernel.org/r/20210718173610.894-10-martin@kaiser.cx
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Martin Kaiser
and committed by
Greg Kroah-Hartman
1126df74
d950b477
+28
-29
+28
-28
drivers/staging/rtl8188eu/include/pwrseq.h
+28
-28
drivers/staging/rtl8188eu/include/pwrseq.h
···
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* },
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* comment here
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*/ \
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-
{0x0006, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
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+
{0x0006, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
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/* wait till 0x04[17] = 1 power ready*/ \
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-
{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \
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+
{0x0002, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \
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/* 0x02[1:0] = 0 reset BB*/ \
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-
{0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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{0x0026, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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/*0x24[23] = 2b'01 schmit trigger */ \
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-
{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \
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{0x0005, PWR_CMD_WRITE, BIT(7), 0}, \
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/* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \
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-
{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \
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+
{0x0005, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \
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/*0x04[12:11] = 2b'00 disable WL suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
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{0x0005, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
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/*0x04[8] = 1 polling until return 0*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(0), 0}, \
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{0x0005, PWR_CMD_POLLING, BIT(0), 0}, \
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/*wait till 0x04[8] = 0*/ \
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{0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
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{0x0023, PWR_CMD_WRITE, BIT(4), 0}, \
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/*LDO normal mode*/
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#define RTL8188E_TRANS_ACT_TO_CARDEMU \
···
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* },
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* comments here
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*/ \
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{0x001F, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \
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{0x001F, PWR_CMD_WRITE, 0xFF, 0}, \
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/*0x1F[7:0] = 0 turn off RF*/ \
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-
{0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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{0x0023, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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/*LDO Sleep mode*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
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{0x0005, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
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/*0x04[9] = 1 turn off MAC by HW state machine*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), 0}, \
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{0x0005, PWR_CMD_POLLING, BIT(1), 0}, \
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/*wait till 0x04[9] = 0 polling until return 0 to disable*/
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#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
···
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* value },
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* comments here
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*/ \
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{0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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{0x0026, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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/*0x24[23] = 2b'01 schmit trigger */ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
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+
{0x0005, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
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/*0x04[12:11] = 2b'01 enable WL suspend*/ \
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{0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \
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+
{0x0007, PWR_CMD_WRITE, 0xFF, 0}, \
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/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
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-
{0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
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{0x0041, PWR_CMD_WRITE, BIT(4), 0}, \
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/*Clear SIC_EN register 0x40[12] = 1'b0 */ \
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{0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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+
{0xfe10, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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/*Set USB suspend enable local register 0xfe10[4]=1 */
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/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
···
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* value },
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* comments here
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*/ \
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-
{0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
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{0x05F8, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
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+
{0x0522, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
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+
{0x05F8, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x05F9, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
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+
{0x05F9, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x05FA, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
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+
{0x05FA, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x05FB, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
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+
{0x05FB, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \
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+
{0x0002, PWR_CMD_WRITE, BIT(0), 0}, \
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/*CCK and OFDM are disabled,and clock are gated*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
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+
{0x0002, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
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/*Delay 1us*/ \
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{0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x3F}, \
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+
{0x0100, PWR_CMD_WRITE, 0xFF, 0x3F}, \
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/*Reset MAC TRX*/ \
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{0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), 0}, \
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+
{0x0101, PWR_CMD_WRITE, BIT(1), 0}, \
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/*check if removed later*/\
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{0x0553, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(5), BIT(5)}, \
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+
{0x0553, PWR_CMD_WRITE, BIT(5), BIT(5)}, \
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/*Respond TxOK to scheduler*/
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#define RTL8188E_TRANS_END \
···
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* value },
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* comments here
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*/ \
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{0xFFFF, PWR_CUT_ALL_MSK, PWR_CMD_END, 0, 0},
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+
{0xFFFF, PWR_CMD_END, 0, 0},
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extern struct wl_pwr_cfg rtl8188E_power_on_flow
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[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];