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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
media: v4l2-mediabus: add support for dual edge sampling
Some devices support sampling of the parallel data at both edges of the
interface pixel clock in order to reduce the pixel clock by two.
Add a mediabus flag that represents this feature.
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
authored by
Michael Riesch
and committed by
Hans Verkuil
10694700
55f6f743
+28
-12
+19
-4
drivers/media/v4l2-core/v4l2-fwnode.c
+19
-4
drivers/media/v4l2-core/v4l2-fwnode.c
···
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if (!fwnode_property_read_u32(fwnode, "pclk-sample", &v)) {
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flags &= ~(V4L2_MBUS_PCLK_SAMPLE_RISING |
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-
V4L2_MBUS_PCLK_SAMPLE_FALLING);
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-
flags |= v ? V4L2_MBUS_PCLK_SAMPLE_RISING :
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-
V4L2_MBUS_PCLK_SAMPLE_FALLING;
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-
pr_debug("pclk-sample %s\n", v ? "high" : "low");
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+
V4L2_MBUS_PCLK_SAMPLE_FALLING |
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+
V4L2_MBUS_PCLK_SAMPLE_DUALEDGE);
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+
switch (v) {
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+
case 0:
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+
flags |= V4L2_MBUS_PCLK_SAMPLE_FALLING;
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+
pr_debug("pclk-sample low\n");
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+
break;
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+
case 1:
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+
flags |= V4L2_MBUS_PCLK_SAMPLE_RISING;
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+
pr_debug("pclk-sample high\n");
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+
break;
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+
case 2:
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+
flags |= V4L2_MBUS_PCLK_SAMPLE_DUALEDGE;
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+
pr_debug("pclk-sample dual edge\n");
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+
break;
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+
default:
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+
pr_warn("invalid argument for pclk-sample");
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+
break;
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+
}
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}
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if (!fwnode_property_read_u32(fwnode, "data-active", &v)) {
+9
-8
include/media/v4l2-mediabus.h
+9
-8
include/media/v4l2-mediabus.h
···
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#define V4L2_MBUS_VSYNC_ACTIVE_LOW BIT(5)
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#define V4L2_MBUS_PCLK_SAMPLE_RISING BIT(6)
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#define V4L2_MBUS_PCLK_SAMPLE_FALLING BIT(7)
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-
#define V4L2_MBUS_DATA_ACTIVE_HIGH BIT(8)
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-
#define V4L2_MBUS_DATA_ACTIVE_LOW BIT(9)
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+
#define V4L2_MBUS_PCLK_SAMPLE_DUALEDGE BIT(8)
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+
#define V4L2_MBUS_DATA_ACTIVE_HIGH BIT(9)
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+
#define V4L2_MBUS_DATA_ACTIVE_LOW BIT(10)
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/* FIELD = 0/1 - Field1 (odd)/Field2 (even) */
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-
#define V4L2_MBUS_FIELD_EVEN_HIGH BIT(10)
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+
#define V4L2_MBUS_FIELD_EVEN_HIGH BIT(11)
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/* FIELD = 1/0 - Field1 (odd)/Field2 (even) */
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-
#define V4L2_MBUS_FIELD_EVEN_LOW BIT(11)
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+
#define V4L2_MBUS_FIELD_EVEN_LOW BIT(12)
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/* Active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively. */
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-
#define V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH BIT(12)
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-
#define V4L2_MBUS_VIDEO_SOG_ACTIVE_LOW BIT(13)
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-
#define V4L2_MBUS_DATA_ENABLE_HIGH BIT(14)
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-
#define V4L2_MBUS_DATA_ENABLE_LOW BIT(15)
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+
#define V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH BIT(13)
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+
#define V4L2_MBUS_VIDEO_SOG_ACTIVE_LOW BIT(14)
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+
#define V4L2_MBUS_DATA_ENABLE_HIGH BIT(15)
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+
#define V4L2_MBUS_DATA_ENABLE_LOW BIT(16)
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/* Serial flags */
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/* Clock non-continuous mode support. */