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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
pinctrl: tegra: Renumber the GG.0 and GG.1 pins
There is no need to define these at a specific offset since they are the
only pins defined for this SoC generation. Begin numbering them at 0.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20200319122737.3063291-9-thierry.reding@gmail.com
Tested-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
authored by
Thierry Reding
and committed by
Linus Walleij
103afc8e
f67499f8
+4
-7
+4
-7
drivers/pinctrl/tegra/pinctrl-tegra194.c
+4
-7
drivers/pinctrl/tegra/pinctrl-tegra194.c
···
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/* Define unique ID for each pins */
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enum pin_id {
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-
TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0 = 256,
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-
TEGRA_PIN_PEX_L5_RST_N_PGG1 = 257,
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-
TEGRA_PIN_NUM_GPIOS = 258,
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+
TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
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+
TEGRA_PIN_PEX_L5_RST_N_PGG1,
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};
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/* Table for pin descriptor */
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static const struct pinctrl_pin_desc tegra194_pins[] = {
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PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
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"TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0"),
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PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1,
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-
"TEGRA_PIN_PEX_L5_RST_N_PGG1"),
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+
PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
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+
PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
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};
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static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {