Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amdgpu: support rom clockgating related function for NV family

Add functions to support enable/disable rom clock gating and get rom
clock gating status.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Likun Gao and committed by
Alex Deucher
1001f2a1 0bf7f2dc

+40
+4
drivers/gpu/drm/amd/amdgpu/nv.c
··· 1144 1144 state == AMD_CG_STATE_GATE); 1145 1145 adev->hdp.funcs->update_clock_gating(adev, 1146 1146 state == AMD_CG_STATE_GATE); 1147 + adev->smuio.funcs->update_rom_clock_gating(adev, 1148 + state == AMD_CG_STATE_GATE); 1147 1149 break; 1148 1150 default: 1149 1151 break; ··· 1170 1168 adev->nbio.funcs->get_clockgating_state(adev, flags); 1171 1169 1172 1170 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1171 + 1172 + adev->smuio.funcs->get_clock_gating_state(adev, flags); 1173 1173 1174 1174 return; 1175 1175 }
+36
drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.c
··· 35 35 return SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA); 36 36 } 37 37 38 + static void smuio_v11_0_6_update_rom_clock_gating(struct amdgpu_device *adev, bool enable) 39 + { 40 + u32 def, data; 41 + 42 + /* enable/disable ROM CG is not supported on APU */ 43 + if (adev->flags & AMD_IS_APU) 44 + return; 45 + 46 + def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0); 47 + 48 + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 49 + data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 50 + CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 51 + else 52 + data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 53 + CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 54 + 55 + if (def != data) 56 + WREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0, data); 57 + } 58 + 59 + static void smuio_v11_0_6_get_clock_gating_state(struct amdgpu_device *adev, u32 *flags) 60 + { 61 + u32 data; 62 + 63 + /* CGTT_ROM_CLK_CTRL0 is not available for APU */ 64 + if (adev->flags & AMD_IS_APU) 65 + return; 66 + 67 + data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0); 68 + if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 69 + *flags |= AMD_CG_SUPPORT_ROM_MGCG; 70 + } 71 + 38 72 const struct amdgpu_smuio_funcs smuio_v11_0_6_funcs = { 39 73 .get_rom_index_offset = smuio_v11_0_6_get_rom_index_offset, 40 74 .get_rom_data_offset = smuio_v11_0_6_get_rom_data_offset, 75 + .update_rom_clock_gating = smuio_v11_0_6_update_rom_clock_gating, 76 + .get_clock_gating_state = smuio_v11_0_6_get_clock_gating_state, 41 77 };