tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
mfd: sec-irq: Convert to using REGMAP_IRQ_REG() macros
Use REGMAP_IRQ_REG macro helpers instead of open coding. This makes the
code a bit shorter and more obvious.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250409-s2mpg10-v4-22-d66d5f39b6bf@linaro.org
Signed-off-by: Lee Jones <lee@kernel.org>
authored by
André Draszik
and committed by
Lee Jones
10008dcc
55684cbb
+75
-268
+75
-268
drivers/mfd/sec-irq.c
+75
-268
drivers/mfd/sec-irq.c
···
74
74
};
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static const struct regmap_irq s2mps11_irqs[] = {
77
-
[S2MPS11_IRQ_PWRONF] = {
78
-
.reg_offset = 0,
79
-
.mask = S2MPS11_IRQ_PWRONF_MASK,
80
-
},
81
-
[S2MPS11_IRQ_PWRONR] = {
82
-
.reg_offset = 0,
83
-
.mask = S2MPS11_IRQ_PWRONR_MASK,
84
-
},
85
-
[S2MPS11_IRQ_JIGONBF] = {
86
-
.reg_offset = 0,
87
-
.mask = S2MPS11_IRQ_JIGONBF_MASK,
88
-
},
89
-
[S2MPS11_IRQ_JIGONBR] = {
90
-
.reg_offset = 0,
91
-
.mask = S2MPS11_IRQ_JIGONBR_MASK,
92
-
},
93
-
[S2MPS11_IRQ_ACOKBF] = {
94
-
.reg_offset = 0,
95
-
.mask = S2MPS11_IRQ_ACOKBF_MASK,
96
-
},
97
-
[S2MPS11_IRQ_ACOKBR] = {
98
-
.reg_offset = 0,
99
-
.mask = S2MPS11_IRQ_ACOKBR_MASK,
100
-
},
101
-
[S2MPS11_IRQ_PWRON1S] = {
102
-
.reg_offset = 0,
103
-
.mask = S2MPS11_IRQ_PWRON1S_MASK,
104
-
},
105
-
[S2MPS11_IRQ_MRB] = {
106
-
.reg_offset = 0,
107
-
.mask = S2MPS11_IRQ_MRB_MASK,
108
-
},
109
-
[S2MPS11_IRQ_RTC60S] = {
110
-
.reg_offset = 1,
111
-
.mask = S2MPS11_IRQ_RTC60S_MASK,
112
-
},
113
-
[S2MPS11_IRQ_RTCA1] = {
114
-
.reg_offset = 1,
115
-
.mask = S2MPS11_IRQ_RTCA1_MASK,
116
-
},
117
-
[S2MPS11_IRQ_RTCA0] = {
118
-
.reg_offset = 1,
119
-
.mask = S2MPS11_IRQ_RTCA0_MASK,
120
-
},
121
-
[S2MPS11_IRQ_SMPL] = {
122
-
.reg_offset = 1,
123
-
.mask = S2MPS11_IRQ_SMPL_MASK,
124
-
},
125
-
[S2MPS11_IRQ_RTC1S] = {
126
-
.reg_offset = 1,
127
-
.mask = S2MPS11_IRQ_RTC1S_MASK,
128
-
},
129
-
[S2MPS11_IRQ_WTSR] = {
130
-
.reg_offset = 1,
131
-
.mask = S2MPS11_IRQ_WTSR_MASK,
132
-
},
133
-
[S2MPS11_IRQ_INT120C] = {
134
-
.reg_offset = 2,
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-
.mask = S2MPS11_IRQ_INT120C_MASK,
136
-
},
137
-
[S2MPS11_IRQ_INT140C] = {
138
-
.reg_offset = 2,
139
-
.mask = S2MPS11_IRQ_INT140C_MASK,
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-
},
77
+
REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
78
+
REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
79
+
REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
80
+
REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
81
+
REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
82
+
REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
83
+
REGMAP_IRQ_REG(S2MPS11_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
84
+
REGMAP_IRQ_REG(S2MPS11_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
85
+
86
+
REGMAP_IRQ_REG(S2MPS11_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
87
+
REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
88
+
REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
89
+
REGMAP_IRQ_REG(S2MPS11_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
90
+
REGMAP_IRQ_REG(S2MPS11_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
91
+
REGMAP_IRQ_REG(S2MPS11_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
92
+
93
+
REGMAP_IRQ_REG(S2MPS11_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
94
+
REGMAP_IRQ_REG(S2MPS11_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
141
95
};
142
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static const struct regmap_irq s2mps14_irqs[] = {
144
-
[S2MPS14_IRQ_PWRONF] = {
145
-
.reg_offset = 0,
146
-
.mask = S2MPS11_IRQ_PWRONF_MASK,
147
-
},
148
-
[S2MPS14_IRQ_PWRONR] = {
149
-
.reg_offset = 0,
150
-
.mask = S2MPS11_IRQ_PWRONR_MASK,
151
-
},
152
-
[S2MPS14_IRQ_JIGONBF] = {
153
-
.reg_offset = 0,
154
-
.mask = S2MPS11_IRQ_JIGONBF_MASK,
155
-
},
156
-
[S2MPS14_IRQ_JIGONBR] = {
157
-
.reg_offset = 0,
158
-
.mask = S2MPS11_IRQ_JIGONBR_MASK,
159
-
},
160
-
[S2MPS14_IRQ_ACOKBF] = {
161
-
.reg_offset = 0,
162
-
.mask = S2MPS11_IRQ_ACOKBF_MASK,
163
-
},
164
-
[S2MPS14_IRQ_ACOKBR] = {
165
-
.reg_offset = 0,
166
-
.mask = S2MPS11_IRQ_ACOKBR_MASK,
167
-
},
168
-
[S2MPS14_IRQ_PWRON1S] = {
169
-
.reg_offset = 0,
170
-
.mask = S2MPS11_IRQ_PWRON1S_MASK,
171
-
},
172
-
[S2MPS14_IRQ_MRB] = {
173
-
.reg_offset = 0,
174
-
.mask = S2MPS11_IRQ_MRB_MASK,
175
-
},
176
-
[S2MPS14_IRQ_RTC60S] = {
177
-
.reg_offset = 1,
178
-
.mask = S2MPS11_IRQ_RTC60S_MASK,
179
-
},
180
-
[S2MPS14_IRQ_RTCA1] = {
181
-
.reg_offset = 1,
182
-
.mask = S2MPS11_IRQ_RTCA1_MASK,
183
-
},
184
-
[S2MPS14_IRQ_RTCA0] = {
185
-
.reg_offset = 1,
186
-
.mask = S2MPS11_IRQ_RTCA0_MASK,
187
-
},
188
-
[S2MPS14_IRQ_SMPL] = {
189
-
.reg_offset = 1,
190
-
.mask = S2MPS11_IRQ_SMPL_MASK,
191
-
},
192
-
[S2MPS14_IRQ_RTC1S] = {
193
-
.reg_offset = 1,
194
-
.mask = S2MPS11_IRQ_RTC1S_MASK,
195
-
},
196
-
[S2MPS14_IRQ_WTSR] = {
197
-
.reg_offset = 1,
198
-
.mask = S2MPS11_IRQ_WTSR_MASK,
199
-
},
200
-
[S2MPS14_IRQ_INT120C] = {
201
-
.reg_offset = 2,
202
-
.mask = S2MPS11_IRQ_INT120C_MASK,
203
-
},
204
-
[S2MPS14_IRQ_INT140C] = {
205
-
.reg_offset = 2,
206
-
.mask = S2MPS11_IRQ_INT140C_MASK,
207
-
},
208
-
[S2MPS14_IRQ_TSD] = {
209
-
.reg_offset = 2,
210
-
.mask = S2MPS14_IRQ_TSD_MASK,
211
-
},
98
+
REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
99
+
REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
100
+
REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
101
+
REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
102
+
REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
103
+
REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
104
+
REGMAP_IRQ_REG(S2MPS14_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
105
+
REGMAP_IRQ_REG(S2MPS14_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
106
+
107
+
REGMAP_IRQ_REG(S2MPS14_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
108
+
REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
109
+
REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
110
+
REGMAP_IRQ_REG(S2MPS14_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
111
+
REGMAP_IRQ_REG(S2MPS14_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
112
+
REGMAP_IRQ_REG(S2MPS14_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
113
+
114
+
REGMAP_IRQ_REG(S2MPS14_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
115
+
REGMAP_IRQ_REG(S2MPS14_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
116
+
REGMAP_IRQ_REG(S2MPS14_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK),
212
117
};
213
118
214
119
static const struct regmap_irq s2mpu02_irqs[] = {
215
-
[S2MPU02_IRQ_PWRONF] = {
216
-
.reg_offset = 0,
217
-
.mask = S2MPS11_IRQ_PWRONF_MASK,
218
-
},
219
-
[S2MPU02_IRQ_PWRONR] = {
220
-
.reg_offset = 0,
221
-
.mask = S2MPS11_IRQ_PWRONR_MASK,
222
-
},
223
-
[S2MPU02_IRQ_JIGONBF] = {
224
-
.reg_offset = 0,
225
-
.mask = S2MPS11_IRQ_JIGONBF_MASK,
226
-
},
227
-
[S2MPU02_IRQ_JIGONBR] = {
228
-
.reg_offset = 0,
229
-
.mask = S2MPS11_IRQ_JIGONBR_MASK,
230
-
},
231
-
[S2MPU02_IRQ_ACOKBF] = {
232
-
.reg_offset = 0,
233
-
.mask = S2MPS11_IRQ_ACOKBF_MASK,
234
-
},
235
-
[S2MPU02_IRQ_ACOKBR] = {
236
-
.reg_offset = 0,
237
-
.mask = S2MPS11_IRQ_ACOKBR_MASK,
238
-
},
239
-
[S2MPU02_IRQ_PWRON1S] = {
240
-
.reg_offset = 0,
241
-
.mask = S2MPS11_IRQ_PWRON1S_MASK,
242
-
},
243
-
[S2MPU02_IRQ_MRB] = {
244
-
.reg_offset = 0,
245
-
.mask = S2MPS11_IRQ_MRB_MASK,
246
-
},
247
-
[S2MPU02_IRQ_RTC60S] = {
248
-
.reg_offset = 1,
249
-
.mask = S2MPS11_IRQ_RTC60S_MASK,
250
-
},
251
-
[S2MPU02_IRQ_RTCA1] = {
252
-
.reg_offset = 1,
253
-
.mask = S2MPS11_IRQ_RTCA1_MASK,
254
-
},
255
-
[S2MPU02_IRQ_RTCA0] = {
256
-
.reg_offset = 1,
257
-
.mask = S2MPS11_IRQ_RTCA0_MASK,
258
-
},
259
-
[S2MPU02_IRQ_SMPL] = {
260
-
.reg_offset = 1,
261
-
.mask = S2MPS11_IRQ_SMPL_MASK,
262
-
},
263
-
[S2MPU02_IRQ_RTC1S] = {
264
-
.reg_offset = 1,
265
-
.mask = S2MPS11_IRQ_RTC1S_MASK,
266
-
},
267
-
[S2MPU02_IRQ_WTSR] = {
268
-
.reg_offset = 1,
269
-
.mask = S2MPS11_IRQ_WTSR_MASK,
270
-
},
271
-
[S2MPU02_IRQ_INT120C] = {
272
-
.reg_offset = 2,
273
-
.mask = S2MPS11_IRQ_INT120C_MASK,
274
-
},
275
-
[S2MPU02_IRQ_INT140C] = {
276
-
.reg_offset = 2,
277
-
.mask = S2MPS11_IRQ_INT140C_MASK,
278
-
},
279
-
[S2MPU02_IRQ_TSD] = {
280
-
.reg_offset = 2,
281
-
.mask = S2MPS14_IRQ_TSD_MASK,
282
-
},
120
+
REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
121
+
REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
122
+
REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
123
+
REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
124
+
REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
125
+
REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
126
+
REGMAP_IRQ_REG(S2MPU02_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
127
+
REGMAP_IRQ_REG(S2MPU02_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
128
+
129
+
REGMAP_IRQ_REG(S2MPU02_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
130
+
REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
131
+
REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
132
+
REGMAP_IRQ_REG(S2MPU02_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
133
+
REGMAP_IRQ_REG(S2MPU02_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
134
+
REGMAP_IRQ_REG(S2MPU02_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
135
+
136
+
REGMAP_IRQ_REG(S2MPU02_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
137
+
REGMAP_IRQ_REG(S2MPU02_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
138
+
REGMAP_IRQ_REG(S2MPU02_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK),
283
139
};
284
140
285
141
static const struct regmap_irq s2mpu05_irqs[] = {
···
159
303
};
160
304
161
305
static const struct regmap_irq s5m8767_irqs[] = {
162
-
[S5M8767_IRQ_PWRR] = {
163
-
.reg_offset = 0,
164
-
.mask = S5M8767_IRQ_PWRR_MASK,
165
-
},
166
-
[S5M8767_IRQ_PWRF] = {
167
-
.reg_offset = 0,
168
-
.mask = S5M8767_IRQ_PWRF_MASK,
169
-
},
170
-
[S5M8767_IRQ_PWR1S] = {
171
-
.reg_offset = 0,
172
-
.mask = S5M8767_IRQ_PWR1S_MASK,
173
-
},
174
-
[S5M8767_IRQ_JIGR] = {
175
-
.reg_offset = 0,
176
-
.mask = S5M8767_IRQ_JIGR_MASK,
177
-
},
178
-
[S5M8767_IRQ_JIGF] = {
179
-
.reg_offset = 0,
180
-
.mask = S5M8767_IRQ_JIGF_MASK,
181
-
},
182
-
[S5M8767_IRQ_LOWBAT2] = {
183
-
.reg_offset = 0,
184
-
.mask = S5M8767_IRQ_LOWBAT2_MASK,
185
-
},
186
-
[S5M8767_IRQ_LOWBAT1] = {
187
-
.reg_offset = 0,
188
-
.mask = S5M8767_IRQ_LOWBAT1_MASK,
189
-
},
190
-
[S5M8767_IRQ_MRB] = {
191
-
.reg_offset = 1,
192
-
.mask = S5M8767_IRQ_MRB_MASK,
193
-
},
194
-
[S5M8767_IRQ_DVSOK2] = {
195
-
.reg_offset = 1,
196
-
.mask = S5M8767_IRQ_DVSOK2_MASK,
197
-
},
198
-
[S5M8767_IRQ_DVSOK3] = {
199
-
.reg_offset = 1,
200
-
.mask = S5M8767_IRQ_DVSOK3_MASK,
201
-
},
202
-
[S5M8767_IRQ_DVSOK4] = {
203
-
.reg_offset = 1,
204
-
.mask = S5M8767_IRQ_DVSOK4_MASK,
205
-
},
206
-
[S5M8767_IRQ_RTC60S] = {
207
-
.reg_offset = 2,
208
-
.mask = S5M8767_IRQ_RTC60S_MASK,
209
-
},
210
-
[S5M8767_IRQ_RTCA1] = {
211
-
.reg_offset = 2,
212
-
.mask = S5M8767_IRQ_RTCA1_MASK,
213
-
},
214
-
[S5M8767_IRQ_RTCA2] = {
215
-
.reg_offset = 2,
216
-
.mask = S5M8767_IRQ_RTCA2_MASK,
217
-
},
218
-
[S5M8767_IRQ_SMPL] = {
219
-
.reg_offset = 2,
220
-
.mask = S5M8767_IRQ_SMPL_MASK,
221
-
},
222
-
[S5M8767_IRQ_RTC1S] = {
223
-
.reg_offset = 2,
224
-
.mask = S5M8767_IRQ_RTC1S_MASK,
225
-
},
226
-
[S5M8767_IRQ_WTSR] = {
227
-
.reg_offset = 2,
228
-
.mask = S5M8767_IRQ_WTSR_MASK,
229
-
},
306
+
REGMAP_IRQ_REG(S5M8767_IRQ_PWRR, 0, S5M8767_IRQ_PWRR_MASK),
307
+
REGMAP_IRQ_REG(S5M8767_IRQ_PWRF, 0, S5M8767_IRQ_PWRF_MASK),
308
+
REGMAP_IRQ_REG(S5M8767_IRQ_PWR1S, 0, S5M8767_IRQ_PWR1S_MASK),
309
+
REGMAP_IRQ_REG(S5M8767_IRQ_JIGR, 0, S5M8767_IRQ_JIGR_MASK),
310
+
REGMAP_IRQ_REG(S5M8767_IRQ_JIGF, 0, S5M8767_IRQ_JIGF_MASK),
311
+
REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT2, 0, S5M8767_IRQ_LOWBAT2_MASK),
312
+
REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT1, 0, S5M8767_IRQ_LOWBAT1_MASK),
313
+
314
+
REGMAP_IRQ_REG(S5M8767_IRQ_MRB, 1, S5M8767_IRQ_MRB_MASK),
315
+
REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK2, 1, S5M8767_IRQ_DVSOK2_MASK),
316
+
REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK3, 1, S5M8767_IRQ_DVSOK3_MASK),
317
+
REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK4, 1, S5M8767_IRQ_DVSOK4_MASK),
318
+
319
+
REGMAP_IRQ_REG(S5M8767_IRQ_RTC60S, 2, S5M8767_IRQ_RTC60S_MASK),
320
+
REGMAP_IRQ_REG(S5M8767_IRQ_RTCA1, 2, S5M8767_IRQ_RTCA1_MASK),
321
+
REGMAP_IRQ_REG(S5M8767_IRQ_RTCA2, 2, S5M8767_IRQ_RTCA2_MASK),
322
+
REGMAP_IRQ_REG(S5M8767_IRQ_SMPL, 2, S5M8767_IRQ_SMPL_MASK),
323
+
REGMAP_IRQ_REG(S5M8767_IRQ_RTC1S, 2, S5M8767_IRQ_RTC1S_MASK),
324
+
REGMAP_IRQ_REG(S5M8767_IRQ_WTSR, 2, S5M8767_IRQ_WTSR_MASK),
230
325
};
231
326
232
327
/* All S2MPG10 interrupt sources are read-only and don't require clearing */