KVM: arm64: nv: Add handling of NXS-flavoured TLBI operations

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Latest kid on the block: NXS (Non-eXtra-Slow) TLBI operations.

Let's add those in bulk (NSH, ISH, OSH, both normal and range)
as they directly map to their XS (the standard ones) counterparts.

Not a lot to say about them, they are basically useless.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240614144552.2773592-17-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

authored by

Marc Zyngier and committed by

Oliver Upton 2 years ago 0feec776 5d476ca5

+119

2 changed files

expand all

arch

arm64

kvm

hyp

vhe

tlb.c

sys_regs.c

+46

arch/arm64/kvm/hyp/vhe/tlb.c

··· 227 227 * - a TLBI targeting EL2 S1 is remapped to EL1 S1 228 228 * - a non-shareable TLBI is upgraded to being inner-shareable 229 229 * - an outer-shareable TLBI is also mapped to inner-shareable 230 + * - an nXS TLBI is upgraded to XS 230 231 */ 231 232 int __kvm_tlbi_s1e2(struct kvm_s2_mmu *mmu, u64 va, u64 sys_encoding) 232 233 { ··· 251 250 case OP_TLBI_VMALLE1: 252 251 case OP_TLBI_VMALLE1IS: 253 252 case OP_TLBI_VMALLE1OS: 253 + case OP_TLBI_ALLE2NXS: 254 + case OP_TLBI_ALLE2ISNXS: 255 + case OP_TLBI_ALLE2OSNXS: 256 + case OP_TLBI_VMALLE1NXS: 257 + case OP_TLBI_VMALLE1ISNXS: 258 + case OP_TLBI_VMALLE1OSNXS: 254 259 __tlbi(vmalle1is); 255 260 break; 256 261 case OP_TLBI_VAE2: ··· 265 258 case OP_TLBI_VAE1: 266 259 case OP_TLBI_VAE1IS: 267 260 case OP_TLBI_VAE1OS: 261 + case OP_TLBI_VAE2NXS: 262 + case OP_TLBI_VAE2ISNXS: 263 + case OP_TLBI_VAE2OSNXS: 264 + case OP_TLBI_VAE1NXS: 265 + case OP_TLBI_VAE1ISNXS: 266 + case OP_TLBI_VAE1OSNXS: 268 267 __tlbi(vae1is, va); 269 268 break; 270 269 case OP_TLBI_VALE2: ··· 279 266 case OP_TLBI_VALE1: 280 267 case OP_TLBI_VALE1IS: 281 268 case OP_TLBI_VALE1OS: 269 + case OP_TLBI_VALE2NXS: 270 + case OP_TLBI_VALE2ISNXS: 271 + case OP_TLBI_VALE2OSNXS: 272 + case OP_TLBI_VALE1NXS: 273 + case OP_TLBI_VALE1ISNXS: 274 + case OP_TLBI_VALE1OSNXS: 282 275 __tlbi(vale1is, va); 283 276 break; 284 277 case OP_TLBI_ASIDE1: 285 278 case OP_TLBI_ASIDE1IS: 286 279 case OP_TLBI_ASIDE1OS: 280 + case OP_TLBI_ASIDE1NXS: 281 + case OP_TLBI_ASIDE1ISNXS: 282 + case OP_TLBI_ASIDE1OSNXS: 287 283 __tlbi(aside1is, va); 288 284 break; 289 285 case OP_TLBI_VAAE1: 290 286 case OP_TLBI_VAAE1IS: 291 287 case OP_TLBI_VAAE1OS: 288 + case OP_TLBI_VAAE1NXS: 289 + case OP_TLBI_VAAE1ISNXS: 290 + case OP_TLBI_VAAE1OSNXS: 292 291 __tlbi(vaae1is, va); 293 292 break; 294 293 case OP_TLBI_VAALE1: 295 294 case OP_TLBI_VAALE1IS: 296 295 case OP_TLBI_VAALE1OS: 296 + case OP_TLBI_VAALE1NXS: 297 + case OP_TLBI_VAALE1ISNXS: 298 + case OP_TLBI_VAALE1OSNXS: 297 299 __tlbi(vaale1is, va); 298 300 break; 299 301 case OP_TLBI_RVAE2: ··· 317 289 case OP_TLBI_RVAE1: 318 290 case OP_TLBI_RVAE1IS: 319 291 case OP_TLBI_RVAE1OS: 292 + case OP_TLBI_RVAE2NXS: 293 + case OP_TLBI_RVAE2ISNXS: 294 + case OP_TLBI_RVAE2OSNXS: 295 + case OP_TLBI_RVAE1NXS: 296 + case OP_TLBI_RVAE1ISNXS: 297 + case OP_TLBI_RVAE1OSNXS: 320 298 __tlbi(rvae1is, va); 321 299 break; 322 300 case OP_TLBI_RVALE2: ··· 331 297 case OP_TLBI_RVALE1: 332 298 case OP_TLBI_RVALE1IS: 333 299 case OP_TLBI_RVALE1OS: 300 + case OP_TLBI_RVALE2NXS: 301 + case OP_TLBI_RVALE2ISNXS: 302 + case OP_TLBI_RVALE2OSNXS: 303 + case OP_TLBI_RVALE1NXS: 304 + case OP_TLBI_RVALE1ISNXS: 305 + case OP_TLBI_RVALE1OSNXS: 334 306 __tlbi(rvale1is, va); 335 307 break; 336 308 case OP_TLBI_RVAAE1: 337 309 case OP_TLBI_RVAAE1IS: 338 310 case OP_TLBI_RVAAE1OS: 311 + case OP_TLBI_RVAAE1NXS: 312 + case OP_TLBI_RVAAE1ISNXS: 313 + case OP_TLBI_RVAAE1OSNXS: 339 314 __tlbi(rvaae1is, va); 340 315 break; 341 316 case OP_TLBI_RVAALE1: 342 317 case OP_TLBI_RVAALE1IS: 343 318 case OP_TLBI_RVAALE1OS: 319 + case OP_TLBI_RVAALE1NXS: 320 + case OP_TLBI_RVAALE1ISNXS: 321 + case OP_TLBI_RVAALE1OSNXS: 344 322 __tlbi(rvaale1is, va); 345 323 break; 346 324 default:

+73

arch/arm64/kvm/sys_regs.c

··· 3046 3046 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 3047 3047 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 3048 3048 3049 + SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 3050 + SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 3051 + SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 3052 + SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 3053 + SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 3054 + SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 3055 + 3056 + SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 3057 + SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 3058 + SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 3059 + SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 3060 + 3061 + SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 3062 + SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 3063 + SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 3064 + SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 3065 + SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 3066 + SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 3067 + 3068 + SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 3069 + SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 3070 + SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 3071 + SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 3072 + 3073 + SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 3074 + SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 3075 + SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 3076 + SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 3077 + 3078 + SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 3079 + SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 3080 + SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 3081 + SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 3082 + SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 3083 + SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 3084 + 3049 3085 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 3050 3086 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 3051 3087 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), ··· 3112 3076 SYS_INSN(TLBI_RVALE2, trap_undef), 3113 3077 SYS_INSN(TLBI_ALLE1, handle_alle1is), 3114 3078 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 3079 + 3080 + SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 3081 + SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 3082 + SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 3083 + SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 3084 + 3085 + SYS_INSN(TLBI_ALLE2OSNXS, trap_undef), 3086 + SYS_INSN(TLBI_VAE2OSNXS, trap_undef), 3087 + SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 3088 + SYS_INSN(TLBI_VALE2OSNXS, trap_undef), 3089 + SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 3090 + 3091 + SYS_INSN(TLBI_RVAE2ISNXS, trap_undef), 3092 + SYS_INSN(TLBI_RVALE2ISNXS, trap_undef), 3093 + SYS_INSN(TLBI_ALLE2ISNXS, trap_undef), 3094 + SYS_INSN(TLBI_VAE2ISNXS, trap_undef), 3095 + 3096 + SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 3097 + SYS_INSN(TLBI_VALE2ISNXS, trap_undef), 3098 + SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 3099 + SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 3100 + SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 3101 + SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 3102 + SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 3103 + SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 3104 + SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 3105 + SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 3106 + SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 3107 + SYS_INSN(TLBI_RVAE2OSNXS, trap_undef), 3108 + SYS_INSN(TLBI_RVALE2OSNXS, trap_undef), 3109 + SYS_INSN(TLBI_RVAE2NXS, trap_undef), 3110 + SYS_INSN(TLBI_RVALE2NXS, trap_undef), 3111 + SYS_INSN(TLBI_ALLE2NXS, trap_undef), 3112 + SYS_INSN(TLBI_VAE2NXS, trap_undef), 3113 + SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 3114 + SYS_INSN(TLBI_VALE2NXS, trap_undef), 3115 + SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 3115 3116 }; 3116 3117 3117 3118 static const struct sys_reg_desc *first_idreg;