tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu/gfx11: switch to amdgpu_gfx_rlc_init_microcode

switch to common helper to initialize rlc firmware
for gfx11

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by Hawking Zhang and committed by Alex Deucher 0fd85e89 04fa38cc

options
unified split
Changed files
+4 -152
drivers
gpu
drm
amd
amdgpu
gfx_v11_0.c
+4 -152
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 474 474 kfree(adev->gfx.rlc.register_list_format); 475 475 } 476 476 477 - static void gfx_v11_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 478 - { 479 - const struct rlc_firmware_header_v2_1 *rlc_hdr; 480 - 481 - rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 482 - adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 483 - adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 484 - adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 485 - adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 486 - adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 487 - adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 488 - adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 489 - adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 490 - adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 491 - adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 492 - adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 493 - adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 494 - adev->gfx.rlc.reg_list_format_direct_reg_list_length = 495 - le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 496 - } 497 - 498 - static void gfx_v11_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 499 - { 500 - const struct rlc_firmware_header_v2_2 *rlc_hdr; 501 - 502 - rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 503 - adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 504 - adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 505 - adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 506 - adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 507 - } 508 - 509 - static void gfx_v11_0_init_rlcp_rlcv_microcode(struct amdgpu_device *adev) 510 - { 511 - const struct rlc_firmware_header_v2_3 *rlc_hdr; 512 - 513 - rlc_hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 514 - adev->gfx.rlcp_ucode_version = le32_to_cpu(rlc_hdr->rlcp_ucode_version); 515 - adev->gfx.rlcp_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcp_ucode_feature_version); 516 - adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes); 517 - adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes); 518 - 519 - adev->gfx.rlcv_ucode_version = le32_to_cpu(rlc_hdr->rlcv_ucode_version); 520 - adev->gfx.rlcv_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcv_ucode_feature_version); 521 - adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes); 522 - adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes); 523 - } 524 - 525 477 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 526 478 { 527 479 char fw_name[40]; ··· 484 532 const struct gfx_firmware_header_v1_0 *cp_hdr; 485 533 const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0; 486 534 const struct rlc_firmware_header_v2_0 *rlc_hdr; 487 - unsigned int *tmp = NULL; 488 - unsigned int i = 0; 489 535 uint16_t version_major; 490 536 uint16_t version_minor; 491 537 ··· 538 588 if (err) 539 589 goto out; 540 590 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 591 + if (err) 592 + goto out; 541 593 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 542 594 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 543 595 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 544 - 545 - adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 546 - adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 547 - adev->gfx.rlc.save_and_restore_offset = 548 - le32_to_cpu(rlc_hdr->save_and_restore_offset); 549 - adev->gfx.rlc.clear_state_descriptor_offset = 550 - le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 551 - adev->gfx.rlc.avail_scratch_ram_locations = 552 - le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 553 - adev->gfx.rlc.reg_restore_list_size = 554 - le32_to_cpu(rlc_hdr->reg_restore_list_size); 555 - adev->gfx.rlc.reg_list_format_start = 556 - le32_to_cpu(rlc_hdr->reg_list_format_start); 557 - adev->gfx.rlc.reg_list_format_separate_start = 558 - le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 559 - adev->gfx.rlc.starting_offsets_start = 560 - le32_to_cpu(rlc_hdr->starting_offsets_start); 561 - adev->gfx.rlc.reg_list_format_size_bytes = 562 - le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 563 - adev->gfx.rlc.reg_list_size_bytes = 564 - le32_to_cpu(rlc_hdr->reg_list_size_bytes); 565 - adev->gfx.rlc.register_list_format = 566 - kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 567 - adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 568 - if (!adev->gfx.rlc.register_list_format) { 569 - err = -ENOMEM; 596 + err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 597 + if (err) 570 598 goto out; 571 - } 572 - 573 - tmp = (unsigned int *)((uintptr_t)rlc_hdr + 574 - le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 575 - for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 576 - adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 577 - 578 - adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 579 - 580 - tmp = (unsigned int *)((uintptr_t)rlc_hdr + 581 - le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 582 - for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 583 - adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 584 - 585 - if (version_major == 2) { 586 - if (version_minor >= 1) 587 - gfx_v11_0_init_rlc_ext_microcode(adev); 588 - if (version_minor >= 2) 589 - gfx_v11_0_init_rlc_iram_dram_microcode(adev); 590 - if (version_minor == 3) 591 - gfx_v11_0_init_rlcp_rlcv_microcode(adev); 592 - } 593 599 } 594 600 595 601 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); ··· 679 773 info->fw = adev->gfx.mec_fw; 680 774 adev->firmware.fw_size += 681 775 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 682 - } 683 - 684 - info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 685 - info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 686 - info->fw = adev->gfx.rlc_fw; 687 - if (info->fw) { 688 - header = (const struct common_firmware_header *)info->fw->data; 689 - adev->firmware.fw_size += 690 - ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 691 - } 692 - if (adev->gfx.rlc.save_restore_list_gpm_size_bytes && 693 - adev->gfx.rlc.save_restore_list_srm_size_bytes) { 694 - info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 695 - info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 696 - info->fw = adev->gfx.rlc_fw; 697 - adev->firmware.fw_size += 698 - ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 699 - 700 - info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 701 - info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 702 - info->fw = adev->gfx.rlc_fw; 703 - adev->firmware.fw_size += 704 - ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 705 - } 706 - 707 - if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 708 - adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 709 - info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 710 - info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 711 - info->fw = adev->gfx.rlc_fw; 712 - adev->firmware.fw_size += 713 - ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 714 - 715 - info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 716 - info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 717 - info->fw = adev->gfx.rlc_fw; 718 - adev->firmware.fw_size += 719 - ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 720 - } 721 - 722 - if (adev->gfx.rlc.rlcp_ucode_size_bytes) { 723 - info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P]; 724 - info->ucode_id = AMDGPU_UCODE_ID_RLC_P; 725 - info->fw = adev->gfx.rlc_fw; 726 - adev->firmware.fw_size += 727 - ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE); 728 - } 729 - 730 - if (adev->gfx.rlc.rlcv_ucode_size_bytes) { 731 - info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V]; 732 - info->ucode_id = AMDGPU_UCODE_ID_RLC_V; 733 - info->fw = adev->gfx.rlc_fw; 734 - adev->firmware.fw_size += 735 - ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE); 736 776 } 737 777 } 738 778