tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/mediatek: add hdmi driver for MT2701 and MT7623
This patch adds hdmi dirver suppot for both MT2701 and MT7623.
And also support other (existing or future) chips that use
the same binding and driver.
Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
authored by
chunhui dai
and committed by
CK Hu
0fc721b2
d1ef028d
+225
-2
+1
drivers/gpu/drm/mediatek/Makefile
+1
drivers/gpu/drm/mediatek/Makefile
+7
-2
drivers/gpu/drm/mediatek/mtk_hdmi.c
+7
-2
drivers/gpu/drm/mediatek/mtk_hdmi.c
···
241
241
* The ARM trusted firmware provides an API for the HDMI driver to set
242
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* this control bit to enable HDMI output in supervisor mode.
243
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*/
244
-
arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
245
-
0, 0, 0, 0, 0, &res);
244
+
if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled)
245
+
regmap_update_bits(hdmi->sys_regmap,
246
+
hdmi->sys_offset + HDMI_SYS_CFG20,
247
+
0x80008005, enable ? 0x80000005 : 0x8000);
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+
else
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arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
250
+
0x80000000, 0, 0, 0, 0, 0, &res);
246
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247
252
regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
248
253
HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
+3
drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
+3
drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
+2
drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
+2
drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
···
20
20
struct mtk_hdmi_phy;
21
21
22
22
struct mtk_hdmi_phy_conf {
23
+
bool tz_disabled;
23
24
const struct clk_ops *hdmi_phy_clk_ops;
24
25
void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
25
26
void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
···
55
54
56
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extern struct platform_driver mtk_hdmi_phy_driver;
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extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
57
+
extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
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58
59
59
#endif /* _MTK_HDMI_PHY_H */
+212
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
+212
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2018 MediaTek Inc.
4
+
* Author: Chunhui Dai <chunhui.dai@mediatek.com>
5
+
*/
6
+
7
+
#include "mtk_hdmi_phy.h"
8
+
9
+
#define HDMI_CON0 0x00
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+
#define RG_HDMITX_DRV_IBIAS 0
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+
#define RG_HDMITX_DRV_IBIAS_MASK (0x3f << 0)
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+
#define RG_HDMITX_EN_SER 12
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+
#define RG_HDMITX_EN_SER_MASK (0x0f << 12)
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+
#define RG_HDMITX_EN_SLDO 16
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+
#define RG_HDMITX_EN_SLDO_MASK (0x0f << 16)
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+
#define RG_HDMITX_EN_PRED 20
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+
#define RG_HDMITX_EN_PRED_MASK (0x0f << 20)
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+
#define RG_HDMITX_EN_IMP 24
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+
#define RG_HDMITX_EN_IMP_MASK (0x0f << 24)
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#define RG_HDMITX_EN_DRV 28
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+
#define RG_HDMITX_EN_DRV_MASK (0x0f << 28)
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+
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+
#define HDMI_CON1 0x04
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+
#define RG_HDMITX_PRED_IBIAS 18
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#define RG_HDMITX_PRED_IBIAS_MASK (0x0f << 18)
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+
#define RG_HDMITX_PRED_IMP (0x01 << 22)
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#define RG_HDMITX_DRV_IMP 26
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#define RG_HDMITX_DRV_IMP_MASK (0x3f << 26)
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+
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#define HDMI_CON2 0x08
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#define RG_HDMITX_EN_TX_CKLDO (0x01 << 0)
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#define RG_HDMITX_EN_TX_POSDIV (0x01 << 1)
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#define RG_HDMITX_TX_POSDIV 3
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#define RG_HDMITX_TX_POSDIV_MASK (0x03 << 3)
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#define RG_HDMITX_EN_MBIAS (0x01 << 6)
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#define RG_HDMITX_MBIAS_LPF_EN (0x01 << 7)
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+
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#define HDMI_CON4 0x10
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#define RG_HDMITX_RESERVE_MASK (0xffffffff << 0)
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+
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#define HDMI_CON6 0x18
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#define RG_HTPLL_BR 0
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#define RG_HTPLL_BR_MASK (0x03 << 0)
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#define RG_HTPLL_BC 2
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#define RG_HTPLL_BC_MASK (0x03 << 2)
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#define RG_HTPLL_BP 4
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#define RG_HTPLL_BP_MASK (0x0f << 4)
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#define RG_HTPLL_IR 8
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#define RG_HTPLL_IR_MASK (0x0f << 8)
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#define RG_HTPLL_IC 12
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#define RG_HTPLL_IC_MASK (0x0f << 12)
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#define RG_HTPLL_POSDIV 16
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#define RG_HTPLL_POSDIV_MASK (0x03 << 16)
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#define RG_HTPLL_PREDIV 18
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#define RG_HTPLL_PREDIV_MASK (0x03 << 18)
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#define RG_HTPLL_FBKSEL 20
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#define RG_HTPLL_FBKSEL_MASK (0x03 << 20)
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#define RG_HTPLL_RLH_EN (0x01 << 22)
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#define RG_HTPLL_FBKDIV 24
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#define RG_HTPLL_FBKDIV_MASK (0x7f << 24)
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#define RG_HTPLL_EN (0x01 << 31)
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+
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#define HDMI_CON7 0x1c
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+
#define RG_HTPLL_AUTOK_EN (0x01 << 23)
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#define RG_HTPLL_DIVEN 28
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#define RG_HTPLL_DIVEN_MASK (0x07 << 28)
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+
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+
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
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+
{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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+
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
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usleep_range(80, 100);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
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+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
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+
usleep_range(80, 100);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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+
usleep_range(80, 100);
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return 0;
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+
}
89
+
90
+
static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
91
+
{
92
+
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
93
+
94
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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+
usleep_range(80, 100);
100
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
101
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
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+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
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+
usleep_range(80, 100);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
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+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
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+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
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usleep_range(80, 100);
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+
}
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+
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+
static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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+
unsigned long parent_rate)
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+
{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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+
u32 pos_div;
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+
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if (rate <= 64000000)
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pos_div = 3;
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else if (rate <= 12800000)
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pos_div = 1;
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+
else
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pos_div = 1;
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+
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+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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+
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
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+
RG_HTPLL_IC_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
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+
RG_HTPLL_IR_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
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+
RG_HDMITX_TX_POSDIV_MASK);
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+
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
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+
RG_HTPLL_FBKSEL_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
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+
RG_HTPLL_FBKDIV_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
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+
RG_HTPLL_DIVEN_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
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+
RG_HTPLL_BP_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
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+
RG_HTPLL_BC_MASK);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
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+
RG_HTPLL_BR_MASK);
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+
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
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RG_HDMITX_PRED_IBIAS_MASK);
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+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
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+
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
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+
RG_HDMITX_DRV_IMP_MASK);
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+
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
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+
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
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+
RG_HDMITX_DRV_IBIAS_MASK);
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return 0;
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+
}
156
+
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+
static const struct clk_ops mtk_hdmi_phy_pll_ops = {
158
+
.prepare = mtk_hdmi_pll_prepare,
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+
.unprepare = mtk_hdmi_pll_unprepare,
160
+
.set_rate = mtk_hdmi_pll_set_rate,
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+
.round_rate = mtk_hdmi_pll_round_rate,
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+
.recalc_rate = mtk_hdmi_pll_recalc_rate,
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+
};
164
+
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+
static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
166
+
{
167
+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
168
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
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+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
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+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
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+
usleep_range(80, 100);
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+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
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+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
174
+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
175
+
usleep_range(80, 100);
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+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
178
+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
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+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
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+
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
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+
usleep_range(80, 100);
182
+
}
183
+
184
+
static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
185
+
{
186
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
187
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
188
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
189
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
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+
usleep_range(80, 100);
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+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
193
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
194
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
195
+
usleep_range(80, 100);
196
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
197
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
198
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
199
+
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
200
+
usleep_range(80, 100);
201
+
}
202
+
203
+
struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = {
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+
.tz_disabled = true,
205
+
.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
206
+
.hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
207
+
.hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
208
+
};
209
+
210
+
MODULE_AUTHOR("Chunhui Dai <chunhui.dai@mediatek.com>");
211
+
MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
212
+
MODULE_LICENSE("GPL v2");