drm/imagination: Update register defs for newer GPUs

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Update the register define header to a newer version that covers more
recent GPUs, including BXS-4-64.

Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-3-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>

authored by

Alessio Belle and committed by

Matt Coster 1 year ago 0fb32b77 86e3f3a6

+134 -19

1 changed file

expand all

drivers

gpu

drm

imagination

pvr_rogue_cr_defs.h

+134 -19

drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h

··· 827 827 #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU 828 828 #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_EN 0x00000001U 829 829 830 + /* Register ROGUE_CR_EVENT_CLEAR */ 831 + #define ROGUE_CR_EVENT_CLEAR 0x0138U 832 + #define ROGUE_CR_EVENT_CLEAR__ROGUEXE__MASKFULL 0x00000000E01DFFFFULL 833 + #define ROGUE_CR_EVENT_CLEAR__SIGNALS__MASKFULL 0x00000000E007FFFFULL 834 + #define ROGUE_CR_EVENT_CLEAR_MASKFULL 0x00000000FFFFFFFFULL 835 + #define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_SHIFT 31U 836 + #define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_CLRMSK 0x7FFFFFFFU 837 + #define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_EN 0x80000000U 838 + #define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_SHIFT 30U 839 + #define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_CLRMSK 0xBFFFFFFFU 840 + #define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_EN 0x40000000U 841 + #define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_SHIFT 29U 842 + #define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_CLRMSK 0xDFFFFFFFU 843 + #define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_EN 0x20000000U 844 + #define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_SHIFT 28U 845 + #define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_CLRMSK 0xEFFFFFFFU 846 + #define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_EN 0x10000000U 847 + #define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_SHIFT 27U 848 + #define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_CLRMSK 0xF7FFFFFFU 849 + #define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_EN 0x08000000U 850 + #define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_SHIFT 26U 851 + #define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_CLRMSK 0xFBFFFFFFU 852 + #define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_EN 0x04000000U 853 + #define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_SHIFT 25U 854 + #define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_CLRMSK 0xFDFFFFFFU 855 + #define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_EN 0x02000000U 856 + #define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_SHIFT 24U 857 + #define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_CLRMSK 0xFEFFFFFFU 858 + #define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_EN 0x01000000U 859 + #define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_SHIFT 23U 860 + #define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_CLRMSK 0xFF7FFFFFU 861 + #define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_EN 0x00800000U 862 + #define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_SHIFT 22U 863 + #define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_CLRMSK 0xFFBFFFFFU 864 + #define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_EN 0x00400000U 865 + #define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_SHIFT 21U 866 + #define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_CLRMSK 0xFFDFFFFFU 867 + #define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_EN 0x00200000U 868 + #define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_SHIFT 20U 869 + #define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_CLRMSK 0xFFEFFFFFU 870 + #define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_EN 0x00100000U 871 + #define ROGUE_CR_EVENT_CLEAR_SAFETY_SHIFT 20U 872 + #define ROGUE_CR_EVENT_CLEAR_SAFETY_CLRMSK 0xFFEFFFFFU 873 + #define ROGUE_CR_EVENT_CLEAR_SAFETY_EN 0x00100000U 874 + #define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_SHIFT 19U 875 + #define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_CLRMSK 0xFFF7FFFFU 876 + #define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_EN 0x00080000U 877 + #define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_SHIFT 19U 878 + #define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_CLRMSK 0xFFF7FFFFU 879 + #define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_EN 0x00080000U 880 + #define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_SHIFT 18U 881 + #define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_CLRMSK 0xFFFBFFFFU 882 + #define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_EN 0x00040000U 883 + #define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_SHIFT 18U 884 + #define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_CLRMSK 0xFFFBFFFFU 885 + #define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_EN 0x00040000U 886 + #define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_SHIFT 17U 887 + #define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_CLRMSK 0xFFFDFFFFU 888 + #define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_EN 0x00020000U 889 + #define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_SHIFT 17U 890 + #define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_CLRMSK 0xFFFDFFFFU 891 + #define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_EN 0x00020000U 892 + #define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_SHIFT 16U 893 + #define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_CLRMSK 0xFFFEFFFFU 894 + #define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_EN 0x00010000U 895 + #define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_SHIFT 15U 896 + #define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_CLRMSK 0xFFFF7FFFU 897 + #define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_EN 0x00008000U 898 + #define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_SHIFT 14U 899 + #define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_CLRMSK 0xFFFFBFFFU 900 + #define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_EN 0x00004000U 901 + #define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_SHIFT 13U 902 + #define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_CLRMSK 0xFFFFDFFFU 903 + #define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_EN 0x00002000U 904 + #define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_SHIFT 12U 905 + #define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_CLRMSK 0xFFFFEFFFU 906 + #define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_EN 0x00001000U 907 + #define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_SHIFT 11U 908 + #define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_CLRMSK 0xFFFFF7FFU 909 + #define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_EN 0x00000800U 910 + #define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_SHIFT 10U 911 + #define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_CLRMSK 0xFFFFFBFFU 912 + #define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_EN 0x00000400U 913 + #define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_SHIFT 9U 914 + #define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_CLRMSK 0xFFFFFDFFU 915 + #define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_EN 0x00000200U 916 + #define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_SHIFT 8U 917 + #define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_CLRMSK 0xFFFFFEFFU 918 + #define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_EN 0x00000100U 919 + #define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_SHIFT 7U 920 + #define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_CLRMSK 0xFFFFFF7FU 921 + #define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_EN 0x00000080U 922 + #define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_SHIFT 6U 923 + #define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_CLRMSK 0xFFFFFFBFU 924 + #define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_EN 0x00000040U 925 + #define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_SHIFT 5U 926 + #define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_CLRMSK 0xFFFFFFDFU 927 + #define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_EN 0x00000020U 928 + #define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_SHIFT 4U 929 + #define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_CLRMSK 0xFFFFFFEFU 930 + #define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_EN 0x00000010U 931 + #define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_SHIFT 3U 932 + #define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_CLRMSK 0xFFFFFFF7U 933 + #define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_EN 0x00000008U 934 + #define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_SHIFT 2U 935 + #define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_CLRMSK 0xFFFFFFFBU 936 + #define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_EN 0x00000004U 937 + #define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_SHIFT 1U 938 + #define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_CLRMSK 0xFFFFFFFDU 939 + #define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_EN 0x00000002U 940 + #define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_SHIFT 0U 941 + #define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU 942 + #define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_EN 0x00000001U 943 + 830 944 /* Register ROGUE_CR_TIMER */ 831 945 #define ROGUE_CR_TIMER 0x0160U 832 946 #define ROGUE_CR_TIMER_MASKFULL 0x8000FFFFFFFFFFFFULL ··· 6145 6031 #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_SHIFT 0U 6146 6032 #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U 6147 6033 6148 - /* Register ROGUE_CR_ECC_RAM_ERR_INJ */ 6149 - #define ROGUE_CR_ECC_RAM_ERR_INJ 0xF340U 6150 - #define ROGUE_CR_ECC_RAM_ERR_INJ_MASKFULL 0x000000000000001FULL 6151 - #define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_SHIFT 4U 6152 - #define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU 6153 - #define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_EN 0x00000010U 6154 - #define ROGUE_CR_ECC_RAM_ERR_INJ_USC_SHIFT 3U 6155 - #define ROGUE_CR_ECC_RAM_ERR_INJ_USC_CLRMSK 0xFFFFFFF7U 6156 - #define ROGUE_CR_ECC_RAM_ERR_INJ_USC_EN 0x00000008U 6157 - #define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_SHIFT 2U 6158 - #define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU 6159 - #define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_EN 0x00000004U 6160 - #define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_SHIFT 1U 6161 - #define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_CLRMSK 0xFFFFFFFDU 6162 - #define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_EN 0x00000002U 6163 - #define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_SHIFT 0U 6164 - #define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_CLRMSK 0xFFFFFFFEU 6165 - #define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_EN 0x00000001U 6166 - 6167 6034 /* Register ROGUE_CR_ECC_RAM_INIT_KICK */ 6168 6035 #define ROGUE_CR_ECC_RAM_INIT_KICK 0xF348U 6169 6036 #define ROGUE_CR_ECC_RAM_INIT_KICK_MASKFULL 0x000000000000001FULL ··· 6257 6162 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U 6258 6163 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU 6259 6164 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U 6165 + 6166 + /* Register ROGUE_CR_FAULT_FW_STATUS */ 6167 + #define ROGUE_CR_FAULT_FW_STATUS 0xF3B0U 6168 + #define ROGUE_CR_FAULT_FW_STATUS_MASKFULL 0x0000000000010001ULL 6169 + #define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_SHIFT 16U 6170 + #define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_CLRMSK 0xFFFEFFFFU 6171 + #define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_EN 0x00010000U 6172 + #define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_SHIFT 0U 6173 + #define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_CLRMSK 0xFFFFFFFEU 6174 + #define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_EN 0x00000001U 6175 + 6176 + /* Register ROGUE_CR_FAULT_FW_CLEAR */ 6177 + #define ROGUE_CR_FAULT_FW_CLEAR 0xF3B8U 6178 + #define ROGUE_CR_FAULT_FW_CLEAR_MASKFULL 0x0000000000010001ULL 6179 + #define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_SHIFT 16U 6180 + #define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_CLRMSK 0xFFFEFFFFU 6181 + #define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_EN 0x00010000U 6182 + #define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_SHIFT 0U 6183 + #define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_CLRMSK 0xFFFFFFFEU 6184 + #define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_EN 0x00000001U 6260 6185 6261 6186 /* Register ROGUE_CR_MTS_SAFETY_EVENT_ENABLE */ 6262 6187 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE 0xF3D8U