Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

ARM: dts: ux500: Move generic pin configs out of ste-href-family-pinctrl.dtsi

All existing Ux500 boards make use of ste-href-family-pinctrl.dtsi,
which contains shared pin configurations for UART, I2C and SDI.
Most of these can be also used for devices not based on HREF.

Move the generic pin configs into a new device tree include
"ste-dbx5x0-pinctrl.dtsi". There is no functional change (yet),
as a next step we will rename the pin configs to use more generic
names.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125122256.53482-1-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Stephan Gerhold and committed by
Linus Walleij
0f8e7414 6cfeb611

+530 -531
+529
arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 + /* 3 + * Copyright 2013 Linaro Ltd. 4 + */ 5 + 6 + #include "ste-nomadik-pinctrl.dtsi" 7 + 8 + &pinctrl { 9 + /* Settings for all UART default and sleep states */ 10 + uart0 { 11 + uart0_default_mode: uart0_default { 12 + default_mux { 13 + function = "u0"; 14 + groups = "u0_a_1"; 15 + }; 16 + default_cfg1 { 17 + pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ 18 + ste,config = <&in_pu>; 19 + }; 20 + default_cfg2 { 21 + pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ 22 + ste,config = <&out_hi>; 23 + }; 24 + }; 25 + 26 + uart0_sleep_mode: uart0_sleep { 27 + sleep_cfg1 { 28 + pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ 29 + ste,config = <&slpm_in_wkup_pdis>; 30 + }; 31 + sleep_cfg2 { 32 + pins = "GPIO1_AJ3"; /* RTS */ 33 + ste,config = <&slpm_out_hi_wkup_pdis>; 34 + }; 35 + sleep_cfg3 { 36 + pins = "GPIO3_AH3"; /* TXD */ 37 + ste,config = <&slpm_out_wkup_pdis>; 38 + }; 39 + }; 40 + }; 41 + 42 + uart1 { 43 + uart1_default_mode: uart1_default { 44 + default_mux { 45 + function = "u1"; 46 + groups = "u1rxtx_a_1"; 47 + }; 48 + default_cfg1 { 49 + pins = "GPIO4_AH6"; /* RXD */ 50 + ste,config = <&in_pu>; 51 + }; 52 + default_cfg2 { 53 + pins = "GPIO5_AG6"; /* TXD */ 54 + ste,config = <&out_hi>; 55 + }; 56 + }; 57 + 58 + uart1_sleep_mode: uart1_sleep { 59 + sleep_cfg1 { 60 + pins = "GPIO4_AH6"; /* RXD */ 61 + ste,config = <&slpm_in_wkup_pdis>; 62 + }; 63 + sleep_cfg2 { 64 + pins = "GPIO5_AG6"; /* TXD */ 65 + ste,config = <&slpm_out_wkup_pdis>; 66 + }; 67 + }; 68 + }; 69 + 70 + uart2 { 71 + uart2_default_mode: uart2_default { 72 + default_mux { 73 + function = "u2"; 74 + groups = "u2rxtx_c_1"; 75 + }; 76 + default_cfg1 { 77 + pins = "GPIO29_W2"; /* RXD */ 78 + ste,config = <&in_pu>; 79 + }; 80 + default_cfg2 { 81 + pins = "GPIO30_W3"; /* TXD */ 82 + ste,config = <&out_hi>; 83 + }; 84 + }; 85 + 86 + uart2_sleep_mode: uart2_sleep { 87 + sleep_cfg1 { 88 + pins = "GPIO29_W2"; /* RXD */ 89 + ste,config = <&in_wkup_pdis>; 90 + }; 91 + sleep_cfg2 { 92 + pins = "GPIO30_W3"; /* TXD */ 93 + ste,config = <&out_wkup_pdis>; 94 + }; 95 + }; 96 + }; 97 + 98 + /* Settings for all I2C default and sleep states */ 99 + i2c0 { 100 + i2c0_default_mode: i2c_default { 101 + default_mux { 102 + function = "i2c0"; 103 + groups = "i2c0_a_1"; 104 + }; 105 + default_cfg1 { 106 + pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ 107 + ste,config = <&in_pu>; 108 + }; 109 + }; 110 + 111 + i2c0_sleep_mode: i2c_sleep { 112 + sleep_cfg1 { 113 + pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ 114 + ste,config = <&slpm_in_wkup_pdis>; 115 + }; 116 + }; 117 + }; 118 + 119 + i2c1 { 120 + i2c1_default_mode: i2c_default { 121 + default_mux { 122 + function = "i2c1"; 123 + groups = "i2c1_b_2"; 124 + }; 125 + default_cfg1 { 126 + pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ 127 + ste,config = <&in_pu>; 128 + }; 129 + }; 130 + 131 + i2c1_sleep_mode: i2c_sleep { 132 + sleep_cfg1 { 133 + pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ 134 + ste,config = <&slpm_in_wkup_pdis>; 135 + }; 136 + }; 137 + }; 138 + 139 + i2c2 { 140 + i2c2_default_mode: i2c_default { 141 + default_mux { 142 + function = "i2c2"; 143 + groups = "i2c2_b_2"; 144 + }; 145 + default_cfg1 { 146 + pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ 147 + ste,config = <&in_pu>; 148 + }; 149 + }; 150 + 151 + i2c2_sleep_mode: i2c_sleep { 152 + sleep_cfg1 { 153 + pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ 154 + ste,config = <&slpm_in_wkup_pdis>; 155 + }; 156 + }; 157 + }; 158 + 159 + i2c3 { 160 + i2c3_default_mode: i2c_default { 161 + default_mux { 162 + function = "i2c3"; 163 + groups = "i2c3_c_2"; 164 + }; 165 + default_cfg1 { 166 + pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ 167 + ste,config = <&in_pu>; 168 + }; 169 + }; 170 + 171 + i2c3_sleep_mode: i2c_sleep { 172 + sleep_cfg1 { 173 + pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ 174 + ste,config = <&slpm_in_wkup_pdis>; 175 + }; 176 + }; 177 + }; 178 + 179 + /* 180 + * Activating I2C4 will conflict with UART1 about the same pins so do not 181 + * enable I2C4 and UART1 at the same time. 182 + */ 183 + i2c4 { 184 + i2c4_default_mode: i2c_default { 185 + default_mux { 186 + function = "i2c4"; 187 + groups = "i2c4_b_1"; 188 + }; 189 + default_cfg1 { 190 + pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ 191 + ste,config = <&in_pu>; 192 + }; 193 + }; 194 + 195 + i2c4_sleep_mode: i2c_sleep { 196 + sleep_cfg1 { 197 + pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ 198 + ste,config = <&slpm_in_wkup_pdis>; 199 + }; 200 + }; 201 + }; 202 + 203 + /* Settings for all MMC/SD/SDIO default and sleep states */ 204 + sdi0 { 205 + /* This is the external SD card slot, 4 bits wide */ 206 + sdi0_default_mode: sdi0_default { 207 + default_mux { 208 + function = "mc0"; 209 + groups = "mc0_a_1"; 210 + }; 211 + default_cfg1 { 212 + pins = 213 + "GPIO18_AC2", /* CMDDIR */ 214 + "GPIO19_AC1", /* DAT0DIR */ 215 + "GPIO20_AB4"; /* DAT2DIR */ 216 + ste,config = <&out_hi>; 217 + }; 218 + default_cfg2 { 219 + pins = "GPIO22_AA3"; /* FBCLK */ 220 + ste,config = <&in_nopull>; 221 + }; 222 + default_cfg3 { 223 + pins = "GPIO23_AA4"; /* CLK */ 224 + ste,config = <&out_lo>; 225 + }; 226 + default_cfg4 { 227 + pins = 228 + "GPIO24_AB2", /* CMD */ 229 + "GPIO25_Y4", /* DAT0 */ 230 + "GPIO26_Y2", /* DAT1 */ 231 + "GPIO27_AA2", /* DAT2 */ 232 + "GPIO28_AA1"; /* DAT3 */ 233 + ste,config = <&in_pu>; 234 + }; 235 + }; 236 + 237 + sdi0_sleep_mode: sdi0_sleep { 238 + sleep_cfg1 { 239 + pins = 240 + "GPIO18_AC2", /* CMDDIR */ 241 + "GPIO19_AC1", /* DAT0DIR */ 242 + "GPIO20_AB4"; /* DAT2DIR */ 243 + ste,config = <&slpm_out_hi_wkup_pdis>; 244 + }; 245 + sleep_cfg2 { 246 + pins = 247 + "GPIO22_AA3", /* FBCLK */ 248 + "GPIO24_AB2", /* CMD */ 249 + "GPIO25_Y4", /* DAT0 */ 250 + "GPIO26_Y2", /* DAT1 */ 251 + "GPIO27_AA2", /* DAT2 */ 252 + "GPIO28_AA1"; /* DAT3 */ 253 + ste,config = <&slpm_in_wkup_pdis>; 254 + }; 255 + sleep_cfg3 { 256 + pins = "GPIO23_AA4"; /* CLK */ 257 + ste,config = <&slpm_out_lo_wkup_pdis>; 258 + }; 259 + }; 260 + }; 261 + 262 + sdi1 { 263 + /* This is the WLAN SDIO 4 bits wide */ 264 + sdi1_default_mode: sdi1_default { 265 + default_mux { 266 + function = "mc1"; 267 + groups = "mc1_a_1"; 268 + }; 269 + default_cfg1 { 270 + pins = "GPIO208_AH16"; /* CLK */ 271 + ste,config = <&out_lo>; 272 + }; 273 + default_cfg2 { 274 + pins = "GPIO209_AG15"; /* FBCLK */ 275 + ste,config = <&in_nopull>; 276 + }; 277 + default_cfg3 { 278 + pins = 279 + "GPIO210_AJ15", /* CMD */ 280 + "GPIO211_AG14", /* DAT0 */ 281 + "GPIO212_AF13", /* DAT1 */ 282 + "GPIO213_AG13", /* DAT2 */ 283 + "GPIO214_AH15"; /* DAT3 */ 284 + ste,config = <&in_pu>; 285 + }; 286 + }; 287 + 288 + sdi1_sleep_mode: sdi1_sleep { 289 + sleep_cfg1 { 290 + pins = "GPIO208_AH16"; /* CLK */ 291 + ste,config = <&slpm_out_lo_wkup_pdis>; 292 + }; 293 + sleep_cfg2 { 294 + pins = 295 + "GPIO209_AG15", /* FBCLK */ 296 + "GPIO210_AJ15", /* CMD */ 297 + "GPIO211_AG14", /* DAT0 */ 298 + "GPIO212_AF13", /* DAT1 */ 299 + "GPIO213_AG13", /* DAT2 */ 300 + "GPIO214_AH15"; /* DAT3 */ 301 + ste,config = <&slpm_in_wkup_pdis>; 302 + }; 303 + }; 304 + }; 305 + 306 + sdi2 { 307 + /* This is the eMMC 8 bits wide, usually PoP eMMC */ 308 + sdi2_default_mode: sdi2_default { 309 + default_mux { 310 + function = "mc2"; 311 + groups = "mc2_a_1"; 312 + }; 313 + default_cfg1 { 314 + pins = "GPIO128_A5"; /* CLK */ 315 + ste,config = <&out_lo>; 316 + }; 317 + default_cfg2 { 318 + pins = "GPIO130_C8"; /* FBCLK */ 319 + ste,config = <&in_nopull>; 320 + }; 321 + default_cfg3 { 322 + pins = 323 + "GPIO129_B4", /* CMD */ 324 + "GPIO131_A12", /* DAT0 */ 325 + "GPIO132_C10", /* DAT1 */ 326 + "GPIO133_B10", /* DAT2 */ 327 + "GPIO134_B9", /* DAT3 */ 328 + "GPIO135_A9", /* DAT4 */ 329 + "GPIO136_C7", /* DAT5 */ 330 + "GPIO137_A7", /* DAT6 */ 331 + "GPIO138_C5"; /* DAT7 */ 332 + ste,config = <&in_pu>; 333 + }; 334 + }; 335 + 336 + sdi2_sleep_mode: sdi2_sleep { 337 + sleep_cfg1 { 338 + pins = "GPIO128_A5"; /* CLK */ 339 + ste,config = <&out_lo_wkup_pdis>; 340 + }; 341 + sleep_cfg2 { 342 + pins = 343 + "GPIO130_C8", /* FBCLK */ 344 + "GPIO129_B4"; /* CMD */ 345 + ste,config = <&in_wkup_pdis_en>; 346 + }; 347 + sleep_cfg3 { 348 + pins = 349 + "GPIO131_A12", /* DAT0 */ 350 + "GPIO132_C10", /* DAT1 */ 351 + "GPIO133_B10", /* DAT2 */ 352 + "GPIO134_B9", /* DAT3 */ 353 + "GPIO135_A9", /* DAT4 */ 354 + "GPIO136_C7", /* DAT5 */ 355 + "GPIO137_A7", /* DAT6 */ 356 + "GPIO138_C5"; /* DAT7 */ 357 + ste,config = <&in_wkup_pdis>; 358 + }; 359 + }; 360 + }; 361 + 362 + sdi4 { 363 + /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */ 364 + sdi4_default_mode: sdi4_default { 365 + default_mux { 366 + function = "mc4"; 367 + groups = "mc4_a_1"; 368 + }; 369 + default_cfg1 { 370 + pins = "GPIO203_AE23"; /* CLK */ 371 + ste,config = <&out_lo>; 372 + }; 373 + default_cfg2 { 374 + pins = "GPIO202_AF25"; /* FBCLK */ 375 + ste,config = <&in_nopull>; 376 + }; 377 + default_cfg3 { 378 + pins = 379 + "GPIO201_AF24", /* CMD */ 380 + "GPIO200_AH26", /* DAT0 */ 381 + "GPIO199_AH23", /* DAT1 */ 382 + "GPIO198_AG25", /* DAT2 */ 383 + "GPIO197_AH24", /* DAT3 */ 384 + "GPIO207_AJ23", /* DAT4 */ 385 + "GPIO206_AG24", /* DAT5 */ 386 + "GPIO205_AG23", /* DAT6 */ 387 + "GPIO204_AF23"; /* DAT7 */ 388 + ste,config = <&in_pu>; 389 + }; 390 + }; 391 + 392 + sdi4_sleep_mode: sdi4_sleep { 393 + sleep_cfg1 { 394 + pins = "GPIO203_AE23"; /* CLK */ 395 + ste,config = <&out_lo_wkup_pdis>; 396 + }; 397 + sleep_cfg2 { 398 + pins = 399 + "GPIO202_AF25", /* FBCLK */ 400 + "GPIO201_AF24", /* CMD */ 401 + "GPIO200_AH26", /* DAT0 */ 402 + "GPIO199_AH23", /* DAT1 */ 403 + "GPIO198_AG25", /* DAT2 */ 404 + "GPIO197_AH24", /* DAT3 */ 405 + "GPIO207_AJ23", /* DAT4 */ 406 + "GPIO206_AG24", /* DAT5 */ 407 + "GPIO205_AG23", /* DAT6 */ 408 + "GPIO204_AF23"; /* DAT7 */ 409 + ste,config = <&slpm_in_wkup_pdis>; 410 + }; 411 + }; 412 + }; 413 + 414 + /* 415 + * Multi-rate serial ports (MSPs) - MSP3 output is internal and 416 + * cannot be muxed onto any pins. 417 + */ 418 + msp0 { 419 + msp0_default_mode: msp0_default { 420 + default_msp0_mux { 421 + function = "msp0"; 422 + groups = "msp0txrx_a_1", "msp0tfstck_a_1"; 423 + }; 424 + default_msp0_cfg { 425 + pins = 426 + "GPIO12_AC4", /* TXD */ 427 + "GPIO15_AC3", /* RXD */ 428 + "GPIO13_AF3", /* TFS */ 429 + "GPIO14_AE3"; /* TCK */ 430 + ste,config = <&in_nopull>; 431 + }; 432 + }; 433 + }; 434 + 435 + msp1 { 436 + msp1_default_mode: msp1_default { 437 + default_mux { 438 + function = "msp1"; 439 + groups = "msp1txrx_a_1", "msp1_a_1"; 440 + }; 441 + default_cfg1 { 442 + pins = "GPIO33_AF2"; 443 + ste,config = <&out_lo>; 444 + }; 445 + default_cfg2 { 446 + pins = 447 + "GPIO34_AE1", 448 + "GPIO35_AE2", 449 + "GPIO36_AG2"; 450 + ste,config = <&in_nopull>; 451 + }; 452 + }; 453 + }; 454 + 455 + msp2 { 456 + msp2_default_mode: msp2_default { 457 + /* MSP2 usually used for HDMI audio */ 458 + default_mux { 459 + function = "msp2"; 460 + groups = "msp2_a_1"; 461 + }; 462 + default_cfg1 { 463 + pins = 464 + "GPIO193_AH27", /* TXD */ 465 + "GPIO194_AF27", /* TCK */ 466 + "GPIO195_AG28"; /* TFS */ 467 + ste,config = <&in_pd>; 468 + }; 469 + default_cfg2 { 470 + pins = "GPIO196_AG26"; /* RXD */ 471 + ste,config = <&out_lo>; 472 + }; 473 + }; 474 + }; 475 + 476 + musb { 477 + musb_default_mode: musb_default { 478 + default_mux { 479 + function = "usb"; 480 + groups = "usb_a_1"; 481 + }; 482 + default_cfg1 { 483 + pins = 484 + "GPIO256_AF28", /* NXT */ 485 + "GPIO258_AD29", /* XCLK */ 486 + "GPIO259_AC29", /* DIR */ 487 + "GPIO260_AD28", /* DAT7 */ 488 + "GPIO261_AD26", /* DAT6 */ 489 + "GPIO262_AE26", /* DAT5 */ 490 + "GPIO263_AG29", /* DAT4 */ 491 + "GPIO264_AE27", /* DAT3 */ 492 + "GPIO265_AD27", /* DAT2 */ 493 + "GPIO266_AC28", /* DAT1 */ 494 + "GPIO267_AC27"; /* DAT0 */ 495 + ste,config = <&in_nopull>; 496 + }; 497 + default_cfg2 { 498 + pins = "GPIO257_AE29"; /* STP */ 499 + ste,config = <&out_hi>; 500 + }; 501 + }; 502 + 503 + musb_sleep_mode: musb_sleep { 504 + sleep_cfg1 { 505 + pins = 506 + "GPIO256_AF28", /* NXT */ 507 + "GPIO258_AD29", /* XCLK */ 508 + "GPIO259_AC29"; /* DIR */ 509 + ste,config = <&slpm_wkup_pdis_en>; 510 + }; 511 + sleep_cfg2 { 512 + pins = "GPIO257_AE29"; /* STP */ 513 + ste,config = <&slpm_out_hi_wkup_pdis>; 514 + }; 515 + sleep_cfg3 { 516 + pins = 517 + "GPIO260_AD28", /* DAT7 */ 518 + "GPIO261_AD26", /* DAT6 */ 519 + "GPIO262_AE26", /* DAT5 */ 520 + "GPIO263_AG29", /* DAT4 */ 521 + "GPIO264_AE27", /* DAT3 */ 522 + "GPIO265_AD27", /* DAT2 */ 523 + "GPIO266_AC28", /* DAT1 */ 524 + "GPIO267_AC27"; /* DAT0 */ 525 + ste,config = <&slpm_in_wkup_pdis_en>; 526 + }; 527 + }; 528 + }; 529 + };
+1 -531
arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
··· 3 3 * Copyright 2013 Linaro Ltd. 4 4 */ 5 5 6 - #include "ste-nomadik-pinctrl.dtsi" 6 + #include "ste-dbx5x0-pinctrl.dtsi" 7 7 8 8 / { 9 9 soc { 10 10 pinctrl { 11 - /* Settings for all UART default and sleep states */ 12 - uart0 { 13 - uart0_default_mode: uart0_default { 14 - default_mux { 15 - function = "u0"; 16 - groups = "u0_a_1"; 17 - }; 18 - default_cfg1 { 19 - pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ 20 - ste,config = <&in_pu>; 21 - }; 22 - 23 - default_cfg2 { 24 - pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ 25 - ste,config = <&out_hi>; 26 - }; 27 - }; 28 - 29 - uart0_sleep_mode: uart0_sleep { 30 - sleep_cfg1 { 31 - pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ 32 - ste,config = <&slpm_in_wkup_pdis>; 33 - }; 34 - 35 - sleep_cfg2 { 36 - pins = "GPIO1_AJ3"; /* RTS */ 37 - ste,config = <&slpm_out_hi_wkup_pdis>; 38 - }; 39 - 40 - sleep_cfg3 { 41 - pins = "GPIO3_AH3"; /* TXD */ 42 - ste,config = <&slpm_out_wkup_pdis>; 43 - }; 44 - }; 45 - }; 46 - 47 - uart1 { 48 - uart1_default_mode: uart1_default { 49 - default_mux { 50 - function = "u1"; 51 - groups = "u1rxtx_a_1"; 52 - }; 53 - default_cfg1 { 54 - pins = "GPIO4_AH6"; /* RXD */ 55 - ste,config = <&in_pu>; 56 - }; 57 - 58 - default_cfg2 { 59 - pins = "GPIO5_AG6"; /* TXD */ 60 - ste,config = <&out_hi>; 61 - }; 62 - }; 63 - 64 - uart1_sleep_mode: uart1_sleep { 65 - sleep_cfg1 { 66 - pins = "GPIO4_AH6"; /* RXD */ 67 - ste,config = <&slpm_in_wkup_pdis>; 68 - }; 69 - 70 - sleep_cfg2 { 71 - pins = "GPIO5_AG6"; /* TXD */ 72 - ste,config = <&slpm_out_wkup_pdis>; 73 - }; 74 - }; 75 - }; 76 - 77 - uart2 { 78 - uart2_default_mode: uart2_default { 79 - default_mux { 80 - function = "u2"; 81 - groups = "u2rxtx_c_1"; 82 - }; 83 - default_cfg1 { 84 - pins = "GPIO29_W2"; /* RXD */ 85 - ste,config = <&in_pu>; 86 - }; 87 - 88 - default_cfg2 { 89 - pins = "GPIO30_W3"; /* TXD */ 90 - ste,config = <&out_hi>; 91 - }; 92 - }; 93 - 94 - uart2_sleep_mode: uart2_sleep { 95 - sleep_cfg1 { 96 - pins = "GPIO29_W2"; /* RXD */ 97 - ste,config = <&in_wkup_pdis>; 98 - }; 99 - 100 - sleep_cfg2 { 101 - pins = "GPIO30_W3"; /* TXD */ 102 - ste,config = <&out_wkup_pdis>; 103 - }; 104 - }; 105 - }; 106 - 107 - /* Settings for all I2C default and sleep states */ 108 - i2c0 { 109 - i2c0_default_mode: i2c_default { 110 - default_mux { 111 - function = "i2c0"; 112 - groups = "i2c0_a_1"; 113 - }; 114 - default_cfg1 { 115 - pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ 116 - ste,config = <&in_pu>; 117 - }; 118 - }; 119 - 120 - i2c0_sleep_mode: i2c_sleep { 121 - sleep_cfg1 { 122 - pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ 123 - ste,config = <&slpm_in_wkup_pdis>; 124 - }; 125 - }; 126 - }; 127 - 128 - i2c1 { 129 - i2c1_default_mode: i2c_default { 130 - default_mux { 131 - function = "i2c1"; 132 - groups = "i2c1_b_2"; 133 - }; 134 - default_cfg1 { 135 - pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ 136 - ste,config = <&in_pu>; 137 - }; 138 - }; 139 - 140 - i2c1_sleep_mode: i2c_sleep { 141 - sleep_cfg1 { 142 - pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ 143 - ste,config = <&slpm_in_wkup_pdis>; 144 - }; 145 - }; 146 - }; 147 - 148 - i2c2 { 149 - i2c2_default_mode: i2c_default { 150 - default_mux { 151 - function = "i2c2"; 152 - groups = "i2c2_b_2"; 153 - }; 154 - default_cfg1 { 155 - pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ 156 - ste,config = <&in_pu>; 157 - }; 158 - }; 159 - 160 - i2c2_sleep_mode: i2c_sleep { 161 - sleep_cfg1 { 162 - pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ 163 - ste,config = <&slpm_in_wkup_pdis>; 164 - }; 165 - }; 166 - }; 167 - 168 - i2c3 { 169 - i2c3_default_mode: i2c_default { 170 - default_mux { 171 - function = "i2c3"; 172 - groups = "i2c3_c_2"; 173 - }; 174 - default_cfg1 { 175 - pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ 176 - ste,config = <&in_pu>; 177 - }; 178 - }; 179 - 180 - i2c3_sleep_mode: i2c_sleep { 181 - sleep_cfg1 { 182 - pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ 183 - ste,config = <&slpm_in_wkup_pdis>; 184 - }; 185 - }; 186 - }; 187 - 188 - /* 189 - * Activating I2C4 will conflict with UART1 about the same pins so do not 190 - * enable I2C4 and UART1 at the same time. 191 - */ 192 - i2c4 { 193 - i2c4_default_mode: i2c_default { 194 - default_mux { 195 - function = "i2c4"; 196 - groups = "i2c4_b_1"; 197 - }; 198 - default_cfg1 { 199 - pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ 200 - ste,config = <&in_pu>; 201 - }; 202 - }; 203 - 204 - i2c4_sleep_mode: i2c_sleep { 205 - sleep_cfg1 { 206 - pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ 207 - ste,config = <&slpm_in_wkup_pdis>; 208 - }; 209 - }; 210 - }; 211 - 212 11 /* Settings for all SPI default and sleep states */ 213 12 spi2 { 214 13 spi2_default_mode: spi_default { ··· 65 266 sleep_cfg3 { 66 267 pins = "GPIO217_AH12"; /* CLK */ 67 268 ste,config = <&slpm_wkup_pdis>; 68 - }; 69 - }; 70 - }; 71 - 72 - /* Settings for all MMC/SD/SDIO default and sleep states */ 73 - sdi0 { 74 - /* This is the external SD card slot, 4 bits wide */ 75 - sdi0_default_mode: sdi0_default { 76 - default_mux { 77 - function = "mc0"; 78 - groups = "mc0_a_1"; 79 - }; 80 - default_cfg1 { 81 - pins = 82 - "GPIO18_AC2", /* CMDDIR */ 83 - "GPIO19_AC1", /* DAT0DIR */ 84 - "GPIO20_AB4"; /* DAT2DIR */ 85 - ste,config = <&out_hi>; 86 - }; 87 - default_cfg2 { 88 - pins = "GPIO22_AA3"; /* FBCLK */ 89 - ste,config = <&in_nopull>; 90 - }; 91 - default_cfg3 { 92 - pins = "GPIO23_AA4"; /* CLK */ 93 - ste,config = <&out_lo>; 94 - }; 95 - default_cfg4 { 96 - pins = 97 - "GPIO24_AB2", /* CMD */ 98 - "GPIO25_Y4", /* DAT0 */ 99 - "GPIO26_Y2", /* DAT1 */ 100 - "GPIO27_AA2", /* DAT2 */ 101 - "GPIO28_AA1"; /* DAT3 */ 102 - ste,config = <&in_pu>; 103 - }; 104 - }; 105 - 106 - sdi0_sleep_mode: sdi0_sleep { 107 - sleep_cfg1 { 108 - pins = 109 - "GPIO18_AC2", /* CMDDIR */ 110 - "GPIO19_AC1", /* DAT0DIR */ 111 - "GPIO20_AB4"; /* DAT2DIR */ 112 - ste,config = <&slpm_out_hi_wkup_pdis>; 113 - }; 114 - sleep_cfg2 { 115 - pins = 116 - "GPIO22_AA3", /* FBCLK */ 117 - "GPIO24_AB2", /* CMD */ 118 - "GPIO25_Y4", /* DAT0 */ 119 - "GPIO26_Y2", /* DAT1 */ 120 - "GPIO27_AA2", /* DAT2 */ 121 - "GPIO28_AA1"; /* DAT3 */ 122 - ste,config = <&slpm_in_wkup_pdis>; 123 - }; 124 - sleep_cfg3 { 125 - pins = "GPIO23_AA4"; /* CLK */ 126 - ste,config = <&slpm_out_lo_wkup_pdis>; 127 - }; 128 - }; 129 - }; 130 - 131 - sdi1 { 132 - /* This is the WLAN SDIO 4 bits wide */ 133 - sdi1_default_mode: sdi1_default { 134 - default_mux { 135 - function = "mc1"; 136 - groups = "mc1_a_1"; 137 - }; 138 - default_cfg1 { 139 - pins = "GPIO208_AH16"; /* CLK */ 140 - ste,config = <&out_lo>; 141 - }; 142 - default_cfg2 { 143 - pins = "GPIO209_AG15"; /* FBCLK */ 144 - ste,config = <&in_nopull>; 145 - }; 146 - default_cfg3 { 147 - pins = 148 - "GPIO210_AJ15", /* CMD */ 149 - "GPIO211_AG14", /* DAT0 */ 150 - "GPIO212_AF13", /* DAT1 */ 151 - "GPIO213_AG13", /* DAT2 */ 152 - "GPIO214_AH15"; /* DAT3 */ 153 - ste,config = <&in_pu>; 154 - }; 155 - }; 156 - 157 - sdi1_sleep_mode: sdi1_sleep { 158 - sleep_cfg1 { 159 - pins = "GPIO208_AH16"; /* CLK */ 160 - ste,config = <&slpm_out_lo_wkup_pdis>; 161 - }; 162 - sleep_cfg2 { 163 - pins = 164 - "GPIO209_AG15", /* FBCLK */ 165 - "GPIO210_AJ15", /* CMD */ 166 - "GPIO211_AG14", /* DAT0 */ 167 - "GPIO212_AF13", /* DAT1 */ 168 - "GPIO213_AG13", /* DAT2 */ 169 - "GPIO214_AH15"; /* DAT3 */ 170 - ste,config = <&slpm_in_wkup_pdis>; 171 - }; 172 - }; 173 - }; 174 - 175 - sdi2 { 176 - /* This is the eMMC 8 bits wide, usually PoP eMMC */ 177 - sdi2_default_mode: sdi2_default { 178 - default_mux { 179 - function = "mc2"; 180 - groups = "mc2_a_1"; 181 - }; 182 - default_cfg1 { 183 - pins = "GPIO128_A5"; /* CLK */ 184 - ste,config = <&out_lo>; 185 - }; 186 - default_cfg2 { 187 - pins = "GPIO130_C8"; /* FBCLK */ 188 - ste,config = <&in_nopull>; 189 - }; 190 - default_cfg3 { 191 - pins = 192 - "GPIO129_B4", /* CMD */ 193 - "GPIO131_A12", /* DAT0 */ 194 - "GPIO132_C10", /* DAT1 */ 195 - "GPIO133_B10", /* DAT2 */ 196 - "GPIO134_B9", /* DAT3 */ 197 - "GPIO135_A9", /* DAT4 */ 198 - "GPIO136_C7", /* DAT5 */ 199 - "GPIO137_A7", /* DAT6 */ 200 - "GPIO138_C5"; /* DAT7 */ 201 - ste,config = <&in_pu>; 202 - }; 203 - }; 204 - 205 - sdi2_sleep_mode: sdi2_sleep { 206 - sleep_cfg1 { 207 - pins = "GPIO128_A5"; /* CLK */ 208 - ste,config = <&out_lo_wkup_pdis>; 209 - }; 210 - sleep_cfg2 { 211 - pins = 212 - "GPIO130_C8", /* FBCLK */ 213 - "GPIO129_B4"; /* CMD */ 214 - ste,config = <&in_wkup_pdis_en>; 215 - }; 216 - sleep_cfg3 { 217 - pins = 218 - "GPIO131_A12", /* DAT0 */ 219 - "GPIO132_C10", /* DAT1 */ 220 - "GPIO133_B10", /* DAT2 */ 221 - "GPIO134_B9", /* DAT3 */ 222 - "GPIO135_A9", /* DAT4 */ 223 - "GPIO136_C7", /* DAT5 */ 224 - "GPIO137_A7", /* DAT6 */ 225 - "GPIO138_C5"; /* DAT7 */ 226 - ste,config = <&in_wkup_pdis>; 227 - }; 228 - }; 229 - }; 230 - 231 - sdi4 { 232 - /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */ 233 - sdi4_default_mode: sdi4_default { 234 - default_mux { 235 - function = "mc4"; 236 - groups = "mc4_a_1"; 237 - }; 238 - default_cfg1 { 239 - pins = "GPIO203_AE23"; /* CLK */ 240 - ste,config = <&out_lo>; 241 - }; 242 - default_cfg2 { 243 - pins = "GPIO202_AF25"; /* FBCLK */ 244 - ste,config = <&in_nopull>; 245 - }; 246 - default_cfg3 { 247 - pins = 248 - "GPIO201_AF24", /* CMD */ 249 - "GPIO200_AH26", /* DAT0 */ 250 - "GPIO199_AH23", /* DAT1 */ 251 - "GPIO198_AG25", /* DAT2 */ 252 - "GPIO197_AH24", /* DAT3 */ 253 - "GPIO207_AJ23", /* DAT4 */ 254 - "GPIO206_AG24", /* DAT5 */ 255 - "GPIO205_AG23", /* DAT6 */ 256 - "GPIO204_AF23"; /* DAT7 */ 257 - ste,config = <&in_pu>; 258 - }; 259 - }; 260 - 261 - sdi4_sleep_mode: sdi4_sleep { 262 - sleep_cfg1 { 263 - pins = "GPIO203_AE23"; /* CLK */ 264 - ste,config = <&out_lo_wkup_pdis>; 265 - }; 266 - sleep_cfg2 { 267 - pins = 268 - "GPIO202_AF25", /* FBCLK */ 269 - "GPIO201_AF24", /* CMD */ 270 - "GPIO200_AH26", /* DAT0 */ 271 - "GPIO199_AH23", /* DAT1 */ 272 - "GPIO198_AG25", /* DAT2 */ 273 - "GPIO197_AH24", /* DAT3 */ 274 - "GPIO207_AJ23", /* DAT4 */ 275 - "GPIO206_AG24", /* DAT5 */ 276 - "GPIO205_AG23", /* DAT6 */ 277 - "GPIO204_AF23"; /* DAT7 */ 278 - ste,config = <&slpm_in_wkup_pdis>; 279 - }; 280 - }; 281 - }; 282 - 283 - /* 284 - * Multi-rate serial ports (MSPs) - MSP3 output is internal and 285 - * cannot be muxed onto any pins. 286 - */ 287 - msp0 { 288 - msp0_default_mode: msp0_default { 289 - default_msp0_mux { 290 - function = "msp0"; 291 - groups = "msp0txrx_a_1", "msp0tfstck_a_1"; 292 - }; 293 - default_msp0_cfg { 294 - pins = 295 - "GPIO12_AC4", /* TXD */ 296 - "GPIO15_AC3", /* RXD */ 297 - "GPIO13_AF3", /* TFS */ 298 - "GPIO14_AE3"; /* TCK */ 299 - ste,config = <&in_nopull>; 300 - }; 301 - }; 302 - }; 303 - 304 - msp1 { 305 - msp1_default_mode: msp1_default { 306 - default_mux { 307 - function = "msp1"; 308 - groups = "msp1txrx_a_1", "msp1_a_1"; 309 - }; 310 - default_cfg1 { 311 - pins = "GPIO33_AF2"; 312 - ste,config = <&out_lo>; 313 - }; 314 - default_cfg2 { 315 - pins = 316 - "GPIO34_AE1", 317 - "GPIO35_AE2", 318 - "GPIO36_AG2"; 319 - ste,config = <&in_nopull>; 320 - }; 321 - 322 - }; 323 - }; 324 - 325 - msp2 { 326 - msp2_default_mode: msp2_default { 327 - /* MSP2 usually used for HDMI audio */ 328 - default_mux { 329 - function = "msp2"; 330 - groups = "msp2_a_1"; 331 - }; 332 - default_cfg1 { 333 - pins = 334 - "GPIO193_AH27", /* TXD */ 335 - "GPIO194_AF27", /* TCK */ 336 - "GPIO195_AG28"; /* TFS */ 337 - ste,config = <&in_pd>; 338 - }; 339 - default_cfg2 { 340 - pins = "GPIO196_AG26"; /* RXD */ 341 - ste,config = <&out_lo>; 342 - }; 343 - }; 344 - }; 345 - 346 - 347 - musb { 348 - musb_default_mode: musb_default { 349 - default_mux { 350 - function = "usb"; 351 - groups = "usb_a_1"; 352 - }; 353 - default_cfg1 { 354 - pins = 355 - "GPIO256_AF28", /* NXT */ 356 - "GPIO258_AD29", /* XCLK */ 357 - "GPIO259_AC29", /* DIR */ 358 - "GPIO260_AD28", /* DAT7 */ 359 - "GPIO261_AD26", /* DAT6 */ 360 - "GPIO262_AE26", /* DAT5 */ 361 - "GPIO263_AG29", /* DAT4 */ 362 - "GPIO264_AE27", /* DAT3 */ 363 - "GPIO265_AD27", /* DAT2 */ 364 - "GPIO266_AC28", /* DAT1 */ 365 - "GPIO267_AC27"; /* DAT0 */ 366 - ste,config = <&in_nopull>; 367 - }; 368 - default_cfg2 { 369 - pins = "GPIO257_AE29"; /* STP */ 370 - ste,config = <&out_hi>; 371 - }; 372 - }; 373 - 374 - musb_sleep_mode: musb_sleep { 375 - sleep_cfg1 { 376 - pins = 377 - "GPIO256_AF28", /* NXT */ 378 - "GPIO258_AD29", /* XCLK */ 379 - "GPIO259_AC29"; /* DIR */ 380 - ste,config = <&slpm_wkup_pdis_en>; 381 - }; 382 - sleep_cfg2 { 383 - pins = "GPIO257_AE29"; /* STP */ 384 - ste,config = <&slpm_out_hi_wkup_pdis>; 385 - }; 386 - sleep_cfg3 { 387 - pins = 388 - "GPIO260_AD28", /* DAT7 */ 389 - "GPIO261_AD26", /* DAT6 */ 390 - "GPIO262_AE26", /* DAT5 */ 391 - "GPIO263_AG29", /* DAT4 */ 392 - "GPIO264_AE27", /* DAT3 */ 393 - "GPIO265_AD27", /* DAT2 */ 394 - "GPIO266_AC28", /* DAT1 */ 395 - "GPIO267_AC27"; /* DAT0 */ 396 - ste,config = <&slpm_in_wkup_pdis_en>; 397 269 }; 398 270 }; 399 271 };