drm/i915/display: convert I915_STATE_WARN() to struct intel_display

+7 -8

drivers/gpu/drm/i915/display/g4x_dp.c

··· 170 170 { 171 171 struct intel_display *display = to_intel_display(intel_dp); 172 172 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 173 - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 174 173 bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN; 175 174 176 - I915_STATE_WARN(dev_priv, cur_state != state, 177 - "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n", 178 - dig_port->base.base.base.id, dig_port->base.base.name, 179 - str_on_off(state), str_on_off(cur_state)); 175 + INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 176 + "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n", 177 + dig_port->base.base.base.id, dig_port->base.base.name, 178 + str_on_off(state), str_on_off(cur_state)); 180 179 } 181 180 #define assert_dp_port_disabled(d) assert_dp_port((d), false) 182 181 ··· 184 185 struct intel_display *display = &dev_priv->display; 185 186 bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE; 186 187 187 - I915_STATE_WARN(dev_priv, cur_state != state, 188 - "eDP PLL state assertion failure (expected %s, current %s)\n", 189 - str_on_off(state), str_on_off(cur_state)); 188 + INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 189 + "eDP PLL state assertion failure (expected %s, current %s)\n", 190 + str_on_off(state), str_on_off(cur_state)); 190 191 } 191 192 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) 192 193 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)

+4 -4

drivers/gpu/drm/i915/display/intel_crtc.c

··· 36 36 37 37 static void assert_vblank_disabled(struct drm_crtc *crtc) 38 38 { 39 - struct drm_i915_private *i915 = to_i915(crtc->dev); 39 + struct intel_display *display = to_intel_display(crtc->dev); 40 40 41 - if (I915_STATE_WARN(i915, drm_crtc_vblank_get(crtc) == 0, 42 - "[CRTC:%d:%s] vblank assertion failure (expected off, current on)\n", 43 - crtc->base.id, crtc->name)) 41 + if (INTEL_DISPLAY_STATE_WARN(display, drm_crtc_vblank_get(crtc) == 0, 42 + "[CRTC:%d:%s] vblank assertion failure (expected off, current on)\n", 43 + crtc->base.id, crtc->name)) 44 44 drm_crtc_vblank_put(crtc); 45 45 } 46 46

+38 -38

drivers/gpu/drm/i915/display/intel_cx0_phy.c

··· 3279 3279 struct intel_encoder *encoder, 3280 3280 struct intel_c10pll_state *mpllb_hw_state) 3281 3281 { 3282 - struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3282 + struct intel_display *display = to_intel_display(state); 3283 3283 const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10; 3284 3284 int i; 3285 3285 3286 3286 for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { 3287 3287 u8 expected = mpllb_sw_state->pll[i]; 3288 3288 3289 - I915_STATE_WARN(i915, mpllb_hw_state->pll[i] != expected, 3290 - "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)", 3291 - crtc->base.base.id, crtc->base.name, i, 3292 - expected, mpllb_hw_state->pll[i]); 3289 + INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->pll[i] != expected, 3290 + "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)", 3291 + crtc->base.base.id, crtc->base.name, i, 3292 + expected, mpllb_hw_state->pll[i]); 3293 3293 } 3294 3294 3295 - I915_STATE_WARN(i915, mpllb_hw_state->tx != mpllb_sw_state->tx, 3296 - "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)", 3297 - crtc->base.base.id, crtc->base.name, 3298 - mpllb_sw_state->tx, mpllb_hw_state->tx); 3295 + INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->tx != mpllb_sw_state->tx, 3296 + "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)", 3297 + crtc->base.base.id, crtc->base.name, 3298 + mpllb_sw_state->tx, mpllb_hw_state->tx); 3299 3299 3300 - I915_STATE_WARN(i915, mpllb_hw_state->cmn != mpllb_sw_state->cmn, 3301 - "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)", 3302 - crtc->base.base.id, crtc->base.name, 3303 - mpllb_sw_state->cmn, mpllb_hw_state->cmn); 3300 + INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->cmn != mpllb_sw_state->cmn, 3301 + "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)", 3302 + crtc->base.base.id, crtc->base.name, 3303 + mpllb_sw_state->cmn, mpllb_hw_state->cmn); 3304 3304 } 3305 3305 3306 3306 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, ··· 3386 3386 struct intel_encoder *encoder, 3387 3387 struct intel_c20pll_state *mpll_hw_state) 3388 3388 { 3389 - struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3389 + struct intel_display *display = to_intel_display(state); 3390 3390 const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20; 3391 3391 bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state); 3392 3392 bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state); 3393 3393 int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state); 3394 3394 int i; 3395 3395 3396 - I915_STATE_WARN(i915, mpll_hw_state->clock != clock, 3397 - "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)", 3398 - crtc->base.base.id, crtc->base.name, 3399 - mpll_sw_state->clock, mpll_hw_state->clock); 3396 + INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->clock != clock, 3397 + "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)", 3398 + crtc->base.base.id, crtc->base.name, 3399 + mpll_sw_state->clock, mpll_hw_state->clock); 3400 3400 3401 - I915_STATE_WARN(i915, sw_use_mpllb != hw_use_mpllb, 3402 - "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)", 3403 - crtc->base.base.id, crtc->base.name, 3404 - sw_use_mpllb, hw_use_mpllb); 3401 + INTEL_DISPLAY_STATE_WARN(display, sw_use_mpllb != hw_use_mpllb, 3402 + "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)", 3403 + crtc->base.base.id, crtc->base.name, 3404 + sw_use_mpllb, hw_use_mpllb); 3405 3405 3406 3406 if (hw_use_mpllb) { 3407 3407 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) { 3408 - I915_STATE_WARN(i915, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i], 3409 - "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)", 3410 - crtc->base.base.id, crtc->base.name, i, 3411 - mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]); 3408 + INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i], 3409 + "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)", 3410 + crtc->base.base.id, crtc->base.name, i, 3411 + mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]); 3412 3412 } 3413 3413 } else { 3414 3414 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) { 3415 - I915_STATE_WARN(i915, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i], 3416 - "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)", 3417 - crtc->base.base.id, crtc->base.name, i, 3418 - mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]); 3415 + INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i], 3416 + "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)", 3417 + crtc->base.base.id, crtc->base.name, i, 3418 + mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]); 3419 3419 } 3420 3420 } 3421 3421 3422 3422 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) { 3423 - I915_STATE_WARN(i915, mpll_hw_state->tx[i] != mpll_sw_state->tx[i], 3424 - "[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)", 3425 - crtc->base.base.id, crtc->base.name, i, 3426 - mpll_sw_state->tx[i], mpll_hw_state->tx[i]); 3423 + INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->tx[i] != mpll_sw_state->tx[i], 3424 + "[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)", 3425 + crtc->base.base.id, crtc->base.name, i, 3426 + mpll_sw_state->tx[i], mpll_hw_state->tx[i]); 3427 3427 } 3428 3428 3429 3429 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) { 3430 - I915_STATE_WARN(i915, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i], 3431 - "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)", 3432 - crtc->base.base.id, crtc->base.name, i, 3433 - mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]); 3430 + INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i], 3431 + "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)", 3432 + crtc->base.base.id, crtc->base.name, i, 3433 + mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]); 3434 3434 } 3435 3435 } 3436 3436

+10 -9

drivers/gpu/drm/i915/display/intel_display.c

··· 422 422 void assert_transcoder(struct drm_i915_private *dev_priv, 423 423 enum transcoder cpu_transcoder, bool state) 424 424 { 425 + struct intel_display *display = &dev_priv->display; 425 426 bool cur_state; 426 427 enum intel_display_power_domain power_domain; 427 428 intel_wakeref_t wakeref; ··· 443 442 cur_state = false; 444 443 } 445 444 446 - I915_STATE_WARN(dev_priv, cur_state != state, 447 - "transcoder %s assertion failure (expected %s, current %s)\n", 448 - transcoder_name(cpu_transcoder), str_on_off(state), 449 - str_on_off(cur_state)); 445 + INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 446 + "transcoder %s assertion failure (expected %s, current %s)\n", 447 + transcoder_name(cpu_transcoder), str_on_off(state), 448 + str_on_off(cur_state)); 450 449 } 451 450 452 451 static void assert_plane(struct intel_plane *plane, bool state) 453 452 { 454 - struct drm_i915_private *i915 = to_i915(plane->base.dev); 453 + struct intel_display *display = to_intel_display(plane->base.dev); 455 454 enum pipe pipe; 456 455 bool cur_state; 457 456 458 457 cur_state = plane->get_hw_state(plane, &pipe); 459 458 460 - I915_STATE_WARN(i915, cur_state != state, 461 - "%s assertion failure (expected %s, current %s)\n", 462 - plane->base.name, str_on_off(state), 463 - str_on_off(cur_state)); 459 + INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 460 + "%s assertion failure (expected %s, current %s)\n", 461 + plane->base.name, str_on_off(state), 462 + str_on_off(cur_state)); 464 463 } 465 464 466 465 #define assert_plane_enabled(p) assert_plane(p, true)

+8 -9

drivers/gpu/drm/i915/display/intel_display.h

··· 585 585 bool assert_port_valid(struct drm_i915_private *i915, enum port port); 586 586 587 587 /* 588 - * Use I915_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw state sanity 589 - * checks to check for unexpected conditions which may not necessarily be a user 590 - * visible problem. This will either WARN() or DRM_ERROR() depending on the 591 - * verbose_state_checks module param, to enable distros and users to tailor 592 - * their preferred amount of i915 abrt spam. 588 + * Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw 589 + * state sanity checks to check for unexpected conditions which may not 590 + * necessarily be a user visible problem. This will either drm_WARN() or 591 + * drm_err() depending on the verbose_state_checks module param, to enable 592 + * distros and users to tailor their preferred amount of i915 abrt spam. 593 593 */ 594 - #define I915_STATE_WARN(__i915, condition, format...) ({ \ 595 - struct drm_device *drm = &(__i915)->drm; \ 594 + #define INTEL_DISPLAY_STATE_WARN(__display, condition, format...) ({ \ 596 595 int __ret_warn_on = !!(condition); \ 597 596 if (unlikely(__ret_warn_on)) \ 598 - if (!drm_WARN(drm, __i915->display.params.verbose_state_checks, format)) \ 599 - drm_err(drm, format); \ 597 + if (!drm_WARN((__display)->drm, (__display)->params.verbose_state_checks, format)) \ 598 + drm_err((__display)->drm, format); \ 600 599 unlikely(__ret_warn_on); \ 601 600 }) 602 601

+36 -35

drivers/gpu/drm/i915/display/intel_display_power.c

··· 1176 1176 1177 1177 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) 1178 1178 { 1179 + struct intel_display *display = &dev_priv->display; 1179 1180 struct intel_crtc *crtc; 1180 1181 1181 - for_each_intel_crtc(&dev_priv->drm, crtc) 1182 - I915_STATE_WARN(dev_priv, crtc->active, 1183 - "CRTC for pipe %c enabled\n", 1184 - pipe_name(crtc->pipe)); 1182 + for_each_intel_crtc(display->drm, crtc) 1183 + INTEL_DISPLAY_STATE_WARN(display, crtc->active, 1184 + "CRTC for pipe %c enabled\n", 1185 + pipe_name(crtc->pipe)); 1185 1186 1186 - I915_STATE_WARN(dev_priv, intel_de_read(dev_priv, HSW_PWR_WELL_CTL2), 1187 - "Display power well on\n"); 1188 - I915_STATE_WARN(dev_priv, 1189 - intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE, 1190 - "SPLL enabled\n"); 1191 - I915_STATE_WARN(dev_priv, 1192 - intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, 1193 - "WRPLL1 enabled\n"); 1194 - I915_STATE_WARN(dev_priv, 1195 - intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, 1196 - "WRPLL2 enabled\n"); 1197 - I915_STATE_WARN(dev_priv, 1198 - intel_de_read(dev_priv, PP_STATUS(dev_priv, 0)) & PP_ON, 1199 - "Panel power on\n"); 1200 - I915_STATE_WARN(dev_priv, 1201 - intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, 1202 - "CPU PWM1 enabled\n"); 1187 + INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2), 1188 + "Display power well on\n"); 1189 + INTEL_DISPLAY_STATE_WARN(display, 1190 + intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE, 1191 + "SPLL enabled\n"); 1192 + INTEL_DISPLAY_STATE_WARN(display, 1193 + intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, 1194 + "WRPLL1 enabled\n"); 1195 + INTEL_DISPLAY_STATE_WARN(display, 1196 + intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, 1197 + "WRPLL2 enabled\n"); 1198 + INTEL_DISPLAY_STATE_WARN(display, 1199 + intel_de_read(display, PP_STATUS(display, 0)) & PP_ON, 1200 + "Panel power on\n"); 1201 + INTEL_DISPLAY_STATE_WARN(display, 1202 + intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, 1203 + "CPU PWM1 enabled\n"); 1203 1204 if (IS_HASWELL(dev_priv)) 1204 - I915_STATE_WARN(dev_priv, 1205 - intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, 1206 - "CPU PWM2 enabled\n"); 1207 - I915_STATE_WARN(dev_priv, 1208 - intel_de_read(dev_priv, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, 1209 - "PCH PWM1 enabled\n"); 1210 - I915_STATE_WARN(dev_priv, 1211 - (intel_de_read(dev_priv, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 1212 - "Utility pin enabled in PWM mode\n"); 1213 - I915_STATE_WARN(dev_priv, 1214 - intel_de_read(dev_priv, PCH_GTC_CTL) & PCH_GTC_ENABLE, 1215 - "PCH GTC enabled\n"); 1205 + INTEL_DISPLAY_STATE_WARN(display, 1206 + intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, 1207 + "CPU PWM2 enabled\n"); 1208 + INTEL_DISPLAY_STATE_WARN(display, 1209 + intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, 1210 + "PCH PWM1 enabled\n"); 1211 + INTEL_DISPLAY_STATE_WARN(display, 1212 + (intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 1213 + "Utility pin enabled in PWM mode\n"); 1214 + INTEL_DISPLAY_STATE_WARN(display, 1215 + intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE, 1216 + "PCH GTC enabled\n"); 1216 1217 1217 1218 /* 1218 1219 * In theory we can still leave IRQs enabled, as long as only the HPD ··· 1221 1220 * gen-specific and since we only disable LCPLL after we fully disable 1222 1221 * the interrupts, the check below should be enough. 1223 1222 */ 1224 - I915_STATE_WARN(dev_priv, intel_irqs_enabled(dev_priv), 1225 - "IRQs enabled\n"); 1223 + INTEL_DISPLAY_STATE_WARN(display, intel_irqs_enabled(dev_priv), 1224 + "IRQs enabled\n"); 1226 1225 } 1227 1226 1228 1227 static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)

+5 -4

drivers/gpu/drm/i915/display/intel_dpll.c

··· 2331 2331 static void assert_pll(struct drm_i915_private *dev_priv, 2332 2332 enum pipe pipe, bool state) 2333 2333 { 2334 + struct intel_display *display = &dev_priv->display; 2334 2335 bool cur_state; 2335 2336 2336 - cur_state = intel_de_read(dev_priv, DPLL(dev_priv, pipe)) & DPLL_VCO_ENABLE; 2337 - I915_STATE_WARN(dev_priv, cur_state != state, 2338 - "PLL state assertion failure (expected %s, current %s)\n", 2339 - str_on_off(state), str_on_off(cur_state)); 2337 + cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE; 2338 + INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 2339 + "PLL state assertion failure (expected %s, current %s)\n", 2340 + str_on_off(state), str_on_off(cur_state)); 2340 2341 } 2341 2342 2342 2343 void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)

+47 -43

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

··· 173 173 struct intel_shared_dpll *pll, 174 174 bool state) 175 175 { 176 + struct intel_display *display = &i915->display; 176 177 bool cur_state; 177 178 struct intel_dpll_hw_state hw_state; 178 179 179 - if (drm_WARN(&i915->drm, !pll, 180 + if (drm_WARN(display->drm, !pll, 180 181 "asserting DPLL %s with no DPLL\n", str_on_off(state))) 181 182 return; 182 183 183 184 cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state); 184 - I915_STATE_WARN(i915, cur_state != state, 185 - "%s assertion failure (expected %s, current %s)\n", 186 - pll->info->name, str_on_off(state), 187 - str_on_off(cur_state)); 185 + INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 186 + "%s assertion failure (expected %s, current %s)\n", 187 + pll->info->name, str_on_off(state), 188 + str_on_off(cur_state)); 188 189 } 189 190 190 191 static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id) ··· 546 545 547 546 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915) 548 547 { 548 + struct intel_display *display = &i915->display; 549 549 u32 val; 550 550 bool enabled; 551 551 552 - val = intel_de_read(i915, PCH_DREF_CONTROL); 552 + val = intel_de_read(display, PCH_DREF_CONTROL); 553 553 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | 554 554 DREF_SUPERSPREAD_SOURCE_MASK)); 555 - I915_STATE_WARN(i915, !enabled, 556 - "PCH refclk assertion failure, should be active but is disabled\n"); 555 + INTEL_DISPLAY_STATE_WARN(display, !enabled, 556 + "PCH refclk assertion failure, should be active but is disabled\n"); 557 557 } 558 558 559 559 static void ibx_pch_dpll_enable(struct drm_i915_private *i915, ··· 4621 4619 struct intel_crtc *crtc, 4622 4620 const struct intel_crtc_state *new_crtc_state) 4623 4621 { 4622 + struct intel_display *display = &i915->display; 4624 4623 struct intel_dpll_hw_state dpll_hw_state = {}; 4625 4624 u8 pipe_mask; 4626 4625 bool active; ··· 4629 4626 active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state); 4630 4627 4631 4628 if (!pll->info->always_on) { 4632 - I915_STATE_WARN(i915, !pll->on && pll->active_mask, 4633 - "%s: pll in active use but not on in sw tracking\n", 4634 - pll->info->name); 4635 - I915_STATE_WARN(i915, pll->on && !pll->active_mask, 4636 - "%s: pll is on but not used by any active pipe\n", 4637 - pll->info->name); 4638 - I915_STATE_WARN(i915, pll->on != active, 4639 - "%s: pll on state mismatch (expected %i, found %i)\n", 4640 - pll->info->name, pll->on, active); 4629 + INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask, 4630 + "%s: pll in active use but not on in sw tracking\n", 4631 + pll->info->name); 4632 + INTEL_DISPLAY_STATE_WARN(display, pll->on && !pll->active_mask, 4633 + "%s: pll is on but not used by any active pipe\n", 4634 + pll->info->name); 4635 + INTEL_DISPLAY_STATE_WARN(display, pll->on != active, 4636 + "%s: pll on state mismatch (expected %i, found %i)\n", 4637 + pll->info->name, pll->on, active); 4641 4638 } 4642 4639 4643 4640 if (!crtc) { 4644 - I915_STATE_WARN(i915, 4645 - pll->active_mask & ~pll->state.pipe_mask, 4646 - "%s: more active pll users than references: 0x%x vs 0x%x\n", 4647 - pll->info->name, pll->active_mask, pll->state.pipe_mask); 4641 + INTEL_DISPLAY_STATE_WARN(display, 4642 + pll->active_mask & ~pll->state.pipe_mask, 4643 + "%s: more active pll users than references: 0x%x vs 0x%x\n", 4644 + pll->info->name, pll->active_mask, pll->state.pipe_mask); 4648 4645 4649 4646 return; 4650 4647 } ··· 4652 4649 pipe_mask = BIT(crtc->pipe); 4653 4650 4654 4651 if (new_crtc_state->hw.active) 4655 - I915_STATE_WARN(i915, !(pll->active_mask & pipe_mask), 4656 - "%s: pll active mismatch (expected pipe %c in active mask 0x%x)\n", 4657 - pll->info->name, pipe_name(crtc->pipe), pll->active_mask); 4652 + INTEL_DISPLAY_STATE_WARN(display, !(pll->active_mask & pipe_mask), 4653 + "%s: pll active mismatch (expected pipe %c in active mask 0x%x)\n", 4654 + pll->info->name, pipe_name(crtc->pipe), pll->active_mask); 4658 4655 else 4659 - I915_STATE_WARN(i915, pll->active_mask & pipe_mask, 4660 - "%s: pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", 4661 - pll->info->name, pipe_name(crtc->pipe), pll->active_mask); 4656 + INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask, 4657 + "%s: pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", 4658 + pll->info->name, pipe_name(crtc->pipe), pll->active_mask); 4662 4659 4663 - I915_STATE_WARN(i915, !(pll->state.pipe_mask & pipe_mask), 4664 - "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", 4665 - pll->info->name, pipe_mask, pll->state.pipe_mask); 4660 + INTEL_DISPLAY_STATE_WARN(display, !(pll->state.pipe_mask & pipe_mask), 4661 + "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", 4662 + pll->info->name, pipe_mask, pll->state.pipe_mask); 4666 4663 4667 - I915_STATE_WARN(i915, 4668 - pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state, 4669 - sizeof(dpll_hw_state)), 4670 - "%s: pll hw state mismatch\n", 4671 - pll->info->name); 4664 + INTEL_DISPLAY_STATE_WARN(display, 4665 + pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state, 4666 + sizeof(dpll_hw_state)), 4667 + "%s: pll hw state mismatch\n", 4668 + pll->info->name); 4672 4669 } 4673 4670 4674 4671 static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll, ··· 4681 4678 void intel_shared_dpll_state_verify(struct intel_atomic_state *state, 4682 4679 struct intel_crtc *crtc) 4683 4680 { 4681 + struct intel_display *display = to_intel_display(state); 4684 4682 struct drm_i915_private *i915 = to_i915(state->base.dev); 4685 4683 const struct intel_crtc_state *old_crtc_state = 4686 4684 intel_atomic_get_old_crtc_state(state, crtc); ··· 4697 4693 u8 pipe_mask = BIT(crtc->pipe); 4698 4694 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; 4699 4695 4700 - I915_STATE_WARN(i915, pll->active_mask & pipe_mask, 4701 - "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", 4702 - pll->info->name, pipe_name(crtc->pipe), pll->active_mask); 4696 + INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask, 4697 + "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", 4698 + pll->info->name, pipe_name(crtc->pipe), pll->active_mask); 4703 4699 4704 4700 /* TC ports have both MG/TC and TBT PLL referenced simultaneously */ 4705 - I915_STATE_WARN(i915, !has_alt_port_dpll(old_crtc_state->shared_dpll, 4706 - new_crtc_state->shared_dpll) && 4707 - pll->state.pipe_mask & pipe_mask, 4708 - "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n", 4709 - pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask); 4701 + INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->shared_dpll, 4702 + new_crtc_state->shared_dpll) && 4703 + pll->state.pipe_mask & pipe_mask, 4704 + "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n", 4705 + pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask); 4710 4706 } 4711 4707 } 4712 4708

+23 -19

drivers/gpu/drm/i915/display/intel_fdi.c

··· 26 26 static void assert_fdi_tx(struct drm_i915_private *dev_priv, 27 27 enum pipe pipe, bool state) 28 28 { 29 + struct intel_display *display = &dev_priv->display; 29 30 bool cur_state; 30 31 31 - if (HAS_DDI(dev_priv)) { 32 + if (HAS_DDI(display)) { 32 33 /* 33 34 * DDI does not have a specific FDI_TX register. 34 35 * ··· 37 36 * so pipe->transcoder cast is fine here. 38 37 */ 39 38 enum transcoder cpu_transcoder = (enum transcoder)pipe; 40 - cur_state = intel_de_read(dev_priv, 41 - TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; 39 + cur_state = intel_de_read(display, 40 + TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; 42 41 } else { 43 - cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; 42 + cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; 44 43 } 45 - I915_STATE_WARN(dev_priv, cur_state != state, 46 - "FDI TX state assertion failure (expected %s, current %s)\n", 47 - str_on_off(state), str_on_off(cur_state)); 44 + INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 45 + "FDI TX state assertion failure (expected %s, current %s)\n", 46 + str_on_off(state), str_on_off(cur_state)); 48 47 } 49 48 50 49 void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe) ··· 60 59 static void assert_fdi_rx(struct drm_i915_private *dev_priv, 61 60 enum pipe pipe, bool state) 62 61 { 62 + struct intel_display *display = &dev_priv->display; 63 63 bool cur_state; 64 64 65 - cur_state = intel_de_read(dev_priv, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE; 66 - I915_STATE_WARN(dev_priv, cur_state != state, 67 - "FDI RX state assertion failure (expected %s, current %s)\n", 68 - str_on_off(state), str_on_off(cur_state)); 65 + cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE; 66 + INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 67 + "FDI RX state assertion failure (expected %s, current %s)\n", 68 + str_on_off(state), str_on_off(cur_state)); 69 69 } 70 70 71 71 void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe) ··· 82 80 void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915, 83 81 enum pipe pipe) 84 82 { 83 + struct intel_display *display = &i915->display; 85 84 bool cur_state; 86 85 87 86 /* ILK FDI PLL is always enabled */ ··· 90 87 return; 91 88 92 89 /* On Haswell, DDI ports are responsible for the FDI PLL setup */ 93 - if (HAS_DDI(i915)) 90 + if (HAS_DDI(display)) 94 91 return; 95 92 96 - cur_state = intel_de_read(i915, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE; 97 - I915_STATE_WARN(i915, !cur_state, 98 - "FDI TX PLL assertion failure, should be active but is disabled\n"); 93 + cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE; 94 + INTEL_DISPLAY_STATE_WARN(display, !cur_state, 95 + "FDI TX PLL assertion failure, should be active but is disabled\n"); 99 96 } 100 97 101 98 static void assert_fdi_rx_pll(struct drm_i915_private *i915, 102 99 enum pipe pipe, bool state) 103 100 { 101 + struct intel_display *display = &i915->display; 104 102 bool cur_state; 105 103 106 - cur_state = intel_de_read(i915, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE; 107 - I915_STATE_WARN(i915, cur_state != state, 108 - "FDI RX PLL assertion failure (expected %s, current %s)\n", 109 - str_on_off(state), str_on_off(cur_state)); 104 + cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE; 105 + INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 106 + "FDI RX PLL assertion failure (expected %s, current %s)\n", 107 + str_on_off(state), str_on_off(cur_state)); 110 108 } 111 109 112 110 void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)

+46 -43

drivers/gpu/drm/i915/display/intel_modeset_verify.c

··· 27 27 const struct drm_connector_state *conn_state) 28 28 { 29 29 struct intel_connector *connector = to_intel_connector(conn_state->connector); 30 + struct intel_display *display = to_intel_display(connector); 30 31 struct drm_i915_private *i915 = to_i915(connector->base.dev); 31 32 32 33 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", ··· 36 35 if (connector->get_hw_state(connector)) { 37 36 struct intel_encoder *encoder = intel_attached_encoder(connector); 38 37 39 - I915_STATE_WARN(i915, !crtc_state, 40 - "connector enabled without attached crtc\n"); 38 + INTEL_DISPLAY_STATE_WARN(display, !crtc_state, 39 + "connector enabled without attached crtc\n"); 41 40 42 41 if (!crtc_state) 43 42 return; 44 43 45 - I915_STATE_WARN(i915, !crtc_state->hw.active, 46 - "connector is active, but attached crtc isn't\n"); 44 + INTEL_DISPLAY_STATE_WARN(display, !crtc_state->hw.active, 45 + "connector is active, but attached crtc isn't\n"); 47 46 48 47 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) 49 48 return; 50 49 51 - I915_STATE_WARN(i915, 52 - conn_state->best_encoder != &encoder->base, 53 - "atomic encoder doesn't match attached encoder\n"); 50 + INTEL_DISPLAY_STATE_WARN(display, 51 + conn_state->best_encoder != &encoder->base, 52 + "atomic encoder doesn't match attached encoder\n"); 54 53 55 - I915_STATE_WARN(i915, conn_state->crtc != encoder->base.crtc, 56 - "attached encoder crtc differs from connector crtc\n"); 54 + INTEL_DISPLAY_STATE_WARN(display, conn_state->crtc != encoder->base.crtc, 55 + "attached encoder crtc differs from connector crtc\n"); 57 56 } else { 58 - I915_STATE_WARN(i915, crtc_state && crtc_state->hw.active, 59 - "attached crtc is active, but connector isn't\n"); 60 - I915_STATE_WARN(i915, !crtc_state && conn_state->best_encoder, 61 - "best encoder set without crtc!\n"); 57 + INTEL_DISPLAY_STATE_WARN(display, crtc_state && crtc_state->hw.active, 58 + "attached crtc is active, but connector isn't\n"); 59 + INTEL_DISPLAY_STATE_WARN(display, !crtc_state && conn_state->best_encoder, 60 + "best encoder set without crtc!\n"); 62 61 } 63 62 } 64 63 ··· 66 65 verify_connector_state(struct intel_atomic_state *state, 67 66 struct intel_crtc *crtc) 68 67 { 68 + struct intel_display *display = to_intel_display(state); 69 69 struct drm_connector *connector; 70 70 const struct drm_connector_state *new_conn_state; 71 71 int i; ··· 83 81 84 82 intel_connector_verify_state(crtc_state, new_conn_state); 85 83 86 - I915_STATE_WARN(to_i915(connector->dev), new_conn_state->best_encoder != encoder, 87 - "connector's atomic encoder doesn't match legacy encoder\n"); 84 + INTEL_DISPLAY_STATE_WARN(display, new_conn_state->best_encoder != encoder, 85 + "connector's atomic encoder doesn't match legacy encoder\n"); 88 86 } 89 87 } 90 88 ··· 111 109 static void 112 110 verify_encoder_state(struct intel_atomic_state *state) 113 111 { 112 + struct intel_display *display = to_intel_display(state); 114 113 struct drm_i915_private *i915 = to_i915(state->base.dev); 115 114 struct intel_encoder *encoder; 116 115 struct drm_connector *connector; ··· 137 134 found = true; 138 135 enabled = true; 139 136 140 - I915_STATE_WARN(i915, 141 - new_conn_state->crtc != encoder->base.crtc, 142 - "connector's crtc doesn't match encoder crtc\n"); 137 + INTEL_DISPLAY_STATE_WARN(display, 138 + new_conn_state->crtc != encoder->base.crtc, 139 + "connector's crtc doesn't match encoder crtc\n"); 143 140 } 144 141 145 142 if (!found) 146 143 continue; 147 144 148 - I915_STATE_WARN(i915, !!encoder->base.crtc != enabled, 149 - "encoder's enabled state mismatch (expected %i, found %i)\n", 150 - !!encoder->base.crtc, enabled); 145 + INTEL_DISPLAY_STATE_WARN(display, !!encoder->base.crtc != enabled, 146 + "encoder's enabled state mismatch (expected %i, found %i)\n", 147 + !!encoder->base.crtc, enabled); 151 148 152 149 if (!encoder->base.crtc) { 153 150 bool active; 154 151 155 152 active = encoder->get_hw_state(encoder, &pipe); 156 - I915_STATE_WARN(i915, active, 157 - "encoder detached but still enabled on pipe %c.\n", 158 - pipe_name(pipe)); 153 + INTEL_DISPLAY_STATE_WARN(display, active, 154 + "encoder detached but still enabled on pipe %c.\n", 155 + pipe_name(pipe)); 159 156 } 160 157 } 161 158 } ··· 164 161 verify_crtc_state(struct intel_atomic_state *state, 165 162 struct intel_crtc *crtc) 166 163 { 167 - struct drm_device *dev = crtc->base.dev; 168 - struct drm_i915_private *i915 = to_i915(dev); 164 + struct intel_display *display = to_intel_display(state); 165 + struct drm_i915_private *i915 = to_i915(display->drm); 169 166 const struct intel_crtc_state *sw_crtc_state = 170 167 intel_atomic_get_new_crtc_state(state, crtc); 171 168 struct intel_crtc_state *hw_crtc_state; ··· 176 173 if (!hw_crtc_state) 177 174 return; 178 175 179 - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, 176 + drm_dbg_kms(display->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, 180 177 crtc->base.name); 181 178 182 179 hw_crtc_state->hw.enable = sw_crtc_state->hw.enable; ··· 187 184 if (IS_I830(i915) && hw_crtc_state->hw.active) 188 185 hw_crtc_state->hw.active = sw_crtc_state->hw.active; 189 186 190 - I915_STATE_WARN(i915, 191 - sw_crtc_state->hw.active != hw_crtc_state->hw.active, 192 - "crtc active state doesn't match with hw state (expected %i, found %i)\n", 193 - sw_crtc_state->hw.active, hw_crtc_state->hw.active); 187 + INTEL_DISPLAY_STATE_WARN(display, 188 + sw_crtc_state->hw.active != hw_crtc_state->hw.active, 189 + "crtc active state doesn't match with hw state (expected %i, found %i)\n", 190 + sw_crtc_state->hw.active, hw_crtc_state->hw.active); 194 191 195 - I915_STATE_WARN(i915, crtc->active != sw_crtc_state->hw.active, 196 - "transitional active state does not match atomic hw state (expected %i, found %i)\n", 197 - sw_crtc_state->hw.active, crtc->active); 192 + INTEL_DISPLAY_STATE_WARN(display, crtc->active != sw_crtc_state->hw.active, 193 + "transitional active state does not match atomic hw state (expected %i, found %i)\n", 194 + sw_crtc_state->hw.active, crtc->active); 198 195 199 196 primary_crtc = intel_primary_crtc(sw_crtc_state); 200 197 201 - for_each_encoder_on_crtc(dev, &primary_crtc->base, encoder) { 198 + for_each_encoder_on_crtc(display->drm, &primary_crtc->base, encoder) { 202 199 enum pipe pipe; 203 200 bool active; 204 201 205 202 active = encoder->get_hw_state(encoder, &pipe); 206 - I915_STATE_WARN(i915, active != sw_crtc_state->hw.active, 207 - "[ENCODER:%i] active %i with crtc active %i\n", 208 - encoder->base.base.id, active, 209 - sw_crtc_state->hw.active); 203 + INTEL_DISPLAY_STATE_WARN(display, active != sw_crtc_state->hw.active, 204 + "[ENCODER:%i] active %i with crtc active %i\n", 205 + encoder->base.base.id, active, 206 + sw_crtc_state->hw.active); 210 207 211 - I915_STATE_WARN(i915, active && primary_crtc->pipe != pipe, 212 - "Encoder connected to wrong pipe %c\n", 213 - pipe_name(pipe)); 208 + INTEL_DISPLAY_STATE_WARN(display, active && primary_crtc->pipe != pipe, 209 + "Encoder connected to wrong pipe %c\n", 210 + pipe_name(pipe)); 214 211 215 212 if (active) 216 213 intel_encoder_get_config(encoder, hw_crtc_state); ··· 223 220 224 221 if (!intel_pipe_config_compare(sw_crtc_state, 225 222 hw_crtc_state, false)) { 226 - I915_STATE_WARN(i915, 1, "pipe state doesn't match!\n"); 223 + INTEL_DISPLAY_STATE_WARN(display, 1, "pipe state doesn't match!\n"); 227 224 intel_crtc_state_dump(hw_crtc_state, NULL, "hw state"); 228 225 intel_crtc_state_dump(sw_crtc_state, NULL, "sw state"); 229 226 }

+30 -26

drivers/gpu/drm/i915/display/intel_pch_display.c

··· 39 39 enum pipe pipe, enum port port, 40 40 i915_reg_t dp_reg) 41 41 { 42 + struct intel_display *display = &dev_priv->display; 42 43 enum pipe port_pipe; 43 44 bool state; 44 45 45 46 state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe); 46 47 47 - I915_STATE_WARN(dev_priv, state && port_pipe == pipe, 48 - "PCH DP %c enabled on transcoder %c, should be disabled\n", 49 - port_name(port), pipe_name(pipe)); 48 + INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe, 49 + "PCH DP %c enabled on transcoder %c, should be disabled\n", 50 + port_name(port), pipe_name(pipe)); 50 51 51 - I915_STATE_WARN(dev_priv, 52 - HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 53 - "IBX PCH DP %c still using transcoder B\n", 54 - port_name(port)); 52 + INTEL_DISPLAY_STATE_WARN(display, 53 + HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 54 + "IBX PCH DP %c still using transcoder B\n", 55 + port_name(port)); 55 56 } 56 57 57 58 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 58 59 enum pipe pipe, enum port port, 59 60 i915_reg_t hdmi_reg) 60 61 { 62 + struct intel_display *display = &dev_priv->display; 61 63 enum pipe port_pipe; 62 64 bool state; 63 65 64 66 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe); 65 67 66 - I915_STATE_WARN(dev_priv, state && port_pipe == pipe, 67 - "PCH HDMI %c enabled on transcoder %c, should be disabled\n", 68 - port_name(port), pipe_name(pipe)); 68 + INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe, 69 + "PCH HDMI %c enabled on transcoder %c, should be disabled\n", 70 + port_name(port), pipe_name(pipe)); 69 71 70 - I915_STATE_WARN(dev_priv, 71 - HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 72 - "IBX PCH HDMI %c still using transcoder B\n", 73 - port_name(port)); 72 + INTEL_DISPLAY_STATE_WARN(display, 73 + HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 74 + "IBX PCH HDMI %c still using transcoder B\n", 75 + port_name(port)); 74 76 } 75 77 76 78 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 77 79 enum pipe pipe) 78 80 { 81 + struct intel_display *display = &dev_priv->display; 79 82 enum pipe port_pipe; 80 83 81 84 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); 82 85 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C); 83 86 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D); 84 87 85 - I915_STATE_WARN(dev_priv, 86 - intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && port_pipe == pipe, 87 - "PCH VGA enabled on transcoder %c, should be disabled\n", 88 - pipe_name(pipe)); 88 + INTEL_DISPLAY_STATE_WARN(display, 89 + intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && port_pipe == pipe, 90 + "PCH VGA enabled on transcoder %c, should be disabled\n", 91 + pipe_name(pipe)); 89 92 90 - I915_STATE_WARN(dev_priv, 91 - intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && port_pipe == pipe, 92 - "PCH LVDS enabled on transcoder %c, should be disabled\n", 93 - pipe_name(pipe)); 93 + INTEL_DISPLAY_STATE_WARN(display, 94 + intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && port_pipe == pipe, 95 + "PCH LVDS enabled on transcoder %c, should be disabled\n", 96 + pipe_name(pipe)); 94 97 95 98 /* PCH SDVOB multiplex with HDMIB */ 96 99 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); ··· 104 101 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 105 102 enum pipe pipe) 106 103 { 104 + struct intel_display *display = &dev_priv->display; 107 105 u32 val; 108 106 bool enabled; 109 107 110 - val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)); 108 + val = intel_de_read(display, PCH_TRANSCONF(pipe)); 111 109 enabled = !!(val & TRANS_ENABLE); 112 - I915_STATE_WARN(dev_priv, enabled, 113 - "transcoder assertion failed, should be off on pipe %c but is still active\n", 114 - pipe_name(pipe)); 110 + INTEL_DISPLAY_STATE_WARN(display, enabled, 111 + "transcoder assertion failed, should be off on pipe %c but is still active\n", 112 + pipe_name(pipe)); 115 113 } 116 114 117 115 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,

+12 -14

drivers/gpu/drm/i915/display/intel_pps.c

··· 809 809 void intel_pps_vdd_on(struct intel_dp *intel_dp) 810 810 { 811 811 struct intel_display *display = to_intel_display(intel_dp); 812 - struct drm_i915_private *i915 = to_i915(display->drm); 813 812 intel_wakeref_t wakeref; 814 813 bool vdd; 815 814 ··· 818 819 vdd = false; 819 820 with_intel_pps_lock(intel_dp, wakeref) 820 821 vdd = intel_pps_vdd_on_unlocked(intel_dp); 821 - I915_STATE_WARN(i915, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n", 822 - dp_to_dig_port(intel_dp)->base.base.base.id, 823 - dp_to_dig_port(intel_dp)->base.base.name, 824 - pps_name(intel_dp)); 822 + INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n", 823 + dp_to_dig_port(intel_dp)->base.base.base.id, 824 + dp_to_dig_port(intel_dp)->base.base.name, 825 + pps_name(intel_dp)); 825 826 } 826 827 827 828 static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp) ··· 928 929 void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync) 929 930 { 930 931 struct intel_display *display = to_intel_display(intel_dp); 931 - struct drm_i915_private *dev_priv = to_i915(display->drm); 932 932 933 933 lockdep_assert_held(&display->pps.mutex); 934 934 935 935 if (!intel_dp_is_edp(intel_dp)) 936 936 return; 937 937 938 - I915_STATE_WARN(dev_priv, !intel_dp->pps.want_panel_vdd, 939 - "[ENCODER:%d:%s] %s VDD not forced on", 940 - dp_to_dig_port(intel_dp)->base.base.base.id, 941 - dp_to_dig_port(intel_dp)->base.base.name, 942 - pps_name(intel_dp)); 938 + INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd, 939 + "[ENCODER:%d:%s] %s VDD not forced on", 940 + dp_to_dig_port(intel_dp)->base.base.base.id, 941 + dp_to_dig_port(intel_dp)->base.base.name, 942 + pps_name(intel_dp)); 943 943 944 944 intel_dp->pps.want_panel_vdd = false; 945 945 ··· 1876 1878 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) 1877 1879 locked = false; 1878 1880 1879 - I915_STATE_WARN(dev_priv, panel_pipe == pipe && locked, 1880 - "panel assertion failure, pipe %c regs locked\n", 1881 - pipe_name(pipe)); 1881 + INTEL_DISPLAY_STATE_WARN(display, panel_pipe == pipe && locked, 1882 + "panel assertion failure, pipe %c regs locked\n", 1883 + pipe_name(pipe)); 1882 1884 }

+6 -5

drivers/gpu/drm/i915/display/intel_snps_phy.c

··· 1997 1997 void intel_mpllb_state_verify(struct intel_atomic_state *state, 1998 1998 struct intel_crtc *crtc) 1999 1999 { 2000 + struct intel_display *display = to_intel_display(state); 2000 2001 struct drm_i915_private *i915 = to_i915(state->base.dev); 2001 2002 const struct intel_crtc_state *new_crtc_state = 2002 2003 intel_atomic_get_new_crtc_state(state, crtc); ··· 2020 2019 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state); 2021 2020 2022 2021 #define MPLLB_CHECK(__name) \ 2023 - I915_STATE_WARN(i915, mpllb_sw_state->__name != mpllb_hw_state.__name, \ 2024 - "[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \ 2025 - crtc->base.base.id, crtc->base.name, \ 2026 - __stringify(__name), \ 2027 - mpllb_sw_state->__name, mpllb_hw_state.__name) 2022 + INTEL_DISPLAY_STATE_WARN(display, mpllb_sw_state->__name != mpllb_hw_state.__name, \ 2023 + "[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \ 2024 + crtc->base.base.id, crtc->base.name, \ 2025 + __stringify(__name), \ 2026 + mpllb_sw_state->__name, mpllb_hw_state.__name) 2028 2027 2029 2028 MPLLB_CHECK(mpllb_cp); 2030 2029 MPLLB_CHECK(mpllb_div);

+4 -3

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

··· 592 592 593 593 static void assert_dsi_pll(struct drm_i915_private *i915, bool state) 594 594 { 595 + struct intel_display *display = &i915->display; 595 596 bool cur_state; 596 597 597 598 vlv_cck_get(i915); 598 599 cur_state = vlv_cck_read(i915, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN; 599 600 vlv_cck_put(i915); 600 601 601 - I915_STATE_WARN(i915, cur_state != state, 602 - "DSI PLL state assertion failure (expected %s, current %s)\n", 603 - str_on_off(state), str_on_off(cur_state)); 602 + INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 603 + "DSI PLL state assertion failure (expected %s, current %s)\n", 604 + str_on_off(state), str_on_off(cur_state)); 604 605 } 605 606 606 607 void assert_dsi_pll_enabled(struct drm_i915_private *i915)