Merge tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Pull some checkpatch silencers from Heiko Stuebner:

Fix quite some checkpatch warnings in the newly added
rk3399 header and also in the clock code itself.

* tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix checkpatch warning in core code
clk: rockchip: drop unnecessary header comment
clk: rockchip: reign in some overly long lines in the rk3399 controller
clk: rockchip: fix checkpatch errors in rk3399 dt-binding header

Stephen Boyd 10 years ago 0f05db65 e708b383

+110 -83

5 changed files

expand all

drivers

clk

rockchip

clk-mmc-phase.c

clk-rk3399.c

clk.c

clk.h

include

dt-bindings

clock

rk3399-cru.h

+2 -1

drivers/clk/rockchip/clk-mmc-phase.c

··· 123 123 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 124 124 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 125 125 raw_value |= nineties; 126 - writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), mmc_clock->reg); 126 + writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), 127 + mmc_clock->reg); 127 128 128 129 pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n", 129 130 clk_hw_get_name(hw), degrees, delay_num,

+71 -48

drivers/clk/rockchip/clk-rk3399.c

··· 117 117 "gpll_aclk_cci_src", 118 118 "npll_aclk_cci_src", 119 119 "vpll_aclk_cci_src" }; 120 - PNAME(mux_cci_trace_p) = { "cpll_cci_trace", "gpll_cci_trace" }; 121 - PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", "npll_cs"}; 122 - PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" }; 120 + PNAME(mux_cci_trace_p) = { "cpll_cci_trace", 121 + "gpll_cci_trace" }; 122 + PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", 123 + "npll_cs"}; 124 + PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src", 125 + "gpll_aclk_perihp_src" }; 123 126 124 127 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; 125 128 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; 126 129 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" }; 127 130 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" }; 128 131 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; 129 - PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll", "ppll" }; 130 - PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll", "xin24m" }; 131 - PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll", "clk_usbphy_480m" }; 132 - PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll", "npll", "upll" }; 133 - PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", "upll", "xin24m" }; 134 - PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" }; 132 + PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll", 133 + "ppll" }; 134 + PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll", 135 + "xin24m" }; 136 + PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll", 137 + "clk_usbphy_480m" }; 138 + PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll", 139 + "npll", "upll" }; 140 + PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", 141 + "upll", "xin24m" }; 142 + PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", 143 + "ppll", "upll", "xin24m" }; 135 144 136 145 PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; 137 - PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", "npll" }; 138 - PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", "xin24m" }; 146 + PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", 147 + "npll" }; 148 + PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", 149 + "xin24m" }; 139 150 140 - PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", "dclk_vop0_frac" }; 141 - PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", "dclk_vop1_frac" }; 151 + PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", 152 + "dclk_vop0_frac" }; 153 + PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", 154 + "dclk_vop1_frac" }; 142 155 143 - PNAME(mux_clk_cif_p) = { "clk_cifout_div", "xin24m" }; 156 + PNAME(mux_clk_cif_p) = { "clk_cifout_div", "xin24m" }; 144 157 145 - PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" }; 146 - PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" }; 147 - PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k", "cpll", "gpll" }; 148 - PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru", "clk_pcie_core_phy" }; 158 + PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" }; 159 + PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" }; 160 + PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k", 161 + "cpll", "gpll" }; 162 + PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru", 163 + "clk_pcie_core_phy" }; 149 164 150 - PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src" }; 165 + PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src", 166 + "gpll_aclk_emmc_src" }; 151 167 152 - PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" }; 168 + PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src", 169 + "gpll_aclk_perilp0_src" }; 153 170 154 - PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src", "gpll_fclk_cm0s_src" }; 171 + PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src", 172 + "gpll_fclk_cm0s_src" }; 155 173 156 - PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" }; 174 + PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src", 175 + "gpll_hclk_perilp1_src" }; 157 176 158 - PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" }; 159 - PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" }; 177 + PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" }; 178 + PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" }; 160 179 161 - PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src", "clk_usbphy1_480m_src" }; 162 - PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src", "gpll_aclk_gmac_src" }; 163 - PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" }; 164 - PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac", 165 - "clkin_i2s", "xin12m" }; 166 - PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", 167 - "clkin_i2s", "xin12m" }; 168 - PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", 169 - "clkin_i2s", "xin12m" }; 170 - PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", 171 - "clkin_i2s", "xin12m" }; 172 - PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1", "clk_i2s2" }; 173 - PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" }; 180 + PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src", 181 + "clk_usbphy1_480m_src" }; 182 + PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src", 183 + "gpll_aclk_gmac_src" }; 184 + PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" }; 185 + PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac", 186 + "clkin_i2s", "xin12m" }; 187 + PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", 188 + "clkin_i2s", "xin12m" }; 189 + PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", 190 + "clkin_i2s", "xin12m" }; 191 + PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", 192 + "clkin_i2s", "xin12m" }; 193 + PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1", 194 + "clk_i2s2" }; 195 + PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" }; 174 196 175 - PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 176 - PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 177 - PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 178 - PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; 197 + PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 198 + PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 199 + PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 200 + PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; 179 201 180 202 /* PMU CRU parents */ 181 - PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" }; 182 - PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; 183 - PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" }; 184 - PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" }; 185 - PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac", "xin24m" }; 186 - PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" }; 203 + PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" }; 204 + PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; 205 + PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" }; 206 + PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" }; 207 + PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac", 208 + "xin24m" }; 209 + PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" }; 187 210 188 211 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { 189 212 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0), ··· 1553 1530 ARRAY_SIZE(rk3399_clk_pmu_branches)); 1554 1531 1555 1532 rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks, 1556 - ARRAY_SIZE(rk3399_pmucru_critical_clocks)); 1533 + ARRAY_SIZE(rk3399_pmucru_critical_clocks)); 1557 1534 1558 1535 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0), 1559 1536 ROCKCHIP_SOFTRST_HIWORD_MASK);

+24 -20

drivers/clk/rockchip/clk.c

··· 42 42 * sometimes without one of those components. 43 43 */ 44 44 static struct clk *rockchip_clk_register_branch(const char *name, 45 - const char *const *parent_names, u8 num_parents, void __iomem *base, 45 + const char *const *parent_names, u8 num_parents, 46 + void __iomem *base, 46 47 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, 47 48 u8 div_shift, u8 div_width, u8 div_flags, 48 49 struct clk_div_table *div_table, int gate_offset, ··· 140 139 pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n", 141 140 __func__, event, ndata->old_rate, ndata->new_rate); 142 141 if (event == PRE_RATE_CHANGE) { 143 - frac->rate_change_idx = frac->mux_ops->get_parent(&frac_mux->hw); 142 + frac->rate_change_idx = 143 + frac->mux_ops->get_parent(&frac_mux->hw); 144 144 if (frac->rate_change_idx != frac->mux_frac_idx) { 145 - frac->mux_ops->set_parent(&frac_mux->hw, frac->mux_frac_idx); 145 + frac->mux_ops->set_parent(&frac_mux->hw, 146 + frac->mux_frac_idx); 146 147 frac->rate_change_remuxed = 1; 147 148 } 148 149 } else if (event == POST_RATE_CHANGE) { ··· 155 152 * reaches the mux itself. 156 153 */ 157 154 if (frac->rate_change_remuxed) { 158 - frac->mux_ops->set_parent(&frac_mux->hw, frac->rate_change_idx); 155 + frac->mux_ops->set_parent(&frac_mux->hw, 156 + frac->rate_change_idx); 159 157 frac->rate_change_remuxed = 0; 160 158 } 161 159 } ··· 330 326 int i; 331 327 332 328 ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL); 333 - if (!ctx) { 334 - pr_err("%s: Could not allocate clock provider context\n", 335 - __func__); 329 + if (!ctx) 336 330 return ERR_PTR(-ENOMEM); 337 - } 338 331 339 332 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); 340 - if (!clk_table) { 341 - pr_err("%s: Could not allocate clock lookup table\n", 342 - __func__); 333 + if (!clk_table) 343 334 goto err_free; 344 - } 345 335 346 336 for (i = 0; i < nr_clks; ++i) 347 337 clk_table[i] = ERR_PTR(-ENOENT); ··· 365 367 struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx) 366 368 { 367 369 if (IS_ERR(ctx->grf)) 368 - ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, "rockchip,grf"); 370 + ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, 371 + "rockchip,grf"); 369 372 return ctx->grf; 370 373 } 371 374 ··· 426 427 if (list->div_table) 427 428 clk = clk_register_divider_table(NULL, 428 429 list->name, list->parent_names[0], 429 - flags, ctx->reg_base + list->muxdiv_offset, 430 + flags, 431 + ctx->reg_base + list->muxdiv_offset, 430 432 list->div_shift, list->div_width, 431 433 list->div_flags, list->div_table, 432 434 &ctx->lock); ··· 441 441 case branch_fraction_divider: 442 442 clk = rockchip_clk_register_frac_branch(ctx, list->name, 443 443 list->parent_names, list->num_parents, 444 - ctx->reg_base, list->muxdiv_offset, list->div_flags, 444 + ctx->reg_base, list->muxdiv_offset, 445 + list->div_flags, 445 446 list->gate_offset, list->gate_shift, 446 447 list->gate_flags, flags, list->child, 447 448 &ctx->lock); ··· 458 457 case branch_composite: 459 458 clk = rockchip_clk_register_branch(list->name, 460 459 list->parent_names, list->num_parents, 461 - ctx->reg_base, list->muxdiv_offset, list->mux_shift, 460 + ctx->reg_base, list->muxdiv_offset, 461 + list->mux_shift, 462 462 list->mux_width, list->mux_flags, 463 463 list->div_shift, list->div_width, 464 464 list->div_flags, list->div_table, ··· 519 517 struct clk *clk; 520 518 521 519 clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents, 522 - reg_data, rates, nrates, ctx->reg_base, 523 - &ctx->lock); 520 + reg_data, rates, nrates, 521 + ctx->reg_base, &ctx->lock); 524 522 if (IS_ERR(clk)) { 525 523 pr_err("%s: failed to register clock %s: %ld\n", 526 524 __func__, name, PTR_ERR(clk)); ··· 562 560 .priority = 128, 563 561 }; 564 562 565 - void __init rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, 566 - unsigned int reg, void (*cb)(void)) 563 + void __init 564 + rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, 565 + unsigned int reg, 566 + void (*cb)(void)) 567 567 { 568 568 int ret; 569 569

+1 -2

drivers/clk/rockchip/clk.h

··· 34 34 #define HIWORD_UPDATE(val, mask, shift) \ 35 35 ((val) << (shift) | (mask) << ((shift) + 16)) 36 36 37 - /* register positions shared by RK2928, RK3036, RK3066, RK3188, RK3228, RK3399 */ 38 37 #define RK2928_PLL_CON(x) ((x) * 0x4) 39 38 #define RK2928_MODE_CON 0x40 40 39 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) ··· 252 253 }; 253 254 254 255 /** 255 - * struct rockchip_cpuclk_reg_data - describes register offsets and masks of the cpuclock 256 + * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock 256 257 * @core_reg: register offset of the core settings register 257 258 * @div_core_shift: core divider offset used to divide the pll value 258 259 * @div_core_mask: core divider mask

+12 -12

include/dt-bindings/clock/rk3399-cru.h

··· 136 136 #define DCLK_VOP1_DIV 183 137 137 #define DCLK_M0_PERILP 184 138 138 139 - #define FCLK_CM0S 190 139 + #define FCLK_CM0S 190 140 140 141 141 /* aclk gates */ 142 142 #define ACLK_PERIHP 192 ··· 207 207 #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 208 208 #define ACLK_ADB400M_PD_CORE_L 258 209 209 #define ACLK_ADB400M_PD_CORE_B 259 210 - #define ACLK_PERF_CORE_L 260 211 - #define ACLK_PERF_CORE_B 261 212 - #define ACLK_GIC_PRE 262 213 - #define ACLK_VOP0_PRE 263 214 - #define ACLK_VOP1_PRE 264 210 + #define ACLK_PERF_CORE_L 260 211 + #define ACLK_PERF_CORE_B 261 212 + #define ACLK_GIC_PRE 262 213 + #define ACLK_VOP0_PRE 263 214 + #define ACLK_VOP1_PRE 264 215 215 216 216 /* pclk gates */ 217 217 #define PCLK_PERIHP 320 ··· 279 279 #define PCLK_EFUSE1024S 382 280 280 #define PCLK_PMU_INTR_ARB 383 281 281 #define PCLK_MAILBOX0 384 282 - #define PCLK_USBPHY_MUX_G 385 283 - #define PCLK_UPHY0_TCPHY_G 386 284 - #define PCLK_UPHY0_TCPD_G 387 285 - #define PCLK_UPHY1_TCPHY_G 388 286 - #define PCLK_UPHY1_TCPD_G 389 287 - #define PCLK_ALIVE 390 282 + #define PCLK_USBPHY_MUX_G 385 283 + #define PCLK_UPHY0_TCPHY_G 386 284 + #define PCLK_UPHY0_TCPD_G 387 285 + #define PCLK_UPHY1_TCPHY_G 388 286 + #define PCLK_UPHY1_TCPD_G 389 287 + #define PCLK_ALIVE 390 288 288 289 289 /* hclk gates */ 290 290 #define HCLK_PERIHP 448