blackfin: fix wrong CTS inversion

The Blackfin serial headers were inverting the CTS value leading to wrong
handling of the CTS line which broke CTS/RTS handling completely.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

authored by Sonic Zhang and committed by Linus Torvalds 0ecf24ef 23198fda

+6 -6
+1 -1
arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
··· 53 53 #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 54 54 #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 55 55 56 - #define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin)) 56 + #define UART_GET_CTS(x) gpio_get_value(x->cts_pin) 57 57 #define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) 58 58 #define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) 59 59 #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
+1 -1
arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
··· 53 53 #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 54 54 #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 55 55 56 - #define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin)) 56 + #define UART_GET_CTS(x) gpio_get_value(x->cts_pin) 57 57 #define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) 58 58 #define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) 59 59 #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
+1 -1
arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
··· 53 53 #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 54 54 #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 55 55 56 - #define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin)) 56 + #define UART_GET_CTS(x) gpio_get_value(x->cts_pin) 57 57 #define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) 58 58 #define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) 59 59 #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
+1 -1
arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
··· 53 53 #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 54 54 #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 55 55 56 - #define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin)) 56 + #define UART_GET_CTS(x) gpio_get_value(x->cts_pin) 57 57 #define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) 58 58 #define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) 59 59 #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
+1 -1
arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
··· 53 53 #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 54 54 #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 55 55 56 - #define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin)) 56 + #define UART_GET_CTS(x) gpio_get_value(x->cts_pin) 57 57 #define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) 58 58 #define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) 59 59 #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
+1 -1
arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
··· 53 53 #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 54 54 #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 55 55 56 - #define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin)) 56 + #define UART_GET_CTS(x) gpio_get_value(x->cts_pin) 57 57 #define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) 58 58 #define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) 59 59 #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)