ide: use PIO/MMIO operations directly where possible (v2)

-2

drivers/ide/h8300/ide-h8300.c

··· 81 81 hwif->OUTSW = mm_outsw; 82 82 hwif->INW = mm_inw; 83 83 hwif->INSW = mm_insw; 84 - hwif->OUTL = NULL; 85 - hwif->INL = NULL; 86 84 hwif->OUTSL = NULL; 87 85 hwif->INSL = NULL; 88 86 }

+4 -1

drivers/ide/ide-dma.c

··· 565 565 } 566 566 567 567 /* PRD table */ 568 - hwif->OUTL(hwif->dmatable_dma, hwif->dma_prdtable); 568 + if (hwif->mmio == 2) 569 + writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable); 570 + else 571 + outl(hwif->dmatable_dma, hwif->dma_prdtable); 569 572 570 573 /* specify r/w */ 571 574 hwif->OUTB(reading, hwif->dma_command);

-24

drivers/ide/ide-iops.c

··· 49 49 insw(port, addr, count); 50 50 } 51 51 52 - static u32 ide_inl (unsigned long port) 53 - { 54 - return (u32) inl(port); 55 - } 56 - 57 52 static void ide_insl (unsigned long port, void *addr, u32 count) 58 53 { 59 54 insl(port, addr, count); ··· 74 79 outsw(port, addr, count); 75 80 } 76 81 77 - static void ide_outl (u32 val, unsigned long port) 78 - { 79 - outl(val, port); 80 - } 81 - 82 82 static void ide_outsl (unsigned long port, void *addr, u32 count) 83 83 { 84 84 outsl(port, addr, count); ··· 84 94 hwif->OUTB = ide_outb; 85 95 hwif->OUTBSYNC = ide_outbsync; 86 96 hwif->OUTW = ide_outw; 87 - hwif->OUTL = ide_outl; 88 97 hwif->OUTSW = ide_outsw; 89 98 hwif->OUTSL = ide_outsl; 90 99 hwif->INB = ide_inb; 91 100 hwif->INW = ide_inw; 92 - hwif->INL = ide_inl; 93 101 hwif->INSW = ide_insw; 94 102 hwif->INSL = ide_insl; 95 103 } ··· 109 121 static void ide_mm_insw (unsigned long port, void *addr, u32 count) 110 122 { 111 123 __ide_mm_insw((void __iomem *) port, addr, count); 112 - } 113 - 114 - static u32 ide_mm_inl (unsigned long port) 115 - { 116 - return (u32) readl((void __iomem *) port); 117 124 } 118 125 119 126 static void ide_mm_insl (unsigned long port, void *addr, u32 count) ··· 136 153 __ide_mm_outsw((void __iomem *) port, addr, count); 137 154 } 138 155 139 - static void ide_mm_outl (u32 value, unsigned long port) 140 - { 141 - writel(value, (void __iomem *) port); 142 - } 143 - 144 156 static void ide_mm_outsl (unsigned long port, void *addr, u32 count) 145 157 { 146 158 __ide_mm_outsl((void __iomem *) port, addr, count); ··· 148 170 this one is controller specific! */ 149 171 hwif->OUTBSYNC = ide_mm_outbsync; 150 172 hwif->OUTW = ide_mm_outw; 151 - hwif->OUTL = ide_mm_outl; 152 173 hwif->OUTSW = ide_mm_outsw; 153 174 hwif->OUTSL = ide_mm_outsl; 154 175 hwif->INB = ide_mm_inb; 155 176 hwif->INW = ide_mm_inw; 156 - hwif->INL = ide_mm_inl; 157 177 hwif->INSW = ide_mm_insw; 158 178 hwif->INSL = ide_mm_insl; 159 179 }

-2

drivers/ide/ide.c

··· 518 518 hwif->OUTB = tmp_hwif->OUTB; 519 519 hwif->OUTBSYNC = tmp_hwif->OUTBSYNC; 520 520 hwif->OUTW = tmp_hwif->OUTW; 521 - hwif->OUTL = tmp_hwif->OUTL; 522 521 hwif->OUTSW = tmp_hwif->OUTSW; 523 522 hwif->OUTSL = tmp_hwif->OUTSL; 524 523 525 524 hwif->INB = tmp_hwif->INB; 526 525 hwif->INW = tmp_hwif->INW; 527 - hwif->INL = tmp_hwif->INL; 528 526 hwif->INSW = tmp_hwif->INSW; 529 527 hwif->INSL = tmp_hwif->INSL; 530 528

+7 -7

drivers/ide/legacy/ht6560b.c

··· 143 143 current_timing = timing; 144 144 if (drive->media != ide_disk || !drive->present) 145 145 select |= HT_PREFETCH_MODE; 146 - (void) HWIF(drive)->INB(HT_CONFIG_PORT); 147 - (void) HWIF(drive)->INB(HT_CONFIG_PORT); 148 - (void) HWIF(drive)->INB(HT_CONFIG_PORT); 149 - (void) HWIF(drive)->INB(HT_CONFIG_PORT); 150 - HWIF(drive)->OUTB(select, HT_CONFIG_PORT); 146 + (void)inb(HT_CONFIG_PORT); 147 + (void)inb(HT_CONFIG_PORT); 148 + (void)inb(HT_CONFIG_PORT); 149 + (void)inb(HT_CONFIG_PORT); 150 + outb(select, HT_CONFIG_PORT); 151 151 /* 152 152 * Set timing for this drive: 153 153 */ 154 - HWIF(drive)->OUTB(timing, IDE_SELECT_REG); 155 - (void) HWIF(drive)->INB(IDE_STATUS_REG); 154 + outb(timing, IDE_SELECT_REG); 155 + (void)inb(IDE_STATUS_REG); 156 156 #ifdef DEBUG 157 157 printk("ht6560b: %s: select=%#x timing=%#x\n", 158 158 drive->name, select, timing);

+3 -3

drivers/ide/pci/aec62xx.c

··· 94 94 switch(hwif->pci_dev->device) { 95 95 case PCI_DEVICE_ID_ARTOP_ATP865: 96 96 case PCI_DEVICE_ID_ARTOP_ATP865R: 97 - mode = (hwif->INB(((hwif->channel) ? 98 - hwif->mate->dma_status : 99 - hwif->dma_status)) & 0x10) ? 4 : 3; 97 + mode = (inb(hwif->channel ? 98 + hwif->mate->dma_status : 99 + hwif->dma_status) & 0x10) ? 4 : 3; 100 100 break; 101 101 case PCI_DEVICE_ID_ARTOP_ATP860: 102 102 case PCI_DEVICE_ID_ARTOP_ATP860R:

+2 -2

drivers/ide/pci/alim15x3.c

··· 852 852 { 853 853 if (m5229_revision < 0x20) 854 854 return; 855 - if (!(hwif->channel)) 856 - hwif->OUTB(hwif->INB(dmabase+2) & 0x60, dmabase+2); 855 + if (!hwif->channel) 856 + outb(inb(dmabase + 2) & 0x60, dmabase + 2); 857 857 ide_setup_dma(hwif, dmabase, 8); 858 858 } 859 859

+9 -9

drivers/ide/pci/cmd64x.c

··· 507 507 508 508 drive->waiting_for_dma = 0; 509 509 /* read DMA command state */ 510 - dma_cmd = hwif->INB(hwif->dma_command); 510 + dma_cmd = inb(hwif->dma_command); 511 511 /* stop DMA */ 512 - hwif->OUTB((dma_cmd & ~1), hwif->dma_command); 512 + outb(dma_cmd & ~1, hwif->dma_command); 513 513 /* get DMA status */ 514 - dma_stat = hwif->INB(hwif->dma_status); 514 + dma_stat = inb(hwif->dma_status); 515 515 /* clear the INTR & ERROR bits */ 516 - hwif->OUTB(dma_stat|6, hwif->dma_status); 516 + outb(dma_stat | 6, hwif->dma_status); 517 517 if (cmd64x_alt_dma_status(dev)) { 518 518 u8 dma_intr = 0; 519 519 u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 : ··· 535 535 struct pci_dev *dev = hwif->pci_dev; 536 536 u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 : 537 537 MRDMODE_INTR_CH0; 538 - u8 dma_stat = hwif->INB(hwif->dma_status); 538 + u8 dma_stat = inb(hwif->dma_status); 539 539 540 540 (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat); 541 541 #ifdef DEBUG ··· 565 565 566 566 drive->waiting_for_dma = 0; 567 567 /* get DMA status */ 568 - dma_stat = hwif->INB(hwif->dma_status); 568 + dma_stat = inb(hwif->dma_status); 569 569 /* read DMA command state */ 570 - dma_cmd = hwif->INB(hwif->dma_command); 570 + dma_cmd = inb(hwif->dma_command); 571 571 /* stop DMA */ 572 - hwif->OUTB((dma_cmd & ~1), hwif->dma_command); 572 + outb(dma_cmd & ~1, hwif->dma_command); 573 573 /* clear the INTR & ERROR bits */ 574 - hwif->OUTB(dma_stat|6, hwif->dma_status); 574 + outb(dma_stat | 6, hwif->dma_status); 575 575 /* and free any DMA resources */ 576 576 ide_destroy_dmatable(drive); 577 577 /* verify good DMA status */

+11 -11

drivers/ide/pci/cs5530.c

··· 81 81 82 82 pio = ide_get_best_pio_mode(drive, pio, 4, NULL); 83 83 if (!cs5530_set_xfer_mode(drive, modes[pio])) { 84 - format = (hwif->INL(basereg+4) >> 31) & 1; 85 - hwif->OUTL(cs5530_pio_timings[format][pio], 84 + format = (inl(basereg + 4) >> 31) & 1; 85 + outl(cs5530_pio_timings[format][pio], 86 86 basereg+(drive->select.b.unit<<3)); 87 87 } 88 88 } ··· 183 183 break; 184 184 } 185 185 basereg = CS5530_BASEREG(hwif); 186 - reg = hwif->INL(basereg+4); /* get drive0 config register */ 186 + reg = inl(basereg + 4); /* get drive0 config register */ 187 187 timings |= reg & 0x80000000; /* preserve PIO format bit */ 188 188 if (unit == 0) { /* are we configuring drive0? */ 189 - hwif->OUTL(timings, basereg+4); /* write drive0 config register */ 189 + outl(timings, basereg + 4); /* write drive0 config register */ 190 190 } else { 191 191 if (timings & 0x00100000) 192 192 reg |= 0x00100000; /* enable UDMA timings for both drives */ 193 193 else 194 194 reg &= ~0x00100000; /* disable UDMA timings for both drives */ 195 - hwif->OUTL(reg, basereg+4); /* write drive0 config register */ 196 - hwif->OUTL(timings, basereg+12); /* write drive1 config register */ 195 + outl(reg, basereg + 4); /* write drive0 config register */ 196 + outl(timings, basereg + 12); /* write drive1 config register */ 197 197 } 198 198 199 199 /* ··· 315 315 316 316 hwif->tuneproc = &cs5530_tuneproc; 317 317 basereg = CS5530_BASEREG(hwif); 318 - d0_timings = hwif->INL(basereg+0); 318 + d0_timings = inl(basereg + 0); 319 319 if (CS5530_BAD_PIO(d0_timings)) { 320 320 /* PIO timings not initialized? */ 321 - hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+0); 321 + outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0); 322 322 if (!hwif->drives[0].autotune) 323 323 hwif->drives[0].autotune = 1; 324 324 /* needs autotuning later */ 325 325 } 326 - if (CS5530_BAD_PIO(hwif->INL(basereg+8))) { 327 - /* PIO timings not initialized? */ 328 - hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+8); 326 + if (CS5530_BAD_PIO(inl(basereg + 8))) { 327 + /* PIO timings not initialized? */ 328 + outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8); 329 329 if (!hwif->drives[1].autotune) 330 330 hwif->drives[1].autotune = 1; 331 331 /* needs autotuning later */

+6 -6

drivers/ide/pci/cy82c693.c

··· 197 197 #if CY82C693_DEBUG_LOGS 198 198 /* for debug let's show the previous values */ 199 199 200 - HWIF(drive)->OUTB(index, CY82_INDEX_PORT); 201 - data = HWIF(drive)->INB(CY82_DATA_PORT); 200 + outb(index, CY82_INDEX_PORT); 201 + data = inb(CY82_DATA_PORT); 202 202 203 203 printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n", 204 204 drive->name, HWIF(drive)->channel, drive->select.b.unit, ··· 207 207 208 208 data = (u8)mode|(u8)(single<<2); 209 209 210 - HWIF(drive)->OUTB(index, CY82_INDEX_PORT); 211 - HWIF(drive)->OUTB(data, CY82_DATA_PORT); 210 + outb(index, CY82_INDEX_PORT); 211 + outb(data, CY82_DATA_PORT); 212 212 213 213 #if CY82C693_DEBUG_INFO 214 214 printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n", ··· 227 227 */ 228 228 229 229 data = BUSMASTER_TIMEOUT; 230 - HWIF(drive)->OUTB(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT); 231 - HWIF(drive)->OUTB(data, CY82_DATA_PORT); 230 + outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT); 231 + outb(data, CY82_DATA_PORT); 232 232 233 233 #if CY82C693_DEBUG_INFO 234 234 printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",

+1 -1

drivers/ide/pci/hpt366.c

··· 836 836 return 0; 837 837 } 838 838 839 - dma_stat = hwif->INB(hwif->dma_status); 839 + dma_stat = inb(hwif->dma_status); 840 840 /* return 1 if INTR asserted */ 841 841 if (dma_stat & 4) 842 842 return 1;

+5 -5

drivers/ide/pci/ns87415.c

··· 166 166 /* get dma command mode */ 167 167 dma_cmd = hwif->INB(hwif->dma_command); 168 168 /* stop DMA */ 169 - hwif->OUTB(dma_cmd & ~1, hwif->dma_command); 169 + outb(dma_cmd & ~1, hwif->dma_command); 170 170 /* from ERRATA: clear the INTR & ERROR bits */ 171 171 dma_cmd = hwif->INB(hwif->dma_command); 172 - hwif->OUTB(dma_cmd|6, hwif->dma_command); 172 + outb(dma_cmd | 6, hwif->dma_command); 173 173 /* and free any DMA resources */ 174 174 ide_destroy_dmatable(drive); 175 175 /* verify good DMA status */ ··· 243 243 * to SELECT_DRIVE() properly during first probe_hwif(). 244 244 */ 245 245 timeout = 10000; 246 - hwif->OUTB(12, hwif->io_ports[IDE_CONTROL_OFFSET]); 246 + outb(12, hwif->io_ports[IDE_CONTROL_OFFSET]); 247 247 udelay(10); 248 - hwif->OUTB(8, hwif->io_ports[IDE_CONTROL_OFFSET]); 248 + outb(8, hwif->io_ports[IDE_CONTROL_OFFSET]); 249 249 do { 250 250 udelay(50); 251 251 stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); ··· 263 263 if (!hwif->dma_base) 264 264 return; 265 265 266 - hwif->OUTB(0x60, hwif->dma_status); 266 + outb(0x60, hwif->dma_status); 267 267 hwif->dma_setup = &ns87415_ide_dma_setup; 268 268 hwif->ide_dma_check = &ns87415_ide_dma_check; 269 269 hwif->ide_dma_end = &ns87415_ide_dma_end;

+32 -31

drivers/ide/pci/opti621.c

··· 176 176 return ((time*bus_speed+999)/1000); 177 177 } 178 178 179 - static void write_reg(ide_hwif_t *hwif, u8 value, int reg) 180 179 /* Write value to register reg, base of register 181 180 * is at reg_base (0x1f0 primary, 0x170 secondary, 182 181 * if not changed by PCI configuration). 183 182 * This is from setupvic.exe program. 184 183 */ 184 + static void write_reg(u8 value, int reg) 185 185 { 186 - hwif->INW(reg_base+1); 187 - hwif->INW(reg_base+1); 188 - hwif->OUTB(3, reg_base+2); 189 - hwif->OUTB(value, reg_base+reg); 190 - hwif->OUTB(0x83, reg_base+2); 186 + inw(reg_base + 1); 187 + inw(reg_base + 1); 188 + outb(3, reg_base + 2); 189 + outb(value, reg_base + reg); 190 + outb(0x83, reg_base + 2); 191 191 } 192 192 193 - static u8 read_reg(ide_hwif_t *hwif, int reg) 194 193 /* Read value from register reg, base of register 195 194 * is at reg_base (0x1f0 primary, 0x170 secondary, 196 195 * if not changed by PCI configuration). 197 196 * This is from setupvic.exe program. 198 197 */ 198 + static u8 read_reg(int reg) 199 199 { 200 200 u8 ret = 0; 201 201 202 - hwif->INW(reg_base+1); 203 - hwif->INW(reg_base+1); 204 - hwif->OUTB(3, reg_base+2); 205 - ret = hwif->INB(reg_base+reg); 206 - hwif->OUTB(0x83, reg_base+2); 202 + inw(reg_base + 1); 203 + inw(reg_base + 1); 204 + outb(3, reg_base + 2); 205 + ret = inb(reg_base + reg); 206 + outb(0x83, reg_base + 2); 207 + 207 208 return ret; 208 209 } 209 210 ··· 287 286 reg_base = hwif->io_ports[IDE_DATA_OFFSET]; 288 287 289 288 /* allow Register-B */ 290 - hwif->OUTB(0xc0, reg_base+CNTRL_REG); 289 + outb(0xc0, reg_base + CNTRL_REG); 291 290 /* hmm, setupvic.exe does this ;-) */ 292 - hwif->OUTB(0xff, reg_base+5); 291 + outb(0xff, reg_base + 5); 293 292 /* if reads 0xff, adapter not exist? */ 294 - (void) hwif->INB(reg_base+CNTRL_REG); 293 + (void)inb(reg_base + CNTRL_REG); 295 294 /* if reads 0xc0, no interface exist? */ 296 - read_reg(hwif, CNTRL_REG); 295 + read_reg(CNTRL_REG); 297 296 /* read version, probably 0 */ 298 - read_reg(hwif, STRAP_REG); 297 + read_reg(STRAP_REG); 299 298 300 299 /* program primary drive */ 301 - /* select Index-0 for Register-A */ 302 - write_reg(hwif, 0, MISC_REG); 303 - /* set read cycle timings */ 304 - write_reg(hwif, cycle1, READ_REG); 305 - /* set write cycle timings */ 306 - write_reg(hwif, cycle1, WRITE_REG); 300 + /* select Index-0 for Register-A */ 301 + write_reg(0, MISC_REG); 302 + /* set read cycle timings */ 303 + write_reg(cycle1, READ_REG); 304 + /* set write cycle timings */ 305 + write_reg(cycle1, WRITE_REG); 307 306 308 307 /* program secondary drive */ 309 - /* select Index-1 for Register-B */ 310 - write_reg(hwif, 1, MISC_REG); 311 - /* set read cycle timings */ 312 - write_reg(hwif, cycle2, READ_REG); 313 - /* set write cycle timings */ 314 - write_reg(hwif, cycle2, WRITE_REG); 308 + /* select Index-1 for Register-B */ 309 + write_reg(1, MISC_REG); 310 + /* set read cycle timings */ 311 + write_reg(cycle2, READ_REG); 312 + /* set write cycle timings */ 313 + write_reg(cycle2, WRITE_REG); 315 314 316 315 /* use Register-A for drive 0 */ 317 316 /* use Register-B for drive 1 */ 318 - write_reg(hwif, 0x85, CNTRL_REG); 317 + write_reg(0x85, CNTRL_REG); 319 318 320 319 /* set address setup, DRDY timings, */ 321 320 /* and read prefetch for both drives */ 322 - write_reg(hwif, misc, MISC_REG); 321 + write_reg(misc, MISC_REG); 323 322 324 323 spin_unlock_irqrestore(&ide_lock, flags); 325 324 }

+4 -4

drivers/ide/pci/pdc202xx_new.c

··· 101 101 { 102 102 u8 value; 103 103 104 - hwif->OUTB(index, hwif->dma_vendor1); 105 - value = hwif->INB(hwif->dma_vendor3); 104 + outb(index, hwif->dma_vendor1); 105 + value = inb(hwif->dma_vendor3); 106 106 107 107 DBG("index[%02X] value[%02X]\n", index, value); 108 108 return value; ··· 115 115 */ 116 116 static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value) 117 117 { 118 - hwif->OUTB(index, hwif->dma_vendor1); 119 - hwif->OUTB(value, hwif->dma_vendor3); 118 + outb(index, hwif->dma_vendor1); 119 + outb(value, hwif->dma_vendor3); 120 120 DBG("index[%02X] value[%02X]\n", index, value); 121 121 } 122 122

+20 -21

drivers/ide/pci/pdc202xx_old.c

··· 240 240 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif) 241 241 { 242 242 unsigned long clock_reg = hwif->dma_master + 0x11; 243 - u8 clock = hwif->INB(clock_reg); 243 + u8 clock = inb(clock_reg); 244 244 245 - hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg); 245 + outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg); 246 246 } 247 247 248 248 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif) 249 249 { 250 250 unsigned long clock_reg = hwif->dma_master + 0x11; 251 - u8 clock = hwif->INB(clock_reg); 251 + u8 clock = inb(clock_reg); 252 252 253 - hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); 253 + outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); 254 254 } 255 255 256 256 static int config_chipset_for_dma (ide_drive_t *drive) ··· 357 357 unsigned long high_16 = hwif->dma_master; 358 358 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); 359 359 u32 word_count = 0; 360 - u8 clock = hwif->INB(high_16 + 0x11); 360 + u8 clock = inb(high_16 + 0x11); 361 361 362 - hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11); 362 + outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11); 363 363 word_count = (rq->nr_sectors << 8); 364 364 word_count = (rq_data_dir(rq) == READ) ? 365 365 word_count | 0x05000000 : 366 366 word_count | 0x06000000; 367 - hwif->OUTL(word_count, atapi_reg); 367 + outl(word_count, atapi_reg); 368 368 } 369 369 ide_dma_start(drive); 370 370 } ··· 377 377 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); 378 378 u8 clock = 0; 379 379 380 - hwif->OUTL(0, atapi_reg); /* zero out extra */ 381 - clock = hwif->INB(high_16 + 0x11); 382 - hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11); 380 + outl(0, atapi_reg); /* zero out extra */ 381 + clock = inb(high_16 + 0x11); 382 + outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11); 383 383 } 384 384 if (drive->current_speed > XFER_UDMA_2) 385 385 pdc_old_disable_66MHz_clock(drive->hwif); ··· 390 390 { 391 391 ide_hwif_t *hwif = HWIF(drive); 392 392 unsigned long high_16 = hwif->dma_master; 393 - u8 dma_stat = hwif->INB(hwif->dma_status); 394 - u8 sc1d = hwif->INB((high_16 + 0x001d)); 393 + u8 dma_stat = inb(hwif->dma_status); 394 + u8 sc1d = inb(high_16 + 0x001d); 395 395 396 396 if (hwif->channel) { 397 397 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */ ··· 427 427 static void pdc202xx_reset_host (ide_hwif_t *hwif) 428 428 { 429 429 unsigned long high_16 = hwif->dma_master; 430 - u8 udma_speed_flag = hwif->INB(high_16|0x001f); 430 + u8 udma_speed_flag = inb(high_16 | 0x001f); 431 431 432 - hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f)); 432 + outb(udma_speed_flag | 0x10, high_16 | 0x001f); 433 433 mdelay(100); 434 - hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f)); 434 + outb(udma_speed_flag & ~0x10, high_16 | 0x001f); 435 435 mdelay(2000); /* 2 seconds ?! */ 436 436 437 437 printk(KERN_WARNING "PDC202XX: %s channel reset.\n", ··· 519 519 return; 520 520 } 521 521 522 - udma_speed_flag = hwif->INB((dmabase|0x1f)); 523 - primary_mode = hwif->INB((dmabase|0x1a)); 524 - secondary_mode = hwif->INB((dmabase|0x1b)); 522 + udma_speed_flag = inb(dmabase | 0x1f); 523 + primary_mode = inb(dmabase | 0x1a); 524 + secondary_mode = inb(dmabase | 0x1b); 525 525 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \ 526 526 "Primary %s Mode " \ 527 527 "Secondary %s Mode.\n", hwif->cds->name, ··· 534 534 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ", 535 535 hwif->cds->name, udma_speed_flag, 536 536 (udma_speed_flag|1)); 537 - hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f)); 538 - printk("%sACTIVE\n", 539 - (hwif->INB(dmabase|0x1f)&1) ? "":"IN"); 537 + outb(udma_speed_flag | 1, dmabase | 0x1f); 538 + printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN"); 540 539 } 541 540 #endif /* CONFIG_PDC202XX_BURST */ 542 541

+2 -2

drivers/ide/pci/serverworks.c

··· 160 160 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || 161 161 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { 162 162 if (!drive->init_speed) { 163 - u8 dma_stat = hwif->INB(hwif->dma_status); 163 + u8 dma_stat = inb(hwif->dma_status); 164 164 165 165 dma_pio: 166 166 if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) && ··· 529 529 if (!noautodma) 530 530 hwif->autodma = 1; 531 531 532 - dma_stat = hwif->INB(hwif->dma_status); 532 + dma_stat = inb(hwif->dma_status); 533 533 hwif->drives[0].autodma = (dma_stat & 0x20); 534 534 hwif->drives[1].autodma = (dma_stat & 0x40); 535 535 hwif->drives[0].autotune = (!(dma_stat & 0x20));

+35 -32

drivers/ide/pci/sgiioc4.c

··· 110 110 static void 111 111 sgiioc4_maskproc(ide_drive_t * drive, int mask) 112 112 { 113 - ide_hwif_t *hwif = HWIF(drive); 114 - hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2), 115 - IDE_CONTROL_REG); 113 + writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2), 114 + (void __iomem *)IDE_CONTROL_REG); 116 115 } 117 116 118 117 119 118 static int 120 119 sgiioc4_checkirq(ide_hwif_t * hwif) 121 120 { 122 - u8 intr_reg = 123 - hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4); 121 + unsigned long intr_addr = 122 + hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4; 124 123 125 - if (intr_reg & 0x03) 124 + if ((u8)readl((void __iomem *)intr_addr) & 0x03) 126 125 return 1; 127 126 128 127 return 0; 129 128 } 130 129 130 + static u8 sgiioc4_INB(unsigned long); 131 131 132 132 static int 133 133 sgiioc4_clearirq(ide_drive_t * drive) ··· 138 138 hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2); 139 139 140 140 /* Code to check for PCI error conditions */ 141 - intr_reg = hwif->INL(other_ir); 141 + intr_reg = readl((void __iomem *)other_ir); 142 142 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */ 143 143 /* 144 - * Using hwif->INB to read the IDE_STATUS_REG has a side effect 144 + * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect 145 145 * of clearing the interrupt. The first read should clear it 146 146 * if it is set. The second read should return a "clear" status 147 147 * if it got cleared. If not, then spin for a bit trying to 148 148 * clear it. 149 149 */ 150 - u8 stat = hwif->INB(IDE_STATUS_REG); 150 + u8 stat = sgiioc4_INB(IDE_STATUS_REG); 151 151 int count = 0; 152 - stat = hwif->INB(IDE_STATUS_REG); 152 + stat = sgiioc4_INB(IDE_STATUS_REG); 153 153 while ((stat & 0x80) && (count++ < 100)) { 154 154 udelay(1); 155 - stat = hwif->INB(IDE_STATUS_REG); 155 + stat = sgiioc4_INB(IDE_STATUS_REG); 156 156 } 157 157 158 158 if (intr_reg & 0x02) { ··· 161 161 pci_stat_cmd_reg; 162 162 163 163 pci_err_addr_low = 164 - hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET]); 164 + readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]); 165 165 pci_err_addr_high = 166 - hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + 4); 166 + readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4)); 167 167 pci_read_config_dword(hwif->pci_dev, PCI_COMMAND, 168 168 &pci_stat_cmd_reg); 169 169 printk(KERN_ERR ··· 180 180 } 181 181 182 182 /* Clear the Interrupt, Error bits on the IOC4 */ 183 - hwif->OUTL(0x03, other_ir); 183 + writel(0x03, (void __iomem *)other_ir); 184 184 185 - intr_reg = hwif->INL(other_ir); 185 + intr_reg = readl((void __iomem *)other_ir); 186 186 } 187 187 188 188 return intr_reg & 3; ··· 191 191 static void sgiioc4_ide_dma_start(ide_drive_t * drive) 192 192 { 193 193 ide_hwif_t *hwif = HWIF(drive); 194 - unsigned int reg = hwif->INL(hwif->dma_base + IOC4_DMA_CTRL * 4); 194 + unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4; 195 + unsigned int reg = readl((void __iomem *)ioc4_dma_addr); 195 196 unsigned int temp_reg = reg | IOC4_S_DMA_START; 196 197 197 - hwif->OUTL(temp_reg, hwif->dma_base + IOC4_DMA_CTRL * 4); 198 + writel(temp_reg, (void __iomem *)ioc4_dma_addr); 198 199 } 199 200 200 201 static u32 201 202 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base) 202 203 { 204 + unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4; 203 205 u32 ioc4_dma; 204 206 int count; 205 207 206 208 count = 0; 207 - ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4); 209 + ioc4_dma = readl((void __iomem *)ioc4_dma_addr); 208 210 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) { 209 211 udelay(1); 210 - ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4); 212 + ioc4_dma = readl((void __iomem *)ioc4_dma_addr); 211 213 } 212 214 return ioc4_dma; 213 215 } ··· 220 218 { 221 219 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0; 222 220 ide_hwif_t *hwif = HWIF(drive); 223 - u64 dma_base = hwif->dma_base; 221 + unsigned long dma_base = hwif->dma_base; 224 222 int dma_stat = 0; 225 223 unsigned long *ending_dma = ide_get_hwifdata(hwif); 226 224 227 - hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4); 225 + writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4)); 228 226 229 227 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); 230 228 ··· 256 254 dma_stat = 1; 257 255 } 258 256 259 - bc_dev = hwif->INL(dma_base + IOC4_BC_DEV * 4); 260 - bc_mem = hwif->INL(dma_base + IOC4_BC_MEM * 4); 257 + bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4)); 258 + bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4)); 261 259 262 260 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) { 263 261 if (bc_dev > bc_mem + 8) { ··· 438 436 { 439 437 u32 ioc4_dma; 440 438 ide_hwif_t *hwif = HWIF(drive); 441 - u64 dma_base = hwif->dma_base; 439 + unsigned long dma_base = hwif->dma_base; 440 + unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4; 442 441 u32 dma_addr, ending_dma_addr; 443 442 444 - ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4); 443 + ioc4_dma = readl((void __iomem *)ioc4_dma_addr); 445 444 446 445 if (ioc4_dma & IOC4_S_DMA_ACTIVE) { 447 446 printk(KERN_WARNING 448 447 "%s(%s):Warning!! DMA from previous transfer was still active\n", 449 448 __FUNCTION__, drive->name); 450 - hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4); 449 + writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr); 451 450 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); 452 451 453 452 if (ioc4_dma & IOC4_S_DMA_STOP) ··· 457 454 __FUNCTION__, drive->name); 458 455 } 459 456 460 - ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4); 457 + ioc4_dma = readl((void __iomem *)ioc4_dma_addr); 461 458 if (ioc4_dma & IOC4_S_DMA_ERROR) { 462 459 printk(KERN_WARNING 463 460 "%s(%s) : Warning!! - DMA Error during Previous" 464 461 " transfer | status 0x%x\n", 465 462 __FUNCTION__, drive->name, ioc4_dma); 466 - hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4); 463 + writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr); 467 464 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); 468 465 469 466 if (ioc4_dma & IOC4_S_DMA_STOP) ··· 474 471 475 472 /* Address of the Scatter Gather List */ 476 473 dma_addr = cpu_to_le32(hwif->dmatable_dma); 477 - hwif->OUTL(dma_addr, dma_base + IOC4_DMA_PTR_L * 4); 474 + writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4)); 478 475 479 476 /* Address of the Ending DMA */ 480 477 memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE); 481 478 ending_dma_addr = cpu_to_le32(hwif->dma_status); 482 - hwif->OUTL(ending_dma_addr, dma_base + IOC4_DMA_END_ADDR * 4); 479 + writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4)); 483 480 484 - hwif->OUTL(dma_direction, dma_base + IOC4_DMA_CTRL * 4); 481 + writel(dma_direction, (void __iomem *)ioc4_dma_addr); 485 482 drive->waiting_for_dma = 1; 486 483 } 487 484 ··· 691 688 default_hwif_mmiops(hwif); 692 689 693 690 /* Initializing chipset IRQ Registers */ 694 - hwif->OUTL(0x03, irqport + IOC4_INTR_SET * 4); 691 + writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4)); 695 692 696 693 ide_init_sgiioc4(hwif); 697 694

+13 -11

drivers/ide/pci/siimage.c

··· 460 460 unsigned long addr = siimage_selreg(hwif, 0x1); 461 461 462 462 if (SATA_ERROR_REG) { 463 - u32 ext_stat = hwif->INL(base + 0x10); 463 + u32 ext_stat = readl((void __iomem *)(base + 0x10)); 464 464 u8 watchdog = 0; 465 465 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { 466 - u32 sata_error = hwif->INL(SATA_ERROR_REG); 467 - hwif->OUTL(sata_error, SATA_ERROR_REG); 466 + u32 sata_error = readl((void __iomem *)SATA_ERROR_REG); 467 + writel(sata_error, (void __iomem *)SATA_ERROR_REG); 468 468 watchdog = (sata_error & 0x00680000) ? 1 : 0; 469 469 printk(KERN_WARNING "%s: sata_error = 0x%08x, " 470 470 "watchdog = %d, %s\n", ··· 481 481 } 482 482 483 483 /* return 1 if INTR asserted */ 484 - if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04) 484 + if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04) 485 485 return 1; 486 486 487 487 /* return 1 if Device INTR asserted */ 488 - if ((hwif->INB(addr) & 8) == 8) 488 + if ((readb((void __iomem *)addr) & 8) == 8) 489 489 return 0; //return 1; 490 490 491 491 return 0; ··· 507 507 u32 stat_config = 0; 508 508 unsigned long addr = siimage_selreg(hwif, 0); 509 509 510 - if (hwif->mmio) { 511 - stat_config = hwif->INL(addr); 512 - } else 510 + if (hwif->mmio) 511 + stat_config = readl((void __iomem *)addr); 512 + else 513 513 pci_read_config_dword(hwif->pci_dev, addr, &stat_config); 514 514 515 515 switch (state) { ··· 545 545 if (SATA_STATUS_REG) { 546 546 ide_hwif_t *hwif = HWIF(drive); 547 547 548 - if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) { 548 + /* SATA_STATUS_REG is valid only when in MMIO mode */ 549 + if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) { 549 550 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", 550 - hwif->name, hwif->INL(SATA_STATUS_REG)); 551 + hwif->name, readl((void __iomem *)SATA_STATUS_REG)); 551 552 HWGROUP(drive)->polling = 0; 552 553 return ide_started; 553 554 } ··· 608 607 } 609 608 610 609 if (SATA_STATUS_REG) { 611 - u32 sata_stat = hwif->INL(SATA_STATUS_REG); 610 + /* SATA_STATUS_REG is valid only when in MMIO mode */ 611 + u32 sata_stat = readl((void __iomem *)SATA_STATUS_REG); 612 612 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n", 613 613 hwif->name, sata_stat, __FUNCTION__); 614 614 if (!(sata_stat)) {

+1 -1

drivers/ide/pci/sl82c105.c

··· 215 215 * Was DMA enabled? If so, disable it - we're resetting the 216 216 * host. The IDE layer will be handling the drive for us. 217 217 */ 218 - val = hwif->INB(dma_base); 218 + val = inb(dma_base); 219 219 if (val & 1) { 220 220 outb(val & ~1, dma_base); 221 221 printk("sl82c105: DMA was enabled\n");

+13 -13

drivers/ide/pci/tc86c001.c

··· 45 45 46 46 scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f; 47 47 scr |= mode; 48 - hwif->OUTW(scr, scr_port); 48 + outw(scr, scr_port); 49 49 50 50 return ide_config_drive_speed(drive, speed); 51 51 } ··· 89 89 "attempting recovery...\n", drive->name); 90 90 91 91 /* Stop DMA */ 92 - hwif->OUTB(dma_cmd & ~0x01, hwif->dma_command); 92 + outb(dma_cmd & ~0x01, hwif->dma_command); 93 93 94 94 /* Setup the dummy DMA transfer */ 95 - hwif->OUTW(0, sc_base + 0x0a); /* Sector Count */ 96 - hwif->OUTW(0, twcr_port); /* Transfer Word Count 1 or 2 */ 95 + outw(0, sc_base + 0x0a); /* Sector Count */ 96 + outw(0, twcr_port); /* Transfer Word Count 1 or 2 */ 97 97 98 98 /* Start the dummy DMA transfer */ 99 - hwif->OUTB(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */ 100 - hwif->OUTB(0x01, hwif->dma_command); /* set START_STOPBM */ 99 + outb(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */ 100 + outb(0x01, hwif->dma_command); /* set START_STOPBM */ 101 101 102 102 /* 103 103 * If an interrupt was pending, it should come thru shortly. ··· 128 128 * the appropriate system control registers for DMA to work 129 129 * with LBA48 and ATAPI devices... 130 130 */ 131 - hwif->OUTW(nsectors, sc_base + 0x0a); /* Sector Count */ 132 - hwif->OUTW(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */ 131 + outw(nsectors, sc_base + 0x0a); /* Sector Count */ 132 + outw(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */ 133 133 134 134 /* Install our timeout expiry hook, saving the current handler... */ 135 135 ide_set_hwifdata(hwif, hwgroup->expiry); ··· 168 168 } 169 169 170 170 /* System Control 1 Register bit 11 (ATA Hard Reset) write */ 171 - hwif->OUTW(scr1, sc_base + 0x00); 171 + outw(scr1, sc_base + 0x00); 172 172 return 0; 173 173 } 174 174 ··· 204 204 u16 scr1 = hwif->INW(sc_base + 0x00);; 205 205 206 206 /* System Control 1 Register bit 15 (Soft Reset) set */ 207 - hwif->OUTW(scr1 | 0x8000, sc_base + 0x00); 207 + outw(scr1 | 0x8000, sc_base + 0x00); 208 208 209 209 /* System Control 1 Register bit 14 (FIFO Reset) set */ 210 - hwif->OUTW(scr1 | 0x4000, sc_base + 0x00); 210 + outw(scr1 | 0x4000, sc_base + 0x00); 211 211 212 212 /* System Control 1 Register: reset clear */ 213 - hwif->OUTW(scr1 & ~0xc000, sc_base + 0x00); 213 + outw(scr1 & ~0xc000, sc_base + 0x00); 214 214 215 215 /* Store the system control register base for convenience... */ 216 216 hwif->config_data = sc_base; ··· 228 228 * Sector Count Control Register bits 0 and 1 set: 229 229 * software sets Sector Count Register for master and slave device 230 230 */ 231 - hwif->OUTW(0x0003, sc_base + 0x0c); 231 + outw(0x0003, sc_base + 0x0c); 232 232 233 233 /* Sector Count Register limit */ 234 234 hwif->rqsize = 0xffff;

+18 -20

drivers/ide/pci/trm290.c

··· 157 157 if (reg != hwif->select_data) { 158 158 hwif->select_data = reg; 159 159 /* set PIO/DMA */ 160 - hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1); 161 - hwif->OUTW(reg & 0xff, hwif->config_data); 160 + outb(0x51 | (hwif->channel << 3), hwif->config_data + 1); 161 + outw(reg & 0xff, hwif->config_data); 162 162 } 163 163 164 164 /* enable IRQ if not probing */ 165 165 if (drive->present) { 166 - reg = hwif->INW(hwif->config_data + 3); 166 + reg = inw(hwif->config_data + 3); 167 167 reg &= 0x13; 168 168 reg &= ~(1 << hwif->channel); 169 - hwif->OUTW(reg, hwif->config_data+3); 169 + outw(reg, hwif->config_data + 3); 170 170 } 171 171 172 172 local_irq_restore(flags); ··· 179 179 180 180 static void trm290_ide_dma_exec_cmd(ide_drive_t *drive, u8 command) 181 181 { 182 - ide_hwif_t *hwif = HWIF(drive); 183 - 184 182 BUG_ON(HWGROUP(drive)->handler != NULL); /* paranoia check */ 185 183 ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL); 186 184 /* issue cmd to drive */ 187 - hwif->OUTB(command, IDE_COMMAND_REG); 185 + outb(command, IDE_COMMAND_REG); 188 186 } 189 187 190 188 static int trm290_ide_dma_setup(ide_drive_t *drive) ··· 208 210 } 209 211 /* select DMA xfer */ 210 212 trm290_prepare_drive(drive, 1); 211 - hwif->OUTL(hwif->dmatable_dma|rw, hwif->dma_command); 213 + outl(hwif->dmatable_dma | rw, hwif->dma_command); 212 214 drive->waiting_for_dma = 1; 213 215 /* start DMA */ 214 - hwif->OUTW((count * 2) - 1, hwif->dma_status); 216 + outw((count * 2) - 1, hwif->dma_status); 215 217 return 0; 216 218 } 217 219 ··· 227 229 drive->waiting_for_dma = 0; 228 230 /* purge DMA mappings */ 229 231 ide_destroy_dmatable(drive); 230 - status = hwif->INW(hwif->dma_status); 232 + status = inw(hwif->dma_status); 231 233 return (status != 0x00ff); 232 234 } 233 235 ··· 236 238 ide_hwif_t *hwif = HWIF(drive); 237 239 u16 status = 0; 238 240 239 - status = hwif->INW(hwif->dma_status); 241 + status = inw(hwif->dma_status); 240 242 return (status == 0x00ff); 241 243 } 242 244 ··· 265 267 266 268 local_irq_save(flags); 267 269 /* put config reg into first byte of hwif->select_data */ 268 - hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1); 270 + outb(0x51 | (hwif->channel << 3), hwif->config_data + 1); 269 271 /* select PIO as default */ 270 272 hwif->select_data = 0x21; 271 - hwif->OUTB(hwif->select_data, hwif->config_data); 273 + outb(hwif->select_data, hwif->config_data); 272 274 /* get IRQ info */ 273 - reg = hwif->INB(hwif->config_data+3); 275 + reg = inb(hwif->config_data + 3); 274 276 /* mask IRQs for both ports */ 275 277 reg = (reg & 0x10) | 0x03; 276 - hwif->OUTB(reg, hwif->config_data+3); 278 + outb(reg, hwif->config_data + 3); 277 279 local_irq_restore(flags); 278 280 279 281 if ((reg & 0x10)) ··· 306 308 static u16 next_offset = 0; 307 309 u8 old_mask; 308 310 309 - hwif->OUTB(0x54|(hwif->channel<<3), hwif->config_data+1); 310 - old = hwif->INW(hwif->config_data); 311 + outb(0x54 | (hwif->channel << 3), hwif->config_data + 1); 312 + old = inw(hwif->config_data); 311 313 old &= ~1; 312 - old_mask = hwif->INB(old+2); 314 + old_mask = inb(old + 2); 313 315 if (old != compat && old_mask == 0xff) { 314 316 /* leave lower 10 bits untouched */ 315 317 compat += (next_offset += 0x400); 316 318 hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2; 317 - hwif->OUTW(compat|1, hwif->config_data); 318 - new = hwif->INW(hwif->config_data); 319 + outw(compat | 1, hwif->config_data); 320 + new = inw(hwif->config_data); 319 321 printk(KERN_INFO "%s: control basereg workaround: " 320 322 "old=0x%04x, new=0x%04x\n", 321 323 hwif->name, old, new & ~1);

+76 -46

drivers/ide/ppc/scc_pata.c

··· 132 132 return (u16)data; 133 133 } 134 134 135 - static u32 scc_ide_inl(unsigned long port) 136 - { 137 - u32 data = in_be32((void*)port); 138 - return data; 139 - } 140 - 141 135 static void scc_ide_insw(unsigned long port, void *addr, u32 count) 142 136 { 143 137 u16 *ptr = (u16 *)addr; ··· 155 161 } 156 162 157 163 static void scc_ide_outw(u16 addr, unsigned long port) 158 - { 159 - out_be32((void*)port, addr); 160 - } 161 - 162 - static void scc_ide_outl(u32 addr, unsigned long port) 163 164 { 164 165 out_be32((void*)port, addr); 165 166 } ··· 247 258 break; 248 259 } 249 260 250 - reg = hwif->INL(cckctrl_port); 261 + reg = in_be32((void __iomem *)cckctrl_port); 251 262 if (reg & CCKCTRL_ATACLKOEN) { 252 263 offset = 1; /* 133MHz */ 253 264 } else { 254 265 offset = 0; /* 100MHz */ 255 266 } 256 267 reg = JCHSTtbl[offset][mode_wanted] << 16 | JCHHTtbl[offset][mode_wanted]; 257 - hwif->OUTL(reg, piosht_port); 268 + out_be32((void __iomem *)piosht_port, reg); 258 269 reg = JCHCTtbl[offset][mode_wanted]; 259 - hwif->OUTL(reg, pioct_port); 270 + out_be32((void __iomem *)pioct_port, reg); 260 271 261 272 ide_config_drive_speed(drive, speed); 262 273 } ··· 288 299 unsigned long reg; 289 300 unsigned long jcactsel; 290 301 291 - reg = hwif->INL(cckctrl_port); 302 + reg = in_be32((void __iomem *)cckctrl_port); 292 303 if (reg & CCKCTRL_ATACLKOEN) { 293 304 offset = 1; /* 133MHz */ 294 305 } else { ··· 323 334 324 335 jcactsel = JCACTSELtbl[offset][idx]; 325 336 if (is_slave) { 326 - hwif->OUTL(JCHDCTxtbl[offset][idx], sdmact_port); 327 - hwif->OUTL(JCSTWTxtbl[offset][idx], scrcst_port); 328 - jcactsel = jcactsel << 2 ; 329 - hwif->OUTL( (hwif->INL( tdvhsel_port ) & ~TDVHSEL_SLAVE) | jcactsel, tdvhsel_port ); 337 + out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]); 338 + out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]); 339 + jcactsel = jcactsel << 2; 340 + out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel); 330 341 } else { 331 - hwif->OUTL(JCHDCTxtbl[offset][idx], mdmact_port); 332 - hwif->OUTL(JCSTWTxtbl[offset][idx], mcrcst_port); 333 - hwif->OUTL( (hwif->INL( tdvhsel_port ) & ~TDVHSEL_MASTER) | jcactsel, tdvhsel_port ); 342 + out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]); 343 + out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]); 344 + out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel); 334 345 } 335 346 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]; 336 - hwif->OUTL(reg, udenvt_port); 347 + out_be32((void __iomem *)udenvt_port, reg); 337 348 338 349 return ide_config_drive_speed(drive, speed); 339 350 } ··· 384 395 } 385 396 386 397 /** 398 + * scc_ide_dma_setup - begin a DMA phase 399 + * @drive: target device 400 + * 401 + * Build an IDE DMA PRD (IDE speak for scatter gather table) 402 + * and then set up the DMA transfer registers. 403 + * 404 + * Returns 0 on success. If a PIO fallback is required then 1 405 + * is returned. 406 + */ 407 + 408 + static int scc_dma_setup(ide_drive_t *drive) 409 + { 410 + ide_hwif_t *hwif = drive->hwif; 411 + struct request *rq = HWGROUP(drive)->rq; 412 + unsigned int reading; 413 + u8 dma_stat; 414 + 415 + if (rq_data_dir(rq)) 416 + reading = 0; 417 + else 418 + reading = 1 << 3; 419 + 420 + /* fall back to pio! */ 421 + if (!ide_build_dmatable(drive, rq)) { 422 + ide_map_sg(drive, rq); 423 + return 1; 424 + } 425 + 426 + /* PRD table */ 427 + out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma); 428 + 429 + /* specify r/w */ 430 + out_be32((void __iomem *)hwif->dma_command, reading); 431 + 432 + /* read dma_status for INTR & ERROR flags */ 433 + dma_stat = in_be32((void __iomem *)hwif->dma_status); 434 + 435 + /* clear INTR & ERROR flags */ 436 + out_be32((void __iomem *)hwif->dma_status, dma_stat|6); 437 + drive->waiting_for_dma = 1; 438 + return 0; 439 + } 440 + 441 + 442 + /** 387 443 * scc_ide_dma_end - Stop DMA 388 444 * @drive: IDE drive 389 445 * ··· 443 409 u32 reg; 444 410 445 411 while (1) { 446 - reg = hwif->INL(intsts_port); 412 + reg = in_be32((void __iomem *)intsts_port); 447 413 448 414 if (reg & INTSTS_SERROR) { 449 415 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME); 450 - hwif->OUTL(INTSTS_SERROR|INTSTS_BMSINT, intsts_port); 416 + out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT); 451 417 452 - hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS, 453 - hwif->dma_command); 418 + out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); 454 419 continue; 455 420 } 456 421 ··· 457 424 u32 maea0, maec0; 458 425 unsigned long ctl_base = hwif->config_data; 459 426 460 - maea0 = hwif->INL(ctl_base + 0xF50); 461 - maec0 = hwif->INL(ctl_base + 0xF54); 427 + maea0 = in_be32((void __iomem *)(ctl_base + 0xF50)); 428 + maec0 = in_be32((void __iomem *)(ctl_base + 0xF54)); 462 429 463 430 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0); 464 431 465 - hwif->OUTL(INTSTS_PRERR|INTSTS_BMSINT, intsts_port); 432 + out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT); 466 433 467 - hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS, 468 - hwif->dma_command); 434 + out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); 469 435 continue; 470 436 } 471 437 472 438 if (reg & INTSTS_RERR) { 473 439 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME); 474 - hwif->OUTL(INTSTS_RERR|INTSTS_BMSINT, intsts_port); 440 + out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT); 475 441 476 - hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS, 477 - hwif->dma_command); 442 + out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); 478 443 continue; 479 444 } 480 445 481 446 if (reg & INTSTS_ICERR) { 482 - hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS, 483 - hwif->dma_command); 447 + out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); 484 448 485 449 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME); 486 - hwif->OUTL(INTSTS_ICERR|INTSTS_BMSINT, intsts_port); 450 + out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT); 487 451 continue; 488 452 } 489 453 490 454 if (reg & INTSTS_BMSINT) { 491 455 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME); 492 - hwif->OUTL(INTSTS_BMSINT, intsts_port); 456 + out_be32((void __iomem *)intsts_port, INTSTS_BMSINT); 493 457 494 458 ide_do_reset(drive); 495 459 continue; 496 460 } 497 461 498 462 if (reg & INTSTS_BMHE) { 499 - hwif->OUTL(INTSTS_BMHE, intsts_port); 463 + out_be32((void __iomem *)intsts_port, INTSTS_BMHE); 500 464 continue; 501 465 } 502 466 503 467 if (reg & INTSTS_ACTEINT) { 504 - hwif->OUTL(INTSTS_ACTEINT, intsts_port); 468 + out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT); 505 469 continue; 506 470 } 507 471 508 472 if (reg & INTSTS_IOIRQS) { 509 - hwif->OUTL(INTSTS_IOIRQS, intsts_port); 473 + out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS); 510 474 continue; 511 475 } 512 476 break; ··· 647 617 648 618 hwif->INB = scc_ide_inb; 649 619 hwif->INW = scc_ide_inw; 650 - hwif->INL = scc_ide_inl; 651 620 hwif->INSW = scc_ide_insw; 652 621 hwif->INSL = scc_ide_insl; 653 622 hwif->OUTB = scc_ide_outb; 654 623 hwif->OUTBSYNC = scc_ide_outbsync; 655 624 hwif->OUTW = scc_ide_outw; 656 - hwif->OUTL = scc_ide_outl; 657 625 hwif->OUTSW = scc_ide_outsw; 658 626 hwif->OUTSL = scc_ide_outsl; 659 627 ··· 707 679 hwif->dma_status = hwif->dma_base + 0x04; 708 680 hwif->dma_prdtable = hwif->dma_base + 0x08; 709 681 710 - hwif->OUTL(hwif->dmatable_dma, (hwif->dma_base + 0x018)); /* PTERADD */ 682 + /* PTERADD */ 683 + out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma); 711 684 685 + hwif->dma_setup = scc_dma_setup; 712 686 hwif->ide_dma_end = scc_ide_dma_end; 713 687 hwif->speedproc = scc_tune_chipset; 714 688 hwif->tuneproc = scc_tuneproc; ··· 719 689 hwif->drives[0].autotune = IDE_TUNE_AUTO; 720 690 hwif->drives[1].autotune = IDE_TUNE_AUTO; 721 691 722 - if (hwif->INL(hwif->config_data + 0xff0) & CCKCTRL_ATACLKOEN) { 692 + if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) { 723 693 hwif->ultra_mask = 0x7f; /* 133MHz */ 724 694 } else { 725 695 hwif->ultra_mask = 0x3f; /* 100MHz */

-2

include/linux/ide.h

··· 746 746 void (*OUTB)(u8 addr, unsigned long port); 747 747 void (*OUTBSYNC)(ide_drive_t *drive, u8 addr, unsigned long port); 748 748 void (*OUTW)(u16 addr, unsigned long port); 749 - void (*OUTL)(u32 addr, unsigned long port); 750 749 void (*OUTSW)(unsigned long port, void *addr, u32 count); 751 750 void (*OUTSL)(unsigned long port, void *addr, u32 count); 752 751 753 752 u8 (*INB)(unsigned long port); 754 753 u16 (*INW)(unsigned long port); 755 - u32 (*INL)(unsigned long port); 756 754 void (*INSW)(unsigned long port, void *addr, u32 count); 757 755 void (*INSL)(unsigned long port, void *addr, u32 count); 758 756