drm/amd/display: revert Blank eDP on disable/enable drv

+7 -1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

··· 638 638 } 639 639 } 640 640 641 + int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base) 642 + { 643 + return clk_mgr_base->clks.ref_dtbclk_khz; 644 + } 645 + 641 646 static struct clk_mgr_funcs dcn31_funcs = { 642 647 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 648 + .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, 643 649 .update_clocks = dcn31_update_clocks, 644 650 .init_clocks = dcn31_init_clocks, 645 651 .enable_pme_wa = dcn31_enable_pme_wa, ··· 725 719 } 726 720 727 721 clk_mgr->base.base.dprefclk_khz = 600000; 728 - clk_mgr->base.dccg->ref_dtbclk_khz = 600000; 722 + clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; 729 723 dce_clock_read_ss_info(&clk_mgr->base); 730 724 /*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/ 731 725 //clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal, clk_mgr->base.base.dprefclk_khz);

+2

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

··· 51 51 struct pp_smu_funcs *pp_smu, 52 52 struct dccg *dccg); 53 53 54 + int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base); 55 + 54 56 void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int); 55 57 56 58 #endif //__DCN31_CLK_MGR_H__

+3 -2

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

··· 580 580 581 581 static struct clk_mgr_funcs dcn315_funcs = { 582 582 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 583 + .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, 583 584 .update_clocks = dcn315_update_clocks, 584 585 .init_clocks = dcn31_init_clocks, 585 586 .enable_pme_wa = dcn315_enable_pme_wa, ··· 657 656 658 657 clk_mgr->base.base.dprefclk_khz = 600000; 659 658 clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base); 660 - clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; 659 + clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; 661 660 dce_clock_read_ss_info(&clk_mgr->base); 662 - clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz); 661 + clk_mgr->base.base.clks.ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz); 663 662 664 663 clk_mgr->base.base.bw_params = &dcn315_bw_params; 665 664

+2 -1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

··· 571 571 static struct clk_mgr_funcs dcn316_funcs = { 572 572 .enable_pme_wa = dcn316_enable_pme_wa, 573 573 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 574 + .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, 574 575 .update_clocks = dcn316_update_clocks, 575 576 .init_clocks = dcn31_init_clocks, 576 577 .are_clock_states_equal = dcn31_are_clock_states_equal, ··· 686 685 687 686 clk_mgr->base.base.dprefclk_khz = 600000; 688 687 clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base); 689 - clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; 688 + clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; 690 689 dce_clock_read_ss_info(&clk_mgr->base); 691 690 /*clk_mgr->base.dccg->ref_dtbclk_khz = 692 691 dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);*/

+3

drivers/gpu/drm/amd/display/dc/dc.h

··· 416 416 bool p_state_change_support; 417 417 enum dcn_zstate_support_state zstate_support; 418 418 bool dtbclk_en; 419 + int ref_dtbclk_khz; 419 420 enum dcn_pwr_state pwr_state; 420 421 /* 421 422 * Elements below are not compared for the purposes of ··· 720 719 bool apply_vendor_specific_lttpr_wa; 721 720 bool extended_blank_optimization; 722 721 union aux_wake_wa_options aux_wake_wa; 722 + /* uses value at boot and disables switch */ 723 + bool disable_dtb_ref_clk_switch; 723 724 uint8_t psr_power_use_phy_fsm; 724 725 enum dml_hostvm_override_opts dml_hostvm_override; 725 726 };

-4

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c

··· 606 606 607 607 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 608 608 DCCG_AUDIO_DTO_SEL, 4); // 04 - DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK 609 - 610 - dccg->audio_dtbclk_khz = req_audio_dtbclk_khz; 611 609 } else { 612 610 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, 0); 613 611 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, 0); 614 612 615 613 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 616 614 DCCG_AUDIO_DTO_SEL, 3); // 03 - DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO 617 - 618 - dccg->audio_dtbclk_khz = 0; 619 615 } 620 616 } 621 617

+1

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

··· 237 237 bool safe_to_lower); 238 238 239 239 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr); 240 + int (*get_dtb_ref_clk_frequency)(struct clk_mgr *clk_mgr); 240 241 241 242 void (*set_low_power_state)(struct clk_mgr *clk_mgr); 242 243

+12 -6

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

··· 60 60 const struct dccg_funcs *funcs; 61 61 int pipe_dppclk_khz[MAX_PIPES]; 62 62 int ref_dppclk; 63 - int dtbclk_khz[MAX_PIPES]; 64 - int audio_dtbclk_khz; 63 + //int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */ 64 + //int audio_dtbclk_khz;/* TODO needs to be removed */ 65 + //int ref_dtbclk_khz;/* TODO needs to be removed */ 66 + }; 67 + 68 + struct dtbclk_dto_params { 69 + const struct dc_crtc_timing *timing; 70 + int otg_inst; 71 + int pixclk_khz; 72 + int req_audio_dtbclk_khz; 73 + int num_odm_segments; 65 74 int ref_dtbclk_khz; 66 75 }; 67 76 ··· 120 111 121 112 void (*set_dtbclk_dto)( 122 113 struct dccg *dccg, 123 - int dtbclk_inst, 124 - int req_dtbclk_khz, 125 - int num_odm_segments, 126 - const struct dc_crtc_timing *timing); 114 + const struct dtbclk_dto_params *params); 127 115 128 116 void (*set_audio_dtbclk_dto)( 129 117 struct dccg *dccg,

+14 -5

drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c

··· 27 27 #include "core_types.h" 28 28 #include "dccg.h" 29 29 #include "dc_link_dp.h" 30 + #include "clk_mgr.h" 30 31 31 32 static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link) 32 33 { ··· 107 106 struct hpo_dp_link_encoder *link_enc = pipe_ctx->link_res.hpo_dp_link_enc; 108 107 struct dccg *dccg = dc->res_pool->dccg; 109 108 struct timing_generator *tg = pipe_ctx->stream_res.tg; 110 - int odm_segment_count = get_odm_segment_count(pipe_ctx); 109 + struct dtbclk_dto_params dto_params = {0}; 111 110 enum phyd32clk_clock_source phyd32clk = get_phyd32clk_src(pipe_ctx->stream->link); 111 + 112 + dto_params.otg_inst = tg->inst; 113 + dto_params.pixclk_khz = pipe_ctx->stream->phy_pix_clk; 114 + dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx); 115 + dto_params.timing = &pipe_ctx->stream->timing; 116 + dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); 112 117 113 118 dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst); 114 119 dccg->funcs->enable_symclk32_se(dccg, stream_enc->inst, phyd32clk); 115 - dccg->funcs->set_dtbclk_dto(dccg, tg->inst, pipe_ctx->stream->phy_pix_clk, 116 - odm_segment_count, 117 - &pipe_ctx->stream->timing); 120 + dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 118 121 stream_enc->funcs->enable_stream(stream_enc); 119 122 stream_enc->funcs->map_stream_to_link(stream_enc, stream_enc->inst, link_enc->inst); 120 123 } ··· 129 124 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 130 125 struct dccg *dccg = dc->res_pool->dccg; 131 126 struct timing_generator *tg = pipe_ctx->stream_res.tg; 127 + struct dtbclk_dto_params dto_params = {0}; 128 + 129 + dto_params.otg_inst = tg->inst; 130 + dto_params.timing = &pipe_ctx->stream->timing; 132 131 133 132 stream_enc->funcs->disable(stream_enc); 134 - dccg->funcs->set_dtbclk_dto(dccg, tg->inst, 0, 0, &pipe_ctx->stream->timing); 133 + dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 135 134 dccg->funcs->disable_symclk32_se(dccg, stream_enc->inst); 136 135 dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst); 137 136 }