tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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media: platform: mtk-mdp3: add mt8195 MDP3 component settings

Extend the component settings used in MT8195 MDP3.
Additionally, it is crucial to read all component settings in
a specific manner to ensure that shared memory data structure lengths
are aligned across different platforms.

Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>

authored by

Moudy Ho and committed by
Mauro Carvalho Chehab 0e9bd2fc 51d918d6

+851 -4
+57
drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
··· 40 40 num = CFG_COMP(MT8183, param, num_subfrms); 41 41 dis_output = CFG_COMP(MT8183, param, frame.output_disable); 42 42 dis_tile = CFG_COMP(MT8183, param, frame.output_disable); 43 + } else if (CFG_CHECK(MT8195, p_id)) { 44 + num = CFG_COMP(MT8195, param, num_subfrms); 45 + dis_output = CFG_COMP(MT8195, param, frame.output_disable); 46 + dis_tile = CFG_COMP(MT8195, param, frame.output_disable); 43 47 } 44 48 45 49 return (count < num) ? (dis_output || dis_tile) : true; ··· 105 101 106 102 if (CFG_CHECK(MT8183, p_id)) 107 103 num_comp = CFG_GET(MT8183, path->config, num_components); 104 + else if (CFG_CHECK(MT8195, p_id)) 105 + num_comp = CFG_GET(MT8195, path->config, num_components); 108 106 109 107 /* Decide which mutex to use based on the current pipeline */ 110 108 index = __get_pipe(path->mdp_dev, path->comps[0].comp->public_id); ··· 121 115 122 116 if (CFG_CHECK(MT8183, p_id)) 123 117 inner_id = CFG_GET(MT8183, path->config, components[index].type); 118 + else if (CFG_CHECK(MT8195, p_id)) 119 + inner_id = CFG_GET(MT8195, path->config, components[index].type); 120 + 124 121 if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) 125 122 continue; 126 123 ··· 165 156 166 157 if (CFG_CHECK(MT8183, p_id)) 167 158 num_comp = CFG_GET(MT8183, path->config, num_components); 159 + else if (CFG_CHECK(MT8195, p_id)) 160 + num_comp = CFG_GET(MT8195, path->config, num_components); 168 161 169 162 /* Wait WROT SRAM shared to DISP RDMA */ 170 163 /* Clear SOF event for each engine */ 171 164 for (index = 0; index < num_comp; index++) { 172 165 if (CFG_CHECK(MT8183, p_id)) 173 166 inner_id = CFG_GET(MT8183, path->config, components[index].type); 167 + else if (CFG_CHECK(MT8195, p_id)) 168 + inner_id = CFG_GET(MT8195, path->config, components[index].type); 169 + 174 170 if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) 175 171 continue; 176 172 ctx = &path->comps[index]; ··· 194 180 for (index = 0; index < num_comp; index++) { 195 181 if (CFG_CHECK(MT8183, p_id)) 196 182 inner_id = CFG_GET(MT8183, path->config, components[index].type); 183 + else if (CFG_CHECK(MT8195, p_id)) 184 + inner_id = CFG_GET(MT8195, path->config, components[index].type); 185 + 197 186 if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) 198 187 continue; 199 188 ctx = &path->comps[index]; ··· 219 202 220 203 if (CFG_CHECK(MT8183, p_id)) 221 204 num_comp = CFG_GET(MT8183, path->config, num_components); 205 + else if (CFG_CHECK(MT8195, p_id)) 206 + num_comp = CFG_GET(MT8195, path->config, num_components); 222 207 223 208 if (num_comp < 1) 224 209 return -EINVAL; ··· 230 211 231 212 if (CFG_CHECK(MT8183, p_id)) 232 213 inner_id = CFG_GET(MT8183, path->config, components[index].type); 214 + else if (CFG_CHECK(MT8195, p_id)) 215 + inner_id = CFG_GET(MT8195, path->config, components[index].type); 216 + 233 217 if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) 234 218 continue; 235 219 if (CFG_CHECK(MT8183, p_id)) 236 220 param = (void *)CFG_ADDR(MT8183, path->config, components[index]); 221 + else if (CFG_CHECK(MT8195, p_id)) 222 + param = (void *)CFG_ADDR(MT8195, path->config, components[index]); 237 223 ret = mdp_comp_ctx_config(mdp, &path->comps[index], 238 224 param, path->param); 239 225 if (ret) ··· 262 238 263 239 if (CFG_CHECK(MT8183, p_id)) 264 240 num_comp = CFG_GET(MT8183, path->config, num_components); 241 + else if (CFG_CHECK(MT8195, p_id)) 242 + num_comp = CFG_GET(MT8195, path->config, num_components); 265 243 266 244 if (CFG_CHECK(MT8183, p_id)) 267 245 ctrl = CFG_ADDR(MT8183, path->config, ctrls[count]); 246 + else if (CFG_CHECK(MT8195, p_id)) 247 + ctrl = CFG_ADDR(MT8195, path->config, ctrls[count]); 268 248 269 249 /* Acquire components */ 270 250 ret = mdp_path_subfrm_require(path, cmd, &pipe, count); ··· 284 256 for (index = (num_comp - 1); index >= 0; index--) { 285 257 if (CFG_CHECK(MT8183, p_id)) 286 258 inner_id = CFG_GET(MT8183, path->config, components[index].type); 259 + else if (CFG_CHECK(MT8195, p_id)) 260 + inner_id = CFG_GET(MT8195, path->config, components[index].type); 261 + 287 262 if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) 288 263 continue; 289 264 ctx = &path->comps[index]; ··· 304 273 for (index = 0; index < num_comp; index++) { 305 274 if (CFG_CHECK(MT8183, p_id)) 306 275 inner_id = CFG_GET(MT8183, path->config, components[index].type); 276 + else if (CFG_CHECK(MT8195, p_id)) 277 + inner_id = CFG_GET(MT8195, path->config, components[index].type); 278 + 307 279 if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) 308 280 continue; 309 281 ctx = &path->comps[index]; ··· 320 286 for (index = 0; index < num_comp; index++) { 321 287 if (CFG_CHECK(MT8183, p_id)) 322 288 inner_id = CFG_GET(MT8183, path->config, components[index].type); 289 + else if (CFG_CHECK(MT8195, p_id)) 290 + inner_id = CFG_GET(MT8195, path->config, components[index].type); 291 + 323 292 if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) 324 293 continue; 325 294 ctx = &path->comps[index]; ··· 352 315 353 316 if (CFG_CHECK(MT8183, p_id)) 354 317 num_comp = CFG_GET(MT8183, path->config, num_components); 318 + else if (CFG_CHECK(MT8195, p_id)) 319 + num_comp = CFG_GET(MT8195, path->config, num_components); 355 320 356 321 if (CFG_CHECK(MT8183, p_id)) 357 322 num_sub = CFG_GET(MT8183, path->config, num_subfrms); 323 + else if (CFG_CHECK(MT8195, p_id)) 324 + num_sub = CFG_GET(MT8195, path->config, num_subfrms); 358 325 359 326 /* Config path frame */ 360 327 /* Reset components */ 361 328 for (index = 0; index < num_comp; index++) { 362 329 if (CFG_CHECK(MT8183, p_id)) 363 330 inner_id = CFG_GET(MT8183, path->config, components[index].type); 331 + else if (CFG_CHECK(MT8195, p_id)) 332 + inner_id = CFG_GET(MT8195, path->config, components[index].type); 333 + 364 334 if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) 365 335 continue; 366 336 ctx = &path->comps[index]; ··· 383 339 ctx = &path->comps[index]; 384 340 if (CFG_CHECK(MT8183, p_id)) 385 341 inner_id = CFG_GET(MT8183, path->config, components[index].type); 342 + else if (CFG_CHECK(MT8195, p_id)) 343 + inner_id = CFG_GET(MT8195, path->config, components[index].type); 344 + 386 345 if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) 387 346 continue; 388 347 389 348 if (CFG_CHECK(MT8183, p_id)) 390 349 out = CFG_COMP(MT8183, ctx->param, outputs[0]); 350 + else if (CFG_CHECK(MT8195, p_id)) 351 + out = CFG_COMP(MT8195, ctx->param, outputs[0]); 391 352 392 353 compose = path->composes[out]; 393 354 ret = call_op(ctx, config_frame, cmd, compose); ··· 410 361 for (index = 0; index < num_comp; index++) { 411 362 if (CFG_CHECK(MT8183, p_id)) 412 363 inner_id = CFG_GET(MT8183, path->config, components[index].type); 364 + else if (CFG_CHECK(MT8195, p_id)) 365 + inner_id = CFG_GET(MT8195, path->config, components[index].type); 366 + 413 367 if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) 414 368 continue; 415 369 ctx = &path->comps[index]; ··· 567 515 568 516 if (CFG_CHECK(MT8183, p_id)) { 569 517 num_comp = CFG_GET(MT8183, param->config, num_components); 518 + } else if (CFG_CHECK(MT8195, p_id)) { 519 + num_comp = CFG_GET(MT8195, param->config, num_components); 570 520 } else { 571 521 ret = -EINVAL; 572 522 goto err_destroy_pkt; ··· 624 570 625 571 if (CFG_CHECK(MT8183, p_id)) 626 572 inner_id = CFG_GET(MT8183, path->config, components[i].type); 573 + else if (CFG_CHECK(MT8195, p_id)) 574 + inner_id = CFG_GET(MT8195, path->config, components[i].type); 575 + 627 576 if (mdp_cfg_comp_is_dummy(mdp, inner_id)) 628 577 continue; 629 578 memcpy(&comps[i], path->comps[i].comp,
+794 -4
drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c
··· 13 13 #include "mtk-mdp3-core.h" 14 14 #include "mtk-mdp3-regs.h" 15 15 16 - #include "mdp_reg_rdma.h" 16 + #include "mdp_reg_aal.h" 17 17 #include "mdp_reg_ccorr.h" 18 + #include "mdp_reg_color.h" 19 + #include "mdp_reg_fg.h" 20 + #include "mdp_reg_hdr.h" 21 + #include "mdp_reg_merge.h" 22 + #include "mdp_reg_ovl.h" 23 + #include "mdp_reg_pad.h" 24 + #include "mdp_reg_rdma.h" 18 25 #include "mdp_reg_rsz.h" 19 - #include "mdp_reg_wrot.h" 26 + #include "mdp_reg_tdshp.h" 20 27 #include "mdp_reg_wdma.h" 28 + #include "mdp_reg_wrot.h" 21 29 22 30 static u32 mdp_comp_alias_id[MDP_COMP_TYPE_COUNT]; 23 31 static int p_id; ··· 93 85 bool en_ufo = MDP_COLOR_IS_UFP(colorformat); 94 86 phys_addr_t base = ctx->comp->reg_base; 95 87 u8 subsys_id = ctx->comp->subsys_id; 88 + u32 rdma_con_mask = 0; 96 89 u32 reg = 0; 97 90 98 91 if (mdp_cfg && mdp_cfg->rdma_support_10bit) { ··· 114 105 /* Setup source frame info */ 115 106 if (CFG_CHECK(MT8183, p_id)) 116 107 reg = CFG_COMP(MT8183, ctx->param, rdma.src_ctrl); 108 + else if (CFG_CHECK(MT8195, p_id)) 109 + reg = CFG_COMP(MT8195, ctx->param, rdma.src_ctrl); 117 110 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, reg, 118 111 0x03C8FE0F); 119 112 ··· 124 113 /* Setup source buffer base */ 125 114 if (CFG_CHECK(MT8183, p_id)) 126 115 reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_y); 116 + else if (CFG_CHECK(MT8195, p_id)) 117 + reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_y); 127 118 MM_REG_WRITE(cmd, subsys_id, 128 119 base, MDP_RDMA_UFO_DEC_LENGTH_BASE_Y, 129 120 reg, 0xFFFFFFFF); 121 + 130 122 if (CFG_CHECK(MT8183, p_id)) 131 123 reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_c); 124 + else if (CFG_CHECK(MT8195, p_id)) 125 + reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_c); 132 126 MM_REG_WRITE(cmd, subsys_id, 133 127 base, MDP_RDMA_UFO_DEC_LENGTH_BASE_C, 134 128 reg, 0xFFFFFFFF); 129 + 135 130 /* Set 10bit source frame pitch */ 136 131 if (block10bit) { 137 132 if (CFG_CHECK(MT8183, p_id)) 138 133 reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd_in_pxl); 134 + else if (CFG_CHECK(MT8195, p_id)) 135 + reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd_in_pxl); 139 136 MM_REG_WRITE(cmd, subsys_id, 140 137 base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL, 141 138 reg, 0x001FFFFF); 142 139 } 143 140 } 144 141 145 - if (CFG_CHECK(MT8183, p_id)) 142 + if (CFG_CHECK(MT8183, p_id)) { 146 143 reg = CFG_COMP(MT8183, ctx->param, rdma.control); 144 + rdma_con_mask = 0x1110; 145 + } else if (CFG_CHECK(MT8195, p_id)) { 146 + reg = CFG_COMP(MT8195, ctx->param, rdma.control); 147 + rdma_con_mask = 0x1130; 148 + } 147 149 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, reg, 148 - 0x1110); 150 + rdma_con_mask); 151 + 149 152 /* Setup source buffer base */ 150 153 if (CFG_CHECK(MT8183, p_id)) 151 154 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]); 155 + else if (CFG_CHECK(MT8195, p_id)) 156 + reg = CFG_COMP(MT8195, ctx->param, rdma.iova[0]); 152 157 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, reg, 153 158 0xFFFFFFFF); 159 + 154 160 if (CFG_CHECK(MT8183, p_id)) 155 161 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[1]); 162 + else if (CFG_CHECK(MT8195, p_id)) 163 + reg = CFG_COMP(MT8195, ctx->param, rdma.iova[1]); 156 164 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, reg, 157 165 0xFFFFFFFF); 166 + 158 167 if (CFG_CHECK(MT8183, p_id)) 159 168 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[2]); 169 + else if (CFG_CHECK(MT8195, p_id)) 170 + reg = CFG_COMP(MT8195, ctx->param, rdma.iova[2]); 160 171 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, reg, 161 172 0xFFFFFFFF); 173 + 162 174 /* Setup source buffer end */ 163 175 if (CFG_CHECK(MT8183, p_id)) 164 176 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]); 177 + else if (CFG_CHECK(MT8195, p_id)) 178 + reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[0]); 165 179 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0, 166 180 reg, 0xFFFFFFFF); 181 + 167 182 if (CFG_CHECK(MT8183, p_id)) 168 183 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[1]); 184 + else if (CFG_CHECK(MT8195, p_id)) 185 + reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[1]); 169 186 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_1, 170 187 reg, 0xFFFFFFFF); 188 + 171 189 if (CFG_CHECK(MT8183, p_id)) 172 190 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[2]); 191 + else if (CFG_CHECK(MT8195, p_id)) 192 + reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[2]); 173 193 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_2, 174 194 reg, 0xFFFFFFFF); 195 + 175 196 /* Setup source frame pitch */ 176 197 if (CFG_CHECK(MT8183, p_id)) 177 198 reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd); 199 + else if (CFG_CHECK(MT8195, p_id)) 200 + reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd); 178 201 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, 179 202 reg, 0x001FFFFF); 203 + 180 204 if (CFG_CHECK(MT8183, p_id)) 181 205 reg = CFG_COMP(MT8183, ctx->param, rdma.sf_bkgd); 206 + else if (CFG_CHECK(MT8195, p_id)) 207 + reg = CFG_COMP(MT8195, ctx->param, rdma.sf_bkgd); 182 208 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SF_BKGD_SIZE_IN_BYTE, 183 209 reg, 0x001FFFFF); 210 + 184 211 /* Setup color transform */ 185 212 if (CFG_CHECK(MT8183, p_id)) 186 213 reg = CFG_COMP(MT8183, ctx->param, rdma.transform); 214 + else if (CFG_CHECK(MT8195, p_id)) 215 + reg = CFG_COMP(MT8195, ctx->param, rdma.transform); 187 216 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0, 188 217 reg, 0x0F110000); 189 218 219 + if (!mdp_cfg || !mdp_cfg->rdma_esl_setting) 220 + goto rdma_config_done; 221 + 222 + if (CFG_CHECK(MT8195, p_id)) 223 + reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con0); 224 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_0, 225 + reg, 0x0FFF00FF); 226 + 227 + if (CFG_CHECK(MT8195, p_id)) 228 + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con0); 229 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_0, 230 + reg, 0x3FFFFFFF); 231 + 232 + if (CFG_CHECK(MT8195, p_id)) 233 + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con0); 234 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_0, 235 + reg, 0x3FFFFFFF); 236 + 237 + if (CFG_CHECK(MT8195, p_id)) 238 + reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con1); 239 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_1, 240 + reg, 0x0F7F007F); 241 + 242 + if (CFG_CHECK(MT8195, p_id)) 243 + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con1); 244 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_1, 245 + reg, 0x3FFFFFFF); 246 + 247 + if (CFG_CHECK(MT8195, p_id)) 248 + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con1); 249 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_1, 250 + reg, 0x3FFFFFFF); 251 + 252 + if (CFG_CHECK(MT8195, p_id)) 253 + reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con2); 254 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_2, 255 + reg, 0x0F3F003F); 256 + 257 + if (CFG_CHECK(MT8195, p_id)) 258 + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con2); 259 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_2, 260 + reg, 0x3FFFFFFF); 261 + 262 + if (CFG_CHECK(MT8195, p_id)) 263 + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con2); 264 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_2, 265 + reg, 0x3FFFFFFF); 266 + 267 + if (CFG_CHECK(MT8195, p_id)) 268 + reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con3); 269 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_3, 270 + reg, 0x0F3F003F); 271 + 272 + rdma_config_done: 190 273 return 0; 191 274 } 192 275 ··· 302 197 /* Set Y pixel offset */ 303 198 if (CFG_CHECK(MT8183, p_id)) 304 199 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]); 200 + else if (CFG_CHECK(MT8195, p_id)) 201 + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[0]); 305 202 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0, 306 203 reg, 0xFFFFFFFF); 307 204 ··· 312 205 if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) { 313 206 if (CFG_CHECK(MT8183, p_id)) 314 207 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset_0_p); 208 + else if (CFG_CHECK(MT8195, p_id)) 209 + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset_0_p); 315 210 MM_REG_WRITE(cmd, subsys_id, base, 316 211 MDP_RDMA_SRC_OFFSET_0_P, 317 212 reg, 0xFFFFFFFF); ··· 323 214 /* Set U pixel offset */ 324 215 if (CFG_CHECK(MT8183, p_id)) 325 216 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[1]); 217 + else if (CFG_CHECK(MT8195, p_id)) 218 + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[1]); 326 219 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1, 327 220 reg, 0xFFFFFFFF); 221 + 328 222 /* Set V pixel offset */ 329 223 if (CFG_CHECK(MT8183, p_id)) 330 224 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[2]); 225 + else if (CFG_CHECK(MT8195, p_id)) 226 + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[2]); 331 227 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_2, 332 228 reg, 0xFFFFFFFF); 229 + 333 230 /* Set source size */ 334 231 if (CFG_CHECK(MT8183, p_id)) 335 232 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].src); 233 + else if (CFG_CHECK(MT8195, p_id)) 234 + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].src); 336 235 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, reg, 337 236 0x1FFF1FFF); 237 + 338 238 /* Set target size */ 339 239 if (CFG_CHECK(MT8183, p_id)) 340 240 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip); 241 + else if (CFG_CHECK(MT8195, p_id)) 242 + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip); 341 243 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_CLIP_SIZE, 342 244 reg, 0x1FFF1FFF); 245 + 343 246 /* Set crop offset */ 344 247 if (CFG_CHECK(MT8183, p_id)) 345 248 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip_ofst); 249 + else if (CFG_CHECK(MT8195, p_id)) 250 + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip_ofst); 346 251 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1, 347 252 reg, 0x003F001F); 348 253 349 254 if (CFG_CHECK(MT8183, p_id)) { 350 255 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); 351 256 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); 257 + } else if (CFG_CHECK(MT8195, p_id)) { 258 + csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); 259 + csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); 352 260 } 353 261 if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only) 354 262 if ((csf_r - csf_l + 1) > 320) ··· 415 289 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16)); 416 290 /* Enable RSZ */ 417 291 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0)); 292 + 293 + if (CFG_CHECK(MT8195, p_id)) { 294 + struct device *dev; 295 + 296 + dev = ctx->comp->mdp_dev->mm_subsys[MDP_MM_SUBSYS_1].mmsys; 297 + mtk_mmsys_vpp_rsz_dcm_config(dev, true, NULL); 298 + } 299 + 418 300 return 0; 419 301 } 420 302 ··· 430 296 struct mdp_cmdq_cmd *cmd, 431 297 const struct v4l2_rect *compose) 432 298 { 299 + const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); 433 300 phys_addr_t base = ctx->comp->reg_base; 434 301 u8 subsys_id = ctx->comp->subsys_id; 435 302 bool bypass = FALSE; 436 303 u32 reg = 0; 437 304 305 + if (mdp_cfg && mdp_cfg->rsz_etc_control) 306 + MM_REG_WRITE(cmd, subsys_id, base, RSZ_ETC_CONTROL, 0x0, 0xFFFFFFFF); 307 + 438 308 if (CFG_CHECK(MT8183, p_id)) 439 309 bypass = CFG_COMP(MT8183, ctx->param, frame.bypass); 310 + else if (CFG_CHECK(MT8195, p_id)) 311 + bypass = CFG_COMP(MT8195, ctx->param, frame.bypass); 440 312 441 313 if (bypass) { 442 314 /* Disable RSZ */ ··· 452 312 453 313 if (CFG_CHECK(MT8183, p_id)) 454 314 reg = CFG_COMP(MT8183, ctx->param, rsz.control1); 315 + else if (CFG_CHECK(MT8195, p_id)) 316 + reg = CFG_COMP(MT8195, ctx->param, rsz.control1); 455 317 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, reg, 456 318 0x03FFFDF3); 319 + 457 320 if (CFG_CHECK(MT8183, p_id)) 458 321 reg = CFG_COMP(MT8183, ctx->param, rsz.control2); 322 + else if (CFG_CHECK(MT8195, p_id)) 323 + reg = CFG_COMP(MT8195, ctx->param, rsz.control2); 459 324 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 460 325 0x0FFFC290); 326 + 461 327 if (CFG_CHECK(MT8183, p_id)) 462 328 reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_x); 329 + else if (CFG_CHECK(MT8195, p_id)) 330 + reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_x); 463 331 MM_REG_WRITE(cmd, subsys_id, base, PRZ_HORIZONTAL_COEFF_STEP, 464 332 reg, 0x007FFFFF); 333 + 465 334 if (CFG_CHECK(MT8183, p_id)) 466 335 reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_y); 336 + else if (CFG_CHECK(MT8195, p_id)) 337 + reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_y); 467 338 MM_REG_WRITE(cmd, subsys_id, base, PRZ_VERTICAL_COEFF_STEP, 468 339 reg, 0x007FFFFF); 340 + 469 341 return 0; 470 342 } 471 343 ··· 489 337 u8 subsys_id = ctx->comp->subsys_id; 490 338 u32 csf_l = 0, csf_r = 0; 491 339 u32 reg = 0; 340 + u32 id; 492 341 493 342 if (CFG_CHECK(MT8183, p_id)) 494 343 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].control2); 344 + else if (CFG_CHECK(MT8195, p_id)) 345 + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].control2); 495 346 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 496 347 0x00003800); 348 + 497 349 if (CFG_CHECK(MT8183, p_id)) 498 350 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].src); 351 + else if (CFG_CHECK(MT8195, p_id)) 352 + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].src); 499 353 MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, reg, 500 354 0xFFFFFFFF); 501 355 502 356 if (CFG_CHECK(MT8183, p_id)) { 503 357 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); 504 358 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); 359 + } else if (CFG_CHECK(MT8195, p_id)) { 360 + csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); 361 + csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); 505 362 } 506 363 if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) 507 364 if ((csf_r - csf_l + 1) <= 16) ··· 519 358 520 359 if (CFG_CHECK(MT8183, p_id)) 521 360 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left); 361 + else if (CFG_CHECK(MT8195, p_id)) 362 + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left); 522 363 MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET, 523 364 reg, 0xFFFF); 365 + 524 366 if (CFG_CHECK(MT8183, p_id)) 525 367 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left_subpix); 368 + else if (CFG_CHECK(MT8195, p_id)) 369 + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left_subpix); 526 370 MM_REG_WRITE(cmd, subsys_id, 527 371 base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET, 528 372 reg, 0x1FFFFF); 373 + 529 374 if (CFG_CHECK(MT8183, p_id)) 530 375 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top); 376 + else if (CFG_CHECK(MT8195, p_id)) 377 + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top); 531 378 MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET, 532 379 reg, 0xFFFF); 380 + 533 381 if (CFG_CHECK(MT8183, p_id)) 534 382 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top_subpix); 383 + else if (CFG_CHECK(MT8195, p_id)) 384 + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top_subpix); 535 385 MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET, 536 386 reg, 0x1FFFFF); 387 + 537 388 if (CFG_CHECK(MT8183, p_id)) 538 389 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left); 390 + else if (CFG_CHECK(MT8195, p_id)) 391 + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left); 539 392 MM_REG_WRITE(cmd, subsys_id, 540 393 base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET, 541 394 reg, 0xFFFF); 395 + 542 396 if (CFG_CHECK(MT8183, p_id)) 543 397 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left_subpix); 398 + else if (CFG_CHECK(MT8195, p_id)) 399 + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left_subpix); 544 400 MM_REG_WRITE(cmd, subsys_id, 545 401 base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET, 546 402 reg, 0x1FFFFF); 547 403 548 404 if (CFG_CHECK(MT8183, p_id)) 549 405 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].clip); 406 + else if (CFG_CHECK(MT8195, p_id)) 407 + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].clip); 550 408 MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, reg, 551 409 0xFFFFFFFF); 552 410 411 + if (CFG_CHECK(MT8195, p_id)) { 412 + struct device *dev; 413 + struct mdp_comp *merge; 414 + const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data; 415 + enum mtk_mdp_comp_id public_id = ctx->comp->public_id; 416 + 417 + switch (public_id) { 418 + case MDP_COMP_RSZ2: 419 + merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE2]; 420 + break; 421 + case MDP_COMP_RSZ3: 422 + merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE3]; 423 + break; 424 + default: 425 + goto rsz_subfrm_done; 426 + } 427 + 428 + if (CFG_CHECK(MT8195, p_id)) 429 + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].rsz_switch); 430 + 431 + id = data->comp_data[public_id].match.alias_id; 432 + dev = ctx->comp->mdp_dev->mm_subsys[MDP_MM_SUBSYS_1].mmsys; 433 + mtk_mmsys_vpp_rsz_merge_config(dev, id, reg, NULL); 434 + 435 + if (CFG_CHECK(MT8195, p_id)) 436 + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].merge_cfg); 437 + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, 438 + MDP_MERGE_CFG_0, reg, 0xFFFFFFFF); 439 + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, 440 + MDP_MERGE_CFG_4, reg, 0xFFFFFFFF); 441 + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, 442 + MDP_MERGE_CFG_24, reg, 0xFFFFFFFF); 443 + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, 444 + MDP_MERGE_CFG_25, reg, 0xFFFFFFFF); 445 + 446 + /* Bypass mode */ 447 + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, 448 + MDP_MERGE_CFG_12, BIT(0), 0xFFFFFFFF); 449 + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, 450 + MDP_MERGE_ENABLE, BIT(0), 0xFFFFFFFF); 451 + } 452 + 453 + rsz_subfrm_done: 553 454 return 0; 554 455 } 555 456 ··· 628 405 if (CFG_CHECK(MT8183, p_id)) { 629 406 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); 630 407 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); 408 + } else if (CFG_CHECK(MT8195, p_id)) { 409 + csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); 410 + csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); 631 411 } 632 412 633 413 if ((csf_r - csf_l + 1) <= 16) ··· 657 431 /* Reset WROT */ 658 432 MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0)); 659 433 MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, BIT(0), BIT(0)); 434 + 435 + /* Reset setting */ 436 + if (CFG_CHECK(MT8195, p_id)) 437 + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, 0x0, 0xFFFFFFFF); 438 + 660 439 MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0)); 661 440 MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x0, BIT(0)); 662 441 return 0; ··· 679 448 /* Write frame base address */ 680 449 if (CFG_CHECK(MT8183, p_id)) 681 450 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]); 451 + else if (CFG_CHECK(MT8195, p_id)) 452 + reg = CFG_COMP(MT8195, ctx->param, wrot.iova[0]); 682 453 MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, reg, 683 454 0xFFFFFFFF); 455 + 684 456 if (CFG_CHECK(MT8183, p_id)) 685 457 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[1]); 458 + else if (CFG_CHECK(MT8195, p_id)) 459 + reg = CFG_COMP(MT8195, ctx->param, wrot.iova[1]); 686 460 MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, reg, 687 461 0xFFFFFFFF); 462 + 688 463 if (CFG_CHECK(MT8183, p_id)) 689 464 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[2]); 465 + else if (CFG_CHECK(MT8195, p_id)) 466 + reg = CFG_COMP(MT8195, ctx->param, wrot.iova[2]); 690 467 MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, reg, 691 468 0xFFFFFFFF); 469 + 470 + if (mdp_cfg && mdp_cfg->wrot_support_10bit) { 471 + if (CFG_CHECK(MT8195, p_id)) 472 + reg = CFG_COMP(MT8195, ctx->param, wrot.scan_10bit); 473 + MM_REG_WRITE(cmd, subsys_id, base, VIDO_SCAN_10BIT, 474 + reg, 0x0000000F); 475 + 476 + if (CFG_CHECK(MT8195, p_id)) 477 + reg = CFG_COMP(MT8195, ctx->param, wrot.pending_zero); 478 + MM_REG_WRITE(cmd, subsys_id, base, VIDO_PENDING_ZERO, 479 + reg, 0x04000000); 480 + } 481 + 482 + if (CFG_CHECK(MT8195, p_id)) { 483 + reg = CFG_COMP(MT8195, ctx->param, wrot.bit_number); 484 + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL_2, 485 + reg, 0x00000007); 486 + } 487 + 692 488 /* Write frame related registers */ 693 489 if (CFG_CHECK(MT8183, p_id)) 694 490 reg = CFG_COMP(MT8183, ctx->param, wrot.control); 491 + else if (CFG_CHECK(MT8195, p_id)) 492 + reg = CFG_COMP(MT8195, ctx->param, wrot.control); 695 493 MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, reg, 696 494 0xF131510F); 495 + 496 + /* Write pre-ultra threshold */ 497 + if (CFG_CHECK(MT8195, p_id)) { 498 + reg = CFG_COMP(MT8195, ctx->param, wrot.pre_ultra); 499 + MM_REG_WRITE(cmd, subsys_id, base, VIDO_DMA_PREULTRA, reg, 500 + 0x00FFFFFF); 501 + } 502 + 697 503 /* Write frame Y pitch */ 698 504 if (CFG_CHECK(MT8183, p_id)) 699 505 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]); 506 + else if (CFG_CHECK(MT8195, p_id)) 507 + reg = CFG_COMP(MT8195, ctx->param, wrot.stride[0]); 700 508 MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, reg, 701 509 0x0000FFFF); 510 + 702 511 /* Write frame UV pitch */ 703 512 if (CFG_CHECK(MT8183, p_id)) 704 513 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[1]); 514 + else if (CFG_CHECK(MT8195, p_id)) 515 + reg = CFG_COMP(MT8195, ctx->param, wrot.stride[1]); 705 516 MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, reg, 706 517 0xFFFF); 518 + 707 519 if (CFG_CHECK(MT8183, p_id)) 708 520 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[2]); 521 + else if (CFG_CHECK(MT8195, p_id)) 522 + reg = CFG_COMP(MT8195, ctx->param, wrot.stride[2]); 709 523 MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, reg, 710 524 0xFFFF); 525 + 711 526 /* Write matrix control */ 712 527 if (CFG_CHECK(MT8183, p_id)) 713 528 reg = CFG_COMP(MT8183, ctx->param, wrot.mat_ctrl); 529 + else if (CFG_CHECK(MT8195, p_id)) 530 + reg = CFG_COMP(MT8195, ctx->param, wrot.mat_ctrl); 714 531 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3); 715 532 716 533 /* Set the fixed ALPHA as 0xFF */ 717 534 MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000, 718 535 0xFF000000); 536 + 719 537 /* Set VIDO_EOL_SEL */ 720 538 MM_REG_WRITE(cmd, subsys_id, base, VIDO_RSV_1, BIT(31), BIT(31)); 539 + 721 540 /* Set VIDO_FIFO_TEST */ 722 541 if (CFG_CHECK(MT8183, p_id)) 723 542 reg = CFG_COMP(MT8183, ctx->param, wrot.fifo_test); 543 + else if (CFG_CHECK(MT8195, p_id)) 544 + reg = CFG_COMP(MT8195, ctx->param, wrot.fifo_test); 545 + 724 546 if (reg != 0) 725 547 MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST, 726 548 reg, 0xFFF); 549 + 727 550 /* Filter enable */ 728 551 if (mdp_cfg && mdp_cfg->wrot_filter_constraint) { 729 552 if (CFG_CHECK(MT8183, p_id)) 730 553 reg = CFG_COMP(MT8183, ctx->param, wrot.filter); 554 + else if (CFG_CHECK(MT8195, p_id)) 555 + reg = CFG_COMP(MT8195, ctx->param, wrot.filter); 731 556 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 732 557 reg, 0x77); 558 + 559 + /* Turn off WROT DMA DCM */ 560 + if (CFG_CHECK(MT8195, p_id)) 561 + MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 562 + (0x1 << 23) + (0x1 << 20), 0x900000); 733 563 } 734 564 735 565 return 0; ··· 806 514 /* Write Y pixel offset */ 807 515 if (CFG_CHECK(MT8183, p_id)) 808 516 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]); 517 + else if (CFG_CHECK(MT8195, p_id)) 518 + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[0]); 809 519 MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR, 810 520 reg, 0x0FFFFFFF); 521 + 811 522 /* Write U pixel offset */ 812 523 if (CFG_CHECK(MT8183, p_id)) 813 524 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[1]); 525 + else if (CFG_CHECK(MT8195, p_id)) 526 + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[1]); 814 527 MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_C, 815 528 reg, 0x0FFFFFFF); 529 + 816 530 /* Write V pixel offset */ 817 531 if (CFG_CHECK(MT8183, p_id)) 818 532 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[2]); 533 + else if (CFG_CHECK(MT8195, p_id)) 534 + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[2]); 819 535 MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_V, 820 536 reg, 0x0FFFFFFF); 537 + 821 538 /* Write source size */ 822 539 if (CFG_CHECK(MT8183, p_id)) 823 540 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].src); 541 + else if (CFG_CHECK(MT8195, p_id)) 542 + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].src); 824 543 MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, reg, 825 544 0x1FFF1FFF); 545 + 826 546 /* Write target size */ 827 547 if (CFG_CHECK(MT8183, p_id)) 828 548 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip); 549 + else if (CFG_CHECK(MT8195, p_id)) 550 + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip); 829 551 MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, reg, 830 552 0x1FFF1FFF); 553 + 831 554 if (CFG_CHECK(MT8183, p_id)) 832 555 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip_ofst); 556 + else if (CFG_CHECK(MT8195, p_id)) 557 + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip_ofst); 833 558 MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, reg, 834 559 0x1FFF1FFF); 835 560 836 561 if (CFG_CHECK(MT8183, p_id)) 837 562 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].main_buf); 563 + else if (CFG_CHECK(MT8195, p_id)) 564 + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].main_buf); 838 565 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 839 566 reg, 0x1FFF7F00); 840 567 ··· 1019 708 .wait_comp_event = wait_wdma_event, 1020 709 }; 1021 710 711 + static int reset_luma_hist(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) 712 + { 713 + const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); 714 + phys_addr_t base = ctx->comp->reg_base; 715 + u16 subsys_id = ctx->comp->subsys_id; 716 + u32 hist_num, i; 717 + 718 + if (!mdp_cfg) 719 + return -EINVAL; 720 + 721 + hist_num = mdp_cfg->tdshp_hist_num; 722 + 723 + /* Reset histogram */ 724 + for (i = 0; i <= hist_num; i++) 725 + MM_REG_WRITE_MASK(cmd, subsys_id, base, 726 + (MDP_LUMA_HIST_INIT + (i << 2)), 727 + 0, 0xFFFFFFFF); 728 + 729 + if (mdp_cfg->tdshp_constrain) 730 + MM_REG_WRITE(cmd, subsys_id, base, 731 + MDP_DC_TWO_D_W1_RESULT_INIT, 0, 0xFFFFFFFF); 732 + 733 + if (mdp_cfg->tdshp_contour) 734 + for (i = 0; i < hist_num; i++) 735 + MM_REG_WRITE_MASK(cmd, subsys_id, base, 736 + (MDP_CONTOUR_HIST_INIT + (i << 2)), 737 + 0, 0xFFFFFFFF); 738 + 739 + return 0; 740 + } 741 + 742 + static int init_tdshp(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) 743 + { 744 + phys_addr_t base = ctx->comp->reg_base; 745 + u16 subsys_id = ctx->comp->subsys_id; 746 + 747 + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CTRL, BIT(0), BIT(0)); 748 + /* Enable FIFO */ 749 + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, BIT(1), BIT(1)); 750 + 751 + return reset_luma_hist(ctx, cmd); 752 + } 753 + 754 + static int config_tdshp_frame(struct mdp_comp_ctx *ctx, 755 + struct mdp_cmdq_cmd *cmd, 756 + const struct v4l2_rect *compose) 757 + { 758 + phys_addr_t base = ctx->comp->reg_base; 759 + u16 subsys_id = ctx->comp->subsys_id; 760 + u32 reg = 0; 761 + 762 + if (CFG_CHECK(MT8195, p_id)) 763 + reg = CFG_COMP(MT8195, ctx->param, tdshp.cfg); 764 + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, reg, BIT(0)); 765 + 766 + return 0; 767 + } 768 + 769 + static int config_tdshp_subfrm(struct mdp_comp_ctx *ctx, 770 + struct mdp_cmdq_cmd *cmd, u32 index) 771 + { 772 + phys_addr_t base = ctx->comp->reg_base; 773 + u16 subsys_id = ctx->comp->subsys_id; 774 + u32 reg = 0; 775 + 776 + if (CFG_CHECK(MT8195, p_id)) 777 + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].src); 778 + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_INPUT_SIZE, 779 + reg, MDP_TDSHP_INPUT_SIZE_MASK); 780 + 781 + if (CFG_CHECK(MT8195, p_id)) 782 + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip_ofst); 783 + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_OFFSET, 784 + reg, 0x00FF00FF); 785 + 786 + if (CFG_CHECK(MT8195, p_id)) 787 + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip); 788 + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_SIZE, 789 + reg, MDP_TDSHP_OUTPUT_SIZE_MASK); 790 + 791 + if (CFG_CHECK(MT8195, p_id)) 792 + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_0); 793 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_00, reg, 0xFFFFFFFF); 794 + 795 + if (CFG_CHECK(MT8195, p_id)) 796 + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_1); 797 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_01, reg, 0xFFFFFFFF); 798 + 799 + return 0; 800 + } 801 + 802 + static const struct mdp_comp_ops tdshp_ops = { 803 + .get_comp_flag = get_comp_flag, 804 + .init_comp = init_tdshp, 805 + .config_frame = config_tdshp_frame, 806 + .config_subfrm = config_tdshp_subfrm, 807 + }; 808 + 809 + static int init_color(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) 810 + { 811 + phys_addr_t base = ctx->comp->reg_base; 812 + u16 subsys_id = ctx->comp->subsys_id; 813 + 814 + MM_REG_WRITE(cmd, subsys_id, base, 815 + MDP_COLOR_START, 0x1, BIT(1) | BIT(0)); 816 + MM_REG_WRITE(cmd, subsys_id, base, 817 + MDP_COLOR_WIN_X_MAIN, 0xFFFF0000, 0xFFFFFFFF); 818 + MM_REG_WRITE(cmd, subsys_id, base, 819 + MDP_COLOR_WIN_Y_MAIN, 0xFFFF0000, 0xFFFFFFFF); 820 + 821 + /* Reset color matrix */ 822 + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM1_EN, 0x0, BIT(0)); 823 + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM2_EN, 0x0, BIT(0)); 824 + 825 + /* Enable interrupt */ 826 + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTEN, 0x7, 0x7); 827 + 828 + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_OUT_SEL, 0x333, 0x333); 829 + 830 + return 0; 831 + } 832 + 833 + static int config_color_frame(struct mdp_comp_ctx *ctx, 834 + struct mdp_cmdq_cmd *cmd, 835 + const struct v4l2_rect *compose) 836 + { 837 + phys_addr_t base = ctx->comp->reg_base; 838 + u16 subsys_id = ctx->comp->subsys_id; 839 + u32 reg = 0; 840 + 841 + if (CFG_CHECK(MT8195, p_id)) 842 + reg = CFG_COMP(MT8195, ctx->param, color.start); 843 + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_START, 844 + reg, MDP_COLOR_START_MASK); 845 + 846 + return 0; 847 + } 848 + 849 + static int config_color_subfrm(struct mdp_comp_ctx *ctx, 850 + struct mdp_cmdq_cmd *cmd, u32 index) 851 + { 852 + phys_addr_t base = ctx->comp->reg_base; 853 + u16 subsys_id = ctx->comp->subsys_id; 854 + u32 reg = 0; 855 + 856 + if (CFG_CHECK(MT8195, p_id)) 857 + reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_hsize); 858 + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_WIDTH, 859 + reg, 0x00003FFF); 860 + 861 + if (CFG_CHECK(MT8195, p_id)) 862 + reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_vsize); 863 + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_HEIGHT, 864 + reg, 0x00003FFF); 865 + 866 + return 0; 867 + } 868 + 869 + static const struct mdp_comp_ops color_ops = { 870 + .get_comp_flag = get_comp_flag, 871 + .init_comp = init_color, 872 + .config_frame = config_color_frame, 873 + .config_subfrm = config_color_subfrm, 874 + }; 875 + 1022 876 static int init_ccorr(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) 1023 877 { 1024 878 phys_addr_t base = ctx->comp->reg_base; ··· 1225 749 .config_subfrm = config_ccorr_subfrm, 1226 750 }; 1227 751 752 + static int init_aal(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) 753 + { 754 + phys_addr_t base = ctx->comp->reg_base; 755 + u16 subsys_id = ctx->comp->subsys_id; 756 + 757 + /* Always set MDP_AAL enable to 1 */ 758 + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_EN, BIT(0), BIT(0)); 759 + 760 + return 0; 761 + } 762 + 763 + static int config_aal_frame(struct mdp_comp_ctx *ctx, 764 + struct mdp_cmdq_cmd *cmd, 765 + const struct v4l2_rect *compose) 766 + { 767 + phys_addr_t base = ctx->comp->reg_base; 768 + u16 subsys_id = ctx->comp->subsys_id; 769 + u32 reg = 0; 770 + 771 + if (CFG_CHECK(MT8195, p_id)) 772 + reg = CFG_COMP(MT8195, ctx->param, aal.cfg_main); 773 + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG_MAIN, reg, BIT(7)); 774 + 775 + if (CFG_CHECK(MT8195, p_id)) 776 + reg = CFG_COMP(MT8195, ctx->param, aal.cfg); 777 + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG, reg, BIT(0)); 778 + 779 + return 0; 780 + } 781 + 782 + static int config_aal_subfrm(struct mdp_comp_ctx *ctx, 783 + struct mdp_cmdq_cmd *cmd, u32 index) 784 + { 785 + phys_addr_t base = ctx->comp->reg_base; 786 + u16 subsys_id = ctx->comp->subsys_id; 787 + u32 reg = 0; 788 + 789 + if (CFG_CHECK(MT8195, p_id)) 790 + reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].src); 791 + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_SIZE, 792 + reg, MDP_AAL_SIZE_MASK); 793 + 794 + if (CFG_CHECK(MT8195, p_id)) 795 + reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip_ofst); 796 + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_OFFSET, 797 + reg, 0x00FF00FF); 798 + 799 + if (CFG_CHECK(MT8195, p_id)) 800 + reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip); 801 + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_SIZE, 802 + reg, MDP_AAL_OUTPUT_SIZE_MASK); 803 + 804 + return 0; 805 + } 806 + 807 + static const struct mdp_comp_ops aal_ops = { 808 + .get_comp_flag = get_comp_flag, 809 + .init_comp = init_aal, 810 + .config_frame = config_aal_frame, 811 + .config_subfrm = config_aal_subfrm, 812 + }; 813 + 814 + static int init_hdr(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) 815 + { 816 + phys_addr_t base = ctx->comp->reg_base; 817 + u16 subsys_id = ctx->comp->subsys_id; 818 + 819 + /* Always set MDP_HDR enable to 1 */ 820 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, BIT(0), BIT(0)); 821 + 822 + return 0; 823 + } 824 + 825 + static int config_hdr_frame(struct mdp_comp_ctx *ctx, 826 + struct mdp_cmdq_cmd *cmd, 827 + const struct v4l2_rect *compose) 828 + { 829 + phys_addr_t base = ctx->comp->reg_base; 830 + u16 subsys_id = ctx->comp->subsys_id; 831 + u32 reg = 0; 832 + 833 + if (CFG_CHECK(MT8195, p_id)) 834 + reg = CFG_COMP(MT8195, ctx->param, hdr.top); 835 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(29) | BIT(28)); 836 + 837 + if (CFG_CHECK(MT8195, p_id)) 838 + reg = CFG_COMP(MT8195, ctx->param, hdr.relay); 839 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_RELAY, reg, BIT(0)); 840 + 841 + return 0; 842 + } 843 + 844 + static int config_hdr_subfrm(struct mdp_comp_ctx *ctx, 845 + struct mdp_cmdq_cmd *cmd, u32 index) 846 + { 847 + phys_addr_t base = ctx->comp->reg_base; 848 + u16 subsys_id = ctx->comp->subsys_id; 849 + u32 reg = 0; 850 + 851 + if (CFG_CHECK(MT8195, p_id)) 852 + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].win_size); 853 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TILE_POS, 854 + reg, MDP_HDR_TILE_POS_MASK); 855 + 856 + if (CFG_CHECK(MT8195, p_id)) 857 + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].src); 858 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_0, reg, 0x1FFF1FFF); 859 + 860 + if (CFG_CHECK(MT8195, p_id)) 861 + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst0); 862 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_1, reg, 0x1FFF1FFF); 863 + 864 + if (CFG_CHECK(MT8195, p_id)) 865 + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst1); 866 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_2, reg, 0x1FFF1FFF); 867 + 868 + if (CFG_CHECK(MT8195, p_id)) 869 + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_0); 870 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_0, reg, 0x00003FFF); 871 + 872 + if (CFG_CHECK(MT8195, p_id)) 873 + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_1); 874 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_1, reg, 0x00003FFF); 875 + 876 + if (CFG_CHECK(MT8195, p_id)) 877 + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hdr_top); 878 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(6) | BIT(5)); 879 + 880 + /* Enable histogram */ 881 + if (CFG_CHECK(MT8195, p_id)) 882 + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_addr); 883 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_ADDR, reg, BIT(9)); 884 + 885 + return 0; 886 + } 887 + 888 + static const struct mdp_comp_ops hdr_ops = { 889 + .get_comp_flag = get_comp_flag, 890 + .init_comp = init_hdr, 891 + .config_frame = config_hdr_frame, 892 + .config_subfrm = config_hdr_subfrm, 893 + }; 894 + 895 + static int init_fg(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) 896 + { 897 + phys_addr_t base = ctx->comp->reg_base; 898 + u16 subsys_id = ctx->comp->subsys_id; 899 + 900 + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, BIT(2), BIT(2)); 901 + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, 0x0, BIT(2)); 902 + 903 + return 0; 904 + } 905 + 906 + static int config_fg_frame(struct mdp_comp_ctx *ctx, 907 + struct mdp_cmdq_cmd *cmd, 908 + const struct v4l2_rect *compose) 909 + { 910 + phys_addr_t base = ctx->comp->reg_base; 911 + u16 subsys_id = ctx->comp->subsys_id; 912 + u32 reg = 0; 913 + 914 + if (CFG_CHECK(MT8195, p_id)) 915 + reg = CFG_COMP(MT8195, ctx->param, fg.ctrl_0); 916 + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CTRL_0, reg, BIT(0)); 917 + 918 + if (CFG_CHECK(MT8195, p_id)) 919 + reg = CFG_COMP(MT8195, ctx->param, fg.ck_en); 920 + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CK_EN, reg, 0x7); 921 + 922 + return 0; 923 + } 924 + 925 + static int config_fg_subfrm(struct mdp_comp_ctx *ctx, 926 + struct mdp_cmdq_cmd *cmd, u32 index) 927 + { 928 + phys_addr_t base = ctx->comp->reg_base; 929 + u16 subsys_id = ctx->comp->subsys_id; 930 + u32 reg = 0; 931 + 932 + if (CFG_CHECK(MT8195, p_id)) 933 + reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_0); 934 + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_0, reg, 0xFFFFFFFF); 935 + 936 + if (CFG_CHECK(MT8195, p_id)) 937 + reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_1); 938 + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_1, reg, 0xFFFFFFFF); 939 + 940 + return 0; 941 + } 942 + 943 + static const struct mdp_comp_ops fg_ops = { 944 + .get_comp_flag = get_comp_flag, 945 + .init_comp = init_fg, 946 + .config_frame = config_fg_frame, 947 + .config_subfrm = config_fg_subfrm, 948 + }; 949 + 950 + static int init_ovl(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) 951 + { 952 + phys_addr_t base = ctx->comp->reg_base; 953 + u16 subsys_id = ctx->comp->subsys_id; 954 + 955 + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_EN, 956 + BIT(0), MDP_OVL_EN_MASK); 957 + 958 + /* Set to relay mode */ 959 + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, 960 + BIT(9), MDP_OVL_SRC_CON_MASK); 961 + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_DP_CON, 962 + BIT(0), MDP_OVL_DP_CON_MASK); 963 + 964 + return 0; 965 + } 966 + 967 + static int config_ovl_frame(struct mdp_comp_ctx *ctx, 968 + struct mdp_cmdq_cmd *cmd, 969 + const struct v4l2_rect *compose) 970 + { 971 + phys_addr_t base = ctx->comp->reg_base; 972 + u16 subsys_id = ctx->comp->subsys_id; 973 + u32 reg = 0; 974 + 975 + if (CFG_CHECK(MT8195, p_id)) 976 + reg = CFG_COMP(MT8195, ctx->param, ovl.L0_con); 977 + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_CON, reg, BIT(29) | BIT(28)); 978 + 979 + if (CFG_CHECK(MT8195, p_id)) 980 + reg = CFG_COMP(MT8195, ctx->param, ovl.src_con); 981 + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, reg, BIT(0)); 982 + 983 + return 0; 984 + } 985 + 986 + static int config_ovl_subfrm(struct mdp_comp_ctx *ctx, 987 + struct mdp_cmdq_cmd *cmd, u32 index) 988 + { 989 + phys_addr_t base = ctx->comp->reg_base; 990 + u16 subsys_id = ctx->comp->subsys_id; 991 + u32 reg = 0; 992 + 993 + if (CFG_CHECK(MT8195, p_id)) 994 + reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].L0_src_size); 995 + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_SRC_SIZE, 996 + reg, MDP_OVL_L0_SRC_SIZE_MASK); 997 + 998 + /* Setup output size */ 999 + if (CFG_CHECK(MT8195, p_id)) 1000 + reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].roi_size); 1001 + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_ROI_SIZE, 1002 + reg, MDP_OVL_ROI_SIZE_MASK); 1003 + 1004 + return 0; 1005 + } 1006 + 1007 + static const struct mdp_comp_ops ovl_ops = { 1008 + .get_comp_flag = get_comp_flag, 1009 + .init_comp = init_ovl, 1010 + .config_frame = config_ovl_frame, 1011 + .config_subfrm = config_ovl_subfrm, 1012 + }; 1013 + 1014 + static int init_pad(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) 1015 + { 1016 + phys_addr_t base = ctx->comp->reg_base; 1017 + u16 subsys_id = ctx->comp->subsys_id; 1018 + 1019 + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_CON, 1020 + BIT(1), MDP_PAD_CON_MASK); 1021 + /* Reset */ 1022 + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_W_SIZE, 1023 + 0, MDP_PAD_W_SIZE_MASK); 1024 + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_H_SIZE, 1025 + 0, MDP_PAD_H_SIZE_MASK); 1026 + 1027 + return 0; 1028 + } 1029 + 1030 + static int config_pad_subfrm(struct mdp_comp_ctx *ctx, 1031 + struct mdp_cmdq_cmd *cmd, u32 index) 1032 + { 1033 + phys_addr_t base = ctx->comp->reg_base; 1034 + u16 subsys_id = ctx->comp->subsys_id; 1035 + u32 reg = 0; 1036 + 1037 + if (CFG_CHECK(MT8195, p_id)) 1038 + reg = CFG_COMP(MT8195, ctx->param, pad.subfrms[index].pic_size); 1039 + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_PIC_SIZE, 1040 + reg, MDP_PAD_PIC_SIZE_MASK); 1041 + 1042 + return 0; 1043 + } 1044 + 1045 + static const struct mdp_comp_ops pad_ops = { 1046 + .get_comp_flag = get_comp_flag, 1047 + .init_comp = init_pad, 1048 + .config_subfrm = config_pad_subfrm, 1049 + }; 1050 + 1228 1051 static const struct mdp_comp_ops *mdp_comp_ops[MDP_COMP_TYPE_COUNT] = { 1229 1052 [MDP_COMP_TYPE_RDMA] = &rdma_ops, 1230 1053 [MDP_COMP_TYPE_RSZ] = &rsz_ops, 1231 1054 [MDP_COMP_TYPE_WROT] = &wrot_ops, 1232 1055 [MDP_COMP_TYPE_WDMA] = &wdma_ops, 1056 + [MDP_COMP_TYPE_TDSHP] = &tdshp_ops, 1057 + [MDP_COMP_TYPE_COLOR] = &color_ops, 1233 1058 [MDP_COMP_TYPE_CCORR] = &ccorr_ops, 1059 + [MDP_COMP_TYPE_AAL] = &aal_ops, 1060 + [MDP_COMP_TYPE_HDR] = &hdr_ops, 1061 + [MDP_COMP_TYPE_FG] = &fg_ops, 1062 + [MDP_COMP_TYPE_OVL] = &ovl_ops, 1063 + [MDP_COMP_TYPE_PAD] = &pad_ops, 1234 1064 }; 1235 1065 1236 1066 static const struct of_device_id mdp_comp_dt_ids[] __maybe_unused = { ··· 2035 1253 2036 1254 if (CFG_CHECK(MT8183, p_id)) 2037 1255 arg = CFG_COMP(MT8183, param, type); 1256 + else if (CFG_CHECK(MT8195, p_id)) 1257 + arg = CFG_COMP(MT8195, param, type); 2038 1258 else 2039 1259 return -EINVAL; 2040 1260 public_id = mdp_cfg_get_id_public(mdp, arg); ··· 2054 1270 ctx->param = param; 2055 1271 if (CFG_CHECK(MT8183, p_id)) 2056 1272 arg = CFG_COMP(MT8183, param, input); 1273 + else if (CFG_CHECK(MT8195, p_id)) 1274 + arg = CFG_COMP(MT8195, param, input); 2057 1275 else 2058 1276 return -EINVAL; 2059 1277 ctx->input = &frame->inputs[arg]; 2060 1278 if (CFG_CHECK(MT8183, p_id)) 2061 1279 idx = CFG_COMP(MT8183, param, num_outputs); 1280 + else if (CFG_CHECK(MT8195, p_id)) 1281 + idx = CFG_COMP(MT8195, param, num_outputs); 2062 1282 else 2063 1283 return -EINVAL; 2064 1284 for (i = 0; i < idx; i++) { 2065 1285 if (CFG_CHECK(MT8183, p_id)) 2066 1286 arg = CFG_COMP(MT8183, param, outputs[i]); 1287 + else if (CFG_CHECK(MT8195, p_id)) 1288 + arg = CFG_COMP(MT8195, param, outputs[i]); 2067 1289 else 2068 1290 return -EINVAL; 2069 1291 ctx->outputs[i] = &frame->outputs[arg];