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arm64: versal-net: Describe L1/L2/L3/LLC caches

Add missing cache layout description.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f740bf2d0af1e7e50d76196ec050c0fdbeceb049.1757338426.git.michal.simek@amd.com

Michal Simek 0e819604 21ad89cf

+408
+408
arch/arm64/boot/dts/xilinx/versal-net.dtsi
··· 104 104 reg = <0>; 105 105 operating-points-v2 = <&cpu_opp_table>; 106 106 cpu-idle-states = <&CPU_SLEEP_0>; 107 + d-cache-size = <0x10000>; /* 64kB */ 108 + d-cache-line-size = <64>; 109 + /* 4 ways set associativity */ 110 + /* cache_size / (line_size / associativity) */ 111 + d-cache-sets = <256>; 112 + i-cache-size = <0x10000>; /* 64kB */ 113 + i-cache-line-size = <64>; 114 + /* 4 ways set associativity */ 115 + /* cache_size / (line_size / associativity) */ 116 + i-cache-sets = <256>; 117 + next-level-cache = <&l2_00>; 118 + l2_00: l2-cache { 119 + compatible = "cache"; 120 + cache-level = <2>; 121 + cache-size = <0x80000>; /* 512kB */ 122 + cache-line-size = <64>; 123 + /* 8 ways set associativity */ 124 + /* cache_size / (line_size/associativity) */ 125 + cache-sets = <1024>; 126 + cache-unified; 127 + next-level-cache = <&l3_0>; 128 + }; 107 129 }; 108 130 cpu100: cpu@100 { 109 131 compatible = "arm,cortex-a78"; ··· 134 112 reg = <0x100>; 135 113 operating-points-v2 = <&cpu_opp_table>; 136 114 cpu-idle-states = <&CPU_SLEEP_0>; 115 + d-cache-size = <0x10000>; /* 64kB */ 116 + d-cache-line-size = <64>; 117 + /* 4 ways set associativity */ 118 + /* cache_size / (line_size / associativity) */ 119 + d-cache-sets = <256>; 120 + i-cache-size = <0x10000>; /* 64kB */ 121 + i-cache-line-size = <64>; 122 + /* 4 ways set associativity */ 123 + /* cache_size / (line_size / associativity) */ 124 + i-cache-sets = <256>; 125 + next-level-cache = <&l2_01>; 126 + l2_01: l2-cache { 127 + compatible = "cache"; 128 + cache-level = <2>; 129 + cache-size = <0x80000>; /* 512kB */ 130 + cache-line-size = <64>; 131 + /* 8 ways set associativity */ 132 + /* cache_size / (line_size/associativity) */ 133 + cache-sets = <1024>; 134 + cache-unified; 135 + next-level-cache = <&l3_0>; 136 + }; 137 137 }; 138 138 cpu200: cpu@200 { 139 139 compatible = "arm,cortex-a78"; ··· 164 120 reg = <0x200>; 165 121 operating-points-v2 = <&cpu_opp_table>; 166 122 cpu-idle-states = <&CPU_SLEEP_0>; 123 + d-cache-size = <0x10000>; /* 64kB */ 124 + d-cache-line-size = <64>; 125 + /* 4 ways set associativity */ 126 + /* cache_size / (line_size / associativity) */ 127 + d-cache-sets = <256>; 128 + i-cache-size = <0x10000>; /* 64kB */ 129 + i-cache-line-size = <64>; 130 + /* 4 ways set associativity */ 131 + /* cache_size / (line_size / associativity) */ 132 + i-cache-sets = <256>; 133 + next-level-cache = <&l2_02>; 134 + l2_02: l2-cache { 135 + compatible = "cache"; 136 + cache-level = <2>; 137 + cache-size = <0x80000>; /* 512kB */ 138 + cache-line-size = <64>; 139 + /* 8 ways set associativity */ 140 + /* cache_size / (line_size/associativity) */ 141 + cache-sets = <1024>; 142 + cache-unified; 143 + next-level-cache = <&l3_0>; 144 + }; 167 145 }; 168 146 cpu300: cpu@300 { 169 147 compatible = "arm,cortex-a78"; ··· 194 128 reg = <0x300>; 195 129 operating-points-v2 = <&cpu_opp_table>; 196 130 cpu-idle-states = <&CPU_SLEEP_0>; 131 + d-cache-size = <0x10000>; /* 64kB */ 132 + d-cache-line-size = <64>; 133 + /* 4 ways set associativity */ 134 + /* cache_size / (line_size / associativity) */ 135 + d-cache-sets = <256>; 136 + i-cache-size = <0x10000>; /* 64kB */ 137 + i-cache-line-size = <64>; 138 + /* 4 ways set associativity */ 139 + /* cache_size / (line_size / associativity) */ 140 + i-cache-sets = <256>; 141 + next-level-cache = <&l2_03>; 142 + l2_03: l2-cache { 143 + compatible = "cache"; 144 + cache-level = <2>; 145 + cache-size = <0x80000>; /* 512kB */ 146 + cache-line-size = <64>; 147 + /* 8 ways set associativity */ 148 + /* cache_size / (line_size/associativity) */ 149 + cache-sets = <1024>; 150 + cache-unified; 151 + next-level-cache = <&l3_0>; 152 + }; 197 153 }; 198 154 cpu10000: cpu@10000 { 199 155 compatible = "arm,cortex-a78"; ··· 224 136 reg = <0x10000>; 225 137 operating-points-v2 = <&cpu_opp_table>; 226 138 cpu-idle-states = <&CPU_SLEEP_0>; 139 + d-cache-size = <0x10000>; /* 64kB */ 140 + d-cache-line-size = <64>; 141 + /* 4 ways set associativity */ 142 + /* cache_size / (line_size / associativity) */ 143 + d-cache-sets = <256>; 144 + i-cache-size = <0x10000>; /* 64kB */ 145 + i-cache-line-size = <64>; 146 + /* 4 ways set associativity */ 147 + /* cache_size / (line_size / associativity) */ 148 + i-cache-sets = <256>; 149 + next-level-cache = <&l2_10>; 150 + l2_10: l2-cache { 151 + compatible = "cache"; 152 + cache-level = <2>; 153 + cache-size = <0x80000>; /* 512kB */ 154 + cache-line-size = <64>; 155 + /* 8 ways set associativity */ 156 + /* cache_size / (line_size/associativity) */ 157 + cache-sets = <1024>; 158 + cache-unified; 159 + next-level-cache = <&l3_1>; 160 + }; 227 161 }; 228 162 cpu10100: cpu@10100 { 229 163 compatible = "arm,cortex-a78"; ··· 254 144 reg = <0x10100>; 255 145 operating-points-v2 = <&cpu_opp_table>; 256 146 cpu-idle-states = <&CPU_SLEEP_0>; 147 + d-cache-size = <0x10000>; /* 64kB */ 148 + d-cache-line-size = <64>; 149 + /* 4 ways set associativity */ 150 + /* cache_size / (line_size / associativity) */ 151 + d-cache-sets = <256>; 152 + i-cache-size = <0x10000>; /* 64kB */ 153 + i-cache-line-size = <64>; 154 + /* 4 ways set associativity */ 155 + /* cache_size / (line_size / associativity) */ 156 + i-cache-sets = <256>; 157 + next-level-cache = <&l2_11>; 158 + l2_11: l2-cache { 159 + compatible = "cache"; 160 + cache-level = <2>; 161 + cache-size = <0x80000>; /* 512kB */ 162 + cache-line-size = <64>; 163 + /* 8 ways set associativity */ 164 + /* cache_size / (line_size/associativity) */ 165 + cache-sets = <1024>; 166 + cache-unified; 167 + next-level-cache = <&l3_1>; 168 + }; 257 169 }; 258 170 cpu10200: cpu@10200 { 259 171 compatible = "arm,cortex-a78"; ··· 284 152 reg = <0x10200>; 285 153 operating-points-v2 = <&cpu_opp_table>; 286 154 cpu-idle-states = <&CPU_SLEEP_0>; 155 + d-cache-size = <0x10000>; /* 64kB */ 156 + d-cache-line-size = <64>; 157 + /* 4 ways set associativity */ 158 + /* cache_size / (line_size / associativity) */ 159 + d-cache-sets = <256>; 160 + i-cache-size = <0x10000>; /* 64kB */ 161 + i-cache-line-size = <64>; 162 + /* 4 ways set associativity */ 163 + /* cache_size / (line_size / associativity) */ 164 + i-cache-sets = <256>; 165 + next-level-cache = <&l2_12>; 166 + l2_12: l2-cache { 167 + compatible = "cache"; 168 + cache-level = <2>; 169 + cache-size = <0x80000>; /* 512kB */ 170 + cache-line-size = <64>; 171 + /* 8 ways set associativity */ 172 + /* cache_size / (line_size/associativity) */ 173 + cache-sets = <1024>; 174 + cache-unified; 175 + next-level-cache = <&l3_1>; 176 + }; 287 177 }; 288 178 cpu10300: cpu@10300 { 289 179 compatible = "arm,cortex-a78"; ··· 314 160 reg = <0x10300>; 315 161 operating-points-v2 = <&cpu_opp_table>; 316 162 cpu-idle-states = <&CPU_SLEEP_0>; 163 + d-cache-size = <0x10000>; /* 64kB */ 164 + d-cache-line-size = <64>; 165 + /* 4 ways set associativity */ 166 + /* cache_size / (line_size / associativity) */ 167 + d-cache-sets = <256>; 168 + i-cache-size = <0x10000>; /* 64kB */ 169 + i-cache-line-size = <64>; 170 + /* 4 ways set associativity */ 171 + /* cache_size / (line_size / associativity) */ 172 + i-cache-sets = <256>; 173 + next-level-cache = <&l2_13>; 174 + l2_13: l2-cache { 175 + compatible = "cache"; 176 + cache-level = <2>; 177 + cache-size = <0x80000>; /* 512kB */ 178 + cache-line-size = <64>; 179 + /* 8 ways set associativity */ 180 + /* cache_size / (line_size/associativity) */ 181 + cache-sets = <1024>; 182 + cache-unified; 183 + next-level-cache = <&l3_1>; 184 + }; 317 185 }; 318 186 cpu20000: cpu@20000 { 319 187 compatible = "arm,cortex-a78"; ··· 344 168 reg = <0x20000>; 345 169 operating-points-v2 = <&cpu_opp_table>; 346 170 cpu-idle-states = <&CPU_SLEEP_0>; 171 + d-cache-size = <0x10000>; /* 64kB */ 172 + d-cache-line-size = <64>; 173 + /* 4 ways set associativity */ 174 + /* cache_size / (line_size / associativity) */ 175 + d-cache-sets = <256>; 176 + i-cache-size = <0x10000>; /* 64kB */ 177 + i-cache-line-size = <64>; 178 + /* 4 ways set associativity */ 179 + /* cache_size / (line_size / associativity) */ 180 + i-cache-sets = <256>; 181 + next-level-cache = <&l2_20>; 182 + l2_20: l2-cache { 183 + compatible = "cache"; 184 + cache-level = <2>; 185 + cache-size = <0x80000>; /* 512kB */ 186 + cache-line-size = <64>; 187 + /* 8 ways set associativity */ 188 + /* cache_size / (line_size/associativity) */ 189 + cache-sets = <1024>; 190 + cache-unified; 191 + next-level-cache = <&l3_2>; 192 + }; 347 193 }; 348 194 cpu20100: cpu@20100 { 349 195 compatible = "arm,cortex-a78"; ··· 374 176 reg = <0x20100>; 375 177 operating-points-v2 = <&cpu_opp_table>; 376 178 cpu-idle-states = <&CPU_SLEEP_0>; 179 + d-cache-size = <0x10000>; /* 64kB */ 180 + d-cache-line-size = <64>; 181 + /* 4 ways set associativity */ 182 + /* cache_size / (line_size / associativity) */ 183 + d-cache-sets = <256>; 184 + i-cache-size = <0x10000>; /* 64kB */ 185 + i-cache-line-size = <64>; 186 + /* 4 ways set associativity */ 187 + /* cache_size / (line_size / associativity) */ 188 + i-cache-sets = <256>; 189 + next-level-cache = <&l2_21>; 190 + l2_21: l2-cache { 191 + compatible = "cache"; 192 + cache-level = <2>; 193 + cache-size = <0x80000>; /* 512kB */ 194 + cache-line-size = <64>; 195 + /* 8 ways set associativity */ 196 + /* cache_size / (line_size/associativity) */ 197 + cache-sets = <1024>; 198 + cache-unified; 199 + next-level-cache = <&l3_2>; 200 + }; 377 201 }; 378 202 cpu20200: cpu@20200 { 379 203 compatible = "arm,cortex-a78"; ··· 404 184 reg = <0x20200>; 405 185 operating-points-v2 = <&cpu_opp_table>; 406 186 cpu-idle-states = <&CPU_SLEEP_0>; 187 + d-cache-size = <0x10000>; /* 64kB */ 188 + d-cache-line-size = <64>; 189 + /* 4 ways set associativity */ 190 + /* cache_size / (line_size / associativity) */ 191 + d-cache-sets = <256>; 192 + i-cache-size = <0x10000>; /* 64kB */ 193 + i-cache-line-size = <64>; 194 + /* 4 ways set associativity */ 195 + /* cache_size / (line_size / associativity) */ 196 + i-cache-sets = <256>; 197 + next-level-cache = <&l2_22>; 198 + l2_22: l2-cache { 199 + compatible = "cache"; 200 + cache-level = <2>; 201 + cache-size = <0x80000>; /* 512kB */ 202 + cache-line-size = <64>; 203 + /* 8 ways set associativity */ 204 + /* cache_size / (line_size/associativity) */ 205 + cache-sets = <1024>; 206 + cache-unified; 207 + next-level-cache = <&l3_2>; 208 + }; 407 209 }; 408 210 cpu20300: cpu@20300 { 409 211 compatible = "arm,cortex-a78"; ··· 434 192 reg = <0x20300>; 435 193 operating-points-v2 = <&cpu_opp_table>; 436 194 cpu-idle-states = <&CPU_SLEEP_0>; 195 + d-cache-size = <0x10000>; /* 64kB */ 196 + d-cache-line-size = <64>; 197 + /* 4 ways set associativity */ 198 + /* cache_size / (line_size / associativity) */ 199 + d-cache-sets = <256>; 200 + i-cache-size = <0x10000>; /* 64kB */ 201 + i-cache-line-size = <64>; 202 + /* 4 ways set associativity */ 203 + /* cache_size / (line_size / associativity) */ 204 + i-cache-sets = <256>; 205 + next-level-cache = <&l2_23>; 206 + l2_23: l2-cache { 207 + compatible = "cache"; 208 + cache-level = <2>; 209 + cache-size = <0x80000>; /* 512kB */ 210 + cache-line-size = <64>; 211 + /* 8 ways set associativity */ 212 + /* cache_size / (line_size/associativity) */ 213 + cache-sets = <1024>; 214 + cache-unified; 215 + next-level-cache = <&l3_2>; 216 + }; 437 217 }; 438 218 cpu30000: cpu@30000 { 439 219 compatible = "arm,cortex-a78"; ··· 464 200 reg = <0x30000>; 465 201 operating-points-v2 = <&cpu_opp_table>; 466 202 cpu-idle-states = <&CPU_SLEEP_0>; 203 + d-cache-size = <0x10000>; /* 64kB */ 204 + d-cache-line-size = <64>; 205 + /* 4 ways set associativity */ 206 + /* cache_size / (line_size / associativity) */ 207 + d-cache-sets = <256>; 208 + i-cache-size = <0x10000>; /* 64kB */ 209 + i-cache-line-size = <64>; 210 + /* 4 ways set associativity */ 211 + /* cache_size / (line_size / associativity) */ 212 + i-cache-sets = <256>; 213 + next-level-cache = <&l2_30>; 214 + l2_30: l2-cache { 215 + compatible = "cache"; 216 + cache-level = <2>; 217 + cache-size = <0x80000>; /* 512kB */ 218 + cache-line-size = <64>; 219 + /* 8 ways set associativity */ 220 + /* cache_size / (line_size/associativity) */ 221 + cache-sets = <1024>; 222 + cache-unified; 223 + next-level-cache = <&l3_3>; 224 + }; 467 225 }; 468 226 cpu30100: cpu@30100 { 469 227 compatible = "arm,cortex-a78"; ··· 494 208 reg = <0x30100>; 495 209 operating-points-v2 = <&cpu_opp_table>; 496 210 cpu-idle-states = <&CPU_SLEEP_0>; 211 + d-cache-size = <0x10000>; /* 64kB */ 212 + d-cache-line-size = <64>; 213 + /* 4 ways set associativity */ 214 + /* cache_size / (line_size / associativity) */ 215 + d-cache-sets = <256>; 216 + i-cache-size = <0x10000>; /* 64kB */ 217 + i-cache-line-size = <64>; 218 + /* 4 ways set associativity */ 219 + /* cache_size / (line_size / associativity) */ 220 + i-cache-sets = <256>; 221 + next-level-cache = <&l2_31>; 222 + l2_31: l2-cache { 223 + compatible = "cache"; 224 + cache-level = <2>; 225 + cache-size = <0x80000>; /* 512kB */ 226 + cache-line-size = <64>; 227 + /* 8 ways set associativity */ 228 + /* cache_size / (line_size/associativity) */ 229 + cache-sets = <1024>; 230 + cache-unified; 231 + next-level-cache = <&l3_3>; 232 + }; 497 233 }; 498 234 cpu30200: cpu@30200 { 499 235 compatible = "arm,cortex-a78"; ··· 524 216 reg = <0x30200>; 525 217 operating-points-v2 = <&cpu_opp_table>; 526 218 cpu-idle-states = <&CPU_SLEEP_0>; 219 + d-cache-size = <0x10000>; /* 64kB */ 220 + d-cache-line-size = <64>; 221 + /* 4 ways set associativity */ 222 + /* cache_size / (line_size / associativity) */ 223 + d-cache-sets = <256>; 224 + i-cache-size = <0x10000>; /* 64kB */ 225 + i-cache-line-size = <64>; 226 + /* 4 ways set associativity */ 227 + /* cache_size / (line_size / associativity) */ 228 + i-cache-sets = <256>; 229 + next-level-cache = <&l2_32>; 230 + l2_32: l2-cache { 231 + compatible = "cache"; 232 + cache-level = <2>; 233 + cache-size = <0x80000>; /* 512kB */ 234 + cache-line-size = <64>; 235 + /* 8 ways set associativity */ 236 + /* cache_size / (line_size/associativity) */ 237 + cache-sets = <1024>; 238 + cache-unified; 239 + next-level-cache = <&l3_3>; 240 + }; 527 241 }; 528 242 cpu30300: cpu@30300 { 529 243 compatible = "arm,cortex-a78"; ··· 554 224 reg = <0x30300>; 555 225 operating-points-v2 = <&cpu_opp_table>; 556 226 cpu-idle-states = <&CPU_SLEEP_0>; 227 + d-cache-size = <0x10000>; /* 64kB */ 228 + d-cache-line-size = <64>; 229 + /* 4 ways set associativity */ 230 + /* cache_size / (line_size / associativity) */ 231 + d-cache-sets = <256>; 232 + i-cache-size = <0x10000>; /* 64kB */ 233 + i-cache-line-size = <64>; 234 + /* 4 ways set associativity */ 235 + /* cache_size / (line_size / associativity) */ 236 + i-cache-sets = <256>; 237 + next-level-cache = <&l2_33>; 238 + l2_33: l2-cache { 239 + compatible = "cache"; 240 + cache-level = <2>; 241 + cache-size = <0x80000>; /* 512kB */ 242 + cache-line-size = <64>; 243 + /* 8 ways set associativity */ 244 + /* cache_size / (line_size/associativity) */ 245 + cache-sets = <1024>; 246 + cache-unified; 247 + next-level-cache = <&l3_3>; 248 + }; 557 249 }; 250 + 251 + l3_0: l3-0-cache { /* cluster private */ 252 + compatible = "cache"; 253 + cache-level = <3>; 254 + cache-size = <0x200000>; /* 2MB */ 255 + cache-line-size = <64>; 256 + /* 16 ways set associativity */ 257 + /* cache_size / (line_size/associativity) */ 258 + cache-sets = <2048>; 259 + cache-unified; 260 + next-level-cache = <&llc>; 261 + }; 262 + 263 + l3_1: l3-1-cache { /* cluster private */ 264 + compatible = "cache"; 265 + cache-level = <3>; 266 + cache-size = <0x200000>; /* 2MB */ 267 + cache-line-size = <64>; 268 + /* 16 ways set associativity */ 269 + /* cache_size / (line_size/associativity) */ 270 + cache-sets = <2048>; 271 + cache-unified; 272 + next-level-cache = <&llc>; 273 + }; 274 + 275 + l3_2: l3-2-cache { /* cluster private */ 276 + compatible = "cache"; 277 + cache-level = <3>; 278 + cache-size = <0x200000>; /* 2MB */ 279 + cache-line-size = <64>; 280 + /* 16 ways set associativity */ 281 + /* cache_size / (line_size/associativity) */ 282 + cache-sets = <2048>; 283 + cache-unified; 284 + next-level-cache = <&llc>; 285 + }; 286 + 287 + l3_3: l3-3-cache { /* cluster private */ 288 + compatible = "cache"; 289 + cache-level = <3>; 290 + cache-size = <0x200000>; /* 2MB */ 291 + cache-line-size = <64>; 292 + /* 16 ways set associativity */ 293 + /* cache_size / (line_size/associativity) */ 294 + cache-sets = <2048>; 295 + cache-unified; 296 + next-level-cache = <&llc>; 297 + }; 298 + 299 + llc: l4-cache { /* LLC inside CMN */ 300 + compatible = "cache"; 301 + cache-level = <4>; 302 + cache-size = <0x1000000>; /* 16MB */ 303 + cache-unified; 304 + }; 305 + 558 306 idle-states { 559 307 entry-method = "psci"; 560 308