commit 0e4cac557531a4c93de108d9ff11329fcad482ff · tjh.dev/kernel

+6 -49

drivers/misc/cardreader/rts5227.c

··· 83 83 84 84 static void rts5227_init_from_cfg(struct rtsx_pcr *pcr) 85 85 { 86 - struct pci_dev *pdev = pcr->pci; 87 - int l1ss; 88 - u32 lval; 89 86 struct rtsx_cr_option *option = &pcr->option; 90 87 91 - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); 92 - if (!l1ss) 93 - return; 94 - 95 - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); 96 - 97 88 if (CHK_PCI_PID(pcr, 0x522A)) { 98 - if (0 == (lval & 0x0F)) 99 - rtsx_pci_enable_oobs_polling(pcr); 100 - else 89 + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 90 + | PM_L1_1_EN | PM_L1_2_EN)) 101 91 rtsx_pci_disable_oobs_polling(pcr); 92 + else 93 + rtsx_pci_enable_oobs_polling(pcr); 102 94 } 103 - 104 - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) 105 - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); 106 - else 107 - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); 108 - 109 - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) 110 - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); 111 - else 112 - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); 113 - 114 - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) 115 - rtsx_set_dev_flag(pcr, PM_L1_1_EN); 116 - else 117 - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); 118 - 119 - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) 120 - rtsx_set_dev_flag(pcr, PM_L1_2_EN); 121 - else 122 - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); 123 95 124 96 if (option->ltr_en) { 125 - u16 val; 126 - 127 - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); 128 - if (val & PCI_EXP_DEVCTL2_LTR_EN) { 129 - option->ltr_enabled = true; 130 - option->ltr_active = true; 97 + if (option->ltr_enabled) 131 98 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 132 - } else { 133 - option->ltr_enabled = false; 134 - } 135 99 } 136 - 137 - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 138 - | PM_L1_1_EN | PM_L1_2_EN)) 139 - option->force_clkreq_0 = false; 140 - else 141 - option->force_clkreq_0 = true; 142 - 143 100 } 144 101 145 102 static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) ··· 152 195 } 153 196 } 154 197 155 - if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG) 198 + if (option->force_clkreq_0) 156 199 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 157 200 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 158 201 else

+17 -40

drivers/misc/cardreader/rts5228.c

··· 386 386 387 387 static void rts5228_init_from_cfg(struct rtsx_pcr *pcr) 388 388 { 389 - struct pci_dev *pdev = pcr->pci; 390 - int l1ss; 391 - u32 lval; 392 389 struct rtsx_cr_option *option = &pcr->option; 393 390 394 - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); 395 - if (!l1ss) 396 - return; 397 - 398 - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); 399 - 400 - if (0 == (lval & 0x0F)) 401 - rtsx_pci_enable_oobs_polling(pcr); 402 - else 391 + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 392 + | PM_L1_1_EN | PM_L1_2_EN)) 403 393 rtsx_pci_disable_oobs_polling(pcr); 404 - 405 - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) 406 - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); 407 394 else 408 - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); 409 - 410 - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) 411 - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); 412 - else 413 - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); 414 - 415 - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) 416 - rtsx_set_dev_flag(pcr, PM_L1_1_EN); 417 - else 418 - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); 419 - 420 - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) 421 - rtsx_set_dev_flag(pcr, PM_L1_2_EN); 422 - else 423 - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); 395 + rtsx_pci_enable_oobs_polling(pcr); 424 396 425 397 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); 426 - if (option->ltr_en) { 427 - u16 val; 428 398 429 - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); 430 - if (val & PCI_EXP_DEVCTL2_LTR_EN) { 431 - option->ltr_enabled = true; 432 - option->ltr_active = true; 399 + if (option->ltr_en) { 400 + if (option->ltr_enabled) 433 401 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 434 - } else { 435 - option->ltr_enabled = false; 436 - } 437 402 } 438 403 } 439 404 440 405 static int rts5228_extra_init_hw(struct rtsx_pcr *pcr) 441 406 { 407 + struct rtsx_cr_option *option = &pcr->option; 442 408 443 409 rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1, 444 410 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK); ··· 434 468 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30); 435 469 else 436 470 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); 471 + 472 + /* 473 + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 474 + * to drive low, and we forcibly request clock. 475 + */ 476 + if (option->force_clkreq_0) 477 + rtsx_pci_write_register(pcr, PETXCFG, 478 + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 479 + else 480 + rtsx_pci_write_register(pcr, PETXCFG, 481 + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 437 482 438 483 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); 439 484

+7 -49

drivers/misc/cardreader/rts5249.c

··· 86 86 87 87 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) 88 88 { 89 - struct pci_dev *pdev = pcr->pci; 90 - int l1ss; 91 89 struct rtsx_cr_option *option = &(pcr->option); 92 - u32 lval; 93 - 94 - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); 95 - if (!l1ss) 96 - return; 97 - 98 - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); 99 90 100 91 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { 101 - if (0 == (lval & 0x0F)) 102 - rtsx_pci_enable_oobs_polling(pcr); 103 - else 92 + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 93 + | PM_L1_1_EN | PM_L1_2_EN)) 104 94 rtsx_pci_disable_oobs_polling(pcr); 95 + else 96 + rtsx_pci_enable_oobs_polling(pcr); 105 97 } 106 - 107 - 108 - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) 109 - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); 110 - 111 - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) 112 - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); 113 - 114 - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) 115 - rtsx_set_dev_flag(pcr, PM_L1_1_EN); 116 - 117 - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) 118 - rtsx_set_dev_flag(pcr, PM_L1_2_EN); 119 98 120 99 if (option->ltr_en) { 121 - u16 val; 122 - 123 - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); 124 - if (val & PCI_EXP_DEVCTL2_LTR_EN) { 125 - option->ltr_enabled = true; 126 - option->ltr_active = true; 100 + if (option->ltr_enabled) 127 101 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 128 - } else { 129 - option->ltr_enabled = false; 130 - } 131 102 } 132 - } 133 - 134 - static int rts5249_init_from_hw(struct rtsx_pcr *pcr) 135 - { 136 - struct rtsx_cr_option *option = &(pcr->option); 137 - 138 - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 139 - | PM_L1_1_EN | PM_L1_2_EN)) 140 - option->force_clkreq_0 = false; 141 - else 142 - option->force_clkreq_0 = true; 143 - 144 - return 0; 145 103 } 146 104 147 105 static void rts52xa_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) ··· 234 276 struct rtsx_cr_option *option = &(pcr->option); 235 277 236 278 rts5249_init_from_cfg(pcr); 237 - rts5249_init_from_hw(pcr); 238 279 239 280 rtsx_pci_init_cmd(pcr); 240 281 ··· 284 327 } 285 328 } 286 329 330 + 287 331 /* 288 332 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 289 333 * to drive low, and we forcibly request clock. 290 334 */ 291 - if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG) 335 + if (option->force_clkreq_0) 292 336 rtsx_pci_write_register(pcr, PETXCFG, 293 337 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 294 338 else

+13 -30

drivers/misc/cardreader/rts5260.c

··· 480 480 481 481 static void rts5260_init_from_cfg(struct rtsx_pcr *pcr) 482 482 { 483 - struct pci_dev *pdev = pcr->pci; 484 - int l1ss; 485 483 struct rtsx_cr_option *option = &pcr->option; 486 - u32 lval; 487 - 488 - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); 489 - if (!l1ss) 490 - return; 491 - 492 - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); 493 - 494 - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) 495 - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); 496 - 497 - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) 498 - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); 499 - 500 - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) 501 - rtsx_set_dev_flag(pcr, PM_L1_1_EN); 502 - 503 - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) 504 - rtsx_set_dev_flag(pcr, PM_L1_2_EN); 505 484 506 485 rts5260_pwr_saving_setting(pcr); 507 486 508 487 if (option->ltr_en) { 509 - u16 val; 510 - 511 - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); 512 - if (val & PCI_EXP_DEVCTL2_LTR_EN) { 513 - option->ltr_enabled = true; 514 - option->ltr_active = true; 488 + if (option->ltr_enabled) 515 489 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 516 - } else { 517 - option->ltr_enabled = false; 518 - } 519 490 } 520 491 } 521 492 522 493 static int rts5260_extra_init_hw(struct rtsx_pcr *pcr) 523 494 { 495 + struct rtsx_cr_option *option = &pcr->option; 524 496 525 497 /* Set mcu_cnt to 7 to ensure data can be sampled properly */ 526 498 rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07); ··· 510 538 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); 511 539 512 540 rts5260_init_hw(pcr); 541 + 542 + /* 543 + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 544 + * to drive low, and we forcibly request clock. 545 + */ 546 + if (option->force_clkreq_0) 547 + rtsx_pci_write_register(pcr, PETXCFG, 548 + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 549 + else 550 + rtsx_pci_write_register(pcr, PETXCFG, 551 + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 513 552 514 553 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); 515 554

+13 -39

drivers/misc/cardreader/rts5261.c

··· 454 454 455 455 static void rts5261_init_from_cfg(struct rtsx_pcr *pcr) 456 456 { 457 - struct pci_dev *pdev = pcr->pci; 458 - int l1ss; 459 - u32 lval; 460 457 struct rtsx_cr_option *option = &pcr->option; 461 458 462 - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); 463 - if (!l1ss) 464 - return; 465 - 466 - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); 467 - 468 - if (lval & PCI_L1SS_CTL1_ASPM_L1_1) 469 - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); 470 - else 471 - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); 472 - 473 - if (lval & PCI_L1SS_CTL1_ASPM_L1_2) 474 - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); 475 - else 476 - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); 477 - 478 - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) 479 - rtsx_set_dev_flag(pcr, PM_L1_1_EN); 480 - else 481 - rtsx_clear_dev_flag(pcr, PM_L1_1_EN); 482 - 483 - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) 484 - rtsx_set_dev_flag(pcr, PM_L1_2_EN); 485 - else 486 - rtsx_clear_dev_flag(pcr, PM_L1_2_EN); 487 - 488 - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); 489 459 if (option->ltr_en) { 490 - u16 val; 491 - 492 - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); 493 - if (val & PCI_EXP_DEVCTL2_LTR_EN) { 494 - option->ltr_enabled = true; 495 - option->ltr_active = true; 460 + if (option->ltr_enabled) 496 461 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 497 - } else { 498 - option->ltr_enabled = false; 499 - } 500 462 } 501 463 } 502 464 503 465 static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) 504 466 { 467 + struct rtsx_cr_option *option = &pcr->option; 505 468 u32 val; 506 469 507 470 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1, ··· 509 546 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30); 510 547 else 511 548 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); 549 + 550 + /* 551 + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 552 + * to drive low, and we forcibly request clock. 553 + */ 554 + if (option->force_clkreq_0) 555 + rtsx_pci_write_register(pcr, PETXCFG, 556 + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 557 + else 558 + rtsx_pci_write_register(pcr, PETXCFG, 559 + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 512 560 513 561 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); 514 562

+46 -5

drivers/misc/cardreader/rtsx_pcr.c

··· 1326 1326 return err; 1327 1327 } 1328 1328 1329 - if (pcr->aspm_mode == ASPM_MODE_REG) { 1329 + if (pcr->aspm_mode == ASPM_MODE_REG) 1330 1330 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30); 1331 - rtsx_pci_write_register(pcr, PETXCFG, 1332 - FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 1333 - } 1334 1331 1335 1332 /* No CD interrupt if probing driver with card inserted. 1336 1333 * So we need to initialize pcr->card_exist here. ··· 1342 1345 1343 1346 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) 1344 1347 { 1345 - int err; 1348 + struct rtsx_cr_option *option = &(pcr->option); 1349 + int err, l1ss; 1350 + u32 lval; 1346 1351 u16 cfg_val; 1347 1352 u8 val; 1348 1353 ··· 1427 1428 pcr->aspm_enabled = false; 1428 1429 else 1429 1430 pcr->aspm_enabled = true; 1431 + } 1432 + 1433 + l1ss = pci_find_ext_capability(pcr->pci, PCI_EXT_CAP_ID_L1SS); 1434 + if (l1ss) { 1435 + pci_read_config_dword(pcr->pci, l1ss + PCI_L1SS_CTL1, &lval); 1436 + 1437 + if (lval & PCI_L1SS_CTL1_ASPM_L1_1) 1438 + rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); 1439 + else 1440 + rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); 1441 + 1442 + if (lval & PCI_L1SS_CTL1_ASPM_L1_2) 1443 + rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); 1444 + else 1445 + rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); 1446 + 1447 + if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) 1448 + rtsx_set_dev_flag(pcr, PM_L1_1_EN); 1449 + else 1450 + rtsx_clear_dev_flag(pcr, PM_L1_1_EN); 1451 + 1452 + if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) 1453 + rtsx_set_dev_flag(pcr, PM_L1_2_EN); 1454 + else 1455 + rtsx_clear_dev_flag(pcr, PM_L1_2_EN); 1456 + 1457 + pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cfg_val); 1458 + if (cfg_val & PCI_EXP_DEVCTL2_LTR_EN) { 1459 + option->ltr_enabled = true; 1460 + option->ltr_active = true; 1461 + } else { 1462 + option->ltr_enabled = false; 1463 + } 1464 + 1465 + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 1466 + | PM_L1_1_EN | PM_L1_2_EN)) 1467 + option->force_clkreq_0 = false; 1468 + else 1469 + option->force_clkreq_0 = true; 1470 + } else { 1471 + option->ltr_enabled = false; 1472 + option->force_clkreq_0 = true; 1430 1473 } 1431 1474 1432 1475 if (pcr->ops->fetch_vendor_settings)