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arm64: dts: Update cache properties for hisilicon

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

authored by

Pierre Gondois and committed by
Wei Xu
0de459a3 9abf2313

+28
+2
arch/arm64/boot/dts/hisilicon/hi3660.dtsi
··· 203 203 204 204 A53_L2: l2-cache0 { 205 205 compatible = "cache"; 206 + cache-level = <2>; 206 207 }; 207 208 208 209 A73_L2: l2-cache1 { 209 210 compatible = "cache"; 211 + cache-level = <2>; 210 212 }; 211 213 }; 212 214
+2
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
··· 186 186 187 187 CLUSTER0_L2: l2-cache0 { 188 188 compatible = "cache"; 189 + cache-level = <2>; 189 190 }; 190 191 191 192 CLUSTER1_L2: l2-cache1 { 192 193 compatible = "cache"; 194 + cache-level = <2>; 193 195 }; 194 196 }; 195 197
+4
arch/arm64/boot/dts/hisilicon/hip05.dtsi
··· 211 211 212 212 cluster0_l2: l2-cache0 { 213 213 compatible = "cache"; 214 + cache-level = <2>; 214 215 }; 215 216 216 217 cluster1_l2: l2-cache1 { 217 218 compatible = "cache"; 219 + cache-level = <2>; 218 220 }; 219 221 220 222 cluster2_l2: l2-cache2 { 221 223 compatible = "cache"; 224 + cache-level = <2>; 222 225 }; 223 226 224 227 cluster3_l2: l2-cache3 { 225 228 compatible = "cache"; 229 + cache-level = <2>; 226 230 }; 227 231 }; 228 232
+4
arch/arm64/boot/dts/hisilicon/hip06.dtsi
··· 211 211 212 212 cluster0_l2: l2-cache0 { 213 213 compatible = "cache"; 214 + cache-level = <2>; 214 215 }; 215 216 216 217 cluster1_l2: l2-cache1 { 217 218 compatible = "cache"; 219 + cache-level = <2>; 218 220 }; 219 221 220 222 cluster2_l2: l2-cache2 { 221 223 compatible = "cache"; 224 + cache-level = <2>; 222 225 }; 223 226 224 227 cluster3_l2: l2-cache3 { 225 228 compatible = "cache"; 229 + cache-level = <2>; 226 230 }; 227 231 }; 228 232
+16
arch/arm64/boot/dts/hisilicon/hip07.dtsi
··· 842 842 843 843 cluster0_l2: l2-cache0 { 844 844 compatible = "cache"; 845 + cache-level = <2>; 845 846 }; 846 847 847 848 cluster1_l2: l2-cache1 { 848 849 compatible = "cache"; 850 + cache-level = <2>; 849 851 }; 850 852 851 853 cluster2_l2: l2-cache2 { 852 854 compatible = "cache"; 855 + cache-level = <2>; 853 856 }; 854 857 855 858 cluster3_l2: l2-cache3 { 856 859 compatible = "cache"; 860 + cache-level = <2>; 857 861 }; 858 862 859 863 cluster4_l2: l2-cache4 { 860 864 compatible = "cache"; 865 + cache-level = <2>; 861 866 }; 862 867 863 868 cluster5_l2: l2-cache5 { 864 869 compatible = "cache"; 870 + cache-level = <2>; 865 871 }; 866 872 867 873 cluster6_l2: l2-cache6 { 868 874 compatible = "cache"; 875 + cache-level = <2>; 869 876 }; 870 877 871 878 cluster7_l2: l2-cache7 { 872 879 compatible = "cache"; 880 + cache-level = <2>; 873 881 }; 874 882 875 883 cluster8_l2: l2-cache8 { 876 884 compatible = "cache"; 885 + cache-level = <2>; 877 886 }; 878 887 879 888 cluster9_l2: l2-cache9 { 880 889 compatible = "cache"; 890 + cache-level = <2>; 881 891 }; 882 892 883 893 cluster10_l2: l2-cache10 { 884 894 compatible = "cache"; 895 + cache-level = <2>; 885 896 }; 886 897 887 898 cluster11_l2: l2-cache11 { 888 899 compatible = "cache"; 900 + cache-level = <2>; 889 901 }; 890 902 891 903 cluster12_l2: l2-cache12 { 892 904 compatible = "cache"; 905 + cache-level = <2>; 893 906 }; 894 907 895 908 cluster13_l2: l2-cache13 { 896 909 compatible = "cache"; 910 + cache-level = <2>; 897 911 }; 898 912 899 913 cluster14_l2: l2-cache14 { 900 914 compatible = "cache"; 915 + cache-level = <2>; 901 916 }; 902 917 903 918 cluster15_l2: l2-cache15 { 904 919 compatible = "cache"; 920 + cache-level = <2>; 905 921 }; 906 922 }; 907 923