tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: rt5682: add rt5682 codec driver
This is the initial codec driver for rt5682.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Bard Liao
and committed by
Mark Brown
0ddce71c
53af408c
+4104
+50
Documentation/devicetree/bindings/sound/rt5682.txt
+50
Documentation/devicetree/bindings/sound/rt5682.txt
···
1
+
RT5682 audio CODEC
2
+
3
+
This device supports I2C only.
4
+
5
+
Required properties:
6
+
7
+
- compatible : "realtek,rt5682" or "realtek,rt5682i"
8
+
9
+
- reg : The I2C address of the device.
10
+
11
+
Optional properties:
12
+
13
+
- interrupts : The CODEC's interrupt output.
14
+
15
+
- realtek,dmic1-data-pin
16
+
0: dmic1 is not used
17
+
1: using GPIO2 pin as dmic1 data pin
18
+
2: using GPIO5 pin as dmic1 data pin
19
+
20
+
- realtek,dmic1-clk-pin
21
+
0: using GPIO1 pin as dmic1 clock pin
22
+
1: using GPIO3 pin as dmic1 clock pin
23
+
24
+
- realtek,jd-src
25
+
0: No JD is used
26
+
1: using JD1 as JD source
27
+
28
+
- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
29
+
30
+
Pins on the device (for linking into audio routes) for RT5682:
31
+
32
+
* DMIC L1
33
+
* DMIC R1
34
+
* IN1P
35
+
* HPOL
36
+
* HPOR
37
+
38
+
Example:
39
+
40
+
rt5682 {
41
+
compatible = "realtek,rt5682i";
42
+
reg = <0x1a>;
43
+
interrupt-parent = <&gpio>;
44
+
interrupts = <TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
45
+
realtek,ldo1-en-gpios =
46
+
<&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
47
+
realtek,dmic1-data-pin = <1>;
48
+
realtek,dmic1-clk-pin = <1>;
49
+
realtek,jd-src = <1>;
50
+
};
+40
include/sound/rt5682.h
+40
include/sound/rt5682.h
···
1
+
/*
2
+
* linux/sound/rt5682.h -- Platform data for RT5682
3
+
*
4
+
* Copyright 2018 Realtek Microelectronics
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
11
+
#ifndef __LINUX_SND_RT5682_H
12
+
#define __LINUX_SND_RT5682_H
13
+
14
+
enum rt5682_dmic1_data_pin {
15
+
RT5682_DMIC1_NULL,
16
+
RT5682_DMIC1_DATA_GPIO2,
17
+
RT5682_DMIC1_DATA_GPIO5,
18
+
};
19
+
20
+
enum rt5682_dmic1_clk_pin {
21
+
RT5682_DMIC1_CLK_GPIO1,
22
+
RT5682_DMIC1_CLK_GPIO3,
23
+
};
24
+
25
+
enum rt5682_jd_src {
26
+
RT5682_JD_NULL,
27
+
RT5682_JD1,
28
+
};
29
+
30
+
struct rt5682_platform_data {
31
+
32
+
int ldo1_en; /* GPIO for LDO1_EN */
33
+
34
+
enum rt5682_dmic1_data_pin dmic1_data_pin;
35
+
enum rt5682_dmic1_clk_pin dmic1_clk_pin;
36
+
enum rt5682_jd_src jd_src;
37
+
};
38
+
39
+
#endif
40
+
+6
sound/soc/codecs/Kconfig
+6
sound/soc/codecs/Kconfig
···
141
141
select SND_SOC_RT5668 if I2C
142
142
select SND_SOC_RT5670 if I2C
143
143
select SND_SOC_RT5677 if I2C && SPI_MASTER
144
+
select SND_SOC_RT5682 if I2C
144
145
select SND_SOC_SGTL5000 if I2C
145
146
select SND_SOC_SI476X if MFD_SI476X_CORE
146
147
select SND_SOC_SIRF_AUDIO_CODEC
···
779
778
default y if SND_SOC_RT5668=y
780
779
default y if SND_SOC_RT5670=y
781
780
default y if SND_SOC_RT5677=y
781
+
default y if SND_SOC_RT5682=y
782
782
default y if SND_SOC_RT1305=y
783
783
default m if SND_SOC_RT5514=m
784
784
default m if SND_SOC_RT5616=m
···
793
791
default m if SND_SOC_RT5668=m
794
792
default m if SND_SOC_RT5670=m
795
793
default m if SND_SOC_RT5677=m
794
+
default m if SND_SOC_RT5682=m
796
795
default m if SND_SOC_RT1305=m
797
796
798
797
config SND_SOC_RL6347A
···
873
870
config SND_SOC_RT5677_SPI
874
871
tristate
875
872
default SND_SOC_RT5677 && SPI
873
+
874
+
config SND_SOC_RT5682
875
+
tristate
876
876
877
877
#Freescale sgtl5000 codec
878
878
config SND_SOC_SGTL5000
+2
sound/soc/codecs/Makefile
+2
sound/soc/codecs/Makefile
···
146
146
snd-soc-rt5670-objs := rt5670.o
147
147
snd-soc-rt5677-objs := rt5677.o
148
148
snd-soc-rt5677-spi-objs := rt5677-spi.o
149
+
snd-soc-rt5682-objs := rt5682.o
149
150
snd-soc-sgtl5000-objs := sgtl5000.o
150
151
snd-soc-alc5623-objs := alc5623.o
151
152
snd-soc-alc5632-objs := alc5632.o
···
406
405
obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o
407
406
obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o
408
407
obj-$(CONFIG_SND_SOC_RT5677_SPI) += snd-soc-rt5677-spi.o
408
+
obj-$(CONFIG_SND_SOC_RT5682) += snd-soc-rt5682.o
409
409
obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
410
410
obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o
411
411
obj-$(CONFIG_SND_SOC_SIGMADSP_I2C) += snd-soc-sigmadsp-i2c.o
+2682
sound/soc/codecs/rt5682.c
+2682
sound/soc/codecs/rt5682.c
···
1
+
/*
2
+
* rt5682.c -- RT5682 ALSA SoC audio component driver
3
+
*
4
+
* Copyright 2018 Realtek Semiconductor Corp.
5
+
* Author: Bard Liao <bardliao@realtek.com>
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
10
+
*/
11
+
12
+
#include <linux/module.h>
13
+
#include <linux/moduleparam.h>
14
+
#include <linux/init.h>
15
+
#include <linux/delay.h>
16
+
#include <linux/pm.h>
17
+
#include <linux/i2c.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/spi/spi.h>
20
+
#include <linux/acpi.h>
21
+
#include <linux/gpio.h>
22
+
#include <linux/of_gpio.h>
23
+
#include <linux/regulator/consumer.h>
24
+
#include <linux/mutex.h>
25
+
#include <sound/core.h>
26
+
#include <sound/pcm.h>
27
+
#include <sound/pcm_params.h>
28
+
#include <sound/jack.h>
29
+
#include <sound/soc.h>
30
+
#include <sound/soc-dapm.h>
31
+
#include <sound/initval.h>
32
+
#include <sound/tlv.h>
33
+
#include <sound/rt5682.h>
34
+
35
+
#include "rl6231.h"
36
+
#include "rt5682.h"
37
+
38
+
#define RT5682_NUM_SUPPLIES 3
39
+
40
+
static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
41
+
"AVDD",
42
+
"MICVDD",
43
+
"VBAT",
44
+
};
45
+
46
+
struct rt5682_priv {
47
+
struct snd_soc_component *component;
48
+
struct rt5682_platform_data pdata;
49
+
struct regmap *regmap;
50
+
struct snd_soc_jack *hs_jack;
51
+
struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES];
52
+
struct delayed_work jack_detect_work;
53
+
struct delayed_work jd_check_work;
54
+
struct mutex calibrate_mutex;
55
+
56
+
int sysclk;
57
+
int sysclk_src;
58
+
int lrck[RT5682_AIFS];
59
+
int bclk[RT5682_AIFS];
60
+
int master[RT5682_AIFS];
61
+
62
+
int pll_src;
63
+
int pll_in;
64
+
int pll_out;
65
+
66
+
int jack_type;
67
+
};
68
+
69
+
static const struct reg_sequence patch_list[] = {
70
+
{0x01c1, 0x1000},
71
+
};
72
+
73
+
static const struct reg_default rt5682_reg[] = {
74
+
{0x0002, 0x8080},
75
+
{0x0003, 0x8000},
76
+
{0x0005, 0x0000},
77
+
{0x0006, 0x0000},
78
+
{0x0008, 0x800f},
79
+
{0x000b, 0x0000},
80
+
{0x0010, 0x4040},
81
+
{0x0011, 0x0000},
82
+
{0x0012, 0x1404},
83
+
{0x0013, 0x1000},
84
+
{0x0014, 0xa00a},
85
+
{0x0015, 0x0404},
86
+
{0x0016, 0x0404},
87
+
{0x0019, 0xafaf},
88
+
{0x001c, 0x2f2f},
89
+
{0x001f, 0x0000},
90
+
{0x0022, 0x5757},
91
+
{0x0023, 0x0039},
92
+
{0x0024, 0x000b},
93
+
{0x0026, 0xc0c4},
94
+
{0x0029, 0x8080},
95
+
{0x002a, 0xa0a0},
96
+
{0x002b, 0x0300},
97
+
{0x0030, 0x0000},
98
+
{0x003c, 0x0080},
99
+
{0x0044, 0x0c0c},
100
+
{0x0049, 0x0000},
101
+
{0x0061, 0x0000},
102
+
{0x0062, 0x0000},
103
+
{0x0063, 0x003f},
104
+
{0x0064, 0x0000},
105
+
{0x0065, 0x0000},
106
+
{0x0066, 0x0030},
107
+
{0x0067, 0x0000},
108
+
{0x006b, 0x0000},
109
+
{0x006c, 0x0000},
110
+
{0x006d, 0x2200},
111
+
{0x006e, 0x0a10},
112
+
{0x0070, 0x8000},
113
+
{0x0071, 0x8000},
114
+
{0x0073, 0x0000},
115
+
{0x0074, 0x0000},
116
+
{0x0075, 0x0002},
117
+
{0x0076, 0x0001},
118
+
{0x0079, 0x0000},
119
+
{0x007a, 0x0000},
120
+
{0x007b, 0x0000},
121
+
{0x007c, 0x0100},
122
+
{0x007e, 0x0000},
123
+
{0x0080, 0x0000},
124
+
{0x0081, 0x0000},
125
+
{0x0082, 0x0000},
126
+
{0x0083, 0x0000},
127
+
{0x0084, 0x0000},
128
+
{0x0085, 0x0000},
129
+
{0x0086, 0x0005},
130
+
{0x0087, 0x0000},
131
+
{0x0088, 0x0000},
132
+
{0x008c, 0x0003},
133
+
{0x008d, 0x0000},
134
+
{0x008e, 0x0060},
135
+
{0x008f, 0x1000},
136
+
{0x0091, 0x0c26},
137
+
{0x0092, 0x0073},
138
+
{0x0093, 0x0000},
139
+
{0x0094, 0x0080},
140
+
{0x0098, 0x0000},
141
+
{0x009a, 0x0000},
142
+
{0x009b, 0x0000},
143
+
{0x009c, 0x0000},
144
+
{0x009d, 0x0000},
145
+
{0x009e, 0x100c},
146
+
{0x009f, 0x0000},
147
+
{0x00a0, 0x0000},
148
+
{0x00a3, 0x0002},
149
+
{0x00a4, 0x0001},
150
+
{0x00ae, 0x2040},
151
+
{0x00af, 0x0000},
152
+
{0x00b6, 0x0000},
153
+
{0x00b7, 0x0000},
154
+
{0x00b8, 0x0000},
155
+
{0x00b9, 0x0002},
156
+
{0x00be, 0x0000},
157
+
{0x00c0, 0x0160},
158
+
{0x00c1, 0x82a0},
159
+
{0x00c2, 0x0000},
160
+
{0x00d0, 0x0000},
161
+
{0x00d1, 0x2244},
162
+
{0x00d2, 0x3300},
163
+
{0x00d3, 0x2200},
164
+
{0x00d4, 0x0000},
165
+
{0x00d9, 0x0009},
166
+
{0x00da, 0x0000},
167
+
{0x00db, 0x0000},
168
+
{0x00dc, 0x00c0},
169
+
{0x00dd, 0x2220},
170
+
{0x00de, 0x3131},
171
+
{0x00df, 0x3131},
172
+
{0x00e0, 0x3131},
173
+
{0x00e2, 0x0000},
174
+
{0x00e3, 0x4000},
175
+
{0x00e4, 0x0aa0},
176
+
{0x00e5, 0x3131},
177
+
{0x00e6, 0x3131},
178
+
{0x00e7, 0x3131},
179
+
{0x00e8, 0x3131},
180
+
{0x00ea, 0xb320},
181
+
{0x00eb, 0x0000},
182
+
{0x00f0, 0x0000},
183
+
{0x00f1, 0x00d0},
184
+
{0x00f2, 0x00d0},
185
+
{0x00f6, 0x0000},
186
+
{0x00fa, 0x0000},
187
+
{0x00fb, 0x0000},
188
+
{0x00fc, 0x0000},
189
+
{0x00fd, 0x0000},
190
+
{0x00fe, 0x10ec},
191
+
{0x00ff, 0x6530},
192
+
{0x0100, 0xa0a0},
193
+
{0x010b, 0x0000},
194
+
{0x010c, 0xae00},
195
+
{0x010d, 0xaaa0},
196
+
{0x010e, 0x8aa2},
197
+
{0x010f, 0x02a2},
198
+
{0x0110, 0xc000},
199
+
{0x0111, 0x04a2},
200
+
{0x0112, 0x2800},
201
+
{0x0113, 0x0000},
202
+
{0x0117, 0x0100},
203
+
{0x0125, 0x0410},
204
+
{0x0132, 0x6026},
205
+
{0x0136, 0x5555},
206
+
{0x0138, 0x3700},
207
+
{0x013a, 0x2000},
208
+
{0x013b, 0x2000},
209
+
{0x013c, 0x2005},
210
+
{0x013f, 0x0000},
211
+
{0x0142, 0x0000},
212
+
{0x0145, 0x0002},
213
+
{0x0146, 0x0000},
214
+
{0x0147, 0x0000},
215
+
{0x0148, 0x0000},
216
+
{0x0149, 0x0000},
217
+
{0x0150, 0x79a1},
218
+
{0x0151, 0x0000},
219
+
{0x0160, 0x4ec0},
220
+
{0x0161, 0x0080},
221
+
{0x0162, 0x0200},
222
+
{0x0163, 0x0800},
223
+
{0x0164, 0x0000},
224
+
{0x0165, 0x0000},
225
+
{0x0166, 0x0000},
226
+
{0x0167, 0x000f},
227
+
{0x0168, 0x000f},
228
+
{0x0169, 0x0021},
229
+
{0x0190, 0x413d},
230
+
{0x0194, 0x0000},
231
+
{0x0195, 0x0000},
232
+
{0x0197, 0x0022},
233
+
{0x0198, 0x0000},
234
+
{0x0199, 0x0000},
235
+
{0x01af, 0x0000},
236
+
{0x01b0, 0x0400},
237
+
{0x01b1, 0x0000},
238
+
{0x01b2, 0x0000},
239
+
{0x01b3, 0x0000},
240
+
{0x01b4, 0x0000},
241
+
{0x01b5, 0x0000},
242
+
{0x01b6, 0x01c3},
243
+
{0x01b7, 0x02a0},
244
+
{0x01b8, 0x03e9},
245
+
{0x01b9, 0x1389},
246
+
{0x01ba, 0xc351},
247
+
{0x01bb, 0x0009},
248
+
{0x01bc, 0x0018},
249
+
{0x01bd, 0x002a},
250
+
{0x01be, 0x004c},
251
+
{0x01bf, 0x0097},
252
+
{0x01c0, 0x433d},
253
+
{0x01c2, 0x0000},
254
+
{0x01c3, 0x0000},
255
+
{0x01c4, 0x0000},
256
+
{0x01c5, 0x0000},
257
+
{0x01c6, 0x0000},
258
+
{0x01c7, 0x0000},
259
+
{0x01c8, 0x40af},
260
+
{0x01c9, 0x0702},
261
+
{0x01ca, 0x0000},
262
+
{0x01cb, 0x0000},
263
+
{0x01cc, 0x5757},
264
+
{0x01cd, 0x5757},
265
+
{0x01ce, 0x5757},
266
+
{0x01cf, 0x5757},
267
+
{0x01d0, 0x5757},
268
+
{0x01d1, 0x5757},
269
+
{0x01d2, 0x5757},
270
+
{0x01d3, 0x5757},
271
+
{0x01d4, 0x5757},
272
+
{0x01d5, 0x5757},
273
+
{0x01d6, 0x0000},
274
+
{0x01d7, 0x0008},
275
+
{0x01d8, 0x0029},
276
+
{0x01d9, 0x3333},
277
+
{0x01da, 0x0000},
278
+
{0x01db, 0x0004},
279
+
{0x01dc, 0x0000},
280
+
{0x01de, 0x7c00},
281
+
{0x01df, 0x0320},
282
+
{0x01e0, 0x06a1},
283
+
{0x01e1, 0x0000},
284
+
{0x01e2, 0x0000},
285
+
{0x01e3, 0x0000},
286
+
{0x01e4, 0x0000},
287
+
{0x01e6, 0x0001},
288
+
{0x01e7, 0x0000},
289
+
{0x01e8, 0x0000},
290
+
{0x01ea, 0x0000},
291
+
{0x01eb, 0x0000},
292
+
{0x01ec, 0x0000},
293
+
{0x01ed, 0x0000},
294
+
{0x01ee, 0x0000},
295
+
{0x01ef, 0x0000},
296
+
{0x01f0, 0x0000},
297
+
{0x01f1, 0x0000},
298
+
{0x01f2, 0x0000},
299
+
{0x01f3, 0x0000},
300
+
{0x01f4, 0x0000},
301
+
{0x0210, 0x6297},
302
+
{0x0211, 0xa005},
303
+
{0x0212, 0x824c},
304
+
{0x0213, 0xf7ff},
305
+
{0x0214, 0xf24c},
306
+
{0x0215, 0x0102},
307
+
{0x0216, 0x00a3},
308
+
{0x0217, 0x0048},
309
+
{0x0218, 0xa2c0},
310
+
{0x0219, 0x0400},
311
+
{0x021a, 0x00c8},
312
+
{0x021b, 0x00c0},
313
+
{0x021c, 0x0000},
314
+
{0x0250, 0x4500},
315
+
{0x0251, 0x40b3},
316
+
{0x0252, 0x0000},
317
+
{0x0253, 0x0000},
318
+
{0x0254, 0x0000},
319
+
{0x0255, 0x0000},
320
+
{0x0256, 0x0000},
321
+
{0x0257, 0x0000},
322
+
{0x0258, 0x0000},
323
+
{0x0259, 0x0000},
324
+
{0x025a, 0x0005},
325
+
{0x0270, 0x0000},
326
+
{0x02ff, 0x0110},
327
+
{0x0300, 0x001f},
328
+
{0x0301, 0x032c},
329
+
{0x0302, 0x5f21},
330
+
{0x0303, 0x4000},
331
+
{0x0304, 0x4000},
332
+
{0x0305, 0x06d5},
333
+
{0x0306, 0x8000},
334
+
{0x0307, 0x0700},
335
+
{0x0310, 0x4560},
336
+
{0x0311, 0xa4a8},
337
+
{0x0312, 0x7418},
338
+
{0x0313, 0x0000},
339
+
{0x0314, 0x0006},
340
+
{0x0315, 0xffff},
341
+
{0x0316, 0xc400},
342
+
{0x0317, 0x0000},
343
+
{0x03c0, 0x7e00},
344
+
{0x03c1, 0x8000},
345
+
{0x03c2, 0x8000},
346
+
{0x03c3, 0x8000},
347
+
{0x03c4, 0x8000},
348
+
{0x03c5, 0x8000},
349
+
{0x03c6, 0x8000},
350
+
{0x03c7, 0x8000},
351
+
{0x03c8, 0x8000},
352
+
{0x03c9, 0x8000},
353
+
{0x03ca, 0x8000},
354
+
{0x03cb, 0x8000},
355
+
{0x03cc, 0x8000},
356
+
{0x03d0, 0x0000},
357
+
{0x03d1, 0x0000},
358
+
{0x03d2, 0x0000},
359
+
{0x03d3, 0x0000},
360
+
{0x03d4, 0x2000},
361
+
{0x03d5, 0x2000},
362
+
{0x03d6, 0x0000},
363
+
{0x03d7, 0x0000},
364
+
{0x03d8, 0x2000},
365
+
{0x03d9, 0x2000},
366
+
{0x03da, 0x2000},
367
+
{0x03db, 0x2000},
368
+
{0x03dc, 0x0000},
369
+
{0x03dd, 0x0000},
370
+
{0x03de, 0x0000},
371
+
{0x03df, 0x2000},
372
+
{0x03e0, 0x0000},
373
+
{0x03e1, 0x0000},
374
+
{0x03e2, 0x0000},
375
+
{0x03e3, 0x0000},
376
+
{0x03e4, 0x0000},
377
+
{0x03e5, 0x0000},
378
+
{0x03e6, 0x0000},
379
+
{0x03e7, 0x0000},
380
+
{0x03e8, 0x0000},
381
+
{0x03e9, 0x0000},
382
+
{0x03ea, 0x0000},
383
+
{0x03eb, 0x0000},
384
+
{0x03ec, 0x0000},
385
+
{0x03ed, 0x0000},
386
+
{0x03ee, 0x0000},
387
+
{0x03ef, 0x0000},
388
+
{0x03f0, 0x0800},
389
+
{0x03f1, 0x0800},
390
+
{0x03f2, 0x0800},
391
+
{0x03f3, 0x0800},
392
+
};
393
+
394
+
static bool rt5682_volatile_register(struct device *dev, unsigned int reg)
395
+
{
396
+
switch (reg) {
397
+
case RT5682_RESET:
398
+
case RT5682_CBJ_CTRL_2:
399
+
case RT5682_INT_ST_1:
400
+
case RT5682_4BTN_IL_CMD_1:
401
+
case RT5682_AJD1_CTRL:
402
+
case RT5682_HP_CALIB_CTRL_1:
403
+
case RT5682_DEVICE_ID:
404
+
case RT5682_I2C_MODE:
405
+
case RT5682_HP_CALIB_CTRL_10:
406
+
case RT5682_EFUSE_CTRL_2:
407
+
case RT5682_JD_TOP_VC_VTRL:
408
+
case RT5682_HP_IMP_SENS_CTRL_19:
409
+
case RT5682_IL_CMD_1:
410
+
case RT5682_SAR_IL_CMD_2:
411
+
case RT5682_SAR_IL_CMD_4:
412
+
case RT5682_SAR_IL_CMD_10:
413
+
case RT5682_SAR_IL_CMD_11:
414
+
case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
415
+
case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
416
+
return true;
417
+
default:
418
+
return false;
419
+
}
420
+
}
421
+
422
+
static bool rt5682_readable_register(struct device *dev, unsigned int reg)
423
+
{
424
+
switch (reg) {
425
+
case RT5682_RESET:
426
+
case RT5682_VERSION_ID:
427
+
case RT5682_VENDOR_ID:
428
+
case RT5682_DEVICE_ID:
429
+
case RT5682_HP_CTRL_1:
430
+
case RT5682_HP_CTRL_2:
431
+
case RT5682_HPL_GAIN:
432
+
case RT5682_HPR_GAIN:
433
+
case RT5682_I2C_CTRL:
434
+
case RT5682_CBJ_BST_CTRL:
435
+
case RT5682_CBJ_CTRL_1:
436
+
case RT5682_CBJ_CTRL_2:
437
+
case RT5682_CBJ_CTRL_3:
438
+
case RT5682_CBJ_CTRL_4:
439
+
case RT5682_CBJ_CTRL_5:
440
+
case RT5682_CBJ_CTRL_6:
441
+
case RT5682_CBJ_CTRL_7:
442
+
case RT5682_DAC1_DIG_VOL:
443
+
case RT5682_STO1_ADC_DIG_VOL:
444
+
case RT5682_STO1_ADC_BOOST:
445
+
case RT5682_HP_IMP_GAIN_1:
446
+
case RT5682_HP_IMP_GAIN_2:
447
+
case RT5682_SIDETONE_CTRL:
448
+
case RT5682_STO1_ADC_MIXER:
449
+
case RT5682_AD_DA_MIXER:
450
+
case RT5682_STO1_DAC_MIXER:
451
+
case RT5682_A_DAC1_MUX:
452
+
case RT5682_DIG_INF2_DATA:
453
+
case RT5682_REC_MIXER:
454
+
case RT5682_CAL_REC:
455
+
case RT5682_ALC_BACK_GAIN:
456
+
case RT5682_PWR_DIG_1:
457
+
case RT5682_PWR_DIG_2:
458
+
case RT5682_PWR_ANLG_1:
459
+
case RT5682_PWR_ANLG_2:
460
+
case RT5682_PWR_ANLG_3:
461
+
case RT5682_PWR_MIXER:
462
+
case RT5682_PWR_VOL:
463
+
case RT5682_CLK_DET:
464
+
case RT5682_RESET_LPF_CTRL:
465
+
case RT5682_RESET_HPF_CTRL:
466
+
case RT5682_DMIC_CTRL_1:
467
+
case RT5682_I2S1_SDP:
468
+
case RT5682_I2S2_SDP:
469
+
case RT5682_ADDA_CLK_1:
470
+
case RT5682_ADDA_CLK_2:
471
+
case RT5682_I2S1_F_DIV_CTRL_1:
472
+
case RT5682_I2S1_F_DIV_CTRL_2:
473
+
case RT5682_TDM_CTRL:
474
+
case RT5682_TDM_ADDA_CTRL_1:
475
+
case RT5682_TDM_ADDA_CTRL_2:
476
+
case RT5682_DATA_SEL_CTRL_1:
477
+
case RT5682_TDM_TCON_CTRL:
478
+
case RT5682_GLB_CLK:
479
+
case RT5682_PLL_CTRL_1:
480
+
case RT5682_PLL_CTRL_2:
481
+
case RT5682_PLL_TRACK_1:
482
+
case RT5682_PLL_TRACK_2:
483
+
case RT5682_PLL_TRACK_3:
484
+
case RT5682_PLL_TRACK_4:
485
+
case RT5682_PLL_TRACK_5:
486
+
case RT5682_PLL_TRACK_6:
487
+
case RT5682_PLL_TRACK_11:
488
+
case RT5682_SDW_REF_CLK:
489
+
case RT5682_DEPOP_1:
490
+
case RT5682_DEPOP_2:
491
+
case RT5682_HP_CHARGE_PUMP_1:
492
+
case RT5682_HP_CHARGE_PUMP_2:
493
+
case RT5682_MICBIAS_1:
494
+
case RT5682_MICBIAS_2:
495
+
case RT5682_PLL_TRACK_12:
496
+
case RT5682_PLL_TRACK_14:
497
+
case RT5682_PLL2_CTRL_1:
498
+
case RT5682_PLL2_CTRL_2:
499
+
case RT5682_PLL2_CTRL_3:
500
+
case RT5682_PLL2_CTRL_4:
501
+
case RT5682_RC_CLK_CTRL:
502
+
case RT5682_I2S_M_CLK_CTRL_1:
503
+
case RT5682_I2S2_F_DIV_CTRL_1:
504
+
case RT5682_I2S2_F_DIV_CTRL_2:
505
+
case RT5682_EQ_CTRL_1:
506
+
case RT5682_EQ_CTRL_2:
507
+
case RT5682_IRQ_CTRL_1:
508
+
case RT5682_IRQ_CTRL_2:
509
+
case RT5682_IRQ_CTRL_3:
510
+
case RT5682_IRQ_CTRL_4:
511
+
case RT5682_INT_ST_1:
512
+
case RT5682_GPIO_CTRL_1:
513
+
case RT5682_GPIO_CTRL_2:
514
+
case RT5682_GPIO_CTRL_3:
515
+
case RT5682_HP_AMP_DET_CTRL_1:
516
+
case RT5682_HP_AMP_DET_CTRL_2:
517
+
case RT5682_MID_HP_AMP_DET:
518
+
case RT5682_LOW_HP_AMP_DET:
519
+
case RT5682_DELAY_BUF_CTRL:
520
+
case RT5682_SV_ZCD_1:
521
+
case RT5682_SV_ZCD_2:
522
+
case RT5682_IL_CMD_1:
523
+
case RT5682_IL_CMD_2:
524
+
case RT5682_IL_CMD_3:
525
+
case RT5682_IL_CMD_4:
526
+
case RT5682_IL_CMD_5:
527
+
case RT5682_IL_CMD_6:
528
+
case RT5682_4BTN_IL_CMD_1:
529
+
case RT5682_4BTN_IL_CMD_2:
530
+
case RT5682_4BTN_IL_CMD_3:
531
+
case RT5682_4BTN_IL_CMD_4:
532
+
case RT5682_4BTN_IL_CMD_5:
533
+
case RT5682_4BTN_IL_CMD_6:
534
+
case RT5682_4BTN_IL_CMD_7:
535
+
case RT5682_ADC_STO1_HP_CTRL_1:
536
+
case RT5682_ADC_STO1_HP_CTRL_2:
537
+
case RT5682_AJD1_CTRL:
538
+
case RT5682_JD1_THD:
539
+
case RT5682_JD2_THD:
540
+
case RT5682_JD_CTRL_1:
541
+
case RT5682_DUMMY_1:
542
+
case RT5682_DUMMY_2:
543
+
case RT5682_DUMMY_3:
544
+
case RT5682_DAC_ADC_DIG_VOL1:
545
+
case RT5682_BIAS_CUR_CTRL_2:
546
+
case RT5682_BIAS_CUR_CTRL_3:
547
+
case RT5682_BIAS_CUR_CTRL_4:
548
+
case RT5682_BIAS_CUR_CTRL_5:
549
+
case RT5682_BIAS_CUR_CTRL_6:
550
+
case RT5682_BIAS_CUR_CTRL_7:
551
+
case RT5682_BIAS_CUR_CTRL_8:
552
+
case RT5682_BIAS_CUR_CTRL_9:
553
+
case RT5682_BIAS_CUR_CTRL_10:
554
+
case RT5682_VREF_REC_OP_FB_CAP_CTRL:
555
+
case RT5682_CHARGE_PUMP_1:
556
+
case RT5682_DIG_IN_CTRL_1:
557
+
case RT5682_PAD_DRIVING_CTRL:
558
+
case RT5682_SOFT_RAMP_DEPOP:
559
+
case RT5682_CHOP_DAC:
560
+
case RT5682_CHOP_ADC:
561
+
case RT5682_CALIB_ADC_CTRL:
562
+
case RT5682_VOL_TEST:
563
+
case RT5682_SPKVDD_DET_STA:
564
+
case RT5682_TEST_MODE_CTRL_1:
565
+
case RT5682_TEST_MODE_CTRL_2:
566
+
case RT5682_TEST_MODE_CTRL_3:
567
+
case RT5682_TEST_MODE_CTRL_4:
568
+
case RT5682_TEST_MODE_CTRL_5:
569
+
case RT5682_PLL1_INTERNAL:
570
+
case RT5682_PLL2_INTERNAL:
571
+
case RT5682_STO_NG2_CTRL_1:
572
+
case RT5682_STO_NG2_CTRL_2:
573
+
case RT5682_STO_NG2_CTRL_3:
574
+
case RT5682_STO_NG2_CTRL_4:
575
+
case RT5682_STO_NG2_CTRL_5:
576
+
case RT5682_STO_NG2_CTRL_6:
577
+
case RT5682_STO_NG2_CTRL_7:
578
+
case RT5682_STO_NG2_CTRL_8:
579
+
case RT5682_STO_NG2_CTRL_9:
580
+
case RT5682_STO_NG2_CTRL_10:
581
+
case RT5682_STO1_DAC_SIL_DET:
582
+
case RT5682_SIL_PSV_CTRL1:
583
+
case RT5682_SIL_PSV_CTRL2:
584
+
case RT5682_SIL_PSV_CTRL3:
585
+
case RT5682_SIL_PSV_CTRL4:
586
+
case RT5682_SIL_PSV_CTRL5:
587
+
case RT5682_HP_IMP_SENS_CTRL_01:
588
+
case RT5682_HP_IMP_SENS_CTRL_02:
589
+
case RT5682_HP_IMP_SENS_CTRL_03:
590
+
case RT5682_HP_IMP_SENS_CTRL_04:
591
+
case RT5682_HP_IMP_SENS_CTRL_05:
592
+
case RT5682_HP_IMP_SENS_CTRL_06:
593
+
case RT5682_HP_IMP_SENS_CTRL_07:
594
+
case RT5682_HP_IMP_SENS_CTRL_08:
595
+
case RT5682_HP_IMP_SENS_CTRL_09:
596
+
case RT5682_HP_IMP_SENS_CTRL_10:
597
+
case RT5682_HP_IMP_SENS_CTRL_11:
598
+
case RT5682_HP_IMP_SENS_CTRL_12:
599
+
case RT5682_HP_IMP_SENS_CTRL_13:
600
+
case RT5682_HP_IMP_SENS_CTRL_14:
601
+
case RT5682_HP_IMP_SENS_CTRL_15:
602
+
case RT5682_HP_IMP_SENS_CTRL_16:
603
+
case RT5682_HP_IMP_SENS_CTRL_17:
604
+
case RT5682_HP_IMP_SENS_CTRL_18:
605
+
case RT5682_HP_IMP_SENS_CTRL_19:
606
+
case RT5682_HP_IMP_SENS_CTRL_20:
607
+
case RT5682_HP_IMP_SENS_CTRL_21:
608
+
case RT5682_HP_IMP_SENS_CTRL_22:
609
+
case RT5682_HP_IMP_SENS_CTRL_23:
610
+
case RT5682_HP_IMP_SENS_CTRL_24:
611
+
case RT5682_HP_IMP_SENS_CTRL_25:
612
+
case RT5682_HP_IMP_SENS_CTRL_26:
613
+
case RT5682_HP_IMP_SENS_CTRL_27:
614
+
case RT5682_HP_IMP_SENS_CTRL_28:
615
+
case RT5682_HP_IMP_SENS_CTRL_29:
616
+
case RT5682_HP_IMP_SENS_CTRL_30:
617
+
case RT5682_HP_IMP_SENS_CTRL_31:
618
+
case RT5682_HP_IMP_SENS_CTRL_32:
619
+
case RT5682_HP_IMP_SENS_CTRL_33:
620
+
case RT5682_HP_IMP_SENS_CTRL_34:
621
+
case RT5682_HP_IMP_SENS_CTRL_35:
622
+
case RT5682_HP_IMP_SENS_CTRL_36:
623
+
case RT5682_HP_IMP_SENS_CTRL_37:
624
+
case RT5682_HP_IMP_SENS_CTRL_38:
625
+
case RT5682_HP_IMP_SENS_CTRL_39:
626
+
case RT5682_HP_IMP_SENS_CTRL_40:
627
+
case RT5682_HP_IMP_SENS_CTRL_41:
628
+
case RT5682_HP_IMP_SENS_CTRL_42:
629
+
case RT5682_HP_IMP_SENS_CTRL_43:
630
+
case RT5682_HP_LOGIC_CTRL_1:
631
+
case RT5682_HP_LOGIC_CTRL_2:
632
+
case RT5682_HP_LOGIC_CTRL_3:
633
+
case RT5682_HP_CALIB_CTRL_1:
634
+
case RT5682_HP_CALIB_CTRL_2:
635
+
case RT5682_HP_CALIB_CTRL_3:
636
+
case RT5682_HP_CALIB_CTRL_4:
637
+
case RT5682_HP_CALIB_CTRL_5:
638
+
case RT5682_HP_CALIB_CTRL_6:
639
+
case RT5682_HP_CALIB_CTRL_7:
640
+
case RT5682_HP_CALIB_CTRL_9:
641
+
case RT5682_HP_CALIB_CTRL_10:
642
+
case RT5682_HP_CALIB_CTRL_11:
643
+
case RT5682_HP_CALIB_STA_1:
644
+
case RT5682_HP_CALIB_STA_2:
645
+
case RT5682_HP_CALIB_STA_3:
646
+
case RT5682_HP_CALIB_STA_4:
647
+
case RT5682_HP_CALIB_STA_5:
648
+
case RT5682_HP_CALIB_STA_6:
649
+
case RT5682_HP_CALIB_STA_7:
650
+
case RT5682_HP_CALIB_STA_8:
651
+
case RT5682_HP_CALIB_STA_9:
652
+
case RT5682_HP_CALIB_STA_10:
653
+
case RT5682_HP_CALIB_STA_11:
654
+
case RT5682_SAR_IL_CMD_1:
655
+
case RT5682_SAR_IL_CMD_2:
656
+
case RT5682_SAR_IL_CMD_3:
657
+
case RT5682_SAR_IL_CMD_4:
658
+
case RT5682_SAR_IL_CMD_5:
659
+
case RT5682_SAR_IL_CMD_6:
660
+
case RT5682_SAR_IL_CMD_7:
661
+
case RT5682_SAR_IL_CMD_8:
662
+
case RT5682_SAR_IL_CMD_9:
663
+
case RT5682_SAR_IL_CMD_10:
664
+
case RT5682_SAR_IL_CMD_11:
665
+
case RT5682_SAR_IL_CMD_12:
666
+
case RT5682_SAR_IL_CMD_13:
667
+
case RT5682_EFUSE_CTRL_1:
668
+
case RT5682_EFUSE_CTRL_2:
669
+
case RT5682_EFUSE_CTRL_3:
670
+
case RT5682_EFUSE_CTRL_4:
671
+
case RT5682_EFUSE_CTRL_5:
672
+
case RT5682_EFUSE_CTRL_6:
673
+
case RT5682_EFUSE_CTRL_7:
674
+
case RT5682_EFUSE_CTRL_8:
675
+
case RT5682_EFUSE_CTRL_9:
676
+
case RT5682_EFUSE_CTRL_10:
677
+
case RT5682_EFUSE_CTRL_11:
678
+
case RT5682_JD_TOP_VC_VTRL:
679
+
case RT5682_DRC1_CTRL_0:
680
+
case RT5682_DRC1_CTRL_1:
681
+
case RT5682_DRC1_CTRL_2:
682
+
case RT5682_DRC1_CTRL_3:
683
+
case RT5682_DRC1_CTRL_4:
684
+
case RT5682_DRC1_CTRL_5:
685
+
case RT5682_DRC1_CTRL_6:
686
+
case RT5682_DRC1_HARD_LMT_CTRL_1:
687
+
case RT5682_DRC1_HARD_LMT_CTRL_2:
688
+
case RT5682_DRC1_PRIV_1:
689
+
case RT5682_DRC1_PRIV_2:
690
+
case RT5682_DRC1_PRIV_3:
691
+
case RT5682_DRC1_PRIV_4:
692
+
case RT5682_DRC1_PRIV_5:
693
+
case RT5682_DRC1_PRIV_6:
694
+
case RT5682_DRC1_PRIV_7:
695
+
case RT5682_DRC1_PRIV_8:
696
+
case RT5682_EQ_AUTO_RCV_CTRL1:
697
+
case RT5682_EQ_AUTO_RCV_CTRL2:
698
+
case RT5682_EQ_AUTO_RCV_CTRL3:
699
+
case RT5682_EQ_AUTO_RCV_CTRL4:
700
+
case RT5682_EQ_AUTO_RCV_CTRL5:
701
+
case RT5682_EQ_AUTO_RCV_CTRL6:
702
+
case RT5682_EQ_AUTO_RCV_CTRL7:
703
+
case RT5682_EQ_AUTO_RCV_CTRL8:
704
+
case RT5682_EQ_AUTO_RCV_CTRL9:
705
+
case RT5682_EQ_AUTO_RCV_CTRL10:
706
+
case RT5682_EQ_AUTO_RCV_CTRL11:
707
+
case RT5682_EQ_AUTO_RCV_CTRL12:
708
+
case RT5682_EQ_AUTO_RCV_CTRL13:
709
+
case RT5682_ADC_L_EQ_LPF1_A1:
710
+
case RT5682_R_EQ_LPF1_A1:
711
+
case RT5682_L_EQ_LPF1_H0:
712
+
case RT5682_R_EQ_LPF1_H0:
713
+
case RT5682_L_EQ_BPF1_A1:
714
+
case RT5682_R_EQ_BPF1_A1:
715
+
case RT5682_L_EQ_BPF1_A2:
716
+
case RT5682_R_EQ_BPF1_A2:
717
+
case RT5682_L_EQ_BPF1_H0:
718
+
case RT5682_R_EQ_BPF1_H0:
719
+
case RT5682_L_EQ_BPF2_A1:
720
+
case RT5682_R_EQ_BPF2_A1:
721
+
case RT5682_L_EQ_BPF2_A2:
722
+
case RT5682_R_EQ_BPF2_A2:
723
+
case RT5682_L_EQ_BPF2_H0:
724
+
case RT5682_R_EQ_BPF2_H0:
725
+
case RT5682_L_EQ_BPF3_A1:
726
+
case RT5682_R_EQ_BPF3_A1:
727
+
case RT5682_L_EQ_BPF3_A2:
728
+
case RT5682_R_EQ_BPF3_A2:
729
+
case RT5682_L_EQ_BPF3_H0:
730
+
case RT5682_R_EQ_BPF3_H0:
731
+
case RT5682_L_EQ_BPF4_A1:
732
+
case RT5682_R_EQ_BPF4_A1:
733
+
case RT5682_L_EQ_BPF4_A2:
734
+
case RT5682_R_EQ_BPF4_A2:
735
+
case RT5682_L_EQ_BPF4_H0:
736
+
case RT5682_R_EQ_BPF4_H0:
737
+
case RT5682_L_EQ_HPF1_A1:
738
+
case RT5682_R_EQ_HPF1_A1:
739
+
case RT5682_L_EQ_HPF1_H0:
740
+
case RT5682_R_EQ_HPF1_H0:
741
+
case RT5682_L_EQ_PRE_VOL:
742
+
case RT5682_R_EQ_PRE_VOL:
743
+
case RT5682_L_EQ_POST_VOL:
744
+
case RT5682_R_EQ_POST_VOL:
745
+
case RT5682_I2C_MODE:
746
+
return true;
747
+
default:
748
+
return false;
749
+
}
750
+
}
751
+
752
+
static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
753
+
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
754
+
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
755
+
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
756
+
757
+
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
758
+
static const DECLARE_TLV_DB_RANGE(bst_tlv,
759
+
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
760
+
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
761
+
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
762
+
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
763
+
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
764
+
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
765
+
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
766
+
);
767
+
768
+
/* Interface data select */
769
+
static const char * const rt5682_data_select[] = {
770
+
"L/R", "R/L", "L/L", "R/R"
771
+
};
772
+
773
+
static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
774
+
RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
775
+
776
+
static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
777
+
RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
778
+
779
+
static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
780
+
RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
781
+
782
+
static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
783
+
RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
784
+
785
+
static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
786
+
RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
787
+
788
+
static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
789
+
SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
790
+
791
+
static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
792
+
SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
793
+
794
+
static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
795
+
SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
796
+
797
+
static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
798
+
SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
799
+
800
+
static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
801
+
SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
802
+
803
+
static void rt5682_reset(struct regmap *regmap)
804
+
{
805
+
regmap_write(regmap, RT5682_RESET, 0);
806
+
regmap_write(regmap, RT5682_I2C_MODE, 1);
807
+
}
808
+
/**
809
+
* rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
810
+
* @component: SoC audio component device.
811
+
* @filter_mask: mask of filters.
812
+
* @clk_src: clock source
813
+
*
814
+
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
815
+
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
816
+
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
817
+
* ASRC function will track i2s clock and generate a corresponding system clock
818
+
* for codec. This function provides an API to select the clock source for a
819
+
* set of filters specified by the mask. And the component driver will turn on
820
+
* ASRC for these filters if ASRC is selected as their clock source.
821
+
*/
822
+
int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
823
+
unsigned int filter_mask, unsigned int clk_src)
824
+
{
825
+
826
+
switch (clk_src) {
827
+
case RT5682_CLK_SEL_SYS:
828
+
case RT5682_CLK_SEL_I2S1_ASRC:
829
+
case RT5682_CLK_SEL_I2S2_ASRC:
830
+
break;
831
+
832
+
default:
833
+
return -EINVAL;
834
+
}
835
+
836
+
if (filter_mask & RT5682_DA_STEREO1_FILTER) {
837
+
snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
838
+
RT5682_FILTER_CLK_SEL_MASK,
839
+
clk_src << RT5682_FILTER_CLK_SEL_SFT);
840
+
}
841
+
842
+
if (filter_mask & RT5682_AD_STEREO1_FILTER) {
843
+
snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
844
+
RT5682_FILTER_CLK_SEL_MASK,
845
+
clk_src << RT5682_FILTER_CLK_SEL_SFT);
846
+
}
847
+
848
+
return 0;
849
+
}
850
+
EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
851
+
852
+
static int rt5682_button_detect(struct snd_soc_component *component)
853
+
{
854
+
int btn_type, val;
855
+
856
+
val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1);
857
+
btn_type = val & 0xfff0;
858
+
snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
859
+
pr_debug("%s btn_type=%x\n", __func__, btn_type);
860
+
861
+
return btn_type;
862
+
}
863
+
864
+
static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
865
+
bool enable)
866
+
{
867
+
if (enable) {
868
+
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
869
+
RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
870
+
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
871
+
RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
872
+
snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
873
+
snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
874
+
RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
875
+
RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
876
+
snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
877
+
RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN);
878
+
} else {
879
+
snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
880
+
RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
881
+
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
882
+
RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
883
+
snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
884
+
RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
885
+
snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
886
+
RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
887
+
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
888
+
RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
889
+
}
890
+
}
891
+
892
+
/**
893
+
* rt5682_headset_detect - Detect headset.
894
+
* @component: SoC audio component device.
895
+
* @jack_insert: Jack insert or not.
896
+
*
897
+
* Detect whether is headset or not when jack inserted.
898
+
*
899
+
* Returns detect status.
900
+
*/
901
+
static int rt5682_headset_detect(struct snd_soc_component *component,
902
+
int jack_insert)
903
+
{
904
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
905
+
struct snd_soc_dapm_context *dapm =
906
+
snd_soc_component_get_dapm(component);
907
+
unsigned int val, count;
908
+
909
+
if (jack_insert) {
910
+
snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
911
+
snd_soc_dapm_sync(dapm);
912
+
snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
913
+
RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
914
+
915
+
count = 0;
916
+
val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2)
917
+
& RT5682_JACK_TYPE_MASK;
918
+
while (val == 0 && count < 50) {
919
+
usleep_range(10000, 15000);
920
+
val = snd_soc_component_read32(component,
921
+
RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
922
+
count++;
923
+
}
924
+
925
+
switch (val) {
926
+
case 0x1:
927
+
case 0x2:
928
+
rt5682->jack_type = SND_JACK_HEADSET;
929
+
rt5682_enable_push_button_irq(component, true);
930
+
break;
931
+
default:
932
+
rt5682->jack_type = SND_JACK_HEADPHONE;
933
+
}
934
+
935
+
} else {
936
+
rt5682_enable_push_button_irq(component, false);
937
+
snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
938
+
RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
939
+
snd_soc_dapm_disable_pin(dapm, "CBJ Power");
940
+
snd_soc_dapm_sync(dapm);
941
+
942
+
rt5682->jack_type = 0;
943
+
}
944
+
945
+
dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
946
+
return rt5682->jack_type;
947
+
}
948
+
949
+
static irqreturn_t rt5682_irq(int irq, void *data)
950
+
{
951
+
struct rt5682_priv *rt5682 = data;
952
+
953
+
mod_delayed_work(system_power_efficient_wq,
954
+
&rt5682->jack_detect_work, msecs_to_jiffies(250));
955
+
956
+
return IRQ_HANDLED;
957
+
}
958
+
959
+
static void rt5682_jd_check_handler(struct work_struct *work)
960
+
{
961
+
struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv,
962
+
jd_check_work.work);
963
+
964
+
if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
965
+
& RT5682_JDH_RS_MASK) {
966
+
/* jack out */
967
+
rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
968
+
969
+
snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
970
+
SND_JACK_HEADSET |
971
+
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
972
+
SND_JACK_BTN_2 | SND_JACK_BTN_3);
973
+
} else {
974
+
schedule_delayed_work(&rt5682->jd_check_work, 500);
975
+
}
976
+
}
977
+
978
+
static int rt5682_set_jack_detect(struct snd_soc_component *component,
979
+
struct snd_soc_jack *hs_jack, void *data)
980
+
{
981
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
982
+
983
+
switch (rt5682->pdata.jd_src) {
984
+
case RT5682_JD1:
985
+
snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2,
986
+
RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
987
+
snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042);
988
+
snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3,
989
+
RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
990
+
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
991
+
RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
992
+
regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
993
+
RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
994
+
regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
995
+
RT5682_POW_IRQ | RT5682_POW_JDH |
996
+
RT5682_POW_ANA, RT5682_POW_IRQ |
997
+
RT5682_POW_JDH | RT5682_POW_ANA);
998
+
regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
999
+
RT5682_PWR_JDH | RT5682_PWR_JDL,
1000
+
RT5682_PWR_JDH | RT5682_PWR_JDL);
1001
+
regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1002
+
RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1003
+
RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1004
+
mod_delayed_work(system_power_efficient_wq,
1005
+
&rt5682->jack_detect_work, msecs_to_jiffies(250));
1006
+
break;
1007
+
1008
+
case RT5682_JD_NULL:
1009
+
regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1010
+
RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1011
+
regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1012
+
RT5682_POW_JDH | RT5682_POW_JDL, 0);
1013
+
break;
1014
+
1015
+
default:
1016
+
dev_warn(component->dev, "Wrong JD source\n");
1017
+
break;
1018
+
}
1019
+
1020
+
rt5682->hs_jack = hs_jack;
1021
+
1022
+
return 0;
1023
+
}
1024
+
1025
+
static void rt5682_jack_detect_handler(struct work_struct *work)
1026
+
{
1027
+
struct rt5682_priv *rt5682 =
1028
+
container_of(work, struct rt5682_priv, jack_detect_work.work);
1029
+
int val, btn_type;
1030
+
1031
+
while (!rt5682->component)
1032
+
usleep_range(10000, 15000);
1033
+
1034
+
while (!rt5682->component->card->instantiated)
1035
+
usleep_range(10000, 15000);
1036
+
1037
+
mutex_lock(&rt5682->calibrate_mutex);
1038
+
1039
+
val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
1040
+
& RT5682_JDH_RS_MASK;
1041
+
if (!val) {
1042
+
/* jack in */
1043
+
if (rt5682->jack_type == 0) {
1044
+
/* jack was out, report jack type */
1045
+
rt5682->jack_type =
1046
+
rt5682_headset_detect(rt5682->component, 1);
1047
+
} else {
1048
+
/* jack is already in, report button event */
1049
+
rt5682->jack_type = SND_JACK_HEADSET;
1050
+
btn_type = rt5682_button_detect(rt5682->component);
1051
+
/**
1052
+
* rt5682 can report three kinds of button behavior,
1053
+
* one click, double click and hold. However,
1054
+
* currently we will report button pressed/released
1055
+
* event. So all the three button behaviors are
1056
+
* treated as button pressed.
1057
+
*/
1058
+
switch (btn_type) {
1059
+
case 0x8000:
1060
+
case 0x4000:
1061
+
case 0x2000:
1062
+
rt5682->jack_type |= SND_JACK_BTN_0;
1063
+
break;
1064
+
case 0x1000:
1065
+
case 0x0800:
1066
+
case 0x0400:
1067
+
rt5682->jack_type |= SND_JACK_BTN_1;
1068
+
break;
1069
+
case 0x0200:
1070
+
case 0x0100:
1071
+
case 0x0080:
1072
+
rt5682->jack_type |= SND_JACK_BTN_2;
1073
+
break;
1074
+
case 0x0040:
1075
+
case 0x0020:
1076
+
case 0x0010:
1077
+
rt5682->jack_type |= SND_JACK_BTN_3;
1078
+
break;
1079
+
case 0x0000: /* unpressed */
1080
+
break;
1081
+
default:
1082
+
btn_type = 0;
1083
+
dev_err(rt5682->component->dev,
1084
+
"Unexpected button code 0x%04x\n",
1085
+
btn_type);
1086
+
break;
1087
+
}
1088
+
}
1089
+
} else {
1090
+
/* jack out */
1091
+
rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1092
+
}
1093
+
1094
+
snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1095
+
SND_JACK_HEADSET |
1096
+
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1097
+
SND_JACK_BTN_2 | SND_JACK_BTN_3);
1098
+
1099
+
if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1100
+
SND_JACK_BTN_2 | SND_JACK_BTN_3))
1101
+
schedule_delayed_work(&rt5682->jd_check_work, 0);
1102
+
else
1103
+
cancel_delayed_work_sync(&rt5682->jd_check_work);
1104
+
1105
+
mutex_unlock(&rt5682->calibrate_mutex);
1106
+
}
1107
+
1108
+
static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1109
+
/* Headphone Output Volume */
1110
+
SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5682_HPL_GAIN,
1111
+
RT5682_HPR_GAIN, RT5682_G_HP_SFT, 15, 1, hp_vol_tlv),
1112
+
1113
+
/* DAC Digital Volume */
1114
+
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1115
+
RT5682_L_VOL_SFT, RT5682_R_VOL_SFT, 175, 0, dac_vol_tlv),
1116
+
1117
+
/* IN Boost Volume */
1118
+
SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1119
+
RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1120
+
1121
+
/* ADC Digital Volume Control */
1122
+
SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1123
+
RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1124
+
SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1125
+
RT5682_L_VOL_SFT, RT5682_R_VOL_SFT, 127, 0, adc_vol_tlv),
1126
+
1127
+
/* ADC Boost Volume Control */
1128
+
SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1129
+
RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1130
+
3, 0, adc_bst_tlv),
1131
+
};
1132
+
1133
+
1134
+
static int rt5682_div_sel(struct rt5682_priv *rt5682,
1135
+
int target, const int div[], int size)
1136
+
{
1137
+
int i;
1138
+
1139
+
if (rt5682->sysclk < target) {
1140
+
pr_err("sysclk rate %d is too low\n",
1141
+
rt5682->sysclk);
1142
+
return 0;
1143
+
}
1144
+
1145
+
for (i = 0; i < size - 1; i++) {
1146
+
pr_info("div[%d]=%d\n", i, div[i]);
1147
+
if (target * div[i] == rt5682->sysclk)
1148
+
return i;
1149
+
if (target * div[i + 1] > rt5682->sysclk) {
1150
+
pr_err("can't find div for sysclk %d\n",
1151
+
rt5682->sysclk);
1152
+
return i;
1153
+
}
1154
+
}
1155
+
1156
+
if (target * div[i] < rt5682->sysclk)
1157
+
pr_err("sysclk rate %d is too high\n",
1158
+
rt5682->sysclk);
1159
+
1160
+
return size - 1;
1161
+
1162
+
}
1163
+
1164
+
/**
1165
+
* set_dmic_clk - Set parameter of dmic.
1166
+
*
1167
+
* @w: DAPM widget.
1168
+
* @kcontrol: The kcontrol of this widget.
1169
+
* @event: Event id.
1170
+
*
1171
+
* Choose dmic clock between 1MHz and 3MHz.
1172
+
* It is better for clock to approximate 3MHz.
1173
+
*/
1174
+
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1175
+
struct snd_kcontrol *kcontrol, int event)
1176
+
{
1177
+
struct snd_soc_component *component =
1178
+
snd_soc_dapm_to_component(w->dapm);
1179
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1180
+
int idx = -EINVAL;
1181
+
static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1182
+
1183
+
idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div));
1184
+
1185
+
snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1186
+
RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1187
+
1188
+
return 0;
1189
+
}
1190
+
1191
+
static int set_filter_clk(struct snd_soc_dapm_widget *w,
1192
+
struct snd_kcontrol *kcontrol, int event)
1193
+
{
1194
+
struct snd_soc_component *component =
1195
+
snd_soc_dapm_to_component(w->dapm);
1196
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1197
+
int ref, val, reg, sft, mask, idx = -EINVAL;
1198
+
static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1199
+
static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1200
+
1201
+
val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) &
1202
+
RT5682_GP4_PIN_MASK;
1203
+
if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1204
+
val == RT5682_GP4_PIN_ADCDAT2)
1205
+
ref = 256 * rt5682->lrck[RT5682_AIF2];
1206
+
else
1207
+
ref = 256 * rt5682->lrck[RT5682_AIF1];
1208
+
1209
+
idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1210
+
1211
+
if (w->shift == RT5682_PWR_ADC_S1F_BIT) {
1212
+
reg = RT5682_PLL_TRACK_3;
1213
+
sft = RT5682_ADC_OSR_SFT;
1214
+
mask = RT5682_ADC_OSR_MASK;
1215
+
} else {
1216
+
reg = RT5682_PLL_TRACK_2;
1217
+
sft = RT5682_DAC_OSR_SFT;
1218
+
mask = RT5682_DAC_OSR_MASK;
1219
+
}
1220
+
1221
+
snd_soc_component_update_bits(component, reg,
1222
+
RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1223
+
1224
+
/* select over sample rate */
1225
+
for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1226
+
if (rt5682->sysclk <= 12288000 * div_o[idx])
1227
+
break;
1228
+
}
1229
+
1230
+
snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1231
+
mask, idx << sft);
1232
+
1233
+
return 0;
1234
+
}
1235
+
1236
+
static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1237
+
struct snd_soc_dapm_widget *sink)
1238
+
{
1239
+
unsigned int val;
1240
+
struct snd_soc_component *component =
1241
+
snd_soc_dapm_to_component(w->dapm);
1242
+
1243
+
val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1244
+
val &= RT5682_SCLK_SRC_MASK;
1245
+
if (val == RT5682_SCLK_SRC_PLL1)
1246
+
return 1;
1247
+
else
1248
+
return 0;
1249
+
}
1250
+
1251
+
static int is_using_asrc(struct snd_soc_dapm_widget *w,
1252
+
struct snd_soc_dapm_widget *sink)
1253
+
{
1254
+
unsigned int reg, shift, val;
1255
+
struct snd_soc_component *component =
1256
+
snd_soc_dapm_to_component(w->dapm);
1257
+
1258
+
switch (w->shift) {
1259
+
case RT5682_ADC_STO1_ASRC_SFT:
1260
+
reg = RT5682_PLL_TRACK_3;
1261
+
shift = RT5682_FILTER_CLK_SEL_SFT;
1262
+
break;
1263
+
case RT5682_DAC_STO1_ASRC_SFT:
1264
+
reg = RT5682_PLL_TRACK_2;
1265
+
shift = RT5682_FILTER_CLK_SEL_SFT;
1266
+
break;
1267
+
default:
1268
+
return 0;
1269
+
}
1270
+
1271
+
val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1272
+
switch (val) {
1273
+
case RT5682_CLK_SEL_I2S1_ASRC:
1274
+
case RT5682_CLK_SEL_I2S2_ASRC:
1275
+
return 1;
1276
+
default:
1277
+
return 0;
1278
+
}
1279
+
1280
+
}
1281
+
1282
+
/* Digital Mixer */
1283
+
static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1284
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1285
+
RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1286
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1287
+
RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1288
+
};
1289
+
1290
+
static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1291
+
SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1292
+
RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1293
+
SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1294
+
RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1295
+
};
1296
+
1297
+
static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1298
+
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1299
+
RT5682_M_ADCMIX_L_SFT, 1, 1),
1300
+
SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1301
+
RT5682_M_DAC1_L_SFT, 1, 1),
1302
+
};
1303
+
1304
+
static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1305
+
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1306
+
RT5682_M_ADCMIX_R_SFT, 1, 1),
1307
+
SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1308
+
RT5682_M_DAC1_R_SFT, 1, 1),
1309
+
};
1310
+
1311
+
static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1312
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1313
+
RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1314
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1315
+
RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1316
+
};
1317
+
1318
+
static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1319
+
SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1320
+
RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1321
+
SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1322
+
RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1323
+
};
1324
+
1325
+
/* Analog Input Mixer */
1326
+
static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1327
+
SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1328
+
RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1329
+
};
1330
+
1331
+
/* STO1 ADC1 Source */
1332
+
/* MX-26 [13] [5] */
1333
+
static const char * const rt5682_sto1_adc1_src[] = {
1334
+
"DAC MIX", "ADC"
1335
+
};
1336
+
1337
+
static SOC_ENUM_SINGLE_DECL(
1338
+
rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1339
+
RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1340
+
1341
+
static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1342
+
SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1343
+
1344
+
static SOC_ENUM_SINGLE_DECL(
1345
+
rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1346
+
RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1347
+
1348
+
static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1349
+
SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1350
+
1351
+
/* STO1 ADC Source */
1352
+
/* MX-26 [11:10] [3:2] */
1353
+
static const char * const rt5682_sto1_adc_src[] = {
1354
+
"ADC1 L", "ADC1 R"
1355
+
};
1356
+
1357
+
static SOC_ENUM_SINGLE_DECL(
1358
+
rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1359
+
RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1360
+
1361
+
static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1362
+
SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1363
+
1364
+
static SOC_ENUM_SINGLE_DECL(
1365
+
rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1366
+
RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1367
+
1368
+
static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1369
+
SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1370
+
1371
+
/* STO1 ADC2 Source */
1372
+
/* MX-26 [12] [4] */
1373
+
static const char * const rt5682_sto1_adc2_src[] = {
1374
+
"DAC MIX", "DMIC"
1375
+
};
1376
+
1377
+
static SOC_ENUM_SINGLE_DECL(
1378
+
rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1379
+
RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1380
+
1381
+
static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1382
+
SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1383
+
1384
+
static SOC_ENUM_SINGLE_DECL(
1385
+
rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1386
+
RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1387
+
1388
+
static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1389
+
SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1390
+
1391
+
/* MX-79 [6:4] I2S1 ADC data location */
1392
+
static const unsigned int rt5682_if1_adc_slot_values[] = {
1393
+
0,
1394
+
2,
1395
+
4,
1396
+
6,
1397
+
};
1398
+
1399
+
static const char * const rt5682_if1_adc_slot_src[] = {
1400
+
"Slot 0", "Slot 2", "Slot 4", "Slot 6"
1401
+
};
1402
+
1403
+
static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1404
+
RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1405
+
rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1406
+
1407
+
static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1408
+
SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1409
+
1410
+
/* Analog DAC L1 Source, Analog DAC R1 Source*/
1411
+
/* MX-2B [4], MX-2B [0]*/
1412
+
static const char * const rt5682_alg_dac1_src[] = {
1413
+
"Stereo1 DAC Mixer", "DAC1"
1414
+
};
1415
+
1416
+
static SOC_ENUM_SINGLE_DECL(
1417
+
rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1418
+
RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1419
+
1420
+
static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1421
+
SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1422
+
1423
+
static SOC_ENUM_SINGLE_DECL(
1424
+
rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1425
+
RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1426
+
1427
+
static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1428
+
SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1429
+
1430
+
/* Out Switch */
1431
+
static const struct snd_kcontrol_new hpol_switch =
1432
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1433
+
RT5682_L_MUTE_SFT, 1, 1);
1434
+
static const struct snd_kcontrol_new hpor_switch =
1435
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1436
+
RT5682_R_MUTE_SFT, 1, 1);
1437
+
1438
+
static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1439
+
struct snd_kcontrol *kcontrol, int event)
1440
+
{
1441
+
struct snd_soc_component *component =
1442
+
snd_soc_dapm_to_component(w->dapm);
1443
+
1444
+
switch (event) {
1445
+
case SND_SOC_DAPM_PRE_PMU:
1446
+
snd_soc_component_write(component,
1447
+
RT5682_HP_LOGIC_CTRL_2, 0x0012);
1448
+
snd_soc_component_write(component,
1449
+
RT5682_HP_CTRL_2, 0x6000);
1450
+
snd_soc_component_update_bits(component, RT5682_STO_NG2_CTRL_1,
1451
+
RT5682_NG2_EN_MASK, RT5682_NG2_EN);
1452
+
snd_soc_component_update_bits(component,
1453
+
RT5682_DEPOP_1, 0x60, 0x60);
1454
+
break;
1455
+
1456
+
case SND_SOC_DAPM_POST_PMD:
1457
+
snd_soc_component_update_bits(component,
1458
+
RT5682_DEPOP_1, 0x60, 0x0);
1459
+
snd_soc_component_write(component,
1460
+
RT5682_HP_CTRL_2, 0x0000);
1461
+
break;
1462
+
1463
+
default:
1464
+
return 0;
1465
+
}
1466
+
1467
+
return 0;
1468
+
1469
+
}
1470
+
1471
+
static int set_dmic_power(struct snd_soc_dapm_widget *w,
1472
+
struct snd_kcontrol *kcontrol, int event)
1473
+
{
1474
+
switch (event) {
1475
+
case SND_SOC_DAPM_POST_PMU:
1476
+
/*Add delay to avoid pop noise*/
1477
+
msleep(150);
1478
+
break;
1479
+
1480
+
default:
1481
+
return 0;
1482
+
}
1483
+
1484
+
return 0;
1485
+
}
1486
+
1487
+
static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
1488
+
struct snd_kcontrol *kcontrol, int event)
1489
+
{
1490
+
struct snd_soc_component *component =
1491
+
snd_soc_dapm_to_component(w->dapm);
1492
+
1493
+
switch (event) {
1494
+
case SND_SOC_DAPM_PRE_PMU:
1495
+
switch (w->shift) {
1496
+
case RT5682_PWR_VREF1_BIT:
1497
+
snd_soc_component_update_bits(component,
1498
+
RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1499
+
break;
1500
+
1501
+
case RT5682_PWR_VREF2_BIT:
1502
+
snd_soc_component_update_bits(component,
1503
+
RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1504
+
break;
1505
+
1506
+
default:
1507
+
break;
1508
+
}
1509
+
break;
1510
+
1511
+
case SND_SOC_DAPM_POST_PMU:
1512
+
usleep_range(15000, 20000);
1513
+
switch (w->shift) {
1514
+
case RT5682_PWR_VREF1_BIT:
1515
+
snd_soc_component_update_bits(component,
1516
+
RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1517
+
RT5682_PWR_FV1);
1518
+
break;
1519
+
1520
+
case RT5682_PWR_VREF2_BIT:
1521
+
snd_soc_component_update_bits(component,
1522
+
RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1523
+
RT5682_PWR_FV2);
1524
+
break;
1525
+
1526
+
default:
1527
+
break;
1528
+
}
1529
+
break;
1530
+
1531
+
default:
1532
+
return 0;
1533
+
}
1534
+
1535
+
return 0;
1536
+
}
1537
+
1538
+
static const unsigned int rt5682_adcdat_pin_values[] = {
1539
+
1,
1540
+
3,
1541
+
};
1542
+
1543
+
static const char * const rt5682_adcdat_pin_select[] = {
1544
+
"ADCDAT1",
1545
+
"ADCDAT2",
1546
+
};
1547
+
1548
+
static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1549
+
RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1550
+
rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1551
+
1552
+
static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1553
+
SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1554
+
1555
+
static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1556
+
SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1557
+
0, NULL, 0),
1558
+
SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1559
+
0, NULL, 0),
1560
+
SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1561
+
0, NULL, 0),
1562
+
SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1563
+
0, NULL, 0),
1564
+
SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1565
+
rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1566
+
SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0,
1567
+
rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1568
+
1569
+
/* ASRC */
1570
+
SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1571
+
RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1572
+
SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1573
+
RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1574
+
SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1575
+
RT5682_AD_ASRC_SFT, 0, NULL, 0),
1576
+
SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1577
+
RT5682_DA_ASRC_SFT, 0, NULL, 0),
1578
+
SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1579
+
RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1580
+
1581
+
/* Input Side */
1582
+
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1583
+
0, NULL, 0),
1584
+
SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1585
+
0, NULL, 0),
1586
+
1587
+
/* Input Lines */
1588
+
SND_SOC_DAPM_INPUT("DMIC L1"),
1589
+
SND_SOC_DAPM_INPUT("DMIC R1"),
1590
+
1591
+
SND_SOC_DAPM_INPUT("IN1P"),
1592
+
1593
+
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1594
+
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1595
+
SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1596
+
RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1597
+
1598
+
/* Boost */
1599
+
SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1600
+
0, 0, NULL, 0),
1601
+
1602
+
SND_SOC_DAPM_SUPPLY("CBJ Power", RT5682_PWR_ANLG_3,
1603
+
RT5682_PWR_CBJ_BIT, 0, NULL, 0),
1604
+
1605
+
/* REC Mixer */
1606
+
SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1607
+
ARRAY_SIZE(rt5682_rec1_l_mix)),
1608
+
SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1609
+
RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1610
+
1611
+
/* ADCs */
1612
+
SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1613
+
SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1614
+
1615
+
SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1616
+
RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1617
+
SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1618
+
RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1619
+
SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1620
+
RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1621
+
1622
+
/* ADC Mux */
1623
+
SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1624
+
&rt5682_sto1_adc1l_mux),
1625
+
SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1626
+
&rt5682_sto1_adc1r_mux),
1627
+
SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1628
+
&rt5682_sto1_adc2l_mux),
1629
+
SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1630
+
&rt5682_sto1_adc2r_mux),
1631
+
SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1632
+
&rt5682_sto1_adcl_mux),
1633
+
SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1634
+
&rt5682_sto1_adcr_mux),
1635
+
SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1636
+
&rt5682_if1_adc_slot_mux),
1637
+
1638
+
/* ADC Mixer */
1639
+
SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1640
+
RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1641
+
SND_SOC_DAPM_PRE_PMU),
1642
+
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1643
+
RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1644
+
ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1645
+
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1646
+
RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1647
+
ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1648
+
1649
+
/* ADC PGA */
1650
+
SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1651
+
1652
+
/* Digital Interface */
1653
+
SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1654
+
0, NULL, 0),
1655
+
SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1656
+
0, NULL, 0),
1657
+
SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1658
+
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1659
+
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1660
+
1661
+
/* Digital Interface Select */
1662
+
SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1663
+
&rt5682_if1_01_adc_swap_mux),
1664
+
SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1665
+
&rt5682_if1_23_adc_swap_mux),
1666
+
SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1667
+
&rt5682_if1_45_adc_swap_mux),
1668
+
SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1669
+
&rt5682_if1_67_adc_swap_mux),
1670
+
SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1671
+
&rt5682_if2_adc_swap_mux),
1672
+
1673
+
SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1674
+
&rt5682_adcdat_pin_ctrl),
1675
+
1676
+
/* Audio Interface */
1677
+
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1678
+
RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1679
+
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1680
+
RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1681
+
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1682
+
1683
+
/* Output Side */
1684
+
/* DAC mixer before sound effect */
1685
+
SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1686
+
rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1687
+
SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1688
+
rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1689
+
1690
+
/* DAC channel Mux */
1691
+
SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1692
+
&rt5682_alg_dac_l1_mux),
1693
+
SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1694
+
&rt5682_alg_dac_r1_mux),
1695
+
1696
+
/* DAC Mixer */
1697
+
SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1698
+
RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1699
+
SND_SOC_DAPM_PRE_PMU),
1700
+
SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1701
+
rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1702
+
SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1703
+
rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1704
+
1705
+
/* DACs */
1706
+
SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1707
+
RT5682_PWR_DAC_L1_BIT, 0),
1708
+
SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1709
+
RT5682_PWR_DAC_R1_BIT, 0),
1710
+
SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1711
+
RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1712
+
1713
+
/* HPO */
1714
+
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1715
+
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1716
+
1717
+
SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1718
+
RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1719
+
SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1720
+
RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1721
+
SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1722
+
RT5682_PUMP_EN_SFT, 0, NULL, 0),
1723
+
SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1724
+
RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1725
+
1726
+
SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1727
+
&hpol_switch),
1728
+
SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1729
+
&hpor_switch),
1730
+
1731
+
/* CLK DET */
1732
+
SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1733
+
RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1734
+
SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1735
+
RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1736
+
SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1737
+
RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1738
+
SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1739
+
RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1740
+
1741
+
/* Output Lines */
1742
+
SND_SOC_DAPM_OUTPUT("HPOL"),
1743
+
SND_SOC_DAPM_OUTPUT("HPOR"),
1744
+
1745
+
};
1746
+
1747
+
static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1748
+
/*PLL*/
1749
+
{"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1750
+
{"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1751
+
1752
+
/*ASRC*/
1753
+
{"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1754
+
{"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1755
+
{"ADC STO1 ASRC", NULL, "AD ASRC"},
1756
+
{"ADC STO1 ASRC", NULL, "CLKDET"},
1757
+
{"DAC STO1 ASRC", NULL, "DA ASRC"},
1758
+
{"DAC STO1 ASRC", NULL, "CLKDET"},
1759
+
1760
+
/*Vref*/
1761
+
{"MICBIAS1", NULL, "Vref1"},
1762
+
{"MICBIAS1", NULL, "Vref2"},
1763
+
{"MICBIAS2", NULL, "Vref1"},
1764
+
{"MICBIAS2", NULL, "Vref2"},
1765
+
1766
+
{"CLKDET SYS", NULL, "CLKDET"},
1767
+
1768
+
{"IN1P", NULL, "LDO2"},
1769
+
1770
+
{"BST1 CBJ", NULL, "IN1P"},
1771
+
{"BST1 CBJ", NULL, "CBJ Power"},
1772
+
{"CBJ Power", NULL, "Vref2"},
1773
+
1774
+
{"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1775
+
{"RECMIX1L", NULL, "RECMIX1L Power"},
1776
+
1777
+
{"ADC1 L", NULL, "RECMIX1L"},
1778
+
{"ADC1 L", NULL, "ADC1 L Power"},
1779
+
{"ADC1 L", NULL, "ADC1 clock"},
1780
+
1781
+
{"DMIC L1", NULL, "DMIC CLK"},
1782
+
{"DMIC L1", NULL, "DMIC1 Power"},
1783
+
{"DMIC R1", NULL, "DMIC CLK"},
1784
+
{"DMIC R1", NULL, "DMIC1 Power"},
1785
+
{"DMIC CLK", NULL, "DMIC ASRC"},
1786
+
1787
+
{"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1788
+
{"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1789
+
{"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1790
+
{"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1791
+
1792
+
{"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1793
+
{"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1794
+
{"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1795
+
{"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1796
+
1797
+
{"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1798
+
{"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1799
+
{"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1800
+
{"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1801
+
1802
+
{"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1803
+
{"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1804
+
{"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1805
+
1806
+
{"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1807
+
{"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1808
+
{"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1809
+
1810
+
{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1811
+
{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1812
+
1813
+
{"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1814
+
{"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1815
+
{"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1816
+
{"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1817
+
{"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1818
+
{"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1819
+
{"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1820
+
{"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1821
+
{"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1822
+
{"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1823
+
{"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1824
+
{"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1825
+
{"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1826
+
{"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1827
+
{"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1828
+
{"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1829
+
1830
+
{"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1831
+
{"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1832
+
{"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1833
+
{"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1834
+
{"IF1_ADC Mux", NULL, "I2S1"},
1835
+
{"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1836
+
{"AIF1TX", NULL, "ADCDAT Mux"},
1837
+
{"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1838
+
{"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1839
+
{"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1840
+
{"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1841
+
{"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1842
+
{"AIF2TX", NULL, "ADCDAT Mux"},
1843
+
1844
+
{"IF1 DAC1 L", NULL, "AIF1RX"},
1845
+
{"IF1 DAC1 L", NULL, "I2S1"},
1846
+
{"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1847
+
{"IF1 DAC1 R", NULL, "AIF1RX"},
1848
+
{"IF1 DAC1 R", NULL, "I2S1"},
1849
+
{"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1850
+
1851
+
{"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1852
+
{"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1853
+
{"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1854
+
{"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1855
+
1856
+
{"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1857
+
{"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1858
+
1859
+
{"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1860
+
{"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1861
+
1862
+
{"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1863
+
{"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1864
+
{"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1865
+
{"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1866
+
1867
+
{"DAC L1", NULL, "DAC L1 Source"},
1868
+
{"DAC R1", NULL, "DAC R1 Source"},
1869
+
1870
+
{"DAC L1", NULL, "DAC 1 Clock"},
1871
+
{"DAC R1", NULL, "DAC 1 Clock"},
1872
+
1873
+
{"HP Amp", NULL, "DAC L1"},
1874
+
{"HP Amp", NULL, "DAC R1"},
1875
+
{"HP Amp", NULL, "HP Amp L"},
1876
+
{"HP Amp", NULL, "HP Amp R"},
1877
+
{"HP Amp", NULL, "Capless"},
1878
+
{"HP Amp", NULL, "Charge Pump"},
1879
+
{"HP Amp", NULL, "CLKDET SYS"},
1880
+
{"HP Amp", NULL, "CBJ Power"},
1881
+
{"HP Amp", NULL, "Vref2"},
1882
+
{"HPOL Playback", "Switch", "HP Amp"},
1883
+
{"HPOR Playback", "Switch", "HP Amp"},
1884
+
{"HPOL", NULL, "HPOL Playback"},
1885
+
{"HPOR", NULL, "HPOR Playback"},
1886
+
};
1887
+
1888
+
static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1889
+
unsigned int rx_mask, int slots, int slot_width)
1890
+
{
1891
+
struct snd_soc_component *component = dai->component;
1892
+
unsigned int cl, val = 0;
1893
+
1894
+
if (tx_mask || rx_mask)
1895
+
snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1896
+
RT5682_TDM_EN, RT5682_TDM_EN);
1897
+
else
1898
+
snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1899
+
RT5682_TDM_EN, 0);
1900
+
1901
+
switch (slots) {
1902
+
case 4:
1903
+
val |= RT5682_TDM_TX_CH_4;
1904
+
val |= RT5682_TDM_RX_CH_4;
1905
+
break;
1906
+
case 6:
1907
+
val |= RT5682_TDM_TX_CH_6;
1908
+
val |= RT5682_TDM_RX_CH_6;
1909
+
break;
1910
+
case 8:
1911
+
val |= RT5682_TDM_TX_CH_8;
1912
+
val |= RT5682_TDM_RX_CH_8;
1913
+
break;
1914
+
case 2:
1915
+
break;
1916
+
default:
1917
+
return -EINVAL;
1918
+
}
1919
+
1920
+
snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
1921
+
RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
1922
+
1923
+
switch (slot_width) {
1924
+
case 8:
1925
+
if (tx_mask || rx_mask)
1926
+
return -EINVAL;
1927
+
cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
1928
+
break;
1929
+
case 16:
1930
+
val = RT5682_TDM_CL_16;
1931
+
cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
1932
+
break;
1933
+
case 20:
1934
+
val = RT5682_TDM_CL_20;
1935
+
cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
1936
+
break;
1937
+
case 24:
1938
+
val = RT5682_TDM_CL_24;
1939
+
cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
1940
+
break;
1941
+
case 32:
1942
+
val = RT5682_TDM_CL_32;
1943
+
cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
1944
+
break;
1945
+
default:
1946
+
return -EINVAL;
1947
+
}
1948
+
1949
+
snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
1950
+
RT5682_TDM_CL_MASK, val);
1951
+
snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
1952
+
RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
1953
+
1954
+
return 0;
1955
+
}
1956
+
1957
+
1958
+
static int rt5682_hw_params(struct snd_pcm_substream *substream,
1959
+
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1960
+
{
1961
+
struct snd_soc_component *component = dai->component;
1962
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1963
+
unsigned int len_1 = 0, len_2 = 0;
1964
+
int pre_div, frame_size;
1965
+
1966
+
rt5682->lrck[dai->id] = params_rate(params);
1967
+
pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
1968
+
1969
+
frame_size = snd_soc_params_to_frame_size(params);
1970
+
if (frame_size < 0) {
1971
+
dev_err(component->dev, "Unsupported frame size: %d\n",
1972
+
frame_size);
1973
+
return -EINVAL;
1974
+
}
1975
+
1976
+
dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
1977
+
rt5682->lrck[dai->id], pre_div, dai->id);
1978
+
1979
+
switch (params_width(params)) {
1980
+
case 16:
1981
+
break;
1982
+
case 20:
1983
+
len_1 |= RT5682_I2S1_DL_20;
1984
+
len_2 |= RT5682_I2S2_DL_20;
1985
+
break;
1986
+
case 24:
1987
+
len_1 |= RT5682_I2S1_DL_24;
1988
+
len_2 |= RT5682_I2S2_DL_24;
1989
+
break;
1990
+
case 32:
1991
+
len_1 |= RT5682_I2S1_DL_32;
1992
+
len_2 |= RT5682_I2S2_DL_24;
1993
+
break;
1994
+
case 8:
1995
+
len_1 |= RT5682_I2S2_DL_8;
1996
+
len_2 |= RT5682_I2S2_DL_8;
1997
+
break;
1998
+
default:
1999
+
return -EINVAL;
2000
+
}
2001
+
2002
+
switch (dai->id) {
2003
+
case RT5682_AIF1:
2004
+
snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2005
+
RT5682_I2S1_DL_MASK, len_1);
2006
+
if (rt5682->master[RT5682_AIF1]) {
2007
+
snd_soc_component_update_bits(component,
2008
+
RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK,
2009
+
pre_div << RT5682_I2S_M_DIV_SFT);
2010
+
}
2011
+
if (params_channels(params) == 1) /* mono mode */
2012
+
snd_soc_component_update_bits(component,
2013
+
RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2014
+
RT5682_I2S1_MONO_EN);
2015
+
else
2016
+
snd_soc_component_update_bits(component,
2017
+
RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2018
+
RT5682_I2S1_MONO_DIS);
2019
+
break;
2020
+
case RT5682_AIF2:
2021
+
snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2022
+
RT5682_I2S2_DL_MASK, len_2);
2023
+
if (rt5682->master[RT5682_AIF2]) {
2024
+
snd_soc_component_update_bits(component,
2025
+
RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2026
+
pre_div << RT5682_I2S2_M_PD_SFT);
2027
+
}
2028
+
if (params_channels(params) == 1) /* mono mode */
2029
+
snd_soc_component_update_bits(component,
2030
+
RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2031
+
RT5682_I2S2_MONO_EN);
2032
+
else
2033
+
snd_soc_component_update_bits(component,
2034
+
RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2035
+
RT5682_I2S2_MONO_DIS);
2036
+
break;
2037
+
default:
2038
+
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2039
+
return -EINVAL;
2040
+
}
2041
+
2042
+
return 0;
2043
+
}
2044
+
2045
+
static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2046
+
{
2047
+
struct snd_soc_component *component = dai->component;
2048
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2049
+
unsigned int reg_val = 0, tdm_ctrl = 0;
2050
+
2051
+
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2052
+
case SND_SOC_DAIFMT_CBM_CFM:
2053
+
rt5682->master[dai->id] = 1;
2054
+
break;
2055
+
case SND_SOC_DAIFMT_CBS_CFS:
2056
+
rt5682->master[dai->id] = 0;
2057
+
break;
2058
+
default:
2059
+
return -EINVAL;
2060
+
}
2061
+
2062
+
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2063
+
case SND_SOC_DAIFMT_NB_NF:
2064
+
break;
2065
+
case SND_SOC_DAIFMT_IB_NF:
2066
+
reg_val |= RT5682_I2S_BP_INV;
2067
+
tdm_ctrl |= RT5682_TDM_S_BP_INV;
2068
+
break;
2069
+
case SND_SOC_DAIFMT_NB_IF:
2070
+
if (dai->id == RT5682_AIF1)
2071
+
tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2072
+
else
2073
+
return -EINVAL;
2074
+
break;
2075
+
case SND_SOC_DAIFMT_IB_IF:
2076
+
if (dai->id == RT5682_AIF1)
2077
+
tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2078
+
RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2079
+
else
2080
+
return -EINVAL;
2081
+
break;
2082
+
default:
2083
+
return -EINVAL;
2084
+
}
2085
+
2086
+
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2087
+
case SND_SOC_DAIFMT_I2S:
2088
+
break;
2089
+
case SND_SOC_DAIFMT_LEFT_J:
2090
+
reg_val |= RT5682_I2S_DF_LEFT;
2091
+
tdm_ctrl |= RT5682_TDM_DF_LEFT;
2092
+
break;
2093
+
case SND_SOC_DAIFMT_DSP_A:
2094
+
reg_val |= RT5682_I2S_DF_PCM_A;
2095
+
tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2096
+
break;
2097
+
case SND_SOC_DAIFMT_DSP_B:
2098
+
reg_val |= RT5682_I2S_DF_PCM_B;
2099
+
tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2100
+
break;
2101
+
default:
2102
+
return -EINVAL;
2103
+
}
2104
+
2105
+
switch (dai->id) {
2106
+
case RT5682_AIF1:
2107
+
snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2108
+
RT5682_I2S_DF_MASK, reg_val);
2109
+
snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2110
+
RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2111
+
RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2112
+
RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2113
+
tdm_ctrl | rt5682->master[dai->id]);
2114
+
break;
2115
+
case RT5682_AIF2:
2116
+
if (rt5682->master[dai->id] == 0)
2117
+
reg_val |= RT5682_I2S2_MS_S;
2118
+
snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2119
+
RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2120
+
RT5682_I2S_DF_MASK, reg_val);
2121
+
break;
2122
+
default:
2123
+
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2124
+
return -EINVAL;
2125
+
}
2126
+
return 0;
2127
+
}
2128
+
2129
+
static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2130
+
int clk_id, int source, unsigned int freq, int dir)
2131
+
{
2132
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2133
+
unsigned int reg_val = 0, src = 0;
2134
+
2135
+
if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2136
+
return 0;
2137
+
2138
+
switch (clk_id) {
2139
+
case RT5682_SCLK_S_MCLK:
2140
+
reg_val |= RT5682_SCLK_SRC_MCLK;
2141
+
src = RT5682_CLK_SRC_MCLK;
2142
+
break;
2143
+
case RT5682_SCLK_S_PLL1:
2144
+
reg_val |= RT5682_SCLK_SRC_PLL1;
2145
+
src = RT5682_CLK_SRC_PLL1;
2146
+
break;
2147
+
case RT5682_SCLK_S_PLL2:
2148
+
reg_val |= RT5682_SCLK_SRC_PLL2;
2149
+
src = RT5682_CLK_SRC_PLL2;
2150
+
break;
2151
+
case RT5682_SCLK_S_RCCLK:
2152
+
reg_val |= RT5682_SCLK_SRC_RCCLK;
2153
+
src = RT5682_CLK_SRC_RCCLK;
2154
+
break;
2155
+
default:
2156
+
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2157
+
return -EINVAL;
2158
+
}
2159
+
snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2160
+
RT5682_SCLK_SRC_MASK, reg_val);
2161
+
2162
+
if (rt5682->master[RT5682_AIF2]) {
2163
+
snd_soc_component_update_bits(component,
2164
+
RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2165
+
src << RT5682_I2S2_SRC_SFT);
2166
+
}
2167
+
2168
+
rt5682->sysclk = freq;
2169
+
rt5682->sysclk_src = clk_id;
2170
+
2171
+
dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2172
+
freq, clk_id);
2173
+
2174
+
return 0;
2175
+
}
2176
+
2177
+
static int rt5682_set_component_pll(struct snd_soc_component *component,
2178
+
int pll_id, int source, unsigned int freq_in,
2179
+
unsigned int freq_out)
2180
+
{
2181
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2182
+
struct rl6231_pll_code pll_code;
2183
+
int ret;
2184
+
2185
+
if (source == rt5682->pll_src && freq_in == rt5682->pll_in &&
2186
+
freq_out == rt5682->pll_out)
2187
+
return 0;
2188
+
2189
+
if (!freq_in || !freq_out) {
2190
+
dev_dbg(component->dev, "PLL disabled\n");
2191
+
2192
+
rt5682->pll_in = 0;
2193
+
rt5682->pll_out = 0;
2194
+
snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2195
+
RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2196
+
return 0;
2197
+
}
2198
+
2199
+
switch (source) {
2200
+
case RT5682_PLL1_S_MCLK:
2201
+
snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2202
+
RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK);
2203
+
break;
2204
+
case RT5682_PLL1_S_BCLK1:
2205
+
snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2206
+
RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1);
2207
+
break;
2208
+
default:
2209
+
dev_err(component->dev, "Unknown PLL Source %d\n", source);
2210
+
return -EINVAL;
2211
+
}
2212
+
2213
+
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2214
+
if (ret < 0) {
2215
+
dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2216
+
return ret;
2217
+
}
2218
+
2219
+
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2220
+
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2221
+
pll_code.n_code, pll_code.k_code);
2222
+
2223
+
snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2224
+
pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2225
+
snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2226
+
(pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2227
+
pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2228
+
2229
+
rt5682->pll_in = freq_in;
2230
+
rt5682->pll_out = freq_out;
2231
+
rt5682->pll_src = source;
2232
+
2233
+
return 0;
2234
+
}
2235
+
2236
+
static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2237
+
{
2238
+
struct snd_soc_component *component = dai->component;
2239
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2240
+
2241
+
rt5682->bclk[dai->id] = ratio;
2242
+
2243
+
switch (ratio) {
2244
+
case 64:
2245
+
snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2246
+
RT5682_I2S2_BCLK_MS2_MASK,
2247
+
RT5682_I2S2_BCLK_MS2_64);
2248
+
break;
2249
+
case 32:
2250
+
snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2251
+
RT5682_I2S2_BCLK_MS2_MASK,
2252
+
RT5682_I2S2_BCLK_MS2_32);
2253
+
break;
2254
+
default:
2255
+
dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
2256
+
return -EINVAL;
2257
+
}
2258
+
2259
+
return 0;
2260
+
}
2261
+
2262
+
static int rt5682_set_bias_level(struct snd_soc_component *component,
2263
+
enum snd_soc_bias_level level)
2264
+
{
2265
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2266
+
2267
+
switch (level) {
2268
+
case SND_SOC_BIAS_PREPARE:
2269
+
regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2270
+
RT5682_PWR_MB | RT5682_PWR_BG,
2271
+
RT5682_PWR_MB | RT5682_PWR_BG);
2272
+
regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2273
+
RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2274
+
RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2275
+
break;
2276
+
2277
+
case SND_SOC_BIAS_STANDBY:
2278
+
regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2279
+
RT5682_PWR_MB, RT5682_PWR_MB);
2280
+
regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2281
+
RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2282
+
break;
2283
+
case SND_SOC_BIAS_OFF:
2284
+
regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2285
+
RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2286
+
regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2287
+
RT5682_PWR_MB | RT5682_PWR_BG, 0);
2288
+
break;
2289
+
2290
+
default:
2291
+
break;
2292
+
}
2293
+
2294
+
return 0;
2295
+
}
2296
+
2297
+
static int rt5682_probe(struct snd_soc_component *component)
2298
+
{
2299
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2300
+
2301
+
rt5682->component = component;
2302
+
2303
+
return 0;
2304
+
}
2305
+
2306
+
static void rt5682_remove(struct snd_soc_component *component)
2307
+
{
2308
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2309
+
2310
+
rt5682_reset(rt5682->regmap);
2311
+
}
2312
+
2313
+
#ifdef CONFIG_PM
2314
+
static int rt5682_suspend(struct snd_soc_component *component)
2315
+
{
2316
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2317
+
2318
+
regcache_cache_only(rt5682->regmap, true);
2319
+
regcache_mark_dirty(rt5682->regmap);
2320
+
return 0;
2321
+
}
2322
+
2323
+
static int rt5682_resume(struct snd_soc_component *component)
2324
+
{
2325
+
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2326
+
2327
+
regcache_cache_only(rt5682->regmap, false);
2328
+
regcache_sync(rt5682->regmap);
2329
+
2330
+
return 0;
2331
+
}
2332
+
#else
2333
+
#define rt5682_suspend NULL
2334
+
#define rt5682_resume NULL
2335
+
#endif
2336
+
2337
+
#define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2338
+
#define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2339
+
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2340
+
2341
+
static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2342
+
.hw_params = rt5682_hw_params,
2343
+
.set_fmt = rt5682_set_dai_fmt,
2344
+
.set_tdm_slot = rt5682_set_tdm_slot,
2345
+
};
2346
+
2347
+
static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2348
+
.hw_params = rt5682_hw_params,
2349
+
.set_fmt = rt5682_set_dai_fmt,
2350
+
.set_bclk_ratio = rt5682_set_bclk_ratio,
2351
+
};
2352
+
2353
+
static struct snd_soc_dai_driver rt5682_dai[] = {
2354
+
{
2355
+
.name = "rt5682-aif1",
2356
+
.id = RT5682_AIF1,
2357
+
.playback = {
2358
+
.stream_name = "AIF1 Playback",
2359
+
.channels_min = 1,
2360
+
.channels_max = 2,
2361
+
.rates = RT5682_STEREO_RATES,
2362
+
.formats = RT5682_FORMATS,
2363
+
},
2364
+
.capture = {
2365
+
.stream_name = "AIF1 Capture",
2366
+
.channels_min = 1,
2367
+
.channels_max = 2,
2368
+
.rates = RT5682_STEREO_RATES,
2369
+
.formats = RT5682_FORMATS,
2370
+
},
2371
+
.ops = &rt5682_aif1_dai_ops,
2372
+
},
2373
+
{
2374
+
.name = "rt5682-aif2",
2375
+
.id = RT5682_AIF2,
2376
+
.capture = {
2377
+
.stream_name = "AIF2 Capture",
2378
+
.channels_min = 1,
2379
+
.channels_max = 2,
2380
+
.rates = RT5682_STEREO_RATES,
2381
+
.formats = RT5682_FORMATS,
2382
+
},
2383
+
.ops = &rt5682_aif2_dai_ops,
2384
+
},
2385
+
};
2386
+
2387
+
static const struct snd_soc_component_driver soc_component_dev_rt5682 = {
2388
+
.probe = rt5682_probe,
2389
+
.remove = rt5682_remove,
2390
+
.suspend = rt5682_suspend,
2391
+
.resume = rt5682_resume,
2392
+
.set_bias_level = rt5682_set_bias_level,
2393
+
.controls = rt5682_snd_controls,
2394
+
.num_controls = ARRAY_SIZE(rt5682_snd_controls),
2395
+
.dapm_widgets = rt5682_dapm_widgets,
2396
+
.num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2397
+
.dapm_routes = rt5682_dapm_routes,
2398
+
.num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2399
+
.set_sysclk = rt5682_set_component_sysclk,
2400
+
.set_pll = rt5682_set_component_pll,
2401
+
.set_jack = rt5682_set_jack_detect,
2402
+
.use_pmdown_time = 1,
2403
+
.endianness = 1,
2404
+
.non_legacy_dai_naming = 1,
2405
+
};
2406
+
2407
+
static const struct regmap_config rt5682_regmap = {
2408
+
.reg_bits = 16,
2409
+
.val_bits = 16,
2410
+
.max_register = RT5682_I2C_MODE,
2411
+
.volatile_reg = rt5682_volatile_register,
2412
+
.readable_reg = rt5682_readable_register,
2413
+
.cache_type = REGCACHE_RBTREE,
2414
+
.reg_defaults = rt5682_reg,
2415
+
.num_reg_defaults = ARRAY_SIZE(rt5682_reg),
2416
+
.use_single_rw = true,
2417
+
};
2418
+
2419
+
static const struct i2c_device_id rt5682_i2c_id[] = {
2420
+
{"rt5682", 0},
2421
+
{}
2422
+
};
2423
+
MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id);
2424
+
2425
+
static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2426
+
{
2427
+
2428
+
device_property_read_u32(dev, "realtek,dmic1-data-pin",
2429
+
&rt5682->pdata.dmic1_data_pin);
2430
+
device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2431
+
&rt5682->pdata.dmic1_clk_pin);
2432
+
device_property_read_u32(dev, "realtek,jd-src",
2433
+
&rt5682->pdata.jd_src);
2434
+
2435
+
rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2436
+
"realtek,ldo1-en-gpios", 0);
2437
+
2438
+
return 0;
2439
+
}
2440
+
2441
+
static void rt5682_calibrate(struct rt5682_priv *rt5682)
2442
+
{
2443
+
int value, count;
2444
+
2445
+
mutex_lock(&rt5682->calibrate_mutex);
2446
+
2447
+
rt5682_reset(rt5682->regmap);
2448
+
regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2bf);
2449
+
usleep_range(15000, 20000);
2450
+
regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2bf);
2451
+
regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
2452
+
regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x8001);
2453
+
regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
2454
+
regmap_write(rt5682->regmap, RT5682_STO1_DAC_MIXER, 0x2080);
2455
+
regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x4040);
2456
+
regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0069);
2457
+
regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
2458
+
regmap_write(rt5682->regmap, RT5682_HP_CTRL_2, 0x6000);
2459
+
regmap_write(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1, 0x0f26);
2460
+
regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7f05);
2461
+
regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
2462
+
regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
2463
+
regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_9, 0x000f);
2464
+
regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x8d01);
2465
+
regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
2466
+
regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
2467
+
regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2468
+
regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
2469
+
regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
2470
+
regmap_write(rt5682->regmap, RT5682_RESET_HPF_CTRL, 0x0000);
2471
+
regmap_write(rt5682->regmap, RT5682_ADC_STO1_HP_CTRL_1, 0x3320);
2472
+
2473
+
regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
2474
+
2475
+
for (count = 0; count < 60; count++) {
2476
+
regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
2477
+
if (!(value & 0x8000))
2478
+
break;
2479
+
2480
+
usleep_range(10000, 10005);
2481
+
}
2482
+
2483
+
if (count >= 60)
2484
+
pr_err("HP Calibration Failure\n");
2485
+
2486
+
/* restore settings */
2487
+
regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
2488
+
regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
2489
+
2490
+
mutex_unlock(&rt5682->calibrate_mutex);
2491
+
2492
+
}
2493
+
2494
+
static int rt5682_i2c_probe(struct i2c_client *i2c,
2495
+
const struct i2c_device_id *id)
2496
+
{
2497
+
struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev);
2498
+
struct rt5682_priv *rt5682;
2499
+
int i, ret;
2500
+
unsigned int val;
2501
+
2502
+
rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv),
2503
+
GFP_KERNEL);
2504
+
2505
+
if (rt5682 == NULL)
2506
+
return -ENOMEM;
2507
+
2508
+
i2c_set_clientdata(i2c, rt5682);
2509
+
2510
+
if (pdata)
2511
+
rt5682->pdata = *pdata;
2512
+
else
2513
+
rt5682_parse_dt(rt5682, &i2c->dev);
2514
+
2515
+
rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap);
2516
+
if (IS_ERR(rt5682->regmap)) {
2517
+
ret = PTR_ERR(rt5682->regmap);
2518
+
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2519
+
ret);
2520
+
return ret;
2521
+
}
2522
+
2523
+
for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++)
2524
+
rt5682->supplies[i].supply = rt5682_supply_names[i];
2525
+
2526
+
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies),
2527
+
rt5682->supplies);
2528
+
if (ret != 0) {
2529
+
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2530
+
return ret;
2531
+
}
2532
+
2533
+
ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies),
2534
+
rt5682->supplies);
2535
+
if (ret != 0) {
2536
+
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2537
+
return ret;
2538
+
}
2539
+
2540
+
if (gpio_is_valid(rt5682->pdata.ldo1_en)) {
2541
+
if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en,
2542
+
GPIOF_OUT_INIT_HIGH, "rt5682"))
2543
+
dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
2544
+
}
2545
+
2546
+
/* Sleep for 300 ms miniumum */
2547
+
usleep_range(300000, 350000);
2548
+
2549
+
regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1);
2550
+
usleep_range(10000, 15000);
2551
+
2552
+
regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
2553
+
if (val != DEVICE_ID) {
2554
+
pr_err("Device with ID register %x is not rt5682\n", val);
2555
+
return -ENODEV;
2556
+
}
2557
+
2558
+
rt5682_reset(rt5682->regmap);
2559
+
2560
+
rt5682_calibrate(rt5682);
2561
+
2562
+
ret = regmap_register_patch(rt5682->regmap, patch_list,
2563
+
ARRAY_SIZE(patch_list));
2564
+
if (ret != 0)
2565
+
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2566
+
2567
+
regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
2568
+
2569
+
/* DMIC pin*/
2570
+
if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) {
2571
+
switch (rt5682->pdata.dmic1_data_pin) {
2572
+
case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */
2573
+
regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2574
+
RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2);
2575
+
regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2576
+
RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA);
2577
+
break;
2578
+
2579
+
case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
2580
+
regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2581
+
RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5);
2582
+
regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2583
+
RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA);
2584
+
break;
2585
+
2586
+
default:
2587
+
dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
2588
+
break;
2589
+
}
2590
+
2591
+
switch (rt5682->pdata.dmic1_clk_pin) {
2592
+
case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */
2593
+
regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2594
+
RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK);
2595
+
break;
2596
+
2597
+
case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */
2598
+
regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2599
+
RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK);
2600
+
break;
2601
+
2602
+
default:
2603
+
dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
2604
+
break;
2605
+
}
2606
+
}
2607
+
2608
+
regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2609
+
RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
2610
+
RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
2611
+
regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
2612
+
regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2613
+
RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK,
2614
+
RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1);
2615
+
regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
2616
+
2617
+
INIT_DELAYED_WORK(&rt5682->jack_detect_work,
2618
+
rt5682_jack_detect_handler);
2619
+
INIT_DELAYED_WORK(&rt5682->jd_check_work,
2620
+
rt5682_jd_check_handler);
2621
+
2622
+
mutex_init(&rt5682->calibrate_mutex);
2623
+
2624
+
if (i2c->irq) {
2625
+
ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2626
+
rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2627
+
| IRQF_ONESHOT, "rt5682", rt5682);
2628
+
if (ret)
2629
+
dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2630
+
2631
+
}
2632
+
2633
+
return snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5682,
2634
+
rt5682_dai, ARRAY_SIZE(rt5682_dai));
2635
+
}
2636
+
2637
+
static int rt5682_i2c_remove(struct i2c_client *i2c)
2638
+
{
2639
+
snd_soc_unregister_component(&i2c->dev);
2640
+
2641
+
return 0;
2642
+
}
2643
+
2644
+
static void rt5682_i2c_shutdown(struct i2c_client *client)
2645
+
{
2646
+
struct rt5682_priv *rt5682 = i2c_get_clientdata(client);
2647
+
2648
+
rt5682_reset(rt5682->regmap);
2649
+
}
2650
+
2651
+
#ifdef CONFIG_OF
2652
+
static const struct of_device_id rt5682_of_match[] = {
2653
+
{.compatible = "realtek,rt5682i"},
2654
+
{},
2655
+
};
2656
+
MODULE_DEVICE_TABLE(of, rt5682_of_match);
2657
+
#endif
2658
+
2659
+
#ifdef CONFIG_ACPI
2660
+
static const struct acpi_device_id rt5682_acpi_match[] = {
2661
+
{"10EC5682", 0,},
2662
+
{},
2663
+
};
2664
+
MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match);
2665
+
#endif
2666
+
2667
+
static struct i2c_driver rt5682_i2c_driver = {
2668
+
.driver = {
2669
+
.name = "rt5682",
2670
+
.of_match_table = of_match_ptr(rt5682_of_match),
2671
+
.acpi_match_table = ACPI_PTR(rt5682_acpi_match),
2672
+
},
2673
+
.probe = rt5682_i2c_probe,
2674
+
.remove = rt5682_i2c_remove,
2675
+
.shutdown = rt5682_i2c_shutdown,
2676
+
.id_table = rt5682_i2c_id,
2677
+
};
2678
+
module_i2c_driver(rt5682_i2c_driver);
2679
+
2680
+
MODULE_DESCRIPTION("ASoC RT5682 driver");
2681
+
MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2682
+
MODULE_LICENSE("GPL v2");
+1324
sound/soc/codecs/rt5682.h
+1324
sound/soc/codecs/rt5682.h
···
1
+
/*
2
+
* rt5682.h -- RT5682/RT5658 ALSA SoC audio driver
3
+
*
4
+
* Copyright 2018 Realtek Microelectronics
5
+
* Author: Bard Liao <bardliao@realtek.com>
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
10
+
*/
11
+
12
+
#ifndef __RT5682_H__
13
+
#define __RT5682_H__
14
+
15
+
#include <sound/rt5682.h>
16
+
17
+
#define DEVICE_ID 0x6530
18
+
19
+
/* Info */
20
+
#define RT5682_RESET 0x0000
21
+
#define RT5682_VERSION_ID 0x00fd
22
+
#define RT5682_VENDOR_ID 0x00fe
23
+
#define RT5682_DEVICE_ID 0x00ff
24
+
/* I/O - Output */
25
+
#define RT5682_HP_CTRL_1 0x0002
26
+
#define RT5682_HP_CTRL_2 0x0003
27
+
#define RT5682_HPL_GAIN 0x0005
28
+
#define RT5682_HPR_GAIN 0x0006
29
+
30
+
#define RT5682_I2C_CTRL 0x0008
31
+
32
+
/* I/O - Input */
33
+
#define RT5682_CBJ_BST_CTRL 0x000b
34
+
#define RT5682_CBJ_CTRL_1 0x0010
35
+
#define RT5682_CBJ_CTRL_2 0x0011
36
+
#define RT5682_CBJ_CTRL_3 0x0012
37
+
#define RT5682_CBJ_CTRL_4 0x0013
38
+
#define RT5682_CBJ_CTRL_5 0x0014
39
+
#define RT5682_CBJ_CTRL_6 0x0015
40
+
#define RT5682_CBJ_CTRL_7 0x0016
41
+
/* I/O - ADC/DAC/DMIC */
42
+
#define RT5682_DAC1_DIG_VOL 0x0019
43
+
#define RT5682_STO1_ADC_DIG_VOL 0x001c
44
+
#define RT5682_STO1_ADC_BOOST 0x001f
45
+
#define RT5682_HP_IMP_GAIN_1 0x0022
46
+
#define RT5682_HP_IMP_GAIN_2 0x0023
47
+
/* Mixer - D-D */
48
+
#define RT5682_SIDETONE_CTRL 0x0024
49
+
#define RT5682_STO1_ADC_MIXER 0x0026
50
+
#define RT5682_AD_DA_MIXER 0x0029
51
+
#define RT5682_STO1_DAC_MIXER 0x002a
52
+
#define RT5682_A_DAC1_MUX 0x002b
53
+
#define RT5682_DIG_INF2_DATA 0x0030
54
+
/* Mixer - ADC */
55
+
#define RT5682_REC_MIXER 0x003c
56
+
#define RT5682_CAL_REC 0x0044
57
+
#define RT5682_ALC_BACK_GAIN 0x0049
58
+
/* Power */
59
+
#define RT5682_PWR_DIG_1 0x0061
60
+
#define RT5682_PWR_DIG_2 0x0062
61
+
#define RT5682_PWR_ANLG_1 0x0063
62
+
#define RT5682_PWR_ANLG_2 0x0064
63
+
#define RT5682_PWR_ANLG_3 0x0065
64
+
#define RT5682_PWR_MIXER 0x0066
65
+
#define RT5682_PWR_VOL 0x0067
66
+
/* Clock Detect */
67
+
#define RT5682_CLK_DET 0x006b
68
+
/* Filter Auto Reset */
69
+
#define RT5682_RESET_LPF_CTRL 0x006c
70
+
#define RT5682_RESET_HPF_CTRL 0x006d
71
+
/* DMIC */
72
+
#define RT5682_DMIC_CTRL_1 0x006e
73
+
/* Format - ADC/DAC */
74
+
#define RT5682_I2S1_SDP 0x0070
75
+
#define RT5682_I2S2_SDP 0x0071
76
+
#define RT5682_ADDA_CLK_1 0x0073
77
+
#define RT5682_ADDA_CLK_2 0x0074
78
+
#define RT5682_I2S1_F_DIV_CTRL_1 0x0075
79
+
#define RT5682_I2S1_F_DIV_CTRL_2 0x0076
80
+
/* Format - TDM Control */
81
+
#define RT5682_TDM_CTRL 0x0079
82
+
#define RT5682_TDM_ADDA_CTRL_1 0x007a
83
+
#define RT5682_TDM_ADDA_CTRL_2 0x007b
84
+
#define RT5682_DATA_SEL_CTRL_1 0x007c
85
+
#define RT5682_TDM_TCON_CTRL 0x007e
86
+
/* Function - Analog */
87
+
#define RT5682_GLB_CLK 0x0080
88
+
#define RT5682_PLL_CTRL_1 0x0081
89
+
#define RT5682_PLL_CTRL_2 0x0082
90
+
#define RT5682_PLL_TRACK_1 0x0083
91
+
#define RT5682_PLL_TRACK_2 0x0084
92
+
#define RT5682_PLL_TRACK_3 0x0085
93
+
#define RT5682_PLL_TRACK_4 0x0086
94
+
#define RT5682_PLL_TRACK_5 0x0087
95
+
#define RT5682_PLL_TRACK_6 0x0088
96
+
#define RT5682_PLL_TRACK_11 0x008c
97
+
#define RT5682_SDW_REF_CLK 0x008d
98
+
#define RT5682_DEPOP_1 0x008e
99
+
#define RT5682_DEPOP_2 0x008f
100
+
#define RT5682_HP_CHARGE_PUMP_1 0x0091
101
+
#define RT5682_HP_CHARGE_PUMP_2 0x0092
102
+
#define RT5682_MICBIAS_1 0x0093
103
+
#define RT5682_MICBIAS_2 0x0094
104
+
#define RT5682_PLL_TRACK_12 0x0098
105
+
#define RT5682_PLL_TRACK_14 0x009a
106
+
#define RT5682_PLL2_CTRL_1 0x009b
107
+
#define RT5682_PLL2_CTRL_2 0x009c
108
+
#define RT5682_PLL2_CTRL_3 0x009d
109
+
#define RT5682_PLL2_CTRL_4 0x009e
110
+
#define RT5682_RC_CLK_CTRL 0x009f
111
+
#define RT5682_I2S_M_CLK_CTRL_1 0x00a0
112
+
#define RT5682_I2S2_F_DIV_CTRL_1 0x00a3
113
+
#define RT5682_I2S2_F_DIV_CTRL_2 0x00a4
114
+
/* Function - Digital */
115
+
#define RT5682_EQ_CTRL_1 0x00ae
116
+
#define RT5682_EQ_CTRL_2 0x00af
117
+
#define RT5682_IRQ_CTRL_1 0x00b6
118
+
#define RT5682_IRQ_CTRL_2 0x00b7
119
+
#define RT5682_IRQ_CTRL_3 0x00b8
120
+
#define RT5682_IRQ_CTRL_4 0x00b9
121
+
#define RT5682_INT_ST_1 0x00be
122
+
#define RT5682_GPIO_CTRL_1 0x00c0
123
+
#define RT5682_GPIO_CTRL_2 0x00c1
124
+
#define RT5682_GPIO_CTRL_3 0x00c2
125
+
#define RT5682_HP_AMP_DET_CTRL_1 0x00d0
126
+
#define RT5682_HP_AMP_DET_CTRL_2 0x00d1
127
+
#define RT5682_MID_HP_AMP_DET 0x00d2
128
+
#define RT5682_LOW_HP_AMP_DET 0x00d3
129
+
#define RT5682_DELAY_BUF_CTRL 0x00d4
130
+
#define RT5682_SV_ZCD_1 0x00d9
131
+
#define RT5682_SV_ZCD_2 0x00da
132
+
#define RT5682_IL_CMD_1 0x00db
133
+
#define RT5682_IL_CMD_2 0x00dc
134
+
#define RT5682_IL_CMD_3 0x00dd
135
+
#define RT5682_IL_CMD_4 0x00de
136
+
#define RT5682_IL_CMD_5 0x00df
137
+
#define RT5682_IL_CMD_6 0x00e0
138
+
#define RT5682_4BTN_IL_CMD_1 0x00e2
139
+
#define RT5682_4BTN_IL_CMD_2 0x00e3
140
+
#define RT5682_4BTN_IL_CMD_3 0x00e4
141
+
#define RT5682_4BTN_IL_CMD_4 0x00e5
142
+
#define RT5682_4BTN_IL_CMD_5 0x00e6
143
+
#define RT5682_4BTN_IL_CMD_6 0x00e7
144
+
#define RT5682_4BTN_IL_CMD_7 0x00e8
145
+
146
+
#define RT5682_ADC_STO1_HP_CTRL_1 0x00ea
147
+
#define RT5682_ADC_STO1_HP_CTRL_2 0x00eb
148
+
#define RT5682_AJD1_CTRL 0x00f0
149
+
#define RT5682_JD1_THD 0x00f1
150
+
#define RT5682_JD2_THD 0x00f2
151
+
#define RT5682_JD_CTRL_1 0x00f6
152
+
/* General Control */
153
+
#define RT5682_DUMMY_1 0x00fa
154
+
#define RT5682_DUMMY_2 0x00fb
155
+
#define RT5682_DUMMY_3 0x00fc
156
+
157
+
#define RT5682_DAC_ADC_DIG_VOL1 0x0100
158
+
#define RT5682_BIAS_CUR_CTRL_2 0x010b
159
+
#define RT5682_BIAS_CUR_CTRL_3 0x010c
160
+
#define RT5682_BIAS_CUR_CTRL_4 0x010d
161
+
#define RT5682_BIAS_CUR_CTRL_5 0x010e
162
+
#define RT5682_BIAS_CUR_CTRL_6 0x010f
163
+
#define RT5682_BIAS_CUR_CTRL_7 0x0110
164
+
#define RT5682_BIAS_CUR_CTRL_8 0x0111
165
+
#define RT5682_BIAS_CUR_CTRL_9 0x0112
166
+
#define RT5682_BIAS_CUR_CTRL_10 0x0113
167
+
#define RT5682_VREF_REC_OP_FB_CAP_CTRL 0x0117
168
+
#define RT5682_CHARGE_PUMP_1 0x0125
169
+
#define RT5682_DIG_IN_CTRL_1 0x0132
170
+
#define RT5682_PAD_DRIVING_CTRL 0x0136
171
+
#define RT5682_SOFT_RAMP_DEPOP 0x0138
172
+
#define RT5682_CHOP_DAC 0x013a
173
+
#define RT5682_CHOP_ADC 0x013b
174
+
#define RT5682_CALIB_ADC_CTRL 0x013c
175
+
#define RT5682_VOL_TEST 0x013f
176
+
#define RT5682_SPKVDD_DET_STA 0x0142
177
+
#define RT5682_TEST_MODE_CTRL_1 0x0145
178
+
#define RT5682_TEST_MODE_CTRL_2 0x0146
179
+
#define RT5682_TEST_MODE_CTRL_3 0x0147
180
+
#define RT5682_TEST_MODE_CTRL_4 0x0148
181
+
#define RT5682_TEST_MODE_CTRL_5 0x0149
182
+
#define RT5682_PLL1_INTERNAL 0x0150
183
+
#define RT5682_PLL2_INTERNAL 0x0151
184
+
#define RT5682_STO_NG2_CTRL_1 0x0160
185
+
#define RT5682_STO_NG2_CTRL_2 0x0161
186
+
#define RT5682_STO_NG2_CTRL_3 0x0162
187
+
#define RT5682_STO_NG2_CTRL_4 0x0163
188
+
#define RT5682_STO_NG2_CTRL_5 0x0164
189
+
#define RT5682_STO_NG2_CTRL_6 0x0165
190
+
#define RT5682_STO_NG2_CTRL_7 0x0166
191
+
#define RT5682_STO_NG2_CTRL_8 0x0167
192
+
#define RT5682_STO_NG2_CTRL_9 0x0168
193
+
#define RT5682_STO_NG2_CTRL_10 0x0169
194
+
#define RT5682_STO1_DAC_SIL_DET 0x0190
195
+
#define RT5682_SIL_PSV_CTRL1 0x0194
196
+
#define RT5682_SIL_PSV_CTRL2 0x0195
197
+
#define RT5682_SIL_PSV_CTRL3 0x0197
198
+
#define RT5682_SIL_PSV_CTRL4 0x0198
199
+
#define RT5682_SIL_PSV_CTRL5 0x0199
200
+
#define RT5682_HP_IMP_SENS_CTRL_01 0x01af
201
+
#define RT5682_HP_IMP_SENS_CTRL_02 0x01b0
202
+
#define RT5682_HP_IMP_SENS_CTRL_03 0x01b1
203
+
#define RT5682_HP_IMP_SENS_CTRL_04 0x01b2
204
+
#define RT5682_HP_IMP_SENS_CTRL_05 0x01b3
205
+
#define RT5682_HP_IMP_SENS_CTRL_06 0x01b4
206
+
#define RT5682_HP_IMP_SENS_CTRL_07 0x01b5
207
+
#define RT5682_HP_IMP_SENS_CTRL_08 0x01b6
208
+
#define RT5682_HP_IMP_SENS_CTRL_09 0x01b7
209
+
#define RT5682_HP_IMP_SENS_CTRL_10 0x01b8
210
+
#define RT5682_HP_IMP_SENS_CTRL_11 0x01b9
211
+
#define RT5682_HP_IMP_SENS_CTRL_12 0x01ba
212
+
#define RT5682_HP_IMP_SENS_CTRL_13 0x01bb
213
+
#define RT5682_HP_IMP_SENS_CTRL_14 0x01bc
214
+
#define RT5682_HP_IMP_SENS_CTRL_15 0x01bd
215
+
#define RT5682_HP_IMP_SENS_CTRL_16 0x01be
216
+
#define RT5682_HP_IMP_SENS_CTRL_17 0x01bf
217
+
#define RT5682_HP_IMP_SENS_CTRL_18 0x01c0
218
+
#define RT5682_HP_IMP_SENS_CTRL_19 0x01c1
219
+
#define RT5682_HP_IMP_SENS_CTRL_20 0x01c2
220
+
#define RT5682_HP_IMP_SENS_CTRL_21 0x01c3
221
+
#define RT5682_HP_IMP_SENS_CTRL_22 0x01c4
222
+
#define RT5682_HP_IMP_SENS_CTRL_23 0x01c5
223
+
#define RT5682_HP_IMP_SENS_CTRL_24 0x01c6
224
+
#define RT5682_HP_IMP_SENS_CTRL_25 0x01c7
225
+
#define RT5682_HP_IMP_SENS_CTRL_26 0x01c8
226
+
#define RT5682_HP_IMP_SENS_CTRL_27 0x01c9
227
+
#define RT5682_HP_IMP_SENS_CTRL_28 0x01ca
228
+
#define RT5682_HP_IMP_SENS_CTRL_29 0x01cb
229
+
#define RT5682_HP_IMP_SENS_CTRL_30 0x01cc
230
+
#define RT5682_HP_IMP_SENS_CTRL_31 0x01cd
231
+
#define RT5682_HP_IMP_SENS_CTRL_32 0x01ce
232
+
#define RT5682_HP_IMP_SENS_CTRL_33 0x01cf
233
+
#define RT5682_HP_IMP_SENS_CTRL_34 0x01d0
234
+
#define RT5682_HP_IMP_SENS_CTRL_35 0x01d1
235
+
#define RT5682_HP_IMP_SENS_CTRL_36 0x01d2
236
+
#define RT5682_HP_IMP_SENS_CTRL_37 0x01d3
237
+
#define RT5682_HP_IMP_SENS_CTRL_38 0x01d4
238
+
#define RT5682_HP_IMP_SENS_CTRL_39 0x01d5
239
+
#define RT5682_HP_IMP_SENS_CTRL_40 0x01d6
240
+
#define RT5682_HP_IMP_SENS_CTRL_41 0x01d7
241
+
#define RT5682_HP_IMP_SENS_CTRL_42 0x01d8
242
+
#define RT5682_HP_IMP_SENS_CTRL_43 0x01d9
243
+
#define RT5682_HP_LOGIC_CTRL_1 0x01da
244
+
#define RT5682_HP_LOGIC_CTRL_2 0x01db
245
+
#define RT5682_HP_LOGIC_CTRL_3 0x01dc
246
+
#define RT5682_HP_CALIB_CTRL_1 0x01de
247
+
#define RT5682_HP_CALIB_CTRL_2 0x01df
248
+
#define RT5682_HP_CALIB_CTRL_3 0x01e0
249
+
#define RT5682_HP_CALIB_CTRL_4 0x01e1
250
+
#define RT5682_HP_CALIB_CTRL_5 0x01e2
251
+
#define RT5682_HP_CALIB_CTRL_6 0x01e3
252
+
#define RT5682_HP_CALIB_CTRL_7 0x01e4
253
+
#define RT5682_HP_CALIB_CTRL_9 0x01e6
254
+
#define RT5682_HP_CALIB_CTRL_10 0x01e7
255
+
#define RT5682_HP_CALIB_CTRL_11 0x01e8
256
+
#define RT5682_HP_CALIB_STA_1 0x01ea
257
+
#define RT5682_HP_CALIB_STA_2 0x01eb
258
+
#define RT5682_HP_CALIB_STA_3 0x01ec
259
+
#define RT5682_HP_CALIB_STA_4 0x01ed
260
+
#define RT5682_HP_CALIB_STA_5 0x01ee
261
+
#define RT5682_HP_CALIB_STA_6 0x01ef
262
+
#define RT5682_HP_CALIB_STA_7 0x01f0
263
+
#define RT5682_HP_CALIB_STA_8 0x01f1
264
+
#define RT5682_HP_CALIB_STA_9 0x01f2
265
+
#define RT5682_HP_CALIB_STA_10 0x01f3
266
+
#define RT5682_HP_CALIB_STA_11 0x01f4
267
+
#define RT5682_SAR_IL_CMD_1 0x0210
268
+
#define RT5682_SAR_IL_CMD_2 0x0211
269
+
#define RT5682_SAR_IL_CMD_3 0x0212
270
+
#define RT5682_SAR_IL_CMD_4 0x0213
271
+
#define RT5682_SAR_IL_CMD_5 0x0214
272
+
#define RT5682_SAR_IL_CMD_6 0x0215
273
+
#define RT5682_SAR_IL_CMD_7 0x0216
274
+
#define RT5682_SAR_IL_CMD_8 0x0217
275
+
#define RT5682_SAR_IL_CMD_9 0x0218
276
+
#define RT5682_SAR_IL_CMD_10 0x0219
277
+
#define RT5682_SAR_IL_CMD_11 0x021a
278
+
#define RT5682_SAR_IL_CMD_12 0x021b
279
+
#define RT5682_SAR_IL_CMD_13 0x021c
280
+
#define RT5682_EFUSE_CTRL_1 0x0250
281
+
#define RT5682_EFUSE_CTRL_2 0x0251
282
+
#define RT5682_EFUSE_CTRL_3 0x0252
283
+
#define RT5682_EFUSE_CTRL_4 0x0253
284
+
#define RT5682_EFUSE_CTRL_5 0x0254
285
+
#define RT5682_EFUSE_CTRL_6 0x0255
286
+
#define RT5682_EFUSE_CTRL_7 0x0256
287
+
#define RT5682_EFUSE_CTRL_8 0x0257
288
+
#define RT5682_EFUSE_CTRL_9 0x0258
289
+
#define RT5682_EFUSE_CTRL_10 0x0259
290
+
#define RT5682_EFUSE_CTRL_11 0x025a
291
+
#define RT5682_JD_TOP_VC_VTRL 0x0270
292
+
#define RT5682_DRC1_CTRL_0 0x02ff
293
+
#define RT5682_DRC1_CTRL_1 0x0300
294
+
#define RT5682_DRC1_CTRL_2 0x0301
295
+
#define RT5682_DRC1_CTRL_3 0x0302
296
+
#define RT5682_DRC1_CTRL_4 0x0303
297
+
#define RT5682_DRC1_CTRL_5 0x0304
298
+
#define RT5682_DRC1_CTRL_6 0x0305
299
+
#define RT5682_DRC1_HARD_LMT_CTRL_1 0x0306
300
+
#define RT5682_DRC1_HARD_LMT_CTRL_2 0x0307
301
+
#define RT5682_DRC1_PRIV_1 0x0310
302
+
#define RT5682_DRC1_PRIV_2 0x0311
303
+
#define RT5682_DRC1_PRIV_3 0x0312
304
+
#define RT5682_DRC1_PRIV_4 0x0313
305
+
#define RT5682_DRC1_PRIV_5 0x0314
306
+
#define RT5682_DRC1_PRIV_6 0x0315
307
+
#define RT5682_DRC1_PRIV_7 0x0316
308
+
#define RT5682_DRC1_PRIV_8 0x0317
309
+
#define RT5682_EQ_AUTO_RCV_CTRL1 0x03c0
310
+
#define RT5682_EQ_AUTO_RCV_CTRL2 0x03c1
311
+
#define RT5682_EQ_AUTO_RCV_CTRL3 0x03c2
312
+
#define RT5682_EQ_AUTO_RCV_CTRL4 0x03c3
313
+
#define RT5682_EQ_AUTO_RCV_CTRL5 0x03c4
314
+
#define RT5682_EQ_AUTO_RCV_CTRL6 0x03c5
315
+
#define RT5682_EQ_AUTO_RCV_CTRL7 0x03c6
316
+
#define RT5682_EQ_AUTO_RCV_CTRL8 0x03c7
317
+
#define RT5682_EQ_AUTO_RCV_CTRL9 0x03c8
318
+
#define RT5682_EQ_AUTO_RCV_CTRL10 0x03c9
319
+
#define RT5682_EQ_AUTO_RCV_CTRL11 0x03ca
320
+
#define RT5682_EQ_AUTO_RCV_CTRL12 0x03cb
321
+
#define RT5682_EQ_AUTO_RCV_CTRL13 0x03cc
322
+
#define RT5682_ADC_L_EQ_LPF1_A1 0x03d0
323
+
#define RT5682_R_EQ_LPF1_A1 0x03d1
324
+
#define RT5682_L_EQ_LPF1_H0 0x03d2
325
+
#define RT5682_R_EQ_LPF1_H0 0x03d3
326
+
#define RT5682_L_EQ_BPF1_A1 0x03d4
327
+
#define RT5682_R_EQ_BPF1_A1 0x03d5
328
+
#define RT5682_L_EQ_BPF1_A2 0x03d6
329
+
#define RT5682_R_EQ_BPF1_A2 0x03d7
330
+
#define RT5682_L_EQ_BPF1_H0 0x03d8
331
+
#define RT5682_R_EQ_BPF1_H0 0x03d9
332
+
#define RT5682_L_EQ_BPF2_A1 0x03da
333
+
#define RT5682_R_EQ_BPF2_A1 0x03db
334
+
#define RT5682_L_EQ_BPF2_A2 0x03dc
335
+
#define RT5682_R_EQ_BPF2_A2 0x03dd
336
+
#define RT5682_L_EQ_BPF2_H0 0x03de
337
+
#define RT5682_R_EQ_BPF2_H0 0x03df
338
+
#define RT5682_L_EQ_BPF3_A1 0x03e0
339
+
#define RT5682_R_EQ_BPF3_A1 0x03e1
340
+
#define RT5682_L_EQ_BPF3_A2 0x03e2
341
+
#define RT5682_R_EQ_BPF3_A2 0x03e3
342
+
#define RT5682_L_EQ_BPF3_H0 0x03e4
343
+
#define RT5682_R_EQ_BPF3_H0 0x03e5
344
+
#define RT5682_L_EQ_BPF4_A1 0x03e6
345
+
#define RT5682_R_EQ_BPF4_A1 0x03e7
346
+
#define RT5682_L_EQ_BPF4_A2 0x03e8
347
+
#define RT5682_R_EQ_BPF4_A2 0x03e9
348
+
#define RT5682_L_EQ_BPF4_H0 0x03ea
349
+
#define RT5682_R_EQ_BPF4_H0 0x03eb
350
+
#define RT5682_L_EQ_HPF1_A1 0x03ec
351
+
#define RT5682_R_EQ_HPF1_A1 0x03ed
352
+
#define RT5682_L_EQ_HPF1_H0 0x03ee
353
+
#define RT5682_R_EQ_HPF1_H0 0x03ef
354
+
#define RT5682_L_EQ_PRE_VOL 0x03f0
355
+
#define RT5682_R_EQ_PRE_VOL 0x03f1
356
+
#define RT5682_L_EQ_POST_VOL 0x03f2
357
+
#define RT5682_R_EQ_POST_VOL 0x03f3
358
+
#define RT5682_I2C_MODE 0xffff
359
+
360
+
361
+
/* global definition */
362
+
#define RT5682_L_MUTE (0x1 << 15)
363
+
#define RT5682_L_MUTE_SFT 15
364
+
#define RT5682_VOL_L_MUTE (0x1 << 14)
365
+
#define RT5682_VOL_L_SFT 14
366
+
#define RT5682_R_MUTE (0x1 << 7)
367
+
#define RT5682_R_MUTE_SFT 7
368
+
#define RT5682_VOL_R_MUTE (0x1 << 6)
369
+
#define RT5682_VOL_R_SFT 6
370
+
#define RT5682_L_VOL_MASK (0x3f << 8)
371
+
#define RT5682_L_VOL_SFT 8
372
+
#define RT5682_R_VOL_MASK (0x3f)
373
+
#define RT5682_R_VOL_SFT 0
374
+
375
+
/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
376
+
#define RT5682_G_HP (0xf << 8)
377
+
#define RT5682_G_HP_SFT 8
378
+
#define RT5682_G_STO_DA_DMIX (0xf)
379
+
#define RT5682_G_STO_DA_SFT 0
380
+
381
+
/* CBJ Control (0x000b) */
382
+
#define RT5682_BST_CBJ_MASK (0xf << 8)
383
+
#define RT5682_BST_CBJ_SFT 8
384
+
385
+
/* Embeeded Jack and Type Detection Control 1 (0x0010) */
386
+
#define RT5682_EMB_JD_EN (0x1 << 15)
387
+
#define RT5682_EMB_JD_EN_SFT 15
388
+
#define RT5682_EMB_JD_RST (0x1 << 14)
389
+
#define RT5682_JD_MODE (0x1 << 13)
390
+
#define RT5682_JD_MODE_SFT 13
391
+
#define RT5682_DET_TYPE (0x1 << 12)
392
+
#define RT5682_DET_TYPE_SFT 12
393
+
#define RT5682_POLA_EXT_JD_MASK (0x1 << 11)
394
+
#define RT5682_POLA_EXT_JD_LOW (0x1 << 11)
395
+
#define RT5682_POLA_EXT_JD_HIGH (0x0 << 11)
396
+
#define RT5682_EXT_JD_DIG (0x1 << 9)
397
+
#define RT5682_POL_FAST_OFF_MASK (0x1 << 8)
398
+
#define RT5682_POL_FAST_OFF_HIGH (0x1 << 8)
399
+
#define RT5682_POL_FAST_OFF_LOW (0x0 << 8)
400
+
#define RT5682_FAST_OFF_MASK (0x1 << 7)
401
+
#define RT5682_FAST_OFF_EN (0x1 << 7)
402
+
#define RT5682_FAST_OFF_DIS (0x0 << 7)
403
+
#define RT5682_VREF_POW_MASK (0x1 << 6)
404
+
#define RT5682_VREF_POW_FSM (0x0 << 6)
405
+
#define RT5682_VREF_POW_REG (0x1 << 6)
406
+
#define RT5682_MB1_PATH_MASK (0x1 << 5)
407
+
#define RT5682_CTRL_MB1_REG (0x1 << 5)
408
+
#define RT5682_CTRL_MB1_FSM (0x0 << 5)
409
+
#define RT5682_MB2_PATH_MASK (0x1 << 4)
410
+
#define RT5682_CTRL_MB2_REG (0x1 << 4)
411
+
#define RT5682_CTRL_MB2_FSM (0x0 << 4)
412
+
#define RT5682_TRIG_JD_MASK (0x1 << 3)
413
+
#define RT5682_TRIG_JD_HIGH (0x1 << 3)
414
+
#define RT5682_TRIG_JD_LOW (0x0 << 3)
415
+
#define RT5682_MIC_CAP_MASK (0x1 << 1)
416
+
#define RT5682_MIC_CAP_HS (0x1 << 1)
417
+
#define RT5682_MIC_CAP_HP (0x0 << 1)
418
+
#define RT5682_MIC_CAP_SRC_MASK (0x1)
419
+
#define RT5682_MIC_CAP_SRC_REG (0x1)
420
+
#define RT5682_MIC_CAP_SRC_ANA (0x0)
421
+
422
+
/* Embeeded Jack and Type Detection Control 2 (0x0011) */
423
+
#define RT5682_EXT_JD_SRC (0x7 << 4)
424
+
#define RT5682_EXT_JD_SRC_SFT 4
425
+
#define RT5682_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
426
+
#define RT5682_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
427
+
#define RT5682_EXT_JD_SRC_JDH (0x2 << 4)
428
+
#define RT5682_EXT_JD_SRC_JDL (0x3 << 4)
429
+
#define RT5682_EXT_JD_SRC_MANUAL (0x4 << 4)
430
+
#define RT5682_JACK_TYPE_MASK (0x3)
431
+
432
+
/* Combo Jack and Type Detection Control 3 (0x0012) */
433
+
#define RT5682_CBJ_IN_BUF_EN (0x1 << 7)
434
+
435
+
/* Combo Jack and Type Detection Control 4 (0x0013) */
436
+
#define RT5682_SEL_SHT_MID_TON_MASK (0x3 << 12)
437
+
#define RT5682_SEL_SHT_MID_TON_2 (0x0 << 12)
438
+
#define RT5682_SEL_SHT_MID_TON_3 (0x1 << 12)
439
+
#define RT5682_CBJ_JD_TEST_MASK (0x1 << 6)
440
+
#define RT5682_CBJ_JD_TEST_NORM (0x0 << 6)
441
+
#define RT5682_CBJ_JD_TEST_MODE (0x1 << 6)
442
+
443
+
/* DAC1 Digital Volume (0x0019) */
444
+
#define RT5682_DAC_L1_VOL_MASK (0xff << 8)
445
+
#define RT5682_DAC_L1_VOL_SFT 8
446
+
#define RT5682_DAC_R1_VOL_MASK (0xff)
447
+
#define RT5682_DAC_R1_VOL_SFT 0
448
+
449
+
/* ADC Digital Volume Control (0x001c) */
450
+
#define RT5682_ADC_L_VOL_MASK (0x7f << 8)
451
+
#define RT5682_ADC_L_VOL_SFT 8
452
+
#define RT5682_ADC_R_VOL_MASK (0x7f)
453
+
#define RT5682_ADC_R_VOL_SFT 0
454
+
455
+
/* Stereo1 ADC Boost Gain Control (0x001f) */
456
+
#define RT5682_STO1_ADC_L_BST_MASK (0x3 << 14)
457
+
#define RT5682_STO1_ADC_L_BST_SFT 14
458
+
#define RT5682_STO1_ADC_R_BST_MASK (0x3 << 12)
459
+
#define RT5682_STO1_ADC_R_BST_SFT 12
460
+
461
+
/* Sidetone Control (0x0024) */
462
+
#define RT5682_ST_SRC_SEL (0x1 << 8)
463
+
#define RT5682_ST_SRC_SFT 8
464
+
#define RT5682_ST_EN_MASK (0x1 << 6)
465
+
#define RT5682_ST_DIS (0x0 << 6)
466
+
#define RT5682_ST_EN (0x1 << 6)
467
+
#define RT5682_ST_EN_SFT 6
468
+
469
+
/* Stereo1 ADC Mixer Control (0x0026) */
470
+
#define RT5682_M_STO1_ADC_L1 (0x1 << 15)
471
+
#define RT5682_M_STO1_ADC_L1_SFT 15
472
+
#define RT5682_M_STO1_ADC_L2 (0x1 << 14)
473
+
#define RT5682_M_STO1_ADC_L2_SFT 14
474
+
#define RT5682_STO1_ADC1L_SRC_MASK (0x1 << 13)
475
+
#define RT5682_STO1_ADC1L_SRC_SFT 13
476
+
#define RT5682_STO1_ADC1_SRC_ADC (0x1 << 13)
477
+
#define RT5682_STO1_ADC1_SRC_DACMIX (0x0 << 13)
478
+
#define RT5682_STO1_ADC2L_SRC_MASK (0x1 << 12)
479
+
#define RT5682_STO1_ADC2L_SRC_SFT 12
480
+
#define RT5682_STO1_ADCL_SRC_MASK (0x3 << 10)
481
+
#define RT5682_STO1_ADCL_SRC_SFT 10
482
+
#define RT5682_STO1_DD_L_SRC_MASK (0x1 << 9)
483
+
#define RT5682_STO1_DD_L_SRC_SFT 9
484
+
#define RT5682_STO1_DMIC_SRC_MASK (0x1 << 8)
485
+
#define RT5682_STO1_DMIC_SRC_SFT 8
486
+
#define RT5682_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
487
+
#define RT5682_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
488
+
#define RT5682_M_STO1_ADC_R1 (0x1 << 7)
489
+
#define RT5682_M_STO1_ADC_R1_SFT 7
490
+
#define RT5682_M_STO1_ADC_R2 (0x1 << 6)
491
+
#define RT5682_M_STO1_ADC_R2_SFT 6
492
+
#define RT5682_STO1_ADC1R_SRC_MASK (0x1 << 5)
493
+
#define RT5682_STO1_ADC1R_SRC_SFT 5
494
+
#define RT5682_STO1_ADC2R_SRC_MASK (0x1 << 4)
495
+
#define RT5682_STO1_ADC2R_SRC_SFT 4
496
+
#define RT5682_STO1_ADCR_SRC_MASK (0x3 << 2)
497
+
#define RT5682_STO1_ADCR_SRC_SFT 2
498
+
499
+
/* ADC Mixer to DAC Mixer Control (0x0029) */
500
+
#define RT5682_M_ADCMIX_L (0x1 << 15)
501
+
#define RT5682_M_ADCMIX_L_SFT 15
502
+
#define RT5682_M_DAC1_L (0x1 << 14)
503
+
#define RT5682_M_DAC1_L_SFT 14
504
+
#define RT5682_DAC1_R_SEL_MASK (0x1 << 10)
505
+
#define RT5682_DAC1_R_SEL_SFT 10
506
+
#define RT5682_DAC1_L_SEL_MASK (0x1 << 8)
507
+
#define RT5682_DAC1_L_SEL_SFT 8
508
+
#define RT5682_M_ADCMIX_R (0x1 << 7)
509
+
#define RT5682_M_ADCMIX_R_SFT 7
510
+
#define RT5682_M_DAC1_R (0x1 << 6)
511
+
#define RT5682_M_DAC1_R_SFT 6
512
+
513
+
/* Stereo1 DAC Mixer Control (0x002a) */
514
+
#define RT5682_M_DAC_L1_STO_L (0x1 << 15)
515
+
#define RT5682_M_DAC_L1_STO_L_SFT 15
516
+
#define RT5682_G_DAC_L1_STO_L_MASK (0x1 << 14)
517
+
#define RT5682_G_DAC_L1_STO_L_SFT 14
518
+
#define RT5682_M_DAC_R1_STO_L (0x1 << 13)
519
+
#define RT5682_M_DAC_R1_STO_L_SFT 13
520
+
#define RT5682_G_DAC_R1_STO_L_MASK (0x1 << 12)
521
+
#define RT5682_G_DAC_R1_STO_L_SFT 12
522
+
#define RT5682_M_DAC_L1_STO_R (0x1 << 7)
523
+
#define RT5682_M_DAC_L1_STO_R_SFT 7
524
+
#define RT5682_G_DAC_L1_STO_R_MASK (0x1 << 6)
525
+
#define RT5682_G_DAC_L1_STO_R_SFT 6
526
+
#define RT5682_M_DAC_R1_STO_R (0x1 << 5)
527
+
#define RT5682_M_DAC_R1_STO_R_SFT 5
528
+
#define RT5682_G_DAC_R1_STO_R_MASK (0x1 << 4)
529
+
#define RT5682_G_DAC_R1_STO_R_SFT 4
530
+
531
+
/* Analog DAC1 Input Source Control (0x002b) */
532
+
#define RT5682_M_ST_STO_L (0x1 << 9)
533
+
#define RT5682_M_ST_STO_L_SFT 9
534
+
#define RT5682_M_ST_STO_R (0x1 << 8)
535
+
#define RT5682_M_ST_STO_R_SFT 8
536
+
#define RT5682_DAC_L1_SRC_MASK (0x3 << 4)
537
+
#define RT5682_A_DACL1_SFT 4
538
+
#define RT5682_DAC_R1_SRC_MASK (0x3)
539
+
#define RT5682_A_DACR1_SFT 0
540
+
541
+
/* Digital Interface Data Control (0x0030) */
542
+
#define RT5682_IF2_ADC_SEL_MASK (0x3 << 0)
543
+
#define RT5682_IF2_ADC_SEL_SFT 0
544
+
545
+
/* REC Left Mixer Control 2 (0x003c) */
546
+
#define RT5682_G_CBJ_RM1_L (0x7 << 10)
547
+
#define RT5682_G_CBJ_RM1_L_SFT 10
548
+
#define RT5682_M_CBJ_RM1_L (0x1 << 7)
549
+
#define RT5682_M_CBJ_RM1_L_SFT 7
550
+
551
+
/* Power Management for Digital 1 (0x0061) */
552
+
#define RT5682_PWR_I2S1 (0x1 << 15)
553
+
#define RT5682_PWR_I2S1_BIT 15
554
+
#define RT5682_PWR_I2S2 (0x1 << 14)
555
+
#define RT5682_PWR_I2S2_BIT 14
556
+
#define RT5682_PWR_DAC_L1 (0x1 << 11)
557
+
#define RT5682_PWR_DAC_L1_BIT 11
558
+
#define RT5682_PWR_DAC_R1 (0x1 << 10)
559
+
#define RT5682_PWR_DAC_R1_BIT 10
560
+
#define RT5682_PWR_LDO (0x1 << 8)
561
+
#define RT5682_PWR_LDO_BIT 8
562
+
#define RT5682_PWR_ADC_L1 (0x1 << 4)
563
+
#define RT5682_PWR_ADC_L1_BIT 4
564
+
#define RT5682_PWR_ADC_R1 (0x1 << 3)
565
+
#define RT5682_PWR_ADC_R1_BIT 3
566
+
#define RT5682_DIG_GATE_CTRL (0x1 << 0)
567
+
#define RT5682_DIG_GATE_CTRL_SFT 0
568
+
569
+
570
+
/* Power Management for Digital 2 (0x0062) */
571
+
#define RT5682_PWR_ADC_S1F (0x1 << 15)
572
+
#define RT5682_PWR_ADC_S1F_BIT 15
573
+
#define RT5682_PWR_DAC_S1F (0x1 << 10)
574
+
#define RT5682_PWR_DAC_S1F_BIT 10
575
+
576
+
/* Power Management for Analog 1 (0x0063) */
577
+
#define RT5682_PWR_VREF1 (0x1 << 15)
578
+
#define RT5682_PWR_VREF1_BIT 15
579
+
#define RT5682_PWR_FV1 (0x1 << 14)
580
+
#define RT5682_PWR_FV1_BIT 14
581
+
#define RT5682_PWR_VREF2 (0x1 << 13)
582
+
#define RT5682_PWR_VREF2_BIT 13
583
+
#define RT5682_PWR_FV2 (0x1 << 12)
584
+
#define RT5682_PWR_FV2_BIT 12
585
+
#define RT5682_LDO1_DBG_MASK (0x3 << 10)
586
+
#define RT5682_PWR_MB (0x1 << 9)
587
+
#define RT5682_PWR_MB_BIT 9
588
+
#define RT5682_PWR_BG (0x1 << 7)
589
+
#define RT5682_PWR_BG_BIT 7
590
+
#define RT5682_LDO1_BYPASS_MASK (0x1 << 6)
591
+
#define RT5682_LDO1_BYPASS (0x1 << 6)
592
+
#define RT5682_LDO1_NOT_BYPASS (0x0 << 6)
593
+
#define RT5682_PWR_MA_BIT 6
594
+
#define RT5682_LDO1_DVO_MASK (0x3 << 4)
595
+
#define RT5682_LDO1_DVO_09 (0x0 << 4)
596
+
#define RT5682_LDO1_DVO_10 (0x1 << 4)
597
+
#define RT5682_LDO1_DVO_12 (0x2 << 4)
598
+
#define RT5682_LDO1_DVO_14 (0x3 << 4)
599
+
#define RT5682_HP_DRIVER_MASK (0x3 << 2)
600
+
#define RT5682_HP_DRIVER_1X (0x0 << 2)
601
+
#define RT5682_HP_DRIVER_3X (0x1 << 2)
602
+
#define RT5682_HP_DRIVER_5X (0x3 << 2)
603
+
#define RT5682_PWR_HA_L (0x1 << 1)
604
+
#define RT5682_PWR_HA_L_BIT 1
605
+
#define RT5682_PWR_HA_R (0x1 << 0)
606
+
#define RT5682_PWR_HA_R_BIT 0
607
+
608
+
/* Power Management for Analog 2 (0x0064) */
609
+
#define RT5682_PWR_MB1 (0x1 << 11)
610
+
#define RT5682_PWR_MB1_PWR_DOWN (0x0 << 11)
611
+
#define RT5682_PWR_MB1_BIT 11
612
+
#define RT5682_PWR_MB2 (0x1 << 10)
613
+
#define RT5682_PWR_MB2_PWR_DOWN (0x0 << 10)
614
+
#define RT5682_PWR_MB2_BIT 10
615
+
#define RT5682_PWR_JDH (0x1 << 3)
616
+
#define RT5682_PWR_JDH_BIT 3
617
+
#define RT5682_PWR_JDL (0x1 << 2)
618
+
#define RT5682_PWR_JDL_BIT 2
619
+
#define RT5682_PWR_RM1_L (0x1 << 1)
620
+
#define RT5682_PWR_RM1_L_BIT 1
621
+
622
+
/* Power Management for Analog 3 (0x0065) */
623
+
#define RT5682_PWR_CBJ (0x1 << 9)
624
+
#define RT5682_PWR_CBJ_BIT 9
625
+
#define RT5682_PWR_PLL (0x1 << 6)
626
+
#define RT5682_PWR_PLL_BIT 6
627
+
#define RT5682_PWR_PLL2B (0x1 << 5)
628
+
#define RT5682_PWR_PLL2B_BIT 5
629
+
#define RT5682_PWR_PLL2F (0x1 << 4)
630
+
#define RT5682_PWR_PLL2F_BIT 4
631
+
#define RT5682_PWR_LDO2 (0x1 << 2)
632
+
#define RT5682_PWR_LDO2_BIT 2
633
+
#define RT5682_PWR_DET_SPKVDD (0x1 << 1)
634
+
#define RT5682_PWR_DET_SPKVDD_BIT 1
635
+
636
+
/* Power Management for Mixer (0x0066) */
637
+
#define RT5682_PWR_STO1_DAC_L (0x1 << 5)
638
+
#define RT5682_PWR_STO1_DAC_L_BIT 5
639
+
#define RT5682_PWR_STO1_DAC_R (0x1 << 4)
640
+
#define RT5682_PWR_STO1_DAC_R_BIT 4
641
+
642
+
/* MCLK and System Clock Detection Control (0x006b) */
643
+
#define RT5682_SYS_CLK_DET (0x1 << 15)
644
+
#define RT5682_SYS_CLK_DET_SFT 15
645
+
#define RT5682_PLL1_CLK_DET (0x1 << 14)
646
+
#define RT5682_PLL1_CLK_DET_SFT 14
647
+
#define RT5682_PLL2_CLK_DET (0x1 << 13)
648
+
#define RT5682_PLL2_CLK_DET_SFT 13
649
+
#define RT5682_POW_CLK_DET2_SFT 8
650
+
#define RT5682_POW_CLK_DET_SFT 0
651
+
652
+
/* Digital Microphone Control 1 (0x006e) */
653
+
#define RT5682_DMIC_1_EN_MASK (0x1 << 15)
654
+
#define RT5682_DMIC_1_EN_SFT 15
655
+
#define RT5682_DMIC_1_DIS (0x0 << 15)
656
+
#define RT5682_DMIC_1_EN (0x1 << 15)
657
+
#define RT5682_DMIC_1_DP_MASK (0x3 << 4)
658
+
#define RT5682_DMIC_1_DP_SFT 4
659
+
#define RT5682_DMIC_1_DP_GPIO2 (0x0 << 4)
660
+
#define RT5682_DMIC_1_DP_GPIO5 (0x1 << 4)
661
+
#define RT5682_DMIC_CLK_MASK (0xf << 0)
662
+
#define RT5682_DMIC_CLK_SFT 0
663
+
664
+
/* I2S1 Audio Serial Data Port Control (0x0070) */
665
+
#define RT5682_SEL_ADCDAT_MASK (0x1 << 15)
666
+
#define RT5682_SEL_ADCDAT_OUT (0x0 << 15)
667
+
#define RT5682_SEL_ADCDAT_IN (0x1 << 15)
668
+
#define RT5682_SEL_ADCDAT_SFT 15
669
+
#define RT5682_I2S1_TX_CHL_MASK (0x7 << 12)
670
+
#define RT5682_I2S1_TX_CHL_SFT 12
671
+
#define RT5682_I2S1_TX_CHL_16 (0x0 << 12)
672
+
#define RT5682_I2S1_TX_CHL_20 (0x1 << 12)
673
+
#define RT5682_I2S1_TX_CHL_24 (0x2 << 12)
674
+
#define RT5682_I2S1_TX_CHL_32 (0x3 << 12)
675
+
#define RT5682_I2S1_TX_CHL_8 (0x4 << 12)
676
+
#define RT5682_I2S1_RX_CHL_MASK (0x7 << 8)
677
+
#define RT5682_I2S1_RX_CHL_SFT 8
678
+
#define RT5682_I2S1_RX_CHL_16 (0x0 << 8)
679
+
#define RT5682_I2S1_RX_CHL_20 (0x1 << 8)
680
+
#define RT5682_I2S1_RX_CHL_24 (0x2 << 8)
681
+
#define RT5682_I2S1_RX_CHL_32 (0x3 << 8)
682
+
#define RT5682_I2S1_RX_CHL_8 (0x4 << 8)
683
+
#define RT5682_I2S1_MONO_MASK (0x1 << 7)
684
+
#define RT5682_I2S1_MONO_EN (0x1 << 7)
685
+
#define RT5682_I2S1_MONO_DIS (0x0 << 7)
686
+
#define RT5682_I2S2_MONO_MASK (0x1 << 6)
687
+
#define RT5682_I2S2_MONO_EN (0x1 << 6)
688
+
#define RT5682_I2S2_MONO_DIS (0x0 << 6)
689
+
#define RT5682_I2S1_DL_MASK (0x7 << 4)
690
+
#define RT5682_I2S1_DL_SFT 4
691
+
#define RT5682_I2S1_DL_16 (0x0 << 4)
692
+
#define RT5682_I2S1_DL_20 (0x1 << 4)
693
+
#define RT5682_I2S1_DL_24 (0x2 << 4)
694
+
#define RT5682_I2S1_DL_32 (0x3 << 4)
695
+
#define RT5682_I2S1_DL_8 (0x4 << 4)
696
+
697
+
/* I2S1/2 Audio Serial Data Port Control (0x0070)(0x0071) */
698
+
#define RT5682_I2S2_MS_MASK (0x1 << 15)
699
+
#define RT5682_I2S2_MS_SFT 15
700
+
#define RT5682_I2S2_MS_M (0x0 << 15)
701
+
#define RT5682_I2S2_MS_S (0x1 << 15)
702
+
#define RT5682_I2S2_PIN_CFG_MASK (0x1 << 14)
703
+
#define RT5682_I2S2_PIN_CFG_SFT 14
704
+
#define RT5682_I2S2_CLK_SEL_MASK (0x1 << 11)
705
+
#define RT5682_I2S2_CLK_SEL_SFT 11
706
+
#define RT5682_I2S2_OUT_MASK (0x1 << 9)
707
+
#define RT5682_I2S2_OUT_SFT 9
708
+
#define RT5682_I2S2_OUT_UM (0x0 << 9)
709
+
#define RT5682_I2S2_OUT_M (0x1 << 9)
710
+
#define RT5682_I2S_BP_MASK (0x1 << 8)
711
+
#define RT5682_I2S_BP_SFT 8
712
+
#define RT5682_I2S_BP_NOR (0x0 << 8)
713
+
#define RT5682_I2S_BP_INV (0x1 << 8)
714
+
#define RT5682_I2S2_MONO_EN (0x1 << 6)
715
+
#define RT5682_I2S2_MONO_DIS (0x0 << 6)
716
+
#define RT5682_I2S2_DL_MASK (0x3 << 4)
717
+
#define RT5682_I2S2_DL_SFT 4
718
+
#define RT5682_I2S2_DL_16 (0x0 << 4)
719
+
#define RT5682_I2S2_DL_20 (0x1 << 4)
720
+
#define RT5682_I2S2_DL_24 (0x2 << 4)
721
+
#define RT5682_I2S2_DL_8 (0x3 << 4)
722
+
#define RT5682_I2S_DF_MASK (0x7)
723
+
#define RT5682_I2S_DF_SFT 0
724
+
#define RT5682_I2S_DF_I2S (0x0)
725
+
#define RT5682_I2S_DF_LEFT (0x1)
726
+
#define RT5682_I2S_DF_PCM_A (0x2)
727
+
#define RT5682_I2S_DF_PCM_B (0x3)
728
+
#define RT5682_I2S_DF_PCM_A_N (0x6)
729
+
#define RT5682_I2S_DF_PCM_B_N (0x7)
730
+
731
+
/* ADC/DAC Clock Control 1 (0x0073) */
732
+
#define RT5682_ADC_OSR_MASK (0xf << 12)
733
+
#define RT5682_ADC_OSR_SFT 12
734
+
#define RT5682_ADC_OSR_D_1 (0x0 << 12)
735
+
#define RT5682_ADC_OSR_D_2 (0x1 << 12)
736
+
#define RT5682_ADC_OSR_D_4 (0x2 << 12)
737
+
#define RT5682_ADC_OSR_D_6 (0x3 << 12)
738
+
#define RT5682_ADC_OSR_D_8 (0x4 << 12)
739
+
#define RT5682_ADC_OSR_D_12 (0x5 << 12)
740
+
#define RT5682_ADC_OSR_D_16 (0x6 << 12)
741
+
#define RT5682_ADC_OSR_D_24 (0x7 << 12)
742
+
#define RT5682_ADC_OSR_D_32 (0x8 << 12)
743
+
#define RT5682_ADC_OSR_D_48 (0x9 << 12)
744
+
#define RT5682_I2S_M_DIV_MASK (0xf << 12)
745
+
#define RT5682_I2S_M_DIV_SFT 8
746
+
#define RT5682_I2S_M_D_1 (0x0 << 8)
747
+
#define RT5682_I2S_M_D_2 (0x1 << 8)
748
+
#define RT5682_I2S_M_D_3 (0x2 << 8)
749
+
#define RT5682_I2S_M_D_4 (0x3 << 8)
750
+
#define RT5682_I2S_M_D_6 (0x4 << 8)
751
+
#define RT5682_I2S_M_D_8 (0x5 << 8)
752
+
#define RT5682_I2S_M_D_12 (0x6 << 8)
753
+
#define RT5682_I2S_M_D_16 (0x7 << 8)
754
+
#define RT5682_I2S_M_D_24 (0x8 << 8)
755
+
#define RT5682_I2S_M_D_32 (0x9 << 8)
756
+
#define RT5682_I2S_M_D_48 (0x10 << 8)
757
+
#define RT5682_I2S_CLK_SRC_MASK (0x7 << 4)
758
+
#define RT5682_I2S_CLK_SRC_SFT 4
759
+
#define RT5682_I2S_CLK_SRC_MCLK (0x0 << 4)
760
+
#define RT5682_I2S_CLK_SRC_PLL1 (0x1 << 4)
761
+
#define RT5682_I2S_CLK_SRC_PLL2 (0x2 << 4)
762
+
#define RT5682_I2S_CLK_SRC_SDW (0x3 << 4)
763
+
#define RT5682_I2S_CLK_SRC_RCCLK (0x4 << 4) /* 25M */
764
+
#define RT5682_DAC_OSR_MASK (0xf << 0)
765
+
#define RT5682_DAC_OSR_SFT 0
766
+
#define RT5682_DAC_OSR_D_1 (0x0 << 0)
767
+
#define RT5682_DAC_OSR_D_2 (0x1 << 0)
768
+
#define RT5682_DAC_OSR_D_4 (0x2 << 0)
769
+
#define RT5682_DAC_OSR_D_6 (0x3 << 0)
770
+
#define RT5682_DAC_OSR_D_8 (0x4 << 0)
771
+
#define RT5682_DAC_OSR_D_12 (0x5 << 0)
772
+
#define RT5682_DAC_OSR_D_16 (0x6 << 0)
773
+
#define RT5682_DAC_OSR_D_24 (0x7 << 0)
774
+
#define RT5682_DAC_OSR_D_32 (0x8 << 0)
775
+
#define RT5682_DAC_OSR_D_48 (0x9 << 0)
776
+
777
+
/* ADC/DAC Clock Control 2 (0x0074) */
778
+
#define RT5682_I2S2_BCLK_MS2_MASK (0x1 << 11)
779
+
#define RT5682_I2S2_BCLK_MS2_SFT 11
780
+
#define RT5682_I2S2_BCLK_MS2_32 (0x0 << 11)
781
+
#define RT5682_I2S2_BCLK_MS2_64 (0x1 << 11)
782
+
783
+
784
+
/* TDM control 1 (0x0079) */
785
+
#define RT5682_TDM_TX_CH_MASK (0x3 << 12)
786
+
#define RT5682_TDM_TX_CH_2 (0x0 << 12)
787
+
#define RT5682_TDM_TX_CH_4 (0x1 << 12)
788
+
#define RT5682_TDM_TX_CH_6 (0x2 << 12)
789
+
#define RT5682_TDM_TX_CH_8 (0x3 << 12)
790
+
#define RT5682_TDM_RX_CH_MASK (0x3 << 8)
791
+
#define RT5682_TDM_RX_CH_2 (0x0 << 8)
792
+
#define RT5682_TDM_RX_CH_4 (0x1 << 8)
793
+
#define RT5682_TDM_RX_CH_6 (0x2 << 8)
794
+
#define RT5682_TDM_RX_CH_8 (0x3 << 8)
795
+
#define RT5682_TDM_ADC_LCA_MASK (0xf << 4)
796
+
#define RT5682_TDM_ADC_LCA_SFT 4
797
+
#define RT5682_TDM_ADC_DL_SFT 0
798
+
799
+
/* TDM control 2 (0x007a) */
800
+
#define RT5682_IF1_ADC1_SEL_SFT 14
801
+
#define RT5682_IF1_ADC2_SEL_SFT 12
802
+
#define RT5682_IF1_ADC3_SEL_SFT 10
803
+
#define RT5682_IF1_ADC4_SEL_SFT 8
804
+
#define RT5682_TDM_ADC_SEL_SFT 4
805
+
806
+
/* TDM control 3 (0x007b) */
807
+
#define RT5682_TDM_EN (0x1 << 7)
808
+
809
+
/* TDM/I2S control (0x007e) */
810
+
#define RT5682_TDM_S_BP_MASK (0x1 << 15)
811
+
#define RT5682_TDM_S_BP_SFT 15
812
+
#define RT5682_TDM_S_BP_NOR (0x0 << 15)
813
+
#define RT5682_TDM_S_BP_INV (0x1 << 15)
814
+
#define RT5682_TDM_S_LP_MASK (0x1 << 14)
815
+
#define RT5682_TDM_S_LP_SFT 14
816
+
#define RT5682_TDM_S_LP_NOR (0x0 << 14)
817
+
#define RT5682_TDM_S_LP_INV (0x1 << 14)
818
+
#define RT5682_TDM_DF_MASK (0x7 << 11)
819
+
#define RT5682_TDM_DF_SFT 11
820
+
#define RT5682_TDM_DF_I2S (0x0 << 11)
821
+
#define RT5682_TDM_DF_LEFT (0x1 << 11)
822
+
#define RT5682_TDM_DF_PCM_A (0x2 << 11)
823
+
#define RT5682_TDM_DF_PCM_B (0x3 << 11)
824
+
#define RT5682_TDM_DF_PCM_A_N (0x6 << 11)
825
+
#define RT5682_TDM_DF_PCM_B_N (0x7 << 11)
826
+
#define RT5682_TDM_CL_MASK (0x3 << 4)
827
+
#define RT5682_TDM_CL_16 (0x0 << 4)
828
+
#define RT5682_TDM_CL_20 (0x1 << 4)
829
+
#define RT5682_TDM_CL_24 (0x2 << 4)
830
+
#define RT5682_TDM_CL_32 (0x3 << 4)
831
+
#define RT5682_TDM_M_BP_MASK (0x1 << 2)
832
+
#define RT5682_TDM_M_BP_SFT 2
833
+
#define RT5682_TDM_M_BP_NOR (0x0 << 2)
834
+
#define RT5682_TDM_M_BP_INV (0x1 << 2)
835
+
#define RT5682_TDM_M_LP_MASK (0x1 << 1)
836
+
#define RT5682_TDM_M_LP_SFT 1
837
+
#define RT5682_TDM_M_LP_NOR (0x0 << 1)
838
+
#define RT5682_TDM_M_LP_INV (0x1 << 1)
839
+
#define RT5682_TDM_MS_MASK (0x1 << 0)
840
+
#define RT5682_TDM_MS_SFT 0
841
+
#define RT5682_TDM_MS_M (0x0 << 0)
842
+
#define RT5682_TDM_MS_S (0x1 << 0)
843
+
844
+
/* Global Clock Control (0x0080) */
845
+
#define RT5682_SCLK_SRC_MASK (0x7 << 13)
846
+
#define RT5682_SCLK_SRC_SFT 13
847
+
#define RT5682_SCLK_SRC_MCLK (0x0 << 13)
848
+
#define RT5682_SCLK_SRC_PLL1 (0x1 << 13)
849
+
#define RT5682_SCLK_SRC_PLL2 (0x2 << 13)
850
+
#define RT5682_SCLK_SRC_SDW (0x3 << 13)
851
+
#define RT5682_SCLK_SRC_RCCLK (0x4 << 13)
852
+
#define RT5682_PLL1_SRC_MASK (0x3 << 10)
853
+
#define RT5682_PLL1_SRC_SFT 10
854
+
#define RT5682_PLL1_SRC_MCLK (0x0 << 10)
855
+
#define RT5682_PLL1_SRC_BCLK1 (0x1 << 10)
856
+
#define RT5682_PLL1_SRC_SDW (0x2 << 10)
857
+
#define RT5682_PLL1_SRC_RC (0x3 << 10)
858
+
#define RT5682_PLL2_SRC_MASK (0x3 << 8)
859
+
#define RT5682_PLL2_SRC_SFT 8
860
+
#define RT5682_PLL2_SRC_MCLK (0x0 << 8)
861
+
#define RT5682_PLL2_SRC_BCLK1 (0x1 << 8)
862
+
#define RT5682_PLL2_SRC_SDW (0x2 << 8)
863
+
#define RT5682_PLL2_SRC_RC (0x3 << 8)
864
+
865
+
866
+
867
+
#define RT5682_PLL_INP_MAX 40000000
868
+
#define RT5682_PLL_INP_MIN 256000
869
+
/* PLL M/N/K Code Control 1 (0x0081) */
870
+
#define RT5682_PLL_N_MAX 0x001ff
871
+
#define RT5682_PLL_N_MASK (RT5682_PLL_N_MAX << 7)
872
+
#define RT5682_PLL_N_SFT 7
873
+
#define RT5682_PLL_K_MAX 0x001f
874
+
#define RT5682_PLL_K_MASK (RT5682_PLL_K_MAX)
875
+
#define RT5682_PLL_K_SFT 0
876
+
877
+
/* PLL M/N/K Code Control 2 (0x0082) */
878
+
#define RT5682_PLL_M_MAX 0x00f
879
+
#define RT5682_PLL_M_MASK (RT5682_PLL_M_MAX << 12)
880
+
#define RT5682_PLL_M_SFT 12
881
+
#define RT5682_PLL_M_BP (0x1 << 11)
882
+
#define RT5682_PLL_M_BP_SFT 11
883
+
#define RT5682_PLL_K_BP (0x1 << 10)
884
+
#define RT5682_PLL_K_BP_SFT 10
885
+
#define RT5682_PLL_RST (0x1 << 1)
886
+
887
+
/* PLL tracking mode 1 (0x0083) */
888
+
#define RT5682_DA_ASRC_MASK (0x1 << 13)
889
+
#define RT5682_DA_ASRC_SFT 13
890
+
#define RT5682_DAC_STO1_ASRC_MASK (0x1 << 12)
891
+
#define RT5682_DAC_STO1_ASRC_SFT 12
892
+
#define RT5682_AD_ASRC_MASK (0x1 << 8)
893
+
#define RT5682_AD_ASRC_SFT 8
894
+
#define RT5682_AD_ASRC_SEL_MASK (0x1 << 4)
895
+
#define RT5682_AD_ASRC_SEL_SFT 4
896
+
#define RT5682_DMIC_ASRC_MASK (0x1 << 3)
897
+
#define RT5682_DMIC_ASRC_SFT 3
898
+
#define RT5682_ADC_STO1_ASRC_MASK (0x1 << 2)
899
+
#define RT5682_ADC_STO1_ASRC_SFT 2
900
+
#define RT5682_DA_ASRC_SEL_MASK (0x1 << 0)
901
+
#define RT5682_DA_ASRC_SEL_SFT 0
902
+
903
+
/* PLL tracking mode 2 3 (0x0084)(0x0085)*/
904
+
#define RT5682_FILTER_CLK_SEL_MASK (0x7 << 12)
905
+
#define RT5682_FILTER_CLK_SEL_SFT 12
906
+
#define RT5682_FILTER_CLK_DIV_MASK (0xf << 8)
907
+
#define RT5682_FILTER_CLK_DIV_SFT 8
908
+
909
+
/* ASRC Control 4 (0x0086) */
910
+
#define RT5682_ASRCIN_FTK_N1_MASK (0x3 << 14)
911
+
#define RT5682_ASRCIN_FTK_N1_SFT 14
912
+
#define RT5682_ASRCIN_FTK_N2_MASK (0x3 << 12)
913
+
#define RT5682_ASRCIN_FTK_N2_SFT 12
914
+
#define RT5682_ASRCIN_FTK_M1_MASK (0x7 << 8)
915
+
#define RT5682_ASRCIN_FTK_M1_SFT 8
916
+
#define RT5682_ASRCIN_FTK_M2_MASK (0x7 << 4)
917
+
#define RT5682_ASRCIN_FTK_M2_SFT 4
918
+
919
+
/* SoundWire reference clk (0x008d) */
920
+
#define RT5682_PLL2_OUT_MASK (0x1 << 8)
921
+
#define RT5682_PLL2_OUT_98M (0x0 << 8)
922
+
#define RT5682_PLL2_OUT_49M (0x1 << 8)
923
+
#define RT5682_SDW_REF_2_MASK (0xf << 4)
924
+
#define RT5682_SDW_REF_2_SFT 4
925
+
#define RT5682_SDW_REF_2_48K (0x0 << 4)
926
+
#define RT5682_SDW_REF_2_96K (0x1 << 4)
927
+
#define RT5682_SDW_REF_2_192K (0x2 << 4)
928
+
#define RT5682_SDW_REF_2_32K (0x3 << 4)
929
+
#define RT5682_SDW_REF_2_24K (0x4 << 4)
930
+
#define RT5682_SDW_REF_2_16K (0x5 << 4)
931
+
#define RT5682_SDW_REF_2_12K (0x6 << 4)
932
+
#define RT5682_SDW_REF_2_8K (0x7 << 4)
933
+
#define RT5682_SDW_REF_2_44K (0x8 << 4)
934
+
#define RT5682_SDW_REF_2_88K (0x9 << 4)
935
+
#define RT5682_SDW_REF_2_176K (0xa << 4)
936
+
#define RT5682_SDW_REF_2_353K (0xb << 4)
937
+
#define RT5682_SDW_REF_2_22K (0xc << 4)
938
+
#define RT5682_SDW_REF_2_384K (0xd << 4)
939
+
#define RT5682_SDW_REF_2_11K (0xe << 4)
940
+
#define RT5682_SDW_REF_1_MASK (0xf << 0)
941
+
#define RT5682_SDW_REF_1_SFT 0
942
+
#define RT5682_SDW_REF_1_48K (0x0 << 0)
943
+
#define RT5682_SDW_REF_1_96K (0x1 << 0)
944
+
#define RT5682_SDW_REF_1_192K (0x2 << 0)
945
+
#define RT5682_SDW_REF_1_32K (0x3 << 0)
946
+
#define RT5682_SDW_REF_1_24K (0x4 << 0)
947
+
#define RT5682_SDW_REF_1_16K (0x5 << 0)
948
+
#define RT5682_SDW_REF_1_12K (0x6 << 0)
949
+
#define RT5682_SDW_REF_1_8K (0x7 << 0)
950
+
#define RT5682_SDW_REF_1_44K (0x8 << 0)
951
+
#define RT5682_SDW_REF_1_88K (0x9 << 0)
952
+
#define RT5682_SDW_REF_1_176K (0xa << 0)
953
+
#define RT5682_SDW_REF_1_353K (0xb << 0)
954
+
#define RT5682_SDW_REF_1_22K (0xc << 0)
955
+
#define RT5682_SDW_REF_1_384K (0xd << 0)
956
+
#define RT5682_SDW_REF_1_11K (0xe << 0)
957
+
958
+
/* Depop Mode Control 1 (0x008e) */
959
+
#define RT5682_PUMP_EN (0x1 << 3)
960
+
#define RT5682_PUMP_EN_SFT 3
961
+
#define RT5682_CAPLESS_EN (0x1 << 0)
962
+
#define RT5682_CAPLESS_EN_SFT 0
963
+
964
+
/* Depop Mode Control 2 (0x8f) */
965
+
#define RT5682_RAMP_MASK (0x1 << 12)
966
+
#define RT5682_RAMP_SFT 12
967
+
#define RT5682_RAMP_DIS (0x0 << 12)
968
+
#define RT5682_RAMP_EN (0x1 << 12)
969
+
#define RT5682_BPS_MASK (0x1 << 11)
970
+
#define RT5682_BPS_SFT 11
971
+
#define RT5682_BPS_DIS (0x0 << 11)
972
+
#define RT5682_BPS_EN (0x1 << 11)
973
+
#define RT5682_FAST_UPDN_MASK (0x1 << 10)
974
+
#define RT5682_FAST_UPDN_SFT 10
975
+
#define RT5682_FAST_UPDN_DIS (0x0 << 10)
976
+
#define RT5682_FAST_UPDN_EN (0x1 << 10)
977
+
#define RT5682_VLO_MASK (0x1 << 7)
978
+
#define RT5682_VLO_SFT 7
979
+
#define RT5682_VLO_3V (0x0 << 7)
980
+
#define RT5682_VLO_33V (0x1 << 7)
981
+
982
+
/* HPOUT charge pump 1 (0x0091) */
983
+
#define RT5682_OSW_L_MASK (0x1 << 11)
984
+
#define RT5682_OSW_L_SFT 11
985
+
#define RT5682_OSW_L_DIS (0x0 << 11)
986
+
#define RT5682_OSW_L_EN (0x1 << 11)
987
+
#define RT5682_OSW_R_MASK (0x1 << 10)
988
+
#define RT5682_OSW_R_SFT 10
989
+
#define RT5682_OSW_R_DIS (0x0 << 10)
990
+
#define RT5682_OSW_R_EN (0x1 << 10)
991
+
#define RT5682_PM_HP_MASK (0x3 << 8)
992
+
#define RT5682_PM_HP_SFT 8
993
+
#define RT5682_PM_HP_LV (0x0 << 8)
994
+
#define RT5682_PM_HP_MV (0x1 << 8)
995
+
#define RT5682_PM_HP_HV (0x2 << 8)
996
+
#define RT5682_IB_HP_MASK (0x3 << 6)
997
+
#define RT5682_IB_HP_SFT 6
998
+
#define RT5682_IB_HP_125IL (0x0 << 6)
999
+
#define RT5682_IB_HP_25IL (0x1 << 6)
1000
+
#define RT5682_IB_HP_5IL (0x2 << 6)
1001
+
#define RT5682_IB_HP_1IL (0x3 << 6)
1002
+
1003
+
/* Micbias Control1 (0x93) */
1004
+
#define RT5682_MIC1_OV_MASK (0x3 << 14)
1005
+
#define RT5682_MIC1_OV_SFT 14
1006
+
#define RT5682_MIC1_OV_2V7 (0x0 << 14)
1007
+
#define RT5682_MIC1_OV_2V4 (0x1 << 14)
1008
+
#define RT5682_MIC1_OV_2V25 (0x3 << 14)
1009
+
#define RT5682_MIC1_OV_1V8 (0x4 << 14)
1010
+
#define RT5682_MIC1_CLK_MASK (0x1 << 13)
1011
+
#define RT5682_MIC1_CLK_SFT 13
1012
+
#define RT5682_MIC1_CLK_DIS (0x0 << 13)
1013
+
#define RT5682_MIC1_CLK_EN (0x1 << 13)
1014
+
#define RT5682_MIC1_OVCD_MASK (0x1 << 12)
1015
+
#define RT5682_MIC1_OVCD_SFT 12
1016
+
#define RT5682_MIC1_OVCD_DIS (0x0 << 12)
1017
+
#define RT5682_MIC1_OVCD_EN (0x1 << 12)
1018
+
#define RT5682_MIC1_OVTH_MASK (0x3 << 10)
1019
+
#define RT5682_MIC1_OVTH_SFT 10
1020
+
#define RT5682_MIC1_OVTH_768UA (0x0 << 10)
1021
+
#define RT5682_MIC1_OVTH_960UA (0x1 << 10)
1022
+
#define RT5682_MIC1_OVTH_1152UA (0x2 << 10)
1023
+
#define RT5682_MIC1_OVTH_1960UA (0x3 << 10)
1024
+
#define RT5682_MIC2_OV_MASK (0x3 << 8)
1025
+
#define RT5682_MIC2_OV_SFT 8
1026
+
#define RT5682_MIC2_OV_2V7 (0x0 << 8)
1027
+
#define RT5682_MIC2_OV_2V4 (0x1 << 8)
1028
+
#define RT5682_MIC2_OV_2V25 (0x3 << 8)
1029
+
#define RT5682_MIC2_OV_1V8 (0x4 << 8)
1030
+
#define RT5682_MIC2_CLK_MASK (0x1 << 7)
1031
+
#define RT5682_MIC2_CLK_SFT 7
1032
+
#define RT5682_MIC2_CLK_DIS (0x0 << 7)
1033
+
#define RT5682_MIC2_CLK_EN (0x1 << 7)
1034
+
#define RT5682_MIC2_OVTH_MASK (0x3 << 4)
1035
+
#define RT5682_MIC2_OVTH_SFT 4
1036
+
#define RT5682_MIC2_OVTH_768UA (0x0 << 4)
1037
+
#define RT5682_MIC2_OVTH_960UA (0x1 << 4)
1038
+
#define RT5682_MIC2_OVTH_1152UA (0x2 << 4)
1039
+
#define RT5682_MIC2_OVTH_1960UA (0x3 << 4)
1040
+
#define RT5682_PWR_MB_MASK (0x1 << 3)
1041
+
#define RT5682_PWR_MB_SFT 3
1042
+
#define RT5682_PWR_MB_PD (0x0 << 3)
1043
+
#define RT5682_PWR_MB_PU (0x1 << 3)
1044
+
1045
+
/* Micbias Control2 (0x0094) */
1046
+
#define RT5682_PWR_CLK25M_MASK (0x1 << 9)
1047
+
#define RT5682_PWR_CLK25M_SFT 9
1048
+
#define RT5682_PWR_CLK25M_PD (0x0 << 9)
1049
+
#define RT5682_PWR_CLK25M_PU (0x1 << 9)
1050
+
#define RT5682_PWR_CLK1M_MASK (0x1 << 8)
1051
+
#define RT5682_PWR_CLK1M_SFT 8
1052
+
#define RT5682_PWR_CLK1M_PD (0x0 << 8)
1053
+
#define RT5682_PWR_CLK1M_PU (0x1 << 8)
1054
+
1055
+
/* RC Clock Control (0x009f) */
1056
+
#define RT5682_POW_IRQ (0x1 << 15)
1057
+
#define RT5682_POW_JDH (0x1 << 14)
1058
+
#define RT5682_POW_JDL (0x1 << 13)
1059
+
#define RT5682_POW_ANA (0x1 << 12)
1060
+
1061
+
/* I2S Master Mode Clock Control 1 (0x00a0) */
1062
+
#define RT5682_CLK_SRC_MCLK (0x0)
1063
+
#define RT5682_CLK_SRC_PLL1 (0x1)
1064
+
#define RT5682_CLK_SRC_PLL2 (0x2)
1065
+
#define RT5682_CLK_SRC_SDW (0x3)
1066
+
#define RT5682_CLK_SRC_RCCLK (0x4)
1067
+
#define RT5682_I2S_PD_1 (0x0)
1068
+
#define RT5682_I2S_PD_2 (0x1)
1069
+
#define RT5682_I2S_PD_3 (0x2)
1070
+
#define RT5682_I2S_PD_4 (0x3)
1071
+
#define RT5682_I2S_PD_6 (0x4)
1072
+
#define RT5682_I2S_PD_8 (0x5)
1073
+
#define RT5682_I2S_PD_12 (0x6)
1074
+
#define RT5682_I2S_PD_16 (0x7)
1075
+
#define RT5682_I2S_PD_24 (0x8)
1076
+
#define RT5682_I2S_PD_32 (0x9)
1077
+
#define RT5682_I2S_PD_48 (0xa)
1078
+
#define RT5682_I2S2_SRC_MASK (0x3 << 4)
1079
+
#define RT5682_I2S2_SRC_SFT 4
1080
+
#define RT5682_I2S2_M_PD_MASK (0xf << 0)
1081
+
#define RT5682_I2S2_M_PD_SFT 0
1082
+
1083
+
/* IRQ Control 1 (0x00b6) */
1084
+
#define RT5682_JD1_PULSE_EN_MASK (0x1 << 10)
1085
+
#define RT5682_JD1_PULSE_EN_SFT 10
1086
+
#define RT5682_JD1_PULSE_DIS (0x0 << 10)
1087
+
#define RT5682_JD1_PULSE_EN (0x1 << 10)
1088
+
1089
+
/* IRQ Control 2 (0x00b7) */
1090
+
#define RT5682_JD1_EN_MASK (0x1 << 15)
1091
+
#define RT5682_JD1_EN_SFT 15
1092
+
#define RT5682_JD1_DIS (0x0 << 15)
1093
+
#define RT5682_JD1_EN (0x1 << 15)
1094
+
#define RT5682_JD1_POL_MASK (0x1 << 13)
1095
+
#define RT5682_JD1_POL_NOR (0x0 << 13)
1096
+
#define RT5682_JD1_POL_INV (0x1 << 13)
1097
+
1098
+
/* IRQ Control 3 (0x00b8) */
1099
+
#define RT5682_IL_IRQ_MASK (0x1 << 7)
1100
+
#define RT5682_IL_IRQ_DIS (0x0 << 7)
1101
+
#define RT5682_IL_IRQ_EN (0x1 << 7)
1102
+
1103
+
/* GPIO Control 1 (0x00c0) */
1104
+
#define RT5682_GP1_PIN_MASK (0x3 << 14)
1105
+
#define RT5682_GP1_PIN_SFT 14
1106
+
#define RT5682_GP1_PIN_GPIO1 (0x0 << 14)
1107
+
#define RT5682_GP1_PIN_IRQ (0x1 << 14)
1108
+
#define RT5682_GP1_PIN_DMIC_CLK (0x2 << 14)
1109
+
#define RT5682_GP2_PIN_MASK (0x3 << 12)
1110
+
#define RT5682_GP2_PIN_SFT 12
1111
+
#define RT5682_GP2_PIN_GPIO2 (0x0 << 12)
1112
+
#define RT5682_GP2_PIN_LRCK2 (0x1 << 12)
1113
+
#define RT5682_GP2_PIN_DMIC_SDA (0x2 << 12)
1114
+
#define RT5682_GP3_PIN_MASK (0x3 << 10)
1115
+
#define RT5682_GP3_PIN_SFT 10
1116
+
#define RT5682_GP3_PIN_GPIO3 (0x0 << 10)
1117
+
#define RT5682_GP3_PIN_BCLK2 (0x1 << 10)
1118
+
#define RT5682_GP3_PIN_DMIC_CLK (0x2 << 10)
1119
+
#define RT5682_GP4_PIN_MASK (0x3 << 8)
1120
+
#define RT5682_GP4_PIN_SFT 8
1121
+
#define RT5682_GP4_PIN_GPIO4 (0x0 << 8)
1122
+
#define RT5682_GP4_PIN_ADCDAT1 (0x1 << 8)
1123
+
#define RT5682_GP4_PIN_DMIC_CLK (0x2 << 8)
1124
+
#define RT5682_GP4_PIN_ADCDAT2 (0x3 << 8)
1125
+
#define RT5682_GP5_PIN_MASK (0x3 << 6)
1126
+
#define RT5682_GP5_PIN_SFT 6
1127
+
#define RT5682_GP5_PIN_GPIO5 (0x0 << 6)
1128
+
#define RT5682_GP5_PIN_DACDAT1 (0x1 << 6)
1129
+
#define RT5682_GP5_PIN_DMIC_SDA (0x2 << 6)
1130
+
#define RT5682_GP6_PIN_MASK (0x1 << 5)
1131
+
#define RT5682_GP6_PIN_SFT 5
1132
+
#define RT5682_GP6_PIN_GPIO6 (0x0 << 5)
1133
+
#define RT5682_GP6_PIN_LRCK1 (0x1 << 5)
1134
+
1135
+
/* GPIO Control 2 (0x00c1)*/
1136
+
#define RT5682_GP1_PF_MASK (0x1 << 15)
1137
+
#define RT5682_GP1_PF_IN (0x0 << 15)
1138
+
#define RT5682_GP1_PF_OUT (0x1 << 15)
1139
+
#define RT5682_GP1_OUT_MASK (0x1 << 14)
1140
+
#define RT5682_GP1_OUT_L (0x0 << 14)
1141
+
#define RT5682_GP1_OUT_H (0x1 << 14)
1142
+
#define RT5682_GP2_PF_MASK (0x1 << 13)
1143
+
#define RT5682_GP2_PF_IN (0x0 << 13)
1144
+
#define RT5682_GP2_PF_OUT (0x1 << 13)
1145
+
#define RT5682_GP2_OUT_MASK (0x1 << 12)
1146
+
#define RT5682_GP2_OUT_L (0x0 << 12)
1147
+
#define RT5682_GP2_OUT_H (0x1 << 12)
1148
+
#define RT5682_GP3_PF_MASK (0x1 << 11)
1149
+
#define RT5682_GP3_PF_IN (0x0 << 11)
1150
+
#define RT5682_GP3_PF_OUT (0x1 << 11)
1151
+
#define RT5682_GP3_OUT_MASK (0x1 << 10)
1152
+
#define RT5682_GP3_OUT_L (0x0 << 10)
1153
+
#define RT5682_GP3_OUT_H (0x1 << 10)
1154
+
#define RT5682_GP4_PF_MASK (0x1 << 9)
1155
+
#define RT5682_GP4_PF_IN (0x0 << 9)
1156
+
#define RT5682_GP4_PF_OUT (0x1 << 9)
1157
+
#define RT5682_GP4_OUT_MASK (0x1 << 8)
1158
+
#define RT5682_GP4_OUT_L (0x0 << 8)
1159
+
#define RT5682_GP4_OUT_H (0x1 << 8)
1160
+
#define RT5682_GP5_PF_MASK (0x1 << 7)
1161
+
#define RT5682_GP5_PF_IN (0x0 << 7)
1162
+
#define RT5682_GP5_PF_OUT (0x1 << 7)
1163
+
#define RT5682_GP5_OUT_MASK (0x1 << 6)
1164
+
#define RT5682_GP5_OUT_L (0x0 << 6)
1165
+
#define RT5682_GP5_OUT_H (0x1 << 6)
1166
+
#define RT5682_GP6_PF_MASK (0x1 << 5)
1167
+
#define RT5682_GP6_PF_IN (0x0 << 5)
1168
+
#define RT5682_GP6_PF_OUT (0x1 << 5)
1169
+
#define RT5682_GP6_OUT_MASK (0x1 << 4)
1170
+
#define RT5682_GP6_OUT_L (0x0 << 4)
1171
+
#define RT5682_GP6_OUT_H (0x1 << 4)
1172
+
1173
+
1174
+
/* GPIO Status (0x00c2) */
1175
+
#define RT5682_GP6_STA (0x1 << 6)
1176
+
#define RT5682_GP5_STA (0x1 << 5)
1177
+
#define RT5682_GP4_STA (0x1 << 4)
1178
+
#define RT5682_GP3_STA (0x1 << 3)
1179
+
#define RT5682_GP2_STA (0x1 << 2)
1180
+
#define RT5682_GP1_STA (0x1 << 1)
1181
+
1182
+
/* Soft volume and zero cross control 1 (0x00d9) */
1183
+
#define RT5682_SV_MASK (0x1 << 15)
1184
+
#define RT5682_SV_SFT 15
1185
+
#define RT5682_SV_DIS (0x0 << 15)
1186
+
#define RT5682_SV_EN (0x1 << 15)
1187
+
#define RT5682_ZCD_MASK (0x1 << 10)
1188
+
#define RT5682_ZCD_SFT 10
1189
+
#define RT5682_ZCD_PD (0x0 << 10)
1190
+
#define RT5682_ZCD_PU (0x1 << 10)
1191
+
#define RT5682_SV_DLY_MASK (0xf)
1192
+
#define RT5682_SV_DLY_SFT 0
1193
+
1194
+
/* Soft volume and zero cross control 2 (0x00da) */
1195
+
#define RT5682_ZCD_BST1_CBJ_MASK (0x1 << 7)
1196
+
#define RT5682_ZCD_BST1_CBJ_SFT 7
1197
+
#define RT5682_ZCD_BST1_CBJ_DIS (0x0 << 7)
1198
+
#define RT5682_ZCD_BST1_CBJ_EN (0x1 << 7)
1199
+
#define RT5682_ZCD_RECMIX_MASK (0x1)
1200
+
#define RT5682_ZCD_RECMIX_SFT 0
1201
+
#define RT5682_ZCD_RECMIX_DIS (0x0)
1202
+
#define RT5682_ZCD_RECMIX_EN (0x1)
1203
+
1204
+
/* 4 Button Inline Command Control 2 (0x00e3) */
1205
+
#define RT5682_4BTN_IL_MASK (0x1 << 15)
1206
+
#define RT5682_4BTN_IL_EN (0x1 << 15)
1207
+
#define RT5682_4BTN_IL_DIS (0x0 << 15)
1208
+
#define RT5682_4BTN_IL_RST_MASK (0x1 << 14)
1209
+
#define RT5682_4BTN_IL_NOR (0x1 << 14)
1210
+
#define RT5682_4BTN_IL_RST (0x0 << 14)
1211
+
1212
+
/* Analog JD Control (0x00f0) */
1213
+
#define RT5682_JDH_RS_MASK (0x1 << 4)
1214
+
#define RT5682_JDH_NO_PLUG (0x1 << 4)
1215
+
#define RT5682_JDH_PLUG (0x0 << 4)
1216
+
1217
+
/* Chopper and Clock control for DAC (0x013a)*/
1218
+
#define RT5682_CKXEN_DAC1_MASK (0x1 << 13)
1219
+
#define RT5682_CKXEN_DAC1_SFT 13
1220
+
#define RT5682_CKGEN_DAC1_MASK (0x1 << 12)
1221
+
#define RT5682_CKGEN_DAC1_SFT 12
1222
+
1223
+
/* Chopper and Clock control for ADC (0x013b)*/
1224
+
#define RT5682_CKXEN_ADC1_MASK (0x1 << 13)
1225
+
#define RT5682_CKXEN_ADC1_SFT 13
1226
+
#define RT5682_CKGEN_ADC1_MASK (0x1 << 12)
1227
+
#define RT5682_CKGEN_ADC1_SFT 12
1228
+
1229
+
/* Volume test (0x013f)*/
1230
+
#define RT5682_SEL_CLK_VOL_MASK (0x1 << 15)
1231
+
#define RT5682_SEL_CLK_VOL_EN (0x1 << 15)
1232
+
#define RT5682_SEL_CLK_VOL_DIS (0x0 << 15)
1233
+
1234
+
/* Test Mode Control 1 (0x0145) */
1235
+
#define RT5682_AD2DA_LB_MASK (0x1 << 10)
1236
+
#define RT5682_AD2DA_LB_SFT 10
1237
+
1238
+
/* Stereo Noise Gate Control 1 (0x0160) */
1239
+
#define RT5682_NG2_EN_MASK (0x1 << 15)
1240
+
#define RT5682_NG2_EN (0x1 << 15)
1241
+
#define RT5682_NG2_DIS (0x0 << 15)
1242
+
1243
+
/* Stereo1 DAC Silence Detection Control (0x0190) */
1244
+
#define RT5682_DEB_STO_DAC_MASK (0x7 << 4)
1245
+
#define RT5682_DEB_80_MS (0x0 << 4)
1246
+
1247
+
/* SAR ADC Inline Command Control 1 (0x0210) */
1248
+
#define RT5682_SAR_BUTT_DET_MASK (0x1 << 15)
1249
+
#define RT5682_SAR_BUTT_DET_EN (0x1 << 15)
1250
+
#define RT5682_SAR_BUTT_DET_DIS (0x0 << 15)
1251
+
#define RT5682_SAR_BUTDET_MODE_MASK (0x1 << 14)
1252
+
#define RT5682_SAR_BUTDET_POW_SAV (0x1 << 14)
1253
+
#define RT5682_SAR_BUTDET_POW_NORM (0x0 << 14)
1254
+
#define RT5682_SAR_BUTDET_RST_MASK (0x1 << 13)
1255
+
#define RT5682_SAR_BUTDET_RST_NORMAL (0x1 << 13)
1256
+
#define RT5682_SAR_BUTDET_RST (0x0 << 13)
1257
+
#define RT5682_SAR_POW_MASK (0x1 << 12)
1258
+
#define RT5682_SAR_POW_EN (0x1 << 12)
1259
+
#define RT5682_SAR_POW_DIS (0x0 << 12)
1260
+
#define RT5682_SAR_RST_MASK (0x1 << 11)
1261
+
#define RT5682_SAR_RST_NORMAL (0x1 << 11)
1262
+
#define RT5682_SAR_RST (0x0 << 11)
1263
+
#define RT5682_SAR_BYPASS_MASK (0x1 << 10)
1264
+
#define RT5682_SAR_BYPASS_EN (0x1 << 10)
1265
+
#define RT5682_SAR_BYPASS_DIS (0x0 << 10)
1266
+
#define RT5682_SAR_SEL_MB1_MASK (0x1 << 9)
1267
+
#define RT5682_SAR_SEL_MB1_SEL (0x1 << 9)
1268
+
#define RT5682_SAR_SEL_MB1_NOSEL (0x0 << 9)
1269
+
#define RT5682_SAR_SEL_MB2_MASK (0x1 << 8)
1270
+
#define RT5682_SAR_SEL_MB2_SEL (0x1 << 8)
1271
+
#define RT5682_SAR_SEL_MB2_NOSEL (0x0 << 8)
1272
+
#define RT5682_SAR_SEL_MODE_MASK (0x1 << 7)
1273
+
#define RT5682_SAR_SEL_MODE_CMP (0x1 << 7)
1274
+
#define RT5682_SAR_SEL_MODE_ADC (0x0 << 7)
1275
+
#define RT5682_SAR_SEL_MB1_MB2_MASK (0x1 << 5)
1276
+
#define RT5682_SAR_SEL_MB1_MB2_AUTO (0x1 << 5)
1277
+
#define RT5682_SAR_SEL_MB1_MB2_MANU (0x0 << 5)
1278
+
#define RT5682_SAR_SEL_SIGNAL_MASK (0x1 << 4)
1279
+
#define RT5682_SAR_SEL_SIGNAL_AUTO (0x1 << 4)
1280
+
#define RT5682_SAR_SEL_SIGNAL_MANU (0x0 << 4)
1281
+
1282
+
/* SAR ADC Inline Command Control 13 (0x021c) */
1283
+
#define RT5682_SAR_SOUR_MASK (0x3f)
1284
+
#define RT5682_SAR_SOUR_BTN (0x3f)
1285
+
#define RT5682_SAR_SOUR_TYPE (0x0)
1286
+
1287
+
1288
+
/* System Clock Source */
1289
+
enum {
1290
+
RT5682_SCLK_S_MCLK,
1291
+
RT5682_SCLK_S_PLL1,
1292
+
RT5682_SCLK_S_PLL2,
1293
+
RT5682_SCLK_S_RCCLK,
1294
+
};
1295
+
1296
+
/* PLL Source */
1297
+
enum {
1298
+
RT5682_PLL1_S_MCLK,
1299
+
RT5682_PLL1_S_BCLK1,
1300
+
RT5682_PLL1_S_RCCLK,
1301
+
};
1302
+
1303
+
enum {
1304
+
RT5682_AIF1,
1305
+
RT5682_AIF2,
1306
+
RT5682_AIFS
1307
+
};
1308
+
1309
+
/* filter mask */
1310
+
enum {
1311
+
RT5682_DA_STEREO1_FILTER = 0x1,
1312
+
RT5682_AD_STEREO1_FILTER = (0x1 << 1),
1313
+
};
1314
+
1315
+
enum {
1316
+
RT5682_CLK_SEL_SYS,
1317
+
RT5682_CLK_SEL_I2S1_ASRC,
1318
+
RT5682_CLK_SEL_I2S2_ASRC,
1319
+
};
1320
+
1321
+
int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
1322
+
unsigned int filter_mask, unsigned int clk_src);
1323
+
1324
+
#endif /* __RT5682_H__ */