tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (23 commits)
genirq: Expand generic show_interrupts()
gpio: Fold irq_set_chip/irq_set_handler to irq_set_chip_and_handler
gpio: Cleanup genirq namespace
arm: ep93xx: Add basic interrupt info
arm/gpio: Remove three copies of broken and racy debug code
xtensa: Use generic show_interrupts()
xtensa: Convert genirq namespace
xtensa: Use generic IRQ Kconfig and set GENERIC_HARDIRQS_NO_DEPRECATED
xtensa: Convert s6000 gpio irq_chip to new functions
xtensa: Convert main irq_chip to new functions
um: Use generic show_interrupts()
um: Convert genirq namespace
m32r: Use generic show_interrupts()
m32r: Convert genirq namespace
h8300: Use generic show_interrupts()
h8300: Convert genirq namespace
avr32: Cleanup eic_set_irq_type()
avr32: Use generic show_interrupts()
avr: Cleanup genirq namespace
avr32: Use generic IRQ config, enable GENERIC_HARDIRQS_NO_DEPRECATED
...

Fix up trivial conflict in drivers/gpio/timbgpio.c

Linus Torvalds 0dd61be7 8dd90265

+283 -602
unified split
+4 -42
arch/arm/mach-ep93xx/gpio.c
··· 360 360 gpio = ep93xx_chip->chip.base; 361 361 for (i = 0; i < chip->ngpio; i++, gpio++) { 362 362 int is_out = data_dir_reg & (1 << i); 363 + int irq = gpio_to_irq(gpio); 363 364 364 - seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s", 365 + seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s %s\n", 365 366 chip->label, i, gpio, 366 367 gpiochip_is_requested(chip, i) ? : "", 367 368 is_out ? "out" : "in ", 368 - (data_reg & (1 << i)) ? "hi" : "lo"); 369 - 370 - if (!is_out) { 371 - int irq = gpio_to_irq(gpio); 372 - struct irq_desc *desc = irq_desc + irq; 373 - 374 - if (irq >= 0 && desc->action) { 375 - char *trigger; 376 - 377 - switch (desc->status & IRQ_TYPE_SENSE_MASK) { 378 - case IRQ_TYPE_NONE: 379 - trigger = "(default)"; 380 - break; 381 - case IRQ_TYPE_EDGE_FALLING: 382 - trigger = "edge-falling"; 383 - break; 384 - case IRQ_TYPE_EDGE_RISING: 385 - trigger = "edge-rising"; 386 - break; 387 - case IRQ_TYPE_EDGE_BOTH: 388 - trigger = "edge-both"; 389 - break; 390 - case IRQ_TYPE_LEVEL_HIGH: 391 - trigger = "level-high"; 392 - break; 393 - case IRQ_TYPE_LEVEL_LOW: 394 - trigger = "level-low"; 395 - break; 396 - default: 397 - trigger = "?trigger?"; 398 - break; 399 - } 400 - 401 - seq_printf(s, " irq-%d %s%s", 402 - irq, trigger, 403 - (desc->status & IRQ_WAKEUP) 404 - ? " wakeup" : ""); 405 - } 406 - } 407 - 408 - seq_printf(s, "\n"); 369 + (data_reg & (1<< i)) ? "hi" : "lo", 370 + (!is_out && irq>= 0) ? "(interrupt)" : ""); 409 371 } 410 372 } 411 373
-45
arch/arm/plat-nomadik/gpio.c
··· 832 832 : "? ", 833 833 (mode < 0) ? "unknown" : modes[mode], 834 834 pull ? "pull" : "none"); 835 - 836 - if (!is_out) { 837 - int irq = gpio_to_irq(gpio); 838 - struct irq_desc *desc = irq_to_desc(irq); 839 - 840 - /* This races with request_irq(), set_irq_type(), 841 - * and set_irq_wake() ... but those are "rare". 842 - * 843 - * More significantly, trigger type flags aren't 844 - * currently maintained by genirq. 845 - */ 846 - if (irq >= 0 && desc->action) { 847 - char *trigger; 848 - 849 - switch (desc->status & IRQ_TYPE_SENSE_MASK) { 850 - case IRQ_TYPE_NONE: 851 - trigger = "(default)"; 852 - break; 853 - case IRQ_TYPE_EDGE_FALLING: 854 - trigger = "edge-falling"; 855 - break; 856 - case IRQ_TYPE_EDGE_RISING: 857 - trigger = "edge-rising"; 858 - break; 859 - case IRQ_TYPE_EDGE_BOTH: 860 - trigger = "edge-both"; 861 - break; 862 - case IRQ_TYPE_LEVEL_HIGH: 863 - trigger = "level-high"; 864 - break; 865 - case IRQ_TYPE_LEVEL_LOW: 866 - trigger = "level-low"; 867 - break; 868 - default: 869 - trigger = "?trigger?"; 870 - break; 871 - } 872 - 873 - seq_printf(s, " irq-%d %s%s", 874 - irq, trigger, 875 - (desc->status & IRQ_WAKEUP) 876 - ? " wakeup" : ""); 877 - } 878 - } 879 - 880 835 seq_printf(s, "\n"); 881 836 } 882 837 }
+5 -9
arch/avr32/Kconfig
··· 6 6 select HAVE_CLK 7 7 select HAVE_OPROFILE 8 8 select HAVE_KPROBES 9 + select HAVE_GENERIC_HARDIRQS 10 + select GENERIC_IRQ_PROBE 11 + select HARDIRQS_SW_RESEND 12 + select GENERIC_IRQ_SHOW 13 + select GENERIC_HARDIRQS_NO_DEPRECATED 9 14 help 10 15 AVR32 is a high-performance 32-bit RISC microprocessor core, 11 16 designed for cost-sensitive embedded applications, with particular ··· 22 17 config GENERIC_GPIO 23 18 def_bool y 24 19 25 - config GENERIC_HARDIRQS 26 - def_bool y 27 - 28 20 config STACKTRACE_SUPPORT 29 21 def_bool y 30 22 ··· 29 27 def_bool y 30 28 31 29 config TRACE_IRQFLAGS_SUPPORT 32 - def_bool y 33 - 34 - config HARDIRQS_SW_RESEND 35 - def_bool y 36 - 37 - config GENERIC_IRQ_PROBE 38 30 def_bool y 39 31 40 32 config RWSEM_GENERIC_SPINLOCK
+1 -1
arch/avr32/boards/atngw100/mrmt.c
··· 301 301 /* Select the Touchscreen interrupt pin mode */ 302 302 at32_select_periph( GPIO_PIOB_BASE, 1 << (PB_EXTINT_BASE+TS_IRQ), 303 303 GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH); 304 - set_irq_type( AT32_EXTINT(TS_IRQ), IRQ_TYPE_EDGE_FALLING ); 304 + irq_set_irq_type(AT32_EXTINT(TS_IRQ), IRQ_TYPE_EDGE_FALLING); 305 305 at32_spi_setup_slaves(0,spi01_board_info,ARRAY_SIZE(spi01_board_info)); 306 306 spi_register_board_info(spi01_board_info,ARRAY_SIZE(spi01_board_info)); 307 307 #endif
+1 -1
arch/avr32/boards/atngw100/setup.c
··· 322 322 /* set_irq_type() after the arch_initcall for EIC has run, and 323 323 * before the I2C subsystem could try using this IRQ. 324 324 */ 325 - return set_irq_type(AT32_EXTINT(3), IRQ_TYPE_EDGE_FALLING); 325 + return irq_set_irq_type(AT32_EXTINT(3), IRQ_TYPE_EDGE_FALLING); 326 326 } 327 327 arch_initcall(atngw100_arch_init);
-37
arch/avr32/kernel/irq.c
··· 26 26 { 27 27 28 28 } 29 - 30 - #ifdef CONFIG_PROC_FS 31 - int show_interrupts(struct seq_file *p, void *v) 32 - { 33 - int i = *(loff_t *)v, cpu; 34 - struct irqaction *action; 35 - unsigned long flags; 36 - 37 - if (i == 0) { 38 - seq_puts(p, " "); 39 - for_each_online_cpu(cpu) 40 - seq_printf(p, "CPU%d ", cpu); 41 - seq_putc(p, '\n'); 42 - } 43 - 44 - if (i < NR_IRQS) { 45 - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); 46 - action = irq_desc[i].action; 47 - if (!action) 48 - goto unlock; 49 - 50 - seq_printf(p, "%3d: ", i); 51 - for_each_online_cpu(cpu) 52 - seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); 53 - seq_printf(p, " %8s", irq_desc[i].chip->name ? : "-"); 54 - seq_printf(p, " %s", action->name); 55 - for (action = action->next; action; action = action->next) 56 - seq_printf(p, ", %s", action->name); 57 - 58 - seq_putc(p, '\n'); 59 - unlock: 60 - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); 61 - } 62 - 63 - return 0; 64 - } 65 - #endif
+36 -44
arch/avr32/mach-at32ap/extint.c
··· 61 61 static struct eic *nmi_eic; 62 62 static bool nmi_enabled; 63 63 64 - static void eic_ack_irq(unsigned int irq) 64 + static void eic_ack_irq(struct irq_chip *d) 65 65 { 66 - struct eic *eic = get_irq_chip_data(irq); 67 - eic_writel(eic, ICR, 1 << (irq - eic->first_irq)); 66 + struct eic *eic = irq_data_get_irq_chip_data(data); 67 + eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq)); 68 68 } 69 69 70 - static void eic_mask_irq(unsigned int irq) 70 + static void eic_mask_irq(struct irq_chip *d) 71 71 { 72 - struct eic *eic = get_irq_chip_data(irq); 73 - eic_writel(eic, IDR, 1 << (irq - eic->first_irq)); 72 + struct eic *eic = irq_data_get_irq_chip_data(data); 73 + eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq)); 74 74 } 75 75 76 - static void eic_mask_ack_irq(unsigned int irq) 76 + static void eic_mask_ack_irq(struct irq_chip *d) 77 77 { 78 - struct eic *eic = get_irq_chip_data(irq); 79 - eic_writel(eic, ICR, 1 << (irq - eic->first_irq)); 80 - eic_writel(eic, IDR, 1 << (irq - eic->first_irq)); 78 + struct eic *eic = irq_data_get_irq_chip_data(data); 79 + eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq)); 80 + eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq)); 81 81 } 82 82 83 - static void eic_unmask_irq(unsigned int irq) 83 + static void eic_unmask_irq(struct irq_chip *d) 84 84 { 85 - struct eic *eic = get_irq_chip_data(irq); 86 - eic_writel(eic, IER, 1 << (irq - eic->first_irq)); 85 + struct eic *eic = irq_data_get_irq_chip_data(data); 86 + eic_writel(eic, IER, 1 << (d->irq - eic->first_irq)); 87 87 } 88 88 89 - static int eic_set_irq_type(unsigned int irq, unsigned int flow_type) 89 + static int eic_set_irq_type(struct irq_chip *d, unsigned int flow_type) 90 90 { 91 - struct eic *eic = get_irq_chip_data(irq); 92 - struct irq_desc *desc; 91 + struct eic *eic = irq_data_get_irq_chip_data(data); 92 + unsigned int irq = d->irq; 93 93 unsigned int i = irq - eic->first_irq; 94 94 u32 mode, edge, level; 95 - int ret = 0; 96 95 97 96 flow_type &= IRQ_TYPE_SENSE_MASK; 98 97 if (flow_type == IRQ_TYPE_NONE) 99 98 flow_type = IRQ_TYPE_LEVEL_LOW; 100 - 101 - desc = &irq_desc[irq]; 102 99 103 100 mode = eic_readl(eic, MODE); 104 101 edge = eic_readl(eic, EDGE); ··· 119 122 edge &= ~(1 << i); 120 123 break; 121 124 default: 122 - ret = -EINVAL; 123 - break; 125 + return -EINVAL; 124 126 } 125 127 126 - if (ret == 0) { 127 - eic_writel(eic, MODE, mode); 128 - eic_writel(eic, EDGE, edge); 129 - eic_writel(eic, LEVEL, level); 128 + eic_writel(eic, MODE, mode); 129 + eic_writel(eic, EDGE, edge); 130 + eic_writel(eic, LEVEL, level); 130 131 131 - if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) { 132 - flow_type |= IRQ_LEVEL; 133 - __set_irq_handler_unlocked(irq, handle_level_irq); 134 - } else 135 - __set_irq_handler_unlocked(irq, handle_edge_irq); 136 - desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 137 - desc->status |= flow_type; 138 - } 132 + irqd_set_trigger_type(d, flow_type); 133 + if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 134 + __irq_set_handler_locked(irq, handle_level_irq); 135 + else 136 + __irq_set_handler_locked(irq, handle_edge_irq); 139 137 140 - return ret; 138 + return IRQ_SET_MASK_OK_NOCOPY; 141 139 } 142 140 143 141 static struct irq_chip eic_chip = { 144 142 .name = "eic", 145 - .ack = eic_ack_irq, 146 - .mask = eic_mask_irq, 147 - .mask_ack = eic_mask_ack_irq, 148 - .unmask = eic_unmask_irq, 149 - .set_type = eic_set_irq_type, 143 + .irq_ack = eic_ack_irq, 144 + .irq_mask = eic_mask_irq, 145 + .irq_mask_ack = eic_mask_ack_irq, 146 + .irq_unmask = eic_unmask_irq, 147 + .irq_set_type = eic_set_irq_type, 150 148 }; 151 149 152 150 static void demux_eic_irq(unsigned int irq, struct irq_desc *desc) 153 151 { 154 - struct eic *eic = desc->handler_data; 152 + struct eic *eic = irq_desc_get_handler_data(desc); 155 153 unsigned long status, pending; 156 154 unsigned int i; 157 155 ··· 226 234 eic->chip = &eic_chip; 227 235 228 236 for (i = 0; i < nr_of_irqs; i++) { 229 - set_irq_chip_and_handler(eic->first_irq + i, &eic_chip, 237 + irq_set_chip_and_handler(eic->first_irq + i, &eic_chip, 230 238 handle_level_irq); 231 - set_irq_chip_data(eic->first_irq + i, eic); 239 + irq_set_chip_data(eic->first_irq + i, eic); 232 240 } 233 241 234 - set_irq_chained_handler(int_irq, demux_eic_irq); 235 - set_irq_data(int_irq, eic); 242 + irq_set_chained_handler(int_irq, demux_eic_irq); 243 + irq_set_handler_data(int_irq, eic); 236 244 237 245 if (pdev->id == 0) { 238 246 nmi_eic = eic;
+6 -8
arch/avr32/mach-at32ap/intc.c
··· 34 34 * TODO: We may be able to implement mask/unmask by setting IxM flags 35 35 * in the status register. 36 36 */ 37 - static void intc_mask_irq(unsigned int irq) 37 + static void intc_mask_irq(struct irq_data *d) 38 38 { 39 39 40 40 } 41 41 42 - static void intc_unmask_irq(unsigned int irq) 42 + static void intc_unmask_irq(struct irq_data *d) 43 43 { 44 44 45 45 } ··· 47 47 static struct intc intc0 = { 48 48 .chip = { 49 49 .name = "intc", 50 - .mask = intc_mask_irq, 51 - .unmask = intc_unmask_irq, 50 + .irq_mask = intc_mask_irq, 51 + .irq_unmask = intc_unmask_irq, 52 52 }, 53 53 }; 54 54 ··· 57 57 */ 58 58 asmlinkage void do_IRQ(int level, struct pt_regs *regs) 59 59 { 60 - struct irq_desc *desc; 61 60 struct pt_regs *old_regs; 62 61 unsigned int irq; 63 62 unsigned long status_reg; ··· 68 69 irq_enter(); 69 70 70 71 irq = intc_readl(&intc0, INTCAUSE0 - 4 * level); 71 - desc = irq_desc + irq; 72 - desc->handle_irq(irq, desc); 72 + generic_handle_irq(irq); 73 73 74 74 /* 75 75 * Clear all interrupt level masks so that we may handle ··· 126 128 intc_writel(&intc0, INTPR0 + 4 * i, offset); 127 129 readback = intc_readl(&intc0, INTPR0 + 4 * i); 128 130 if (readback == offset) 129 - set_irq_chip_and_handler(i, &intc0.chip, 131 + irq_set_chip_and_handler(i, &intc0.chip, 130 132 handle_simple_irq); 131 133 } 132 134
+17 -20
arch/avr32/mach-at32ap/pio.c
··· 249 249 250 250 /* GPIO IRQ support */ 251 251 252 - static void gpio_irq_mask(unsigned irq) 252 + static void gpio_irq_mask(struct irq_data *d) 253 253 { 254 - unsigned gpio = irq_to_gpio(irq); 254 + unsigned gpio = irq_to_gpio(d->irq); 255 255 struct pio_device *pio = &pio_dev[gpio >> 5]; 256 256 257 257 pio_writel(pio, IDR, 1 << (gpio & 0x1f)); 258 258 } 259 259 260 - static void gpio_irq_unmask(unsigned irq) 260 + static void gpio_irq_unmask(struct irq_data *d)) 261 261 { 262 - unsigned gpio = irq_to_gpio(irq); 262 + unsigned gpio = irq_to_gpio(d->irq); 263 263 struct pio_device *pio = &pio_dev[gpio >> 5]; 264 264 265 265 pio_writel(pio, IER, 1 << (gpio & 0x1f)); 266 266 } 267 267 268 - static int gpio_irq_type(unsigned irq, unsigned type) 268 + static int gpio_irq_type(struct irq_data *d, unsigned type) 269 269 { 270 270 if (type != IRQ_TYPE_EDGE_BOTH && type != IRQ_TYPE_NONE) 271 271 return -EINVAL; ··· 275 275 276 276 static struct irq_chip gpio_irqchip = { 277 277 .name = "gpio", 278 - .mask = gpio_irq_mask, 279 - .unmask = gpio_irq_unmask, 280 - .set_type = gpio_irq_type, 278 + .irq_mask = gpio_irq_mask, 279 + .irq_unmask = gpio_irq_unmask, 280 + .irq_set_type = gpio_irq_type, 281 281 }; 282 282 283 283 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 284 284 { 285 - struct pio_device *pio = get_irq_chip_data(irq); 285 + struct pio_device *pio = get_irq_desc_chip_data(desc); 286 286 unsigned gpio_irq; 287 287 288 - gpio_irq = (unsigned) get_irq_data(irq); 288 + gpio_irq = (unsigned) irq_get_handler_data(irq); 289 289 for (;;) { 290 290 u32 isr; 291 - struct irq_desc *d; 292 291 293 292 /* ack pending GPIO interrupts */ 294 293 isr = pio_readl(pio, ISR) & pio_readl(pio, IMR); ··· 300 301 isr &= ~(1 << i); 301 302 302 303 i += gpio_irq; 303 - d = &irq_desc[i]; 304 - 305 - d->handle_irq(i, d); 304 + generic_handle_irq(i); 306 305 } while (isr); 307 306 } 308 307 } ··· 310 313 { 311 314 unsigned i; 312 315 313 - set_irq_chip_data(irq, pio); 314 - set_irq_data(irq, (void *) gpio_irq); 316 + irq_set_chip_data(irq, pio); 317 + irq_set_handler_data(irq, (void *)gpio_irq); 315 318 316 319 for (i = 0; i < 32; i++, gpio_irq++) { 317 - set_irq_chip_data(gpio_irq, pio); 318 - set_irq_chip_and_handler(gpio_irq, &gpio_irqchip, 319 - handle_simple_irq); 320 + irq_set_chip_data(gpio_irq, pio); 321 + irq_set_chip_and_handler(gpio_irq, &gpio_irqchip, 322 + handle_simple_irq); 320 323 } 321 324 322 - set_irq_chained_handler(irq, gpio_irq_handler); 325 + irq_set_chained_handler(irq, gpio_irq_handler); 323 326 } 324 327 325 328 /*--------------------------------------------------------------------------*/
+1
arch/h8300/Kconfig
··· 4 4 select HAVE_IDE 5 5 select HAVE_GENERIC_HARDIRQS 6 6 select GENERIC_HARDIRQS_NO_DEPRECATED 7 + select GENERIC_IRQ_SHOW 7 8 8 9 config SYMBOL_PREFIX 9 10 string
+1 -32
arch/h8300/kernel/irq.c
··· 155 155 setup_vector(); 156 156 157 157 for (c = 0; c < NR_IRQS; c++) 158 - set_irq_chip_and_handler(c, &h8300irq_chip, handle_simple_irq); 158 + irq_set_chip_and_handler(c, &h8300irq_chip, handle_simple_irq); 159 159 } 160 160 161 161 asmlinkage void do_IRQ(int irq) ··· 164 164 generic_handle_irq(irq); 165 165 irq_exit(); 166 166 } 167 - 168 - #if defined(CONFIG_PROC_FS) 169 - int show_interrupts(struct seq_file *p, void *v) 170 - { 171 - int i = *(loff_t *) v; 172 - struct irqaction * action; 173 - unsigned long flags; 174 - 175 - if (i == 0) 176 - seq_puts(p, " CPU0"); 177 - 178 - if (i < NR_IRQS) { 179 - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); 180 - action = irq_desc[i].action; 181 - if (!action) 182 - goto unlock; 183 - seq_printf(p, "%3d: ",i); 184 - seq_printf(p, "%10u ", kstat_irqs(i)); 185 - seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name); 186 - seq_printf(p, "-%-8s", irq_desc[i].name); 187 - seq_printf(p, " %s", action->name); 188 - 189 - for (action=action->next; action; action = action->next) 190 - seq_printf(p, ", %s", action->name); 191 - seq_putc(p, '\n'); 192 - unlock: 193 - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); 194 - } 195 - return 0; 196 - } 197 - #endif
+1
arch/m32r/Kconfig
··· 10 10 select HAVE_GENERIC_HARDIRQS 11 11 select GENERIC_HARDIRQS_NO_DEPRECATED 12 12 select GENERIC_IRQ_PROBE 13 + select GENERIC_IRQ_SHOW 13 14 14 15 config SBUS 15 16 bool
-45
arch/m32r/kernel/irq.c
··· 18 18 19 19 #include <linux/kernel_stat.h> 20 20 #include <linux/interrupt.h> 21 - #include <linux/seq_file.h> 22 21 #include <linux/module.h> 23 22 #include <asm/uaccess.h> 24 - 25 - /* 26 - * Generic, controller-independent functions: 27 - */ 28 - 29 - int show_interrupts(struct seq_file *p, void *v) 30 - { 31 - int i = *(loff_t *) v, j; 32 - struct irqaction * action; 33 - unsigned long flags; 34 - 35 - if (i == 0) { 36 - seq_printf(p, " "); 37 - for_each_online_cpu(j) 38 - seq_printf(p, "CPU%d ",j); 39 - seq_putc(p, '\n'); 40 - } 41 - 42 - if (i < NR_IRQS) { 43 - struct irq_desc *desc = irq_to_desc(i); 44 - 45 - raw_spin_lock_irqsave(&desc->lock, flags); 46 - action = desc->action; 47 - if (!action) 48 - goto skip; 49 - seq_printf(p, "%3d: ",i); 50 - #ifndef CONFIG_SMP 51 - seq_printf(p, "%10u ", kstat_irqs(i)); 52 - #else 53 - for_each_online_cpu(j) 54 - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); 55 - #endif 56 - seq_printf(p, " %14s", desc->irq_data.chip->name); 57 - seq_printf(p, " %s", action->name); 58 - 59 - for (action=action->next; action; action = action->next) 60 - seq_printf(p, ", %s", action->name); 61 - 62 - seq_putc(p, '\n'); 63 - skip: 64 - raw_spin_unlock_irqrestore(&desc->lock, flags); 65 - } 66 - return 0; 67 - } 68 23 69 24 /* 70 25 * do_IRQ handles all normal device IRQs (the special
+4 -4
arch/m32r/platforms/m32104ut/setup.c
··· 76 76 77 77 #if defined(CONFIG_SMC91X) 78 78 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ 79 - set_irq_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type, 79 + irq_set_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type, 80 80 handle_level_irq); 81 81 /* "H" level sense */ 82 82 cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; ··· 84 84 #endif /* CONFIG_SMC91X */ 85 85 86 86 /* MFT2 : system timer */ 87 - set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type, 87 + irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type, 88 88 handle_level_irq); 89 89 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 90 90 disable_m32104ut_irq(M32R_IRQ_MFT2); 91 91 92 92 #ifdef CONFIG_SERIAL_M32R_SIO 93 93 /* SIO0_R : uart receive data */ 94 - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type, 94 + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type, 95 95 handle_level_irq); 96 96 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; 97 97 disable_m32104ut_irq(M32R_IRQ_SIO0_R); 98 98 99 99 /* SIO0_S : uart send data */ 100 - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type, 100 + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type, 101 101 handle_level_irq); 102 102 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; 103 103 disable_m32104ut_irq(M32R_IRQ_SIO0_S);
+14 -14
arch/m32r/platforms/m32700ut/setup.c
··· 259 259 { 260 260 #if defined(CONFIG_SMC91X) 261 261 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ 262 - set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN, 262 + irq_set_chip_and_handler(M32700UT_LAN_IRQ_LAN, 263 263 &m32700ut_lanpld_irq_type, handle_level_irq); 264 264 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ 265 265 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN); 266 266 #endif /* CONFIG_SMC91X */ 267 267 268 268 /* MFT2 : system timer */ 269 - set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type, 269 + irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type, 270 270 handle_level_irq); 271 271 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 272 272 disable_m32700ut_irq(M32R_IRQ_MFT2); 273 273 274 274 /* SIO0 : receive */ 275 - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type, 275 + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type, 276 276 handle_level_irq); 277 277 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 278 278 disable_m32700ut_irq(M32R_IRQ_SIO0_R); 279 279 280 280 /* SIO0 : send */ 281 - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type, 281 + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type, 282 282 handle_level_irq); 283 283 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 284 284 disable_m32700ut_irq(M32R_IRQ_SIO0_S); 285 285 286 286 /* SIO1 : receive */ 287 - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type, 287 + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type, 288 288 handle_level_irq); 289 289 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 290 290 disable_m32700ut_irq(M32R_IRQ_SIO1_R); 291 291 292 292 /* SIO1 : send */ 293 - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type, 293 + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type, 294 294 handle_level_irq); 295 295 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 296 296 disable_m32700ut_irq(M32R_IRQ_SIO1_S); 297 297 298 298 /* DMA1 : */ 299 - set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type, 299 + irq_set_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type, 300 300 handle_level_irq); 301 301 icu_data[M32R_IRQ_DMA1].icucr = 0; 302 302 disable_m32700ut_irq(M32R_IRQ_DMA1); 303 303 304 304 #ifdef CONFIG_SERIAL_M32R_PLDSIO 305 305 /* INT#1: SIO0 Receive on PLD */ 306 - set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type, 306 + irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type, 307 307 handle_level_irq); 308 308 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 309 309 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); 310 310 311 311 /* INT#1: SIO0 Send on PLD */ 312 - set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type, 312 + irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type, 313 313 handle_level_irq); 314 314 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 315 315 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); 316 316 #endif /* CONFIG_SERIAL_M32R_PLDSIO */ 317 317 318 318 /* INT#1: CFC IREQ on PLD */ 319 - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type, 319 + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type, 320 320 handle_level_irq); 321 321 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 322 322 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); 323 323 324 324 /* INT#1: CFC Insert on PLD */ 325 - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type, 325 + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type, 326 326 handle_level_irq); 327 327 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 328 328 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); 329 329 330 330 /* INT#1: CFC Eject on PLD */ 331 - set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type, 331 + irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type, 332 332 handle_level_irq); 333 333 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 334 334 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); ··· 349 349 350 350 #if defined(CONFIG_USB) 351 351 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ 352 - set_irq_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1, 352 + irq_set_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1, 353 353 &m32700ut_lcdpld_irq_type, handle_level_irq); 354 354 355 355 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ ··· 366 366 /* 367 367 * INT3# is used for AR 368 368 */ 369 - set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type, 369 + irq_set_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type, 370 370 handle_level_irq); 371 371 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 372 372 disable_m32700ut_irq(M32R_IRQ_INT3);
+8 -8
arch/m32r/platforms/mappi/setup.c
··· 75 75 76 76 #ifdef CONFIG_NE2000 77 77 /* INT0 : LAN controller (RTL8019AS) */ 78 - set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, 78 + irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, 79 79 handle_level_irq); 80 80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; 81 81 disable_mappi_irq(M32R_IRQ_INT0); 82 82 #endif /* CONFIG_M32R_NE2000 */ 83 83 84 84 /* MFT2 : system timer */ 85 - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, 85 + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, 86 86 handle_level_irq); 87 87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 88 88 disable_mappi_irq(M32R_IRQ_MFT2); 89 89 90 90 #ifdef CONFIG_SERIAL_M32R_SIO 91 91 /* SIO0_R : uart receive data */ 92 - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, 92 + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, 93 93 handle_level_irq); 94 94 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 95 95 disable_mappi_irq(M32R_IRQ_SIO0_R); 96 96 97 97 /* SIO0_S : uart send data */ 98 - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, 98 + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, 99 99 handle_level_irq); 100 100 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 101 101 disable_mappi_irq(M32R_IRQ_SIO0_S); 102 102 103 103 /* SIO1_R : uart receive data */ 104 - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, 104 + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, 105 105 handle_level_irq); 106 106 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 107 107 disable_mappi_irq(M32R_IRQ_SIO1_R); 108 108 109 109 /* SIO1_S : uart send data */ 110 - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, 110 + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, 111 111 handle_level_irq); 112 112 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 113 113 disable_mappi_irq(M32R_IRQ_SIO1_S); ··· 115 115 116 116 #if defined(CONFIG_M32R_PCC) 117 117 /* INT1 : pccard0 interrupt */ 118 - set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, 118 + irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, 119 119 handle_level_irq); 120 120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 121 121 disable_mappi_irq(M32R_IRQ_INT1); 122 122 123 123 /* INT2 : pccard1 interrupt */ 124 - set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, 124 + irq_set_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, 125 125 handle_level_irq); 126 126 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 127 127 disable_mappi_irq(M32R_IRQ_INT2);
+10 -10
arch/m32r/platforms/mappi2/setup.c
··· 76 76 { 77 77 #if defined(CONFIG_SMC91X) 78 78 /* INT0 : LAN controller (SMC91111) */ 79 - set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type, 79 + irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type, 80 80 handle_level_irq); 81 81 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 82 82 disable_mappi2_irq(M32R_IRQ_INT0); 83 83 #endif /* CONFIG_SMC91X */ 84 84 85 85 /* MFT2 : system timer */ 86 - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type, 86 + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type, 87 87 handle_level_irq); 88 88 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 89 89 disable_mappi2_irq(M32R_IRQ_MFT2); 90 90 91 91 #ifdef CONFIG_SERIAL_M32R_SIO 92 92 /* SIO0_R : uart receive data */ 93 - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type, 93 + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type, 94 94 handle_level_irq); 95 95 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 96 96 disable_mappi2_irq(M32R_IRQ_SIO0_R); 97 97 98 98 /* SIO0_S : uart send data */ 99 - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type, 99 + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type, 100 100 handle_level_irq); 101 101 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 102 102 disable_mappi2_irq(M32R_IRQ_SIO0_S); 103 103 /* SIO1_R : uart receive data */ 104 - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type, 104 + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type, 105 105 handle_level_irq); 106 106 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 107 107 disable_mappi2_irq(M32R_IRQ_SIO1_R); 108 108 109 109 /* SIO1_S : uart send data */ 110 - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type, 110 + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type, 111 111 handle_level_irq); 112 112 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 113 113 disable_mappi2_irq(M32R_IRQ_SIO1_S); ··· 115 115 116 116 #if defined(CONFIG_USB) 117 117 /* INT1 : USB Host controller interrupt */ 118 - set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type, 118 + irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type, 119 119 handle_level_irq); 120 120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 121 121 disable_mappi2_irq(M32R_IRQ_INT1); 122 122 #endif /* CONFIG_USB */ 123 123 124 124 /* ICUCR40: CFC IREQ */ 125 - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type, 125 + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type, 126 126 handle_level_irq); 127 127 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 128 128 disable_mappi2_irq(PLD_IRQ_CFIREQ); 129 129 130 130 #if defined(CONFIG_M32R_CFC) 131 131 /* ICUCR41: CFC Insert */ 132 - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type, 132 + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type, 133 133 handle_level_irq); 134 134 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 135 135 disable_mappi2_irq(PLD_IRQ_CFC_INSERT); 136 136 137 137 /* ICUCR42: CFC Eject */ 138 - set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type, 138 + irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type, 139 139 handle_level_irq); 140 140 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 141 141 disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
+10 -10
arch/m32r/platforms/mappi3/setup.c
··· 75 75 { 76 76 #if defined(CONFIG_SMC91X) 77 77 /* INT0 : LAN controller (SMC91111) */ 78 - set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, 78 + irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, 79 79 handle_level_irq); 80 80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 81 81 disable_mappi3_irq(M32R_IRQ_INT0); 82 82 #endif /* CONFIG_SMC91X */ 83 83 84 84 /* MFT2 : system timer */ 85 - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, 85 + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, 86 86 handle_level_irq); 87 87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 88 88 disable_mappi3_irq(M32R_IRQ_MFT2); 89 89 90 90 #ifdef CONFIG_SERIAL_M32R_SIO 91 91 /* SIO0_R : uart receive data */ 92 - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, 92 + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, 93 93 handle_level_irq); 94 94 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 95 95 disable_mappi3_irq(M32R_IRQ_SIO0_R); 96 96 97 97 /* SIO0_S : uart send data */ 98 - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, 98 + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, 99 99 handle_level_irq); 100 100 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 101 101 disable_mappi3_irq(M32R_IRQ_SIO0_S); 102 102 /* SIO1_R : uart receive data */ 103 - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, 103 + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, 104 104 handle_level_irq); 105 105 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 106 106 disable_mappi3_irq(M32R_IRQ_SIO1_R); 107 107 108 108 /* SIO1_S : uart send data */ 109 - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, 109 + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, 110 110 handle_level_irq); 111 111 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 112 112 disable_mappi3_irq(M32R_IRQ_SIO1_S); ··· 114 114 115 115 #if defined(CONFIG_USB) 116 116 /* INT1 : USB Host controller interrupt */ 117 - set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, 117 + irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, 118 118 handle_level_irq); 119 119 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 120 120 disable_mappi3_irq(M32R_IRQ_INT1); 121 121 #endif /* CONFIG_USB */ 122 122 123 123 /* CFC IREQ */ 124 - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, 124 + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, 125 125 handle_level_irq); 126 126 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 127 127 disable_mappi3_irq(PLD_IRQ_CFIREQ); 128 128 129 129 #if defined(CONFIG_M32R_CFC) 130 130 /* ICUCR41: CFC Insert & eject */ 131 - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, 131 + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, 132 132 handle_level_irq); 133 133 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 134 134 disable_mappi3_irq(PLD_IRQ_CFC_INSERT); ··· 136 136 #endif /* CONFIG_M32R_CFC */ 137 137 138 138 /* IDE IREQ */ 139 - set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, 139 + irq_set_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, 140 140 handle_level_irq); 141 141 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 142 142 disable_mappi3_irq(PLD_IRQ_IDEIREQ);
+6 -6
arch/m32r/platforms/oaks32r/setup.c
··· 74 74 75 75 #ifdef CONFIG_NE2000 76 76 /* INT3 : LAN controller (RTL8019AS) */ 77 - set_irq_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type, 77 + irq_set_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type, 78 78 handle_level_irq); 79 79 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 80 80 disable_oaks32r_irq(M32R_IRQ_INT3); 81 81 #endif /* CONFIG_M32R_NE2000 */ 82 82 83 83 /* MFT2 : system timer */ 84 - set_irq_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type, 84 + irq_set_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type, 85 85 handle_level_irq); 86 86 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 87 87 disable_oaks32r_irq(M32R_IRQ_MFT2); 88 88 89 89 #ifdef CONFIG_SERIAL_M32R_SIO 90 90 /* SIO0_R : uart receive data */ 91 - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, 91 + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, 92 92 handle_level_irq); 93 93 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 94 94 disable_oaks32r_irq(M32R_IRQ_SIO0_R); 95 95 96 96 /* SIO0_S : uart send data */ 97 - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type, 97 + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type, 98 98 handle_level_irq); 99 99 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 100 100 disable_oaks32r_irq(M32R_IRQ_SIO0_S); 101 101 102 102 /* SIO1_R : uart receive data */ 103 - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type, 103 + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type, 104 104 handle_level_irq); 105 105 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 106 106 disable_oaks32r_irq(M32R_IRQ_SIO1_R); 107 107 108 108 /* SIO1_S : uart send data */ 109 - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type, 109 + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type, 110 110 handle_level_irq); 111 111 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 112 112 disable_oaks32r_irq(M32R_IRQ_SIO1_S);
+14 -14
arch/m32r/platforms/opsput/setup.c
··· 259 259 { 260 260 #if defined(CONFIG_SMC91X) 261 261 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ 262 - set_irq_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type, 262 + irq_set_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type, 263 263 handle_level_irq); 264 264 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ 265 265 disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); 266 266 #endif /* CONFIG_SMC91X */ 267 267 268 268 /* MFT2 : system timer */ 269 - set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type, 269 + irq_set_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type, 270 270 handle_level_irq); 271 271 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 272 272 disable_opsput_irq(M32R_IRQ_MFT2); 273 273 274 274 /* SIO0 : receive */ 275 - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, 275 + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, 276 276 handle_level_irq); 277 277 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 278 278 disable_opsput_irq(M32R_IRQ_SIO0_R); 279 279 280 280 /* SIO0 : send */ 281 - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type, 281 + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type, 282 282 handle_level_irq); 283 283 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 284 284 disable_opsput_irq(M32R_IRQ_SIO0_S); 285 285 286 286 /* SIO1 : receive */ 287 - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type, 287 + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type, 288 288 handle_level_irq); 289 289 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 290 290 disable_opsput_irq(M32R_IRQ_SIO1_R); 291 291 292 292 /* SIO1 : send */ 293 - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type, 293 + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type, 294 294 handle_level_irq); 295 295 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 296 296 disable_opsput_irq(M32R_IRQ_SIO1_S); 297 297 298 298 /* DMA1 : */ 299 - set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type, 299 + irq_set_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type, 300 300 handle_level_irq); 301 301 icu_data[M32R_IRQ_DMA1].icucr = 0; 302 302 disable_opsput_irq(M32R_IRQ_DMA1); 303 303 304 304 #ifdef CONFIG_SERIAL_M32R_PLDSIO 305 305 /* INT#1: SIO0 Receive on PLD */ 306 - set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type, 306 + irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type, 307 307 handle_level_irq); 308 308 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 309 309 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); 310 310 311 311 /* INT#1: SIO0 Send on PLD */ 312 - set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type, 312 + irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type, 313 313 handle_level_irq); 314 314 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 315 315 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); 316 316 #endif /* CONFIG_SERIAL_M32R_PLDSIO */ 317 317 318 318 /* INT#1: CFC IREQ on PLD */ 319 - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type, 319 + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type, 320 320 handle_level_irq); 321 321 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 322 322 disable_opsput_pld_irq(PLD_IRQ_CFIREQ); 323 323 324 324 /* INT#1: CFC Insert on PLD */ 325 - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type, 325 + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type, 326 326 handle_level_irq); 327 327 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 328 328 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); 329 329 330 330 /* INT#1: CFC Eject on PLD */ 331 - set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type, 331 + irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type, 332 332 handle_level_irq); 333 333 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 334 334 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); ··· 349 349 350 350 #if defined(CONFIG_USB) 351 351 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ 352 - set_irq_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1, 352 + irq_set_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1, 353 353 &opsput_lcdpld_irq_type, handle_level_irq); 354 354 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ 355 355 disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); ··· 365 365 /* 366 366 * INT3# is used for AR 367 367 */ 368 - set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type, 368 + irq_set_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type, 369 369 handle_level_irq); 370 370 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 371 371 disable_opsput_irq(M32R_IRQ_INT3);
+9 -9
arch/m32r/platforms/usrv/setup.c
··· 138 138 once++; 139 139 140 140 /* MFT2 : system timer */ 141 - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, 141 + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, 142 142 handle_level_irq); 143 143 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 144 144 disable_mappi_irq(M32R_IRQ_MFT2); 145 145 146 146 #if defined(CONFIG_SERIAL_M32R_SIO) 147 147 /* SIO0_R : uart receive data */ 148 - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, 148 + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, 149 149 handle_level_irq); 150 150 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 151 151 disable_mappi_irq(M32R_IRQ_SIO0_R); 152 152 153 153 /* SIO0_S : uart send data */ 154 - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, 154 + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, 155 155 handle_level_irq); 156 156 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 157 157 disable_mappi_irq(M32R_IRQ_SIO0_S); 158 158 159 159 /* SIO1_R : uart receive data */ 160 - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, 160 + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, 161 161 handle_level_irq); 162 162 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 163 163 disable_mappi_irq(M32R_IRQ_SIO1_R); 164 164 165 165 /* SIO1_S : uart send data */ 166 - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, 166 + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, 167 167 handle_level_irq); 168 168 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 169 169 disable_mappi_irq(M32R_IRQ_SIO1_S); ··· 171 171 172 172 /* INT#67-#71: CFC#0 IREQ on PLD */ 173 173 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { 174 - set_irq_chip_and_handler(PLD_IRQ_CF0 + i, 174 + irq_set_chip_and_handler(PLD_IRQ_CF0 + i, 175 175 &m32700ut_pld_irq_type, 176 176 handle_level_irq); 177 177 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr ··· 181 181 182 182 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 183 183 /* INT#76: 16552D#0 IREQ on PLD */ 184 - set_irq_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type, 184 + irq_set_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type, 185 185 handle_level_irq); 186 186 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr 187 187 = PLD_ICUCR_ISMOD03; /* 'H' level sense */ 188 188 disable_m32700ut_pld_irq(PLD_IRQ_UART0); 189 189 190 190 /* INT#77: 16552D#1 IREQ on PLD */ 191 - set_irq_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type, 191 + irq_set_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type, 192 192 handle_level_irq); 193 193 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr 194 194 = PLD_ICUCR_ISMOD03; /* 'H' level sense */ ··· 197 197 198 198 #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) 199 199 /* INT#80: AK4524 IREQ on PLD */ 200 - set_irq_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type, 200 + irq_set_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type, 201 201 handle_level_irq); 202 202 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr 203 203 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
+1
arch/um/Kconfig.common
··· 8 8 default y 9 9 select HAVE_GENERIC_HARDIRQS 10 10 select GENERIC_HARDIRQS_NO_DEPRECATED 11 + select GENERIC_IRQ_SHOW 11 12 12 13 config MMU 13 14 bool
+3 -50
arch/um/kernel/irq.c
··· 18 18 #include "os.h" 19 19 20 20 /* 21 - * Generic, controller-independent functions: 22 - */ 23 - 24 - int show_interrupts(struct seq_file *p, void *v) 25 - { 26 - int i = *(loff_t *) v, j; 27 - struct irqaction * action; 28 - unsigned long flags; 29 - 30 - if (i == 0) { 31 - seq_printf(p, " "); 32 - for_each_online_cpu(j) 33 - seq_printf(p, "CPU%d ",j); 34 - seq_putc(p, '\n'); 35 - } 36 - 37 - if (i < NR_IRQS) { 38 - struct irq_desc *desc = irq_to_desc(i); 39 - 40 - raw_spin_lock_irqsave(&desc->lock, flags); 41 - action = desc->action; 42 - if (!action) 43 - goto skip; 44 - seq_printf(p, "%3d: ",i); 45 - #ifndef CONFIG_SMP 46 - seq_printf(p, "%10u ", kstat_irqs(i)); 47 - #else 48 - for_each_online_cpu(j) 49 - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); 50 - #endif 51 - seq_printf(p, " %14s", get_irq_desc_chip(desc)->name); 52 - seq_printf(p, " %s", action->name); 53 - 54 - for (action=action->next; action; action = action->next) 55 - seq_printf(p, ", %s", action->name); 56 - 57 - seq_putc(p, '\n'); 58 - skip: 59 - raw_spin_unlock_irqrestore(&desc->lock, flags); 60 - } else if (i == NR_IRQS) 61 - seq_putc(p, '\n'); 62 - 63 - return 0; 64 - } 65 - 66 - /* 67 21 * This list is accessed under irq_lock, except in sigio_handler, 68 22 * where it is safe from being modified. IRQ handlers won't change it - 69 23 * if an IRQ source has vanished, it will be freed by free_irqs just ··· 344 390 { 345 391 int i; 346 392 347 - set_irq_chip_and_handler(TIMER_IRQ, &SIGVTALRM_irq_type, handle_edge_irq); 393 + irq_set_chip_and_handler(TIMER_IRQ, &SIGVTALRM_irq_type, handle_edge_irq); 348 394 349 - for (i = 1; i < NR_IRQS; i++) { 350 - set_irq_chip_and_handler(i, &normal_irq_type, handle_edge_irq); 351 - } 395 + for (i = 1; i < NR_IRQS; i++) 396 + irq_set_chip_and_handler(i, &normal_irq_type, handle_edge_irq); 352 397 } 353 398 354 399 /*
+3 -3
arch/xtensa/Kconfig
··· 7 7 config XTENSA 8 8 def_bool y 9 9 select HAVE_IDE 10 + select HAVE_GENERIC_HARDIRQS 11 + select GENERIC_IRQ_SHOW 12 + select GENERIC_HARDIRQS_NO_DEPRECATED 10 13 help 11 14 Xtensa processors are 32-bit RISC machines designed by Tensilica 12 15 primarily for embedded systems. These processors are both ··· 28 25 def_bool y 29 26 30 27 config GENERIC_HWEIGHT 31 - def_bool y 32 - 33 - config GENERIC_HARDIRQS 34 28 def_bool y 35 29 36 30 config GENERIC_GPIO
+34 -70
arch/xtensa/kernel/irq.c
··· 35 35 asmlinkage void do_IRQ(int irq, struct pt_regs *regs) 36 36 { 37 37 struct pt_regs *old_regs = set_irq_regs(regs); 38 - struct irq_desc *desc = irq_desc + irq; 39 38 40 39 if (irq >= NR_IRQS) { 41 40 printk(KERN_EMERG "%s: cannot handle IRQ %d\n", ··· 56 57 sp - sizeof(struct thread_info)); 57 58 } 58 59 #endif 59 - desc->handle_irq(irq, desc); 60 + generic_handle_irq(irq); 60 61 61 62 irq_exit(); 62 63 set_irq_regs(old_regs); 63 64 } 64 65 65 - /* 66 - * Generic, controller-independent functions: 67 - */ 68 - 69 - int show_interrupts(struct seq_file *p, void *v) 66 + int arch_show_interrupts(struct seq_file *p, int prec) 70 67 { 71 - int i = *(loff_t *) v, j; 72 - struct irqaction * action; 73 - unsigned long flags; 68 + int j; 74 69 75 - if (i == 0) { 76 - seq_printf(p, " "); 77 - for_each_online_cpu(j) 78 - seq_printf(p, "CPU%d ",j); 79 - seq_putc(p, '\n'); 80 - } 81 - 82 - if (i < NR_IRQS) { 83 - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); 84 - action = irq_desc[i].action; 85 - if (!action) 86 - goto skip; 87 - seq_printf(p, "%3d: ",i); 88 - #ifndef CONFIG_SMP 89 - seq_printf(p, "%10u ", kstat_irqs(i)); 90 - #else 91 - for_each_online_cpu(j) 92 - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); 93 - #endif 94 - seq_printf(p, " %14s", irq_desc[i].chip->name); 95 - seq_printf(p, " %s", action->name); 96 - 97 - for (action=action->next; action; action = action->next) 98 - seq_printf(p, ", %s", action->name); 99 - 100 - seq_putc(p, '\n'); 101 - skip: 102 - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); 103 - } else if (i == NR_IRQS) { 104 - seq_printf(p, "NMI: "); 105 - for_each_online_cpu(j) 106 - seq_printf(p, "%10u ", nmi_count(j)); 107 - seq_putc(p, '\n'); 108 - seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); 109 - } 70 + seq_printf(p, "%*s: ", prec, "NMI"); 71 + for_each_online_cpu(j) 72 + seq_printf(p, "%10u ", nmi_count(j)); 73 + seq_putc(p, '\n'); 74 + seq_printf(p, "%*s: ", prec, "ERR"); 75 + seq_printf(p, "%10u\n", atomic_read(&irq_err_count)); 110 76 return 0; 111 77 } 112 78 113 - static void xtensa_irq_mask(unsigned int irq) 79 + static void xtensa_irq_mask(struct irq_chip *d) 114 80 { 115 - cached_irq_mask &= ~(1 << irq); 81 + cached_irq_mask &= ~(1 << d->irq); 116 82 set_sr (cached_irq_mask, INTENABLE); 117 83 } 118 84 119 - static void xtensa_irq_unmask(unsigned int irq) 85 + static void xtensa_irq_unmask(struct irq_chip *d) 120 86 { 121 - cached_irq_mask |= 1 << irq; 87 + cached_irq_mask |= 1 << d->irq; 122 88 set_sr (cached_irq_mask, INTENABLE); 123 89 } 124 90 125 - static void xtensa_irq_enable(unsigned int irq) 91 + static void xtensa_irq_enable(struct irq_chip *d) 126 92 { 127 - variant_irq_enable(irq); 128 - xtensa_irq_unmask(irq); 93 + variant_irq_enable(d->irq); 94 + xtensa_irq_unmask(d->irq); 129 95 } 130 96 131 - static void xtensa_irq_disable(unsigned int irq) 97 + static void xtensa_irq_disable(struct irq_chip *d) 132 98 { 133 - xtensa_irq_mask(irq); 134 - variant_irq_disable(irq); 99 + xtensa_irq_mask(d->irq); 100 + variant_irq_disable(d->irq); 135 101 } 136 102 137 - static void xtensa_irq_ack(unsigned int irq) 103 + static void xtensa_irq_ack(struct irq_chip *d) 138 104 { 139 - set_sr(1 << irq, INTCLEAR); 105 + set_sr(1 << d->irq, INTCLEAR); 140 106 } 141 107 142 - static int xtensa_irq_retrigger(unsigned int irq) 108 + static int xtensa_irq_retrigger(struct irq_chip *d) 143 109 { 144 - set_sr (1 << irq, INTSET); 110 + set_sr (1 << d->irq, INTSET); 145 111 return 1; 146 112 } 147 113 148 114 149 115 static struct irq_chip xtensa_irq_chip = { 150 116 .name = "xtensa", 151 - .enable = xtensa_irq_enable, 152 - .disable = xtensa_irq_disable, 153 - .mask = xtensa_irq_mask, 154 - .unmask = xtensa_irq_unmask, 155 - .ack = xtensa_irq_ack, 156 - .retrigger = xtensa_irq_retrigger, 117 + .irq_enable = xtensa_irq_enable, 118 + .irq_disable = xtensa_irq_disable, 119 + .irq_mask = xtensa_irq_mask, 120 + .irq_unmask = xtensa_irq_unmask, 121 + .irq_ack = xtensa_irq_ack, 122 + .irq_retrigger = xtensa_irq_retrigger, 157 123 }; 158 124 159 125 void __init init_IRQ(void) ··· 129 165 int mask = 1 << index; 130 166 131 167 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) 132 - set_irq_chip_and_handler(index, &xtensa_irq_chip, 168 + irq_set_chip_and_handler(index, &xtensa_irq_chip, 133 169 handle_simple_irq); 134 170 135 171 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) 136 - set_irq_chip_and_handler(index, &xtensa_irq_chip, 172 + irq_set_chip_and_handler(index, &xtensa_irq_chip, 137 173 handle_edge_irq); 138 174 139 175 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) 140 - set_irq_chip_and_handler(index, &xtensa_irq_chip, 176 + irq_set_chip_and_handler(index, &xtensa_irq_chip, 141 177 handle_level_irq); 142 178 143 179 else if (mask & XCHAL_INTTYPE_MASK_TIMER) 144 - set_irq_chip_and_handler(index, &xtensa_irq_chip, 180 + irq_set_chip_and_handler(index, &xtensa_irq_chip, 145 181 handle_edge_irq); 146 182 147 183 else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */ 148 184 /* XCHAL_INTTYPE_MASK_NMI */ 149 185 150 - set_irq_chip_and_handler(index, &xtensa_irq_chip, 186 + irq_set_chip_and_handler(index, &xtensa_irq_chip, 151 187 handle_level_irq); 152 188 } 153 189
+1 -1
arch/xtensa/platforms/s6105/device.c
··· 120 120 irq = gpio_to_irq(pin); 121 121 if (irq < 0) 122 122 goto free; 123 - if (set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0) 123 + if (irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0) 124 124 goto free; 125 125 return irq; 126 126 free:
+22 -23
arch/xtensa/variants/s6000/gpio.c
··· 85 85 return gpiochip_add(&gpiochip); 86 86 } 87 87 88 - static void ack(unsigned int irq) 88 + static void ack(struct irq_data *d) 89 89 { 90 - writeb(1 << (irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC); 90 + writeb(1 << (d->irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC); 91 91 } 92 92 93 - static void mask(unsigned int irq) 93 + static void mask(struct irq_data *d) 94 94 { 95 95 u8 r = readb(S6_REG_GPIO + S6_GPIO_IE); 96 - r &= ~(1 << (irq - IRQ_BASE)); 96 + r &= ~(1 << (d->irq - IRQ_BASE)); 97 97 writeb(r, S6_REG_GPIO + S6_GPIO_IE); 98 98 } 99 99 100 - static void unmask(unsigned int irq) 100 + static void unmask(struct irq_data *d) 101 101 { 102 102 u8 m = readb(S6_REG_GPIO + S6_GPIO_IE); 103 - m |= 1 << (irq - IRQ_BASE); 103 + m |= 1 << (d->irq - IRQ_BASE); 104 104 writeb(m, S6_REG_GPIO + S6_GPIO_IE); 105 105 } 106 106 107 - static int set_type(unsigned int irq, unsigned int type) 107 + static int set_type(struct irq_data *d, unsigned int type) 108 108 { 109 - const u8 m = 1 << (irq - IRQ_BASE); 109 + const u8 m = 1 << (d->irq - IRQ_BASE); 110 110 irq_flow_handler_t handler; 111 - struct irq_desc *desc; 112 111 u8 reg; 113 112 114 113 if (type == IRQ_TYPE_PROBE) { ··· 128 129 handler = handle_edge_irq; 129 130 } 130 131 writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS); 131 - desc = irq_to_desc(irq); 132 - desc->handle_irq = handler; 132 + __irq_set_handler_locked(irq, handler); 133 133 134 134 reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV); 135 135 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)) ··· 148 150 149 151 static struct irq_chip gpioirqs = { 150 152 .name = "GPIO", 151 - .ack = ack, 152 - .mask = mask, 153 - .unmask = unmask, 154 - .set_type = set_type, 153 + .irq_ack = ack, 154 + .irq_mask = mask, 155 + .irq_unmask = unmask, 156 + .irq_set_type = set_type, 155 157 }; 156 158 157 159 static u8 demux_masks[4]; 158 160 159 161 static void demux_irqs(unsigned int irq, struct irq_desc *desc) 160 162 { 161 - u8 *mask = get_irq_desc_data(desc); 163 + struct irq_chip *chip = irq_desc_get_chip(desc); 164 + u8 *mask = irq_desc_get_handler_data(desc); 162 165 u8 pending; 163 166 int cirq; 164 167 165 - desc->chip->mask(irq); 166 - desc->chip->ack(irq); 168 + chip->irq_mask(&desc->irq_data); 169 + chip->irq_ack(&desc->irq_data)); 167 170 pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask; 168 171 cirq = IRQ_BASE - 1; 169 172 while (pending) { ··· 173 174 pending >>= n; 174 175 generic_handle_irq(cirq); 175 176 } 176 - desc->chip->unmask(irq); 177 + chip->irq_unmask(&desc->irq_data)); 177 178 } 178 179 179 180 extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS]; ··· 218 219 i = ffs(mask); 219 220 cirq += i; 220 221 mask >>= i; 221 - set_irq_chip(cirq, &gpioirqs); 222 - set_irq_type(irq, IRQ_TYPE_LEVEL_LOW); 222 + irq_set_chip(cirq, &gpioirqs); 223 + irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW); 223 224 } while (mask); 224 - set_irq_data(irq, demux_masks + n); 225 - set_irq_chained_handler(irq, demux_irqs); 225 + irq_set_handler_data(irq, demux_masks + n); 226 + irq_set_chained_handler(irq, demux_irqs); 226 227 if (++n == ARRAY_SIZE(demux_masks)) 227 228 break; 228 229 }
+4 -4
drivers/gpio/adp5588-gpio.c
··· 289 289 290 290 for (gpio = 0; gpio < dev->gpio_chip.ngpio; gpio++) { 291 291 int irq = gpio + dev->irq_base; 292 - set_irq_chip_data(irq, dev); 293 - set_irq_chip_and_handler(irq, &adp5588_irq_chip, 292 + irq_set_chip_data(irq, dev); 293 + irq_set_chip_and_handler(irq, &adp5588_irq_chip, 294 294 handle_level_irq); 295 - set_irq_nested_thread(irq, 1); 295 + irq_set_nested_thread(irq, 1); 296 296 #ifdef CONFIG_ARM 297 297 /* 298 298 * ARM needs us to explicitly flag the IRQ as VALID, ··· 300 300 */ 301 301 set_irq_flags(irq, IRQF_VALID); 302 302 #else 303 - set_irq_noprobe(irq); 303 + irq_set_noprobe(irq); 304 304 #endif 305 305 } 306 306
-45
drivers/gpio/gpiolib.c
··· 1656 1656 chip->get 1657 1657 ? (chip->get(chip, i) ? "hi" : "lo") 1658 1658 : "? "); 1659 - 1660 - if (!is_out) { 1661 - int irq = gpio_to_irq(gpio); 1662 - struct irq_desc *desc = irq_to_desc(irq); 1663 - 1664 - /* This races with request_irq(), set_irq_type(), 1665 - * and set_irq_wake() ... but those are "rare". 1666 - * 1667 - * More significantly, trigger type flags aren't 1668 - * currently maintained by genirq. 1669 - */ 1670 - if (irq >= 0 && desc->action) { 1671 - char *trigger; 1672 - 1673 - switch (desc->status & IRQ_TYPE_SENSE_MASK) { 1674 - case IRQ_TYPE_NONE: 1675 - trigger = "(default)"; 1676 - break; 1677 - case IRQ_TYPE_EDGE_FALLING: 1678 - trigger = "edge-falling"; 1679 - break; 1680 - case IRQ_TYPE_EDGE_RISING: 1681 - trigger = "edge-rising"; 1682 - break; 1683 - case IRQ_TYPE_EDGE_BOTH: 1684 - trigger = "edge-both"; 1685 - break; 1686 - case IRQ_TYPE_LEVEL_HIGH: 1687 - trigger = "level-high"; 1688 - break; 1689 - case IRQ_TYPE_LEVEL_LOW: 1690 - trigger = "level-low"; 1691 - break; 1692 - default: 1693 - trigger = "?trigger?"; 1694 - break; 1695 - } 1696 - 1697 - seq_printf(s, " irq-%d %s%s", 1698 - irq, trigger, 1699 - (desc->status & IRQ_WAKEUP) 1700 - ? " wakeup" : ""); 1701 - } 1702 - } 1703 - 1704 1659 seq_printf(s, "\n"); 1705 1660 } 1706 1661 }
+4 -4
drivers/gpio/max732x.c
··· 470 470 if (!(chip->dir_input & (1 << lvl))) 471 471 continue; 472 472 473 - set_irq_chip_data(irq, chip); 474 - set_irq_chip_and_handler(irq, &max732x_irq_chip, 473 + irq_set_chip_data(irq, chip); 474 + irq_set_chip_and_handler(irq, &max732x_irq_chip, 475 475 handle_edge_irq); 476 - set_irq_nested_thread(irq, 1); 476 + irq_set_nested_thread(irq, 1); 477 477 #ifdef CONFIG_ARM 478 478 set_irq_flags(irq, IRQF_VALID); 479 479 #else 480 - set_irq_noprobe(irq); 480 + irq_set_noprobe(irq); 481 481 #endif 482 482 } 483 483
+3 -3
drivers/gpio/pca953x.c
··· 395 395 for (lvl = 0; lvl < chip->gpio_chip.ngpio; lvl++) { 396 396 int irq = lvl + chip->irq_base; 397 397 398 - set_irq_chip_data(irq, chip); 399 - set_irq_chip_and_handler(irq, &pca953x_irq_chip, 398 + irq_set_chip_data(irq, chip); 399 + irq_set_chip_and_handler(irq, &pca953x_irq_chip, 400 400 handle_edge_irq); 401 401 #ifdef CONFIG_ARM 402 402 set_irq_flags(irq, IRQF_VALID); 403 403 #else 404 - set_irq_noprobe(irq); 404 + irq_set_noprobe(irq); 405 405 #endif 406 406 } 407 407
+7 -7
drivers/gpio/pl061.c
··· 210 210 211 211 static void pl061_irq_handler(unsigned irq, struct irq_desc *desc) 212 212 { 213 - struct list_head *chip_list = get_irq_data(irq); 213 + struct list_head *chip_list = irq_get_handler_data(irq); 214 214 struct list_head *ptr; 215 215 struct pl061_gpio *chip; 216 216 ··· 294 294 ret = -ENODEV; 295 295 goto iounmap; 296 296 } 297 - set_irq_chained_handler(irq, pl061_irq_handler); 297 + irq_set_chained_handler(irq, pl061_irq_handler); 298 298 if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */ 299 299 chip_list = kmalloc(sizeof(*chip_list), GFP_KERNEL); 300 300 if (chip_list == NULL) { ··· 303 303 goto iounmap; 304 304 } 305 305 INIT_LIST_HEAD(chip_list); 306 - set_irq_data(irq, chip_list); 306 + irq_set_handler_data(irq, chip_list); 307 307 } else 308 - chip_list = get_irq_data(irq); 308 + chip_list = irq_get_handler_data(irq); 309 309 list_add(&chip->list, chip_list); 310 310 311 311 for (i = 0; i < PL061_GPIO_NR; i++) { ··· 315 315 else 316 316 pl061_direction_input(&chip->gc, i); 317 317 318 - set_irq_chip(i+chip->irq_base, &pl061_irqchip); 319 - set_irq_handler(i+chip->irq_base, handle_simple_irq); 318 + irq_set_chip_and_handler(i + chip->irq_base, &pl061_irqchip, 319 + handle_simple_irq); 320 320 set_irq_flags(i+chip->irq_base, IRQF_VALID); 321 - set_irq_chip_data(i+chip->irq_base, chip); 321 + irq_set_chip_data(i + chip->irq_base, chip); 322 322 } 323 323 324 324 return 0;
+6 -6
drivers/gpio/stmpe-gpio.c
··· 254 254 int irq; 255 255 256 256 for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) { 257 - set_irq_chip_data(irq, stmpe_gpio); 258 - set_irq_chip_and_handler(irq, &stmpe_gpio_irq_chip, 257 + irq_set_chip_data(irq, stmpe_gpio); 258 + irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip, 259 259 handle_simple_irq); 260 - set_irq_nested_thread(irq, 1); 260 + irq_set_nested_thread(irq, 1); 261 261 #ifdef CONFIG_ARM 262 262 set_irq_flags(irq, IRQF_VALID); 263 263 #else 264 - set_irq_noprobe(irq); 264 + irq_set_noprobe(irq); 265 265 #endif 266 266 } 267 267 ··· 277 277 #ifdef CONFIG_ARM 278 278 set_irq_flags(irq, 0); 279 279 #endif 280 - set_irq_chip_and_handler(irq, NULL, NULL); 281 - set_irq_chip_data(irq, NULL); 280 + irq_set_chip_and_handler(irq, NULL, NULL); 281 + irq_set_chip_data(irq, NULL); 282 282 } 283 283 } 284 284
+4 -5
drivers/gpio/sx150x.c
··· 551 551 552 552 for (n = 0; n < chip->dev_cfg->ngpios; ++n) { 553 553 irq = irq_base + n; 554 - set_irq_chip_and_handler(irq, &chip->irq_chip, handle_edge_irq); 555 - set_irq_nested_thread(irq, 1); 554 + irq_set_chip_and_handler(irq, &chip->irq_chip, handle_edge_irq); 555 + irq_set_nested_thread(irq, 1); 556 556 #ifdef CONFIG_ARM 557 557 set_irq_flags(irq, IRQF_VALID); 558 558 #else 559 - set_irq_noprobe(irq); 559 + irq_set_noprobe(irq); 560 560 #endif 561 561 } 562 562 ··· 583 583 584 584 for (n = 0; n < chip->dev_cfg->ngpios; ++n) { 585 585 irq = chip->irq_base + n; 586 - set_irq_handler(irq, NULL); 587 - set_irq_chip(irq, NULL); 586 + irq_set_chip_and_handler(irq, NULL, NULL); 588 587 } 589 588 } 590 589
+6 -6
drivers/gpio/tc3589x-gpio.c
··· 239 239 int irq; 240 240 241 241 for (irq = base; irq < base + tc3589x_gpio->chip.ngpio; irq++) { 242 - set_irq_chip_data(irq, tc3589x_gpio); 243 - set_irq_chip_and_handler(irq, &tc3589x_gpio_irq_chip, 242 + irq_set_chip_data(irq, tc3589x_gpio); 243 + irq_set_chip_and_handler(irq, &tc3589x_gpio_irq_chip, 244 244 handle_simple_irq); 245 - set_irq_nested_thread(irq, 1); 245 + irq_set_nested_thread(irq, 1); 246 246 #ifdef CONFIG_ARM 247 247 set_irq_flags(irq, IRQF_VALID); 248 248 #else 249 - set_irq_noprobe(irq); 249 + irq_set_noprobe(irq); 250 250 #endif 251 251 } 252 252 ··· 262 262 #ifdef CONFIG_ARM 263 263 set_irq_flags(irq, 0); 264 264 #endif 265 - set_irq_chip_and_handler(irq, NULL, NULL); 266 - set_irq_chip_data(irq, NULL); 265 + irq_set_chip_and_handler(irq, NULL, NULL); 266 + irq_set_chip_data(irq, NULL); 267 267 } 268 268 } 269 269
+9 -9
drivers/gpio/timbgpio.c
··· 196 196 197 197 static void timbgpio_irq(unsigned int irq, struct irq_desc *desc) 198 198 { 199 - struct timbgpio *tgpio = get_irq_data(irq); 199 + struct timbgpio *tgpio = irq_get_handler_data(irq); 200 200 unsigned long ipr; 201 201 int offset; 202 202 ··· 292 292 return 0; 293 293 294 294 for (i = 0; i < pdata->nr_pins; i++) { 295 - set_irq_chip_and_handler_name(tgpio->irq_base + i, 295 + irq_set_chip_and_handler_name(tgpio->irq_base + i, 296 296 &timbgpio_irqchip, handle_simple_irq, "mux"); 297 - set_irq_chip_data(tgpio->irq_base + i, tgpio); 297 + irq_set_chip_data(tgpio->irq_base + i, tgpio); 298 298 #ifdef CONFIG_ARM 299 299 set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE); 300 300 #endif 301 301 } 302 302 303 - set_irq_data(irq, tgpio); 304 - set_irq_chained_handler(irq, timbgpio_irq); 303 + irq_set_handler_data(irq, tgpio); 304 + irq_set_chained_handler(irq, timbgpio_irq); 305 305 306 306 return 0; 307 307 ··· 327 327 if (irq >= 0 && tgpio->irq_base > 0) { 328 328 int i; 329 329 for (i = 0; i < tgpio->gpio.ngpio; i++) { 330 - set_irq_chip(tgpio->irq_base + i, NULL); 331 - set_irq_chip_data(tgpio->irq_base + i, NULL); 330 + irq_set_chip(tgpio->irq_base + i, NULL); 331 + irq_set_chip_data(tgpio->irq_base + i, NULL); 332 332 } 333 333 334 - set_irq_handler(irq, NULL); 335 - set_irq_data(irq, NULL); 334 + irq_set_handler(irq, NULL); 335 + irq_set_handler_data(irq, NULL); 336 336 } 337 337 338 338 err = gpiochip_remove(&tgpio->gpio);
+6 -6
drivers/gpio/vr41xx_giu.c
··· 238 238 break; 239 239 } 240 240 } 241 - set_irq_chip_and_handler(GIU_IRQ(pin), 241 + irq_set_chip_and_handler(GIU_IRQ(pin), 242 242 &giuint_low_irq_chip, 243 243 handle_edge_irq); 244 244 } else { 245 245 giu_clear(GIUINTTYPL, mask); 246 246 giu_clear(GIUINTHTSELL, mask); 247 - set_irq_chip_and_handler(GIU_IRQ(pin), 247 + irq_set_chip_and_handler(GIU_IRQ(pin), 248 248 &giuint_low_irq_chip, 249 249 handle_level_irq); 250 250 } ··· 273 273 break; 274 274 } 275 275 } 276 - set_irq_chip_and_handler(GIU_IRQ(pin), 276 + irq_set_chip_and_handler(GIU_IRQ(pin), 277 277 &giuint_high_irq_chip, 278 278 handle_edge_irq); 279 279 } else { 280 280 giu_clear(GIUINTTYPH, mask); 281 281 giu_clear(GIUINTHTSELH, mask); 282 - set_irq_chip_and_handler(GIU_IRQ(pin), 282 + irq_set_chip_and_handler(GIU_IRQ(pin), 283 283 &giuint_high_irq_chip, 284 284 handle_level_irq); 285 285 } ··· 539 539 chip = &giuint_high_irq_chip; 540 540 541 541 if (trigger & (1 << pin)) 542 - set_irq_chip_and_handler(i, chip, handle_edge_irq); 542 + irq_set_chip_and_handler(i, chip, handle_edge_irq); 543 543 else 544 - set_irq_chip_and_handler(i, chip, handle_level_irq); 544 + irq_set_chip_and_handler(i, chip, handle_level_irq); 545 545 546 546 } 547 547
+4
include/linux/irq.h
··· 28 28 #include <asm/ptrace.h> 29 29 #include <asm/irq_regs.h> 30 30 31 + struct seq_file; 31 32 struct irq_desc; 32 33 struct irq_data; 33 34 typedef void (*irq_flow_handler_t)(unsigned int irq, ··· 271 270 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 272 271 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 273 272 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 273 + * @irq_print_chip: optional to print special chip info in show_interrupts 274 274 * @flags: chip specific flags 275 275 * 276 276 * @release: release function solely used by UML ··· 318 316 319 317 void (*irq_bus_lock)(struct irq_data *data); 320 318 void (*irq_bus_sync_unlock)(struct irq_data *data); 319 + 320 + void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 321 321 322 322 unsigned long flags; 323 323
+4
kernel/irq/Kconfig
··· 31 31 config GENERIC_IRQ_SHOW 32 32 bool 33 33 34 + # Print level/edge extra information 35 + config GENERIC_IRQ_SHOW_LEVEL 36 + bool 37 + 34 38 # Support for delayed migration from interrupt context 35 39 config GENERIC_PENDING_IRQ 36 40 bool
+14 -1
kernel/irq/proc.c
··· 404 404 seq_printf(p, "%*d: ", prec, i); 405 405 for_each_online_cpu(j) 406 406 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); 407 - seq_printf(p, " %8s", desc->irq_data.chip->name); 407 + 408 + if (desc->irq_data.chip) { 409 + if (desc->irq_data.chip->irq_print_chip) 410 + desc->irq_data.chip->irq_print_chip(&desc->irq_data, p); 411 + else if (desc->irq_data.chip->name) 412 + seq_printf(p, " %8s", desc->irq_data.chip->name); 413 + else 414 + seq_printf(p, " %8s", "-"); 415 + } else { 416 + seq_printf(p, " %8s", "None"); 417 + } 418 + #ifdef CONFIG_GENIRC_IRQ_SHOW_LEVEL 419 + seq_printf(p, " %-8s", irqd_is_level_type(&desc->irq_data) ? "Level" : "Edge"); 420 + #endif 408 421 if (desc->name) 409 422 seq_printf(p, "-%-8s", desc->name); 410 423