Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

MIPS: Add Cavium OCTEON processor constants and CPU probe.

Add OCTEON constants to asm/cpu.h and asm/module.h.

Add probe function for Cavium OCTEON CPUs and hook it up.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

David Daney and committed by
Ralf Baechle
0dd4781b 25c30003

+41
+14
arch/mips/include/asm/cpu.h
··· 33 33 #define PRID_COMP_TOSHIBA 0x070000 34 34 #define PRID_COMP_LSI 0x080000 35 35 #define PRID_COMP_LEXRA 0x0b0000 36 + #define PRID_COMP_CAVIUM 0x0d0000 36 37 37 38 38 39 /* ··· 113 112 114 113 #define PRID_IMP_BCM4710 0x4000 115 114 #define PRID_IMP_BCM3302 0x9000 115 + 116 + /* 117 + * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM 118 + */ 119 + 120 + #define PRID_IMP_CAVIUM_CN38XX 0x0000 121 + #define PRID_IMP_CAVIUM_CN31XX 0x0100 122 + #define PRID_IMP_CAVIUM_CN30XX 0x0200 123 + #define PRID_IMP_CAVIUM_CN58XX 0x0300 124 + #define PRID_IMP_CAVIUM_CN56XX 0x0400 125 + #define PRID_IMP_CAVIUM_CN50XX 0x0600 126 + #define PRID_IMP_CAVIUM_CN52XX 0x0700 116 127 117 128 /* 118 129 * Definitions for 7:0 on legacy processors ··· 216 203 * MIPS64 class processors 217 204 */ 218 205 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 206 + CPU_CAVIUM_OCTEON, 219 207 220 208 CPU_LAST 221 209 };
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arch/mips/include/asm/module.h
··· 116 116 #define MODULE_PROC_FAMILY "SB1 " 117 117 #elif defined CONFIG_CPU_LOONGSON2 118 118 #define MODULE_PROC_FAMILY "LOONGSON2 " 119 + #elif defined CONFIG_CPU_CAVIUM_OCTEON 120 + #define MODULE_PROC_FAMILY "OCTEON " 119 121 #else 120 122 #error MODULE_PROC_FAMILY undefined for your processor configuration 121 123 #endif
+25
arch/mips/kernel/cpu-probe.c
··· 154 154 case CPU_25KF: 155 155 case CPU_PR4450: 156 156 case CPU_BCM3302: 157 + case CPU_CAVIUM_OCTEON: 157 158 cpu_wait = r4k_wait; 158 159 break; 159 160 ··· 876 875 } 877 876 } 878 877 878 + static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 879 + { 880 + decode_configs(c); 881 + switch (c->processor_id & 0xff00) { 882 + case PRID_IMP_CAVIUM_CN38XX: 883 + case PRID_IMP_CAVIUM_CN31XX: 884 + case PRID_IMP_CAVIUM_CN30XX: 885 + case PRID_IMP_CAVIUM_CN58XX: 886 + case PRID_IMP_CAVIUM_CN56XX: 887 + case PRID_IMP_CAVIUM_CN50XX: 888 + case PRID_IMP_CAVIUM_CN52XX: 889 + c->cputype = CPU_CAVIUM_OCTEON; 890 + __cpu_name[cpu] = "Cavium Octeon"; 891 + break; 892 + default: 893 + printk(KERN_INFO "Unknown Octeon chip!\n"); 894 + c->cputype = CPU_UNKNOWN; 895 + break; 896 + } 897 + } 898 + 879 899 const char *__cpu_name[NR_CPUS]; 880 900 881 901 __cpuinit void cpu_probe(void) ··· 930 908 break; 931 909 case PRID_COMP_NXP: 932 910 cpu_probe_nxp(c, cpu); 911 + break; 912 + case PRID_COMP_CAVIUM: 913 + cpu_probe_cavium(c, cpu); 933 914 break; 934 915 } 935 916