···22 tristate "Intel Wireless WiFi Next Gen AGN - Wireless-N/Advanced-N/Ultimate-N (iwlwifi) "33 depends on PCI && MAC80211 && HAS_IOMEM44 select FW_LOADER55- select NEW_LEDS66- select LEDS_CLASS77- select LEDS_TRIGGERS88- select MAC80211_LEDS95 ---help---106 Select to build the driver supporting the:117···3842 inserted in and removed from the running kernel whenever you want),3943 say M here and read <file:Documentation/kbuild/modules.txt>. The4044 module will be called iwlwifi.4545+4646+config IWLWIFI_LEDS4747+ bool4848+ depends on IWLWIFI4949+ depends on LEDS_CLASS5050+ select LEDS_TRIGGERS5151+ select MAC80211_LEDS5252+ default y41534254config IWLDVM4355 tristate "Intel Wireless WiFi DVM Firmware support"
···116116/**117117 * enum iwl_ucode_tlv_api - ucode api118118 * @IWL_UCODE_TLV_API_WOWLAN_CONFIG_TID: wowlan config includes tid field.119119+ * @IWL_UCODE_TLV_API_CSA_FLOW: ucode can do unbind-bind flow for CSA.119120 */120121enum iwl_ucode_tlv_api {121122 IWL_UCODE_TLV_API_WOWLAN_CONFIG_TID = BIT(0),123123+ IWL_UCODE_TLV_API_CSA_FLOW = BIT(4),122124};123125124126/**
+38-8
drivers/net/wireless/iwlwifi/iwl-nvm-parse.c
···6262#include <linux/types.h>6363#include <linux/slab.h>6464#include <linux/export.h>6565+#include <linux/etherdevice.h>6566#include "iwl-drv.h"6667#include "iwl-modparams.h"6768#include "iwl-nvm-parse.h"···451450 struct iwl_nvm_data *data,452451 const __le16 *nvm_sec)453452{454454- u8 hw_addr[ETH_ALEN];455455-456456- if (cfg->device_family != IWL_DEVICE_FAMILY_8000)457457- memcpy(hw_addr, nvm_sec + HW_ADDR, ETH_ALEN);458458- else459459- memcpy(hw_addr, nvm_sec + MAC_ADDRESS_OVERRIDE_FAMILY_8000,460460- ETH_ALEN);453453+ const u8 *hw_addr = (const u8 *)(nvm_sec + HW_ADDR);461454462455 /* The byte order is little endian 16 bit, meaning 214365 */463456 data->hw_addr[0] = hw_addr[1];···460465 data->hw_addr[3] = hw_addr[2];461466 data->hw_addr[4] = hw_addr[5];462467 data->hw_addr[5] = hw_addr[4];468468+}469469+470470+static void iwl_set_hw_address_family_8000(const struct iwl_cfg *cfg,471471+ struct iwl_nvm_data *data,472472+ const __le16 *mac_override,473473+ const __le16 *nvm_hw)474474+{475475+ const u8 *hw_addr;476476+477477+ if (mac_override) {478478+ hw_addr = (const u8 *)(mac_override +479479+ MAC_ADDRESS_OVERRIDE_FAMILY_8000);480480+481481+ /* The byte order is little endian 16 bit, meaning 214365 */482482+ data->hw_addr[0] = hw_addr[1];483483+ data->hw_addr[1] = hw_addr[0];484484+ data->hw_addr[2] = hw_addr[3];485485+ data->hw_addr[3] = hw_addr[2];486486+ data->hw_addr[4] = hw_addr[5];487487+ data->hw_addr[5] = hw_addr[4];488488+489489+ if (is_valid_ether_addr(hw_addr))490490+ return;491491+ }492492+493493+ /* take the MAC address from the OTP */494494+ hw_addr = (const u8 *)(nvm_hw + HW_ADDR0_FAMILY_8000);495495+ data->hw_addr[0] = hw_addr[3];496496+ data->hw_addr[1] = hw_addr[2];497497+ data->hw_addr[2] = hw_addr[1];498498+ data->hw_addr[3] = hw_addr[0];499499+500500+ hw_addr = (const u8 *)(nvm_hw + HW_ADDR1_FAMILY_8000);501501+ data->hw_addr[4] = hw_addr[1];502502+ data->hw_addr[5] = hw_addr[0];463503}464504465505struct iwl_nvm_data *···556526 rx_chains);557527 } else {558528 /* MAC address in family 8000 */559559- iwl_set_hw_address(cfg, data, mac_override);529529+ iwl_set_hw_address_family_8000(cfg, data, mac_override, nvm_hw);560530561531 iwl_init_sbands(dev, cfg, data, regulatory,562532 sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains,
+19
drivers/net/wireless/iwlwifi/iwl-trans.h
···463463 * @unref: release a reference previously taken with @ref. Note that464464 * initially the reference count is 1, making an initial @unref465465 * necessary to allow low power states.466466+ * @dump_data: fill a data dump with debug data, maybe containing last467467+ * TX'ed commands and similar. When called with a NULL buffer and468468+ * zero buffer length, provide only the (estimated) required buffer469469+ * length. Return the used buffer length.470470+ * Note that the transport must fill in the proper file headers.466471 */467472struct iwl_trans_ops {468473···516511 u32 value);517512 void (*ref)(struct iwl_trans *trans);518513 void (*unref)(struct iwl_trans *trans);514514+515515+#ifdef CONFIG_IWLWIFI_DEBUGFS516516+ u32 (*dump_data)(struct iwl_trans *trans, void *buf, u32 buflen);517517+#endif519518};520519521520/**···672663 if (trans->ops->unref)673664 trans->ops->unref(trans);674665}666666+667667+#ifdef CONFIG_IWLWIFI_DEBUGFS668668+static inline u32 iwl_trans_dump_data(struct iwl_trans *trans,669669+ void *buf, u32 buflen)670670+{671671+ if (!trans->ops->dump_data)672672+ return 0;673673+ return trans->ops->dump_data(trans, buf, buflen);674674+}675675+#endif675676676677static inline int iwl_trans_send_cmd(struct iwl_trans *trans,677678 struct iwl_host_cmd *cmd)
···187187 * this number of packets were received (typically 1)188188 * @passive2active: is auto switching from passive to active during scan allowed189189 * @rxchain_sel_flags: RXON_RX_CHAIN_*190190- * @max_out_time: in usecs, max out of serving channel time190190+ * @max_out_time: in TUs, max out of serving channel time191191 * @suspend_time: how long to pause scan when returning to service channel:192192- * bits 0-19: beacon interal in usecs (suspend before executing)192192+ * bits 0-19: beacon interal in TUs (suspend before executing)193193 * bits 20-23: reserved194194 * bits 24-31: number of beacons (suspend between channels)195195 * @rxon_flags: RXON_FLG_*···387387 * @quiet_plcp_th: quiet channel num of packets threshold388388 * @good_CRC_th: passive to active promotion threshold389389 * @rx_chain: RXON rx chain.390390- * @max_out_time: max uSec to be out of assoceated channel391391- * @suspend_time: pause scan this long when returning to service channel390390+ * @max_out_time: max TUs to be out of assoceated channel391391+ * @suspend_time: pause scan this TUs when returning to service channel392392 * @flags: RXON flags393393 * @filter_flags: RXONfilter394394 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz.
···295295 /* Read the NVM only at driver load time, no need to do this twice */296296 if (read_nvm) {297297 /* Read nvm */298298- ret = iwl_nvm_init(mvm);298298+ ret = iwl_nvm_init(mvm, true);299299 if (ret) {300300 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);301301 goto error;
···211211 .next_columns = {212212 RS_COLUMN_LEGACY_ANT_B,213213 RS_COLUMN_SISO_ANT_A,214214- RS_COLUMN_SISO_ANT_B,214214+ RS_COLUMN_MIMO2,215215 RS_COLUMN_INVALID,216216 RS_COLUMN_INVALID,217217 RS_COLUMN_INVALID,···223223 .ant = ANT_B,224224 .next_columns = {225225 RS_COLUMN_LEGACY_ANT_A,226226- RS_COLUMN_SISO_ANT_A,227226 RS_COLUMN_SISO_ANT_B,227227+ RS_COLUMN_MIMO2,228228 RS_COLUMN_INVALID,229229 RS_COLUMN_INVALID,230230 RS_COLUMN_INVALID,···238238 RS_COLUMN_SISO_ANT_B,239239 RS_COLUMN_MIMO2,240240 RS_COLUMN_SISO_ANT_A_SGI,241241- RS_COLUMN_SISO_ANT_B_SGI,242241 RS_COLUMN_LEGACY_ANT_A,243242 RS_COLUMN_LEGACY_ANT_B,243243+ RS_COLUMN_INVALID,244244 RS_COLUMN_INVALID,245245 },246246 .checks = {···254254 RS_COLUMN_SISO_ANT_A,255255 RS_COLUMN_MIMO2,256256 RS_COLUMN_SISO_ANT_B_SGI,257257- RS_COLUMN_SISO_ANT_A_SGI,258257 RS_COLUMN_LEGACY_ANT_A,259258 RS_COLUMN_LEGACY_ANT_B,259259+ RS_COLUMN_INVALID,260260 RS_COLUMN_INVALID,261261 },262262 .checks = {···271271 RS_COLUMN_SISO_ANT_B_SGI,272272 RS_COLUMN_MIMO2_SGI,273273 RS_COLUMN_SISO_ANT_A,274274- RS_COLUMN_SISO_ANT_B,275275- RS_COLUMN_MIMO2,276274 RS_COLUMN_LEGACY_ANT_A,277275 RS_COLUMN_LEGACY_ANT_B,276276+ RS_COLUMN_INVALID,277277+ RS_COLUMN_INVALID,278278 },279279 .checks = {280280 rs_siso_allow,···289289 RS_COLUMN_SISO_ANT_A_SGI,290290 RS_COLUMN_MIMO2_SGI,291291 RS_COLUMN_SISO_ANT_B,292292- RS_COLUMN_SISO_ANT_A,293293- RS_COLUMN_MIMO2,294292 RS_COLUMN_LEGACY_ANT_A,295293 RS_COLUMN_LEGACY_ANT_B,294294+ RS_COLUMN_INVALID,295295+ RS_COLUMN_INVALID,296296 },297297 .checks = {298298 rs_siso_allow,···304304 .ant = ANT_AB,305305 .next_columns = {306306 RS_COLUMN_SISO_ANT_A,307307- RS_COLUMN_SISO_ANT_B,308308- RS_COLUMN_SISO_ANT_A_SGI,309309- RS_COLUMN_SISO_ANT_B_SGI,310307 RS_COLUMN_MIMO2_SGI,311308 RS_COLUMN_LEGACY_ANT_A,312309 RS_COLUMN_LEGACY_ANT_B,310310+ RS_COLUMN_INVALID,311311+ RS_COLUMN_INVALID,312312+ RS_COLUMN_INVALID,313313 },314314 .checks = {315315 rs_mimo_allow,···321321 .sgi = true,322322 .next_columns = {323323 RS_COLUMN_SISO_ANT_A_SGI,324324- RS_COLUMN_SISO_ANT_B_SGI,325325- RS_COLUMN_SISO_ANT_A,326326- RS_COLUMN_SISO_ANT_B,327324 RS_COLUMN_MIMO2,328325 RS_COLUMN_LEGACY_ANT_A,329326 RS_COLUMN_LEGACY_ANT_B,327327+ RS_COLUMN_INVALID,328328+ RS_COLUMN_INVALID,329329+ RS_COLUMN_INVALID,330330 },331331 .checks = {332332 rs_mimo_allow,···10311031 return;10321032 }1033103310341034-#ifdef CPTCFG_MAC80211_DEBUGFS10341034+#ifdef CONFIG_MAC80211_DEBUGFS10351035 /* Disable last tx check if we are debugging with fixed rate */10361036 if (lq_sta->dbg_fixed_rate) {10371037 IWL_DEBUG_RATE(mvm, "Fixed rate. avoid rate scaling\n");···13351335 tbl->expected_tpt = rs_get_expected_tpt_table(lq_sta, column, rate->bw);13361336}1337133713381338-/*13391339- * Find starting rate for new "search" high-throughput mode of modulation.13401340- * Goal is to find lowest expected rate (under perfect conditions) that is13411341- * above the current measured throughput of "active" mode, to give new mode13421342- * a fair chance to prove itself without too many challenges.13431343- *13441344- * This gets called when transitioning to more aggressive modulation13451345- * (i.e. legacy to SISO or MIMO, or SISO to MIMO), as well as less aggressive13461346- * (i.e. MIMO to SISO). When moving to MIMO, bit rate will typically need13471347- * to decrease to match "active" throughput. When moving from MIMO to SISO,13481348- * bit rate will typically need to increase, but not if performance was bad.13491349- */13501338static s32 rs_get_best_rate(struct iwl_mvm *mvm,13511339 struct iwl_lq_sta *lq_sta,13521340 struct iwl_scale_tbl_info *tbl, /* "search" */13531353- u16 rate_mask, s8 index)13411341+ unsigned long rate_mask, s8 index)13541342{13551355- /* "active" values */13561343 struct iwl_scale_tbl_info *active_tbl =13571344 &(lq_sta->lq_info[lq_sta->active_tbl]);13581358- s32 active_sr = active_tbl->win[index].success_ratio;13591359- s32 active_tpt = active_tbl->expected_tpt[index];13601360- /* expected "search" throughput */13451345+ s32 success_ratio = active_tbl->win[index].success_ratio;13461346+ u16 expected_current_tpt = active_tbl->expected_tpt[index];13611347 const u16 *tpt_tbl = tbl->expected_tpt;13621362-13631363- s32 new_rate, high, low, start_hi;13641348 u16 high_low;13651365- s8 rate = index;13491349+ u32 target_tpt;13501350+ int rate_idx;1366135113671367- new_rate = high = low = start_hi = IWL_RATE_INVALID;13681368-13691369- while (1) {13701370- high_low = rs_get_adjacent_rate(mvm, rate, rate_mask,13711371- tbl->rate.type);13721372-13731373- low = high_low & 0xff;13741374- high = (high_low >> 8) & 0xff;13751375-13761376- /*13771377- * Lower the "search" bit rate, to give new "search" mode13781378- * approximately the same throughput as "active" if:13791379- *13801380- * 1) "Active" mode has been working modestly well (but not13811381- * great), and expected "search" throughput (under perfect13821382- * conditions) at candidate rate is above the actual13831383- * measured "active" throughput (but less than expected13841384- * "active" throughput under perfect conditions).13851385- * OR13861386- * 2) "Active" mode has been working perfectly or very well13871387- * and expected "search" throughput (under perfect13881388- * conditions) at candidate rate is above expected13891389- * "active" throughput (under perfect conditions).13901390- */13911391- if ((((100 * tpt_tbl[rate]) > lq_sta->last_tpt) &&13921392- ((active_sr > RS_SR_FORCE_DECREASE) &&13931393- (active_sr <= IWL_RATE_HIGH_TH) &&13941394- (tpt_tbl[rate] <= active_tpt))) ||13951395- ((active_sr >= IWL_RATE_SCALE_SWITCH) &&13961396- (tpt_tbl[rate] > active_tpt))) {13971397- /* (2nd or later pass)13981398- * If we've already tried to raise the rate, and are13991399- * now trying to lower it, use the higher rate. */14001400- if (start_hi != IWL_RATE_INVALID) {14011401- new_rate = start_hi;14021402- break;14031403- }14041404-14051405- new_rate = rate;14061406-14071407- /* Loop again with lower rate */14081408- if (low != IWL_RATE_INVALID)14091409- rate = low;14101410-14111411- /* Lower rate not available, use the original */14121412- else14131413- break;14141414-14151415- /* Else try to raise the "search" rate to match "active" */14161416- } else {14171417- /* (2nd or later pass)14181418- * If we've already tried to lower the rate, and are14191419- * now trying to raise it, use the lower rate. */14201420- if (new_rate != IWL_RATE_INVALID)14211421- break;14221422-14231423- /* Loop again with higher rate */14241424- else if (high != IWL_RATE_INVALID) {14251425- start_hi = high;14261426- rate = high;14271427-14281428- /* Higher rate not available, use the original */14291429- } else {14301430- new_rate = rate;14311431- break;14321432- }14331433- }13521352+ if (success_ratio > RS_SR_NO_DECREASE) {13531353+ target_tpt = 100 * expected_current_tpt;13541354+ IWL_DEBUG_RATE(mvm,13551355+ "SR %d high. Find rate exceeding EXPECTED_CURRENT %d\n",13561356+ success_ratio, target_tpt);13571357+ } else {13581358+ target_tpt = lq_sta->last_tpt;13591359+ IWL_DEBUG_RATE(mvm,13601360+ "SR %d not thag good. Find rate exceeding ACTUAL_TPT %d\n",13611361+ success_ratio, target_tpt);14341362 }1435136314361436- return new_rate;13641364+ rate_idx = find_first_bit(&rate_mask, BITS_PER_LONG);13651365+13661366+ while (rate_idx != IWL_RATE_INVALID) {13671367+ if (target_tpt < (100 * tpt_tbl[rate_idx]))13681368+ break;13691369+13701370+ high_low = rs_get_adjacent_rate(mvm, rate_idx, rate_mask,13711371+ tbl->rate.type);13721372+13731373+ rate_idx = (high_low >> 8) & 0xff;13741374+ }13751375+13761376+ IWL_DEBUG_RATE(mvm, "Best rate found %d target_tp %d expected_new %d\n",13771377+ rate_idx, target_tpt,13781378+ rate_idx != IWL_RATE_INVALID ?13791379+ 100 * tpt_tbl[rate_idx] : IWL_INVALID_VALUE);13801380+13811381+ return rate_idx;14371382}1438138314391384static u32 rs_bw_from_sta_bw(struct ieee80211_sta *sta)···1553160815541609 tpt = lq_sta->last_tpt / 100;15551610 expected_tpt_tbl = rs_get_expected_tpt_table(lq_sta, next_col,15561556- tbl->rate.bw);16111611+ rs_bw_from_sta_bw(sta));15571612 if (WARN_ON_ONCE(!expected_tpt_tbl))15581613 continue;15591614···15941649 const struct rs_tx_column *curr_column = &rs_tx_columns[tbl->column];15951650 u32 sz = (sizeof(struct iwl_scale_tbl_info) -15961651 (sizeof(struct iwl_rate_scale_data) * IWL_RATE_COUNT));15971597- u16 rate_mask = 0;16521652+ unsigned long rate_mask = 0;15981653 u32 rate_idx = 0;1599165416001655 memcpy(search_tbl, tbl, sz);···16361691 !(BIT(rate_idx) & rate_mask)) {16371692 IWL_DEBUG_RATE(mvm,16381693 "can not switch with index %d"16391639- " rate mask %x\n",16941694+ " rate mask %lx\n",16401695 rate_idx, rate_mask);1641169616421697 goto err;···17501805 *stronger = TPC_INVALID;17511806}1752180717531753-static bool rs_tpc_allowed(struct iwl_mvm *mvm, struct rs_rate *rate,17541754- enum ieee80211_band band)18081808+static bool rs_tpc_allowed(struct iwl_mvm *mvm, struct ieee80211_vif *vif,18091809+ struct rs_rate *rate, enum ieee80211_band band)17551810{17561811 int index = rate->index;18121812+ bool cam = (iwlmvm_mod_params.power_scheme == IWL_POWER_SCHEME_CAM);18131813+ bool sta_ps_disabled = (vif->type == NL80211_IFTYPE_STATION &&18141814+ !vif->bss_conf.ps);1757181518161816+ IWL_DEBUG_RATE(mvm, "cam: %d sta_ps_disabled %d\n",18171817+ cam, sta_ps_disabled);17581818 /*17591819 * allow tpc only if power management is enabled, or bt coex17601820 * activity grade allows it and we are on 2.4Ghz.17611821 */17621762- if (iwlmvm_mod_params.power_scheme == IWL_POWER_SCHEME_CAM &&18221822+ if ((cam || sta_ps_disabled) &&17631823 !iwl_mvm_bt_coex_is_tpc_allowed(mvm, band))17641824 return false;17651825···18811931 band = chanctx_conf->def.chan->band;18821932 rcu_read_unlock();1883193318841884- if (!rs_tpc_allowed(mvm, rate, band)) {19341934+ if (!rs_tpc_allowed(mvm, vif, rate, band)) {18851935 IWL_DEBUG_RATE(mvm,18861936 "tpc is not allowed. remove txp restrictions");18871937 lq_sta->lq.reduced_tpc = TPC_NO_REDUCTION;···21852235 break;21862236 case RS_ACTION_STAY:21872237 /* No change */21882188- update_lq = rs_tpc_perform(mvm, sta, lq_sta, tbl);22382238+ if (lq_sta->rs_state == RS_STATE_STAY_IN_COLUMN)22392239+ update_lq = rs_tpc_perform(mvm, sta, lq_sta, tbl);21892240 break;21902241 default:21912242 break;···24402489 if (i == IWL_RATE_9M_INDEX)24412490 continue;2442249124432443- /* Disable MCS9 as a workaround */24442444- if (i == IWL_RATE_MCS_9_INDEX)24452445- continue;24462446-24472492 /* VHT MCS9 isn't valid for 20Mhz for NSS=1,2 */24482493 if (i == IWL_RATE_MCS_9_INDEX &&24492494 sta->bandwidth == IEEE80211_STA_RX_BW_20)···24562509 if (highest_mcs >= IWL_RATE_MCS_0_INDEX) {24572510 for (i = IWL_RATE_MCS_0_INDEX; i <= highest_mcs; i++) {24582511 if (i == IWL_RATE_9M_INDEX)24592459- continue;24602460-24612461- /* Disable MCS9 as a workaround */24622462- if (i == IWL_RATE_MCS_9_INDEX)24632512 continue;2464251324652514 /* VHT MCS9 isn't valid for 20Mhz for NSS=1,2 */
+12-41
drivers/net/wireless/iwlwifi/mvm/scan.c
···277277 IEEE80211_IFACE_ITER_NORMAL,278278 iwl_mvm_scan_condition_iterator,279279 &global_bound);280280- /*281281- * Under low latency traffic passive scan is fragmented meaning282282- * that dwell on a particular channel will be fragmented. Each fragment283283- * dwell time is 20ms and fragments period is 105ms. Skipping to next284284- * channel will be delayed by the same period - 105ms. So suspend_time285285- * parameter describing both fragments and channels skipping periods is286286- * set to 105ms. This value is chosen so that overall passive scan287287- * duration will not be too long. Max_out_time in this case is set to288288- * 70ms, so for active scanning operating channel will be left for 70ms289289- * while for passive still for 20ms (fragment dwell).290290- */291291- if (global_bound) {292292- if (!iwl_mvm_low_latency(mvm)) {293293- params->suspend_time = ieee80211_tu_to_usec(100);294294- params->max_out_time = ieee80211_tu_to_usec(600);295295- } else {296296- params->suspend_time = ieee80211_tu_to_usec(105);297297- /* P2P doesn't support fragmented passive scan, so298298- * configure max_out_time to be at least longest dwell299299- * time for passive scan.300300- */301301- if (vif->type == NL80211_IFTYPE_STATION && !vif->p2p) {302302- params->max_out_time = ieee80211_tu_to_usec(70);303303- params->passive_fragmented = true;304304- } else {305305- u32 passive_dwell;306280307307- /*308308- * Use band G so that passive channel dwell time309309- * will be assigned with maximum value.310310- */311311- band = IEEE80211_BAND_2GHZ;312312- passive_dwell = iwl_mvm_get_passive_dwell(band);313313- params->max_out_time =314314- ieee80211_tu_to_usec(passive_dwell);315315- }316316- }281281+ if (!global_bound)282282+ goto not_bound;283283+284284+ params->suspend_time = 100;285285+ params->max_out_time = 600;286286+287287+ if (iwl_mvm_low_latency(mvm)) {288288+ params->suspend_time = 250;289289+ params->max_out_time = 250;317290 }318291292292+not_bound:293293+319294 for (band = IEEE80211_BAND_2GHZ; band < IEEE80211_NUM_BANDS; band++) {320320- if (params->passive_fragmented)321321- params->dwell[band].passive = 20;322322- else323323- params->dwell[band].passive =324324- iwl_mvm_get_passive_dwell(band);295295+ params->dwell[band].passive = iwl_mvm_get_passive_dwell(band);325296 params->dwell[band].active = iwl_mvm_get_active_dwell(band,326297 n_ssids);327298 }
···117117/**118118 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning119119 * @index -- current index120120- * @n_bd -- total number of entries in queue (must be power of 2)121120 */122122-static inline int iwl_queue_inc_wrap(int index, int n_bd)121121+static inline int iwl_queue_inc_wrap(int index)123122{124124- return ++index & (n_bd - 1);123123+ return ++index & (TFD_QUEUE_SIZE_MAX - 1);125124}126125127126/**128127 * iwl_queue_dec_wrap - decrement queue index, wrap back to end129128 * @index -- current index130130- * @n_bd -- total number of entries in queue (must be power of 2)131129 */132132-static inline int iwl_queue_dec_wrap(int index, int n_bd)130130+static inline int iwl_queue_dec_wrap(int index)133131{134134- return --index & (n_bd - 1);132132+ return --index & (TFD_QUEUE_SIZE_MAX - 1);135133}136134137135struct iwl_cmd_meta {···143145 *144146 * Contains common data for Rx and Tx queues.145147 *146146- * Note the difference between n_bd and n_window: the hardware147147- * always assumes 256 descriptors, so n_bd is always 256 (unless148148+ * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware149149+ * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless148150 * there might be HW changes in the future). For the normal TX149151 * queues, n_window, which is the size of the software queue data150152 * is also 256; however, for the command queue, n_window is only151153 * 32 since we don't need so many commands pending. Since the HW152152- * still uses 256 BDs for DMA though, n_bd stays 256. As a result,154154+ * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. As a result,153155 * the software buffers (in the variables @meta, @txb in struct154156 * iwl_txq) only have 32 entries, while the HW buffers (@tfds in155157 * the same struct) have 256.···160162 * data is a window overlayed over the HW queue.161163 */162164struct iwl_queue {163163- int n_bd; /* number of BDs in this queue */164165 int write_ptr; /* 1-st empty entry (index) host_w*/165166 int read_ptr; /* last used entry (index) host_r*/166167 /* use for monitoring and recovering the stuck queue */···369372void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,370373 struct sk_buff_head *skbs);371374void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);375375+376376+static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)377377+{378378+ struct iwl_tfd_tb *tb = &tfd->tbs[idx];379379+380380+ return le16_to_cpu(tb->hi_n_len) >> 4;381381+}372382373383/*****************************************************374384* Error handling
···70707171 /*7272 * To avoid ambiguity between empty and completely full queues, there7373- * should always be less than q->n_bd elements in the queue.7474- * If q->n_window is smaller than q->n_bd, there is no need to reserve7575- * any queue entries for this purpose.7373+ * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.7474+ * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need7575+ * to reserve any queue entries for this purpose.7676 */7777- if (q->n_window < q->n_bd)7777+ if (q->n_window < TFD_QUEUE_SIZE_MAX)7878 max = q->n_window;7979 else8080- max = q->n_bd - 1;8080+ max = TFD_QUEUE_SIZE_MAX - 1;81818282 /*8383- * q->n_bd is a power of 2, so the following is equivalent to modulo by8484- * q->n_bd and is well defined for negative dividends.8383+ * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to8484+ * modulo by TFD_QUEUE_SIZE_MAX and is well defined.8585 */8686- used = (q->write_ptr - q->read_ptr) & (q->n_bd - 1);8686+ used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);87878888 if (WARN_ON(used > max))8989 return 0;···9494/*9595 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes9696 */9797-static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)9797+static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)9898{9999- q->n_bd = count;10099 q->n_window = slots_num;101100 q->id = id;102102-103103- /* count must be power-of-two size, otherwise iwl_queue_inc_wrap104104- * and iwl_queue_dec_wrap are broken. */105105- if (WARN_ON(!is_power_of_2(count)))106106- return -EINVAL;107101108102 /* slots_num must be power-of-two size, otherwise109103 * get_cmd_index is broken. */···191197 IWL_ERR(trans,192198 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",193199 i, active ? "" : "in", fifo, tbl_dw,194194- iwl_read_prph(trans,195195- SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),200200+ iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &201201+ (TFD_QUEUE_SIZE_MAX - 1),196202 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));197203 }198204199205 for (i = q->read_ptr; i != q->write_ptr;200200- i = iwl_queue_inc_wrap(i, q->n_bd))206206+ i = iwl_queue_inc_wrap(i))201207 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,202208 le32_to_cpu(txq->scratchbufs[i].scratch));203209···353359 return addr;354360}355361356356-static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)357357-{358358- struct iwl_tfd_tb *tb = &tfd->tbs[idx];359359-360360- return le16_to_cpu(tb->hi_n_len) >> 4;361361-}362362-363362static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,364363 dma_addr_t addr, u16 len)365364{···412425{413426 struct iwl_tfd *tfd_tmp = txq->tfds;414427415415- /* rd_ptr is bounded by n_bd and idx is bounded by n_window */428428+ /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and429429+ * idx is bounded by n_window430430+ */416431 int rd_ptr = txq->q.read_ptr;417432 int idx = get_cmd_index(&txq->q, rd_ptr);418433419434 lockdep_assert_held(&txq->lock);420435421421- /* We have only q->n_window txq->entries, but we use q->n_bd tfds */436436+ /* We have only q->n_window txq->entries, but we use437437+ * TFD_QUEUE_SIZE_MAX tfds438438+ */422439 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);423440424441 /* free SKB */···443452}444453445454static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,446446- dma_addr_t addr, u16 len, u8 reset)455455+ dma_addr_t addr, u16 len, bool reset)447456{448457 struct iwl_queue *q;449458 struct iwl_tfd *tfd, *tfd_tmp;···556565 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));557566558567 /* Initialize queue's high/low-water marks, and head/tail indexes */559559- ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,560560- txq_id);568568+ ret = iwl_queue_init(&txq->q, slots_num, txq_id);561569 if (ret)562570 return ret;563571···581591 struct iwl_txq *txq = &trans_pcie->txq[txq_id];582592 struct iwl_queue *q = &txq->q;583593584584- if (!q->n_bd)585585- return;586586-587594 spin_lock_bh(&txq->lock);588595 while (q->write_ptr != q->read_ptr) {589596 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",590597 txq_id, q->read_ptr);591598 iwl_pcie_txq_free_tfd(trans, txq);592592- q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);599599+ q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);593600 }594601 txq->active = false;595602 spin_unlock_bh(&txq->lock);···623636 }624637625638 /* De-alloc circular buffer of TFDs */626626- if (txq->q.n_bd) {627627- dma_free_coherent(dev, sizeof(struct iwl_tfd) *628628- txq->q.n_bd, txq->tfds, txq->q.dma_addr);639639+ if (txq->tfds) {640640+ dma_free_coherent(dev,641641+ sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,642642+ txq->tfds, txq->q.dma_addr);629643 txq->q.dma_addr = 0;644644+ txq->tfds = NULL;630645631646 dma_free_coherent(dev,632647 sizeof(*txq->scratchbufs) * txq->q.n_window,···937948{938949 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);939950 struct iwl_txq *txq = &trans_pcie->txq[txq_id];940940- /* n_bd is usually 256 => n_bd - 1 = 0xff */941941- int tfd_num = ssn & (txq->q.n_bd - 1);951951+ int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);942952 struct iwl_queue *q = &txq->q;943953 int last_to_free;944954···961973962974 /*Since we free until index _not_ inclusive, the one before index is963975 * the last we will free. This one must be used */964964- last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd);976976+ last_to_free = iwl_queue_dec_wrap(tfd_num);965977966978 if (!iwl_queue_used(q, last_to_free)) {967979 IWL_ERR(trans,968980 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",969969- __func__, txq_id, last_to_free, q->n_bd,981981+ __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,970982 q->write_ptr, q->read_ptr);971983 goto out;972984 }···976988977989 for (;978990 q->read_ptr != tfd_num;979979- q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {991991+ q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {980992981993 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))982994 continue;···1015102710161028 lockdep_assert_held(&txq->lock);1017102910181018- if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) {10301030+ if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {10191031 IWL_ERR(trans,10201032 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",10211021- __func__, txq_id, idx, q->n_bd,10331033+ __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,10221034 q->write_ptr, q->read_ptr);10231035 return;10241036 }1025103710261026- for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;10271027- q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {10381038+ for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;10391039+ q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {1028104010291041 if (nfreed++ > 0) {10301042 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",···13151327 cmd_pos = offsetof(struct iwl_device_cmd, payload);13161328 copy_size = sizeof(out_cmd->hdr);13171329 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {13181318- int copy = 0;13301330+ int copy;1319133113201332 if (!cmd->len[i])13211333 continue;1322133413231323- /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */13351335+ /* copy everything if not nocopy/dup */13361336+ if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |13371337+ IWL_HCMD_DFL_DUP))) {13381338+ copy = cmd->len[i];13391339+13401340+ memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);13411341+ cmd_pos += copy;13421342+ copy_size += copy;13431343+ continue;13441344+ }13451345+13461346+ /*13471347+ * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied13481348+ * in total (for the scratchbuf handling), but copy up to what13491349+ * we can fit into the payload for debug dump purposes.13501350+ */13511351+ copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);13521352+13531353+ memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);13541354+ cmd_pos += copy;13551355+13561356+ /* However, treat copy_size the proper way, we need it below */13241357 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {13251358 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;1326135913271360 if (copy > cmd->len[i])13281361 copy = cmd->len[i];13291329- }13301330-13311331- /* copy everything if not nocopy/dup */13321332- if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |13331333- IWL_HCMD_DFL_DUP)))13341334- copy = cmd->len[i];13351335-13361336- if (copy) {13371337- memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);13381338- cmd_pos += copy;13391362 copy_size += copy;13401363 }13411364 }···13621363 memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);13631364 iwl_pcie_txq_build_tfd(trans, txq,13641365 iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),13651365- scratch_size, 1);13661366+ scratch_size, true);1366136713671368 /* map first command fragment, if any remains */13681369 if (copy_size > scratch_size) {···13781379 }1379138013801381 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,13811381- copy_size - scratch_size, 0);13821382+ copy_size - scratch_size, false);13821383 }1383138413841385 /* map the remaining (adjusted) nocopy/dup fragments */···14011402 goto out;14021403 }1403140414041404- iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], 0);14051405+ iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);14051406 }1406140714071408 out_meta->flags = cmd->flags;···14441445 }1445144614461447 /* Increment and update queue's write index */14471447- q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);14481448+ q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);14481449 iwl_pcie_txq_inc_wr_ptr(trans, txq);1449145014501451 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);···17391740 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,17401741 IWL_HCMD_SCRATCHBUF_SIZE);17411742 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,17421742- IWL_HCMD_SCRATCHBUF_SIZE, 1);17431743+ IWL_HCMD_SCRATCHBUF_SIZE, true);1743174417441745 /* there must be data left over for TB1 or this code must be changed */17451746 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);···17491750 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);17501751 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))17511752 goto out_err;17521752- iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, 0);17531753+ iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);1753175417541755 /*17551756 * Set up TFD's third entry to point directly to remainder···17651766 &txq->tfds[q->write_ptr]);17661767 goto out_err;17671768 }17681768- iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, 0);17691769+ iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);17691770 }1770177117711772 /* Set up entry for this TFD in Tx byte-count array */···17871788 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);1788178917891790 /* Tell device the write index *just past* this latest filled TFD */17901790- q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);17911791+ q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);17911792 if (!wait_write_ptr)17921793 iwl_pcie_txq_inc_wr_ptr(trans, txq);17931794