powerpc/85xx: Refactor mpc8548cds device tree

+1 -1

arch/powerpc/boot/Makefile

··· 247 247 image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads 248 248 image-$(CONFIG_MPC8560_ADS) += cuImage.mpc8560ads 249 249 image-$(CONFIG_MPC85xx_CDS) += cuImage.mpc8541cds \ 250 - cuImage.mpc8548cds \ 250 + cuImage.mpc8548cds_32b \ 251 251 cuImage.mpc8555cds 252 252 image-$(CONFIG_MPC85xx_MDS) += cuImage.mpc8568mds 253 253 image-$(CONFIG_MPC85xx_DS) += cuImage.mpc8544ds \

-357

arch/powerpc/boot/dts/mpc8548cds.dts

··· 1 - /* 2 - * MPC8548 CDS Device Tree Source 3 - * 4 - * Copyright 2006, 2008, 2011 Freescale Semiconductor Inc. 5 - * 6 - * This program is free software; you can redistribute it and/or modify it 7 - * under the terms of the GNU General Public License as published by the 8 - * Free Software Foundation; either version 2 of the License, or (at your 9 - * option) any later version. 10 - */ 11 - 12 - /include/ "fsl/mpc8548si-pre.dtsi" 13 - 14 - / { 15 - model = "MPC8548CDS"; 16 - compatible = "MPC8548CDS", "MPC85xxCDS"; 17 - 18 - aliases { 19 - ethernet0 = &enet0; 20 - ethernet1 = &enet1; 21 - ethernet2 = &enet2; 22 - ethernet3 = &enet3; 23 - serial0 = &serial0; 24 - serial1 = &serial1; 25 - pci0 = &pci0; 26 - pci1 = &pci1; 27 - pci2 = &pci2; 28 - }; 29 - 30 - memory { 31 - device_type = "memory"; 32 - reg = <0 0 0x0 0x8000000>; // 128M at 0x0 33 - }; 34 - 35 - lbc: localbus@e0005000 { 36 - reg = <0 0xe0005000 0 0x1000>; 37 - 38 - ranges = <0x0 0x0 0x0 0xff000000 0x01000000 39 - 0x1 0x0 0x0 0xf8004000 0x00001000>; 40 - 41 - nor@0,0 { 42 - #address-cells = <1>; 43 - #size-cells = <1>; 44 - compatible = "cfi-flash"; 45 - reg = <0x0 0x0 0x01000000>; 46 - bank-width = <2>; 47 - device-width = <2>; 48 - 49 - partition@0 { 50 - reg = <0x0 0x0b00000>; 51 - label = "ramdisk-nor"; 52 - }; 53 - 54 - partition@300000 { 55 - reg = <0x0b00000 0x0400000>; 56 - label = "kernel-nor"; 57 - }; 58 - 59 - partition@700000 { 60 - reg = <0x0f00000 0x060000>; 61 - label = "dtb-nor"; 62 - }; 63 - 64 - partition@760000 { 65 - reg = <0x0f60000 0x020000>; 66 - label = "env-nor"; 67 - read-only; 68 - }; 69 - 70 - partition@780000 { 71 - reg = <0x0f80000 0x080000>; 72 - label = "u-boot-nor"; 73 - read-only; 74 - }; 75 - }; 76 - 77 - board-control@1,0 { 78 - compatible = "fsl,mpc8548cds-fpga"; 79 - reg = <0x1 0x0 0x1000>; 80 - }; 81 - }; 82 - 83 - soc: soc8548@e0000000 { 84 - ranges = <0 0x0 0xe0000000 0x100000>; 85 - 86 - i2c@3000 { 87 - eeprom@50 { 88 - compatible = "atmel,24c64"; 89 - reg = <0x50>; 90 - }; 91 - 92 - eeprom@56 { 93 - compatible = "atmel,24c64"; 94 - reg = <0x56>; 95 - }; 96 - 97 - eeprom@57 { 98 - compatible = "atmel,24c64"; 99 - reg = <0x57>; 100 - }; 101 - }; 102 - 103 - i2c@3100 { 104 - eeprom@50 { 105 - compatible = "atmel,24c64"; 106 - reg = <0x50>; 107 - }; 108 - }; 109 - 110 - enet0: ethernet@24000 { 111 - tbi-handle = <&tbi0>; 112 - phy-handle = <&phy0>; 113 - }; 114 - 115 - mdio@24520 { 116 - phy0: ethernet-phy@0 { 117 - interrupts = <5 1 0 0>; 118 - reg = <0x0>; 119 - device_type = "ethernet-phy"; 120 - }; 121 - phy1: ethernet-phy@1 { 122 - interrupts = <5 1 0 0>; 123 - reg = <0x1>; 124 - device_type = "ethernet-phy"; 125 - }; 126 - phy2: ethernet-phy@2 { 127 - interrupts = <5 1 0 0>; 128 - reg = <0x2>; 129 - device_type = "ethernet-phy"; 130 - }; 131 - phy3: ethernet-phy@3 { 132 - interrupts = <5 1 0 0>; 133 - reg = <0x3>; 134 - device_type = "ethernet-phy"; 135 - }; 136 - tbi0: tbi-phy@11 { 137 - reg = <0x11>; 138 - device_type = "tbi-phy"; 139 - }; 140 - }; 141 - 142 - enet1: ethernet@25000 { 143 - tbi-handle = <&tbi1>; 144 - phy-handle = <&phy1>; 145 - }; 146 - 147 - mdio@25520 { 148 - tbi1: tbi-phy@11 { 149 - reg = <0x11>; 150 - device_type = "tbi-phy"; 151 - }; 152 - }; 153 - 154 - enet2: ethernet@26000 { 155 - tbi-handle = <&tbi2>; 156 - phy-handle = <&phy2>; 157 - }; 158 - 159 - mdio@26520 { 160 - tbi2: tbi-phy@11 { 161 - reg = <0x11>; 162 - device_type = "tbi-phy"; 163 - }; 164 - }; 165 - 166 - enet3: ethernet@27000 { 167 - tbi-handle = <&tbi3>; 168 - phy-handle = <&phy3>; 169 - }; 170 - 171 - mdio@27520 { 172 - tbi3: tbi-phy@11 { 173 - reg = <0x11>; 174 - device_type = "tbi-phy"; 175 - }; 176 - }; 177 - }; 178 - 179 - pci0: pci@e0008000 { 180 - reg = <0 0xe0008000 0 0x1000>; 181 - ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000 182 - 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>; 183 - clock-frequency = <66666666>; 184 - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 185 - interrupt-map = < 186 - /* IDSEL 0x4 (PCIX Slot 2) */ 187 - 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 188 - 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 189 - 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 190 - 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 191 - 192 - /* IDSEL 0x5 (PCIX Slot 3) */ 193 - 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 194 - 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0 195 - 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0 196 - 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0 197 - 198 - /* IDSEL 0x6 (PCIX Slot 4) */ 199 - 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 200 - 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 201 - 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 202 - 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 203 - 204 - /* IDSEL 0x8 (PCIX Slot 5) */ 205 - 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 206 - 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 207 - 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 208 - 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 209 - 210 - /* IDSEL 0xC (Tsi310 bridge) */ 211 - 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 212 - 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 213 - 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 214 - 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 215 - 216 - /* IDSEL 0x14 (Slot 2) */ 217 - 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 218 - 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 219 - 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 220 - 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 221 - 222 - /* IDSEL 0x15 (Slot 3) */ 223 - 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 224 - 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0 225 - 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0 226 - 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0 227 - 228 - /* IDSEL 0x16 (Slot 4) */ 229 - 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 230 - 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 231 - 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 232 - 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 233 - 234 - /* IDSEL 0x18 (Slot 5) */ 235 - 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 236 - 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 237 - 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 238 - 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 239 - 240 - /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ 241 - 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 242 - 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 243 - 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 244 - 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>; 245 - 246 - pci_bridge@1c { 247 - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 248 - interrupt-map = < 249 - 250 - /* IDSEL 0x00 (PrPMC Site) */ 251 - 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 252 - 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 253 - 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 254 - 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 255 - 256 - /* IDSEL 0x04 (VIA chip) */ 257 - 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 258 - 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 259 - 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 260 - 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 261 - 262 - /* IDSEL 0x05 (8139) */ 263 - 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 264 - 265 - /* IDSEL 0x06 (Slot 6) */ 266 - 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 267 - 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 268 - 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 269 - 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 270 - 271 - /* IDESL 0x07 (Slot 7) */ 272 - 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 273 - 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0 274 - 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0 275 - 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>; 276 - 277 - reg = <0xe000 0x0 0x0 0x0 0x0>; 278 - #interrupt-cells = <1>; 279 - #size-cells = <2>; 280 - #address-cells = <3>; 281 - ranges = <0x2000000 0x0 0x80000000 282 - 0x2000000 0x0 0x80000000 283 - 0x0 0x20000000 284 - 0x1000000 0x0 0x0 285 - 0x1000000 0x0 0x0 286 - 0x0 0x80000>; 287 - clock-frequency = <33333333>; 288 - 289 - isa@4 { 290 - device_type = "isa"; 291 - #interrupt-cells = <2>; 292 - #size-cells = <1>; 293 - #address-cells = <2>; 294 - reg = <0x2000 0x0 0x0 0x0 0x0>; 295 - ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>; 296 - interrupt-parent = <&i8259>; 297 - 298 - i8259: interrupt-controller@20 { 299 - interrupt-controller; 300 - device_type = "interrupt-controller"; 301 - reg = <0x1 0x20 0x2 302 - 0x1 0xa0 0x2 303 - 0x1 0x4d0 0x2>; 304 - #address-cells = <0>; 305 - #interrupt-cells = <2>; 306 - compatible = "chrp,iic"; 307 - interrupts = <0 1 0 0>; 308 - interrupt-parent = <&mpic>; 309 - }; 310 - 311 - rtc@70 { 312 - compatible = "pnpPNP,b00"; 313 - reg = <0x1 0x70 0x2>; 314 - }; 315 - }; 316 - }; 317 - }; 318 - 319 - pci1: pci@e0009000 { 320 - reg = <0 0xe0009000 0 0x1000>; 321 - ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000 322 - 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>; 323 - clock-frequency = <66666666>; 324 - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 325 - interrupt-map = < 326 - 327 - /* IDSEL 0x15 */ 328 - 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0 329 - 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 330 - 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 331 - 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>; 332 - }; 333 - 334 - pci2: pcie@e000a000 { 335 - reg = <0 0xe000a000 0 0x1000>; 336 - ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 337 - 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>; 338 - pcie@0 { 339 - ranges = <0x2000000 0x0 0xa0000000 340 - 0x2000000 0x0 0xa0000000 341 - 0x0 0x20000000 342 - 343 - 0x1000000 0x0 0x0 344 - 0x1000000 0x0 0x0 345 - 0x0 0x100000>; 346 - }; 347 - }; 348 - 349 - rio: rapidio@e00c0000 { 350 - reg = <0x0 0xe00c0000 0x0 0x20000>; 351 - port1 { 352 - ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>; 353 - }; 354 - }; 355 - }; 356 - 357 - /include/ "fsl/mpc8548si-post.dtsi"

+306

arch/powerpc/boot/dts/mpc8548cds.dtsi

··· 1 + /* 2 + * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges) 3 + * 4 + * Copyright 2012 Freescale Semiconductor Inc. 5 + * 6 + * Redistribution and use in source and binary forms, with or without 7 + * modification, are permitted provided that the following conditions are met: 8 + * * Redistributions of source code must retain the above copyright 9 + * notice, this list of conditions and the following disclaimer. 10 + * * Redistributions in binary form must reproduce the above copyright 11 + * notice, this list of conditions and the following disclaimer in the 12 + * documentation and/or other materials provided with the distribution. 13 + * * Neither the name of Freescale Semiconductor nor the 14 + * names of its contributors may be used to endorse or promote products 15 + * derived from this software without specific prior written permission. 16 + * 17 + * 18 + * ALTERNATIVELY, this software may be distributed under the terms of the 19 + * GNU General Public License ("GPL") as published by the Free Software 20 + * Foundation, either version 2 of that License or (at your option) any 21 + * later version. 22 + * 23 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 + */ 34 + 35 + &board_lbc { 36 + nor@0,0 { 37 + #address-cells = <1>; 38 + #size-cells = <1>; 39 + compatible = "cfi-flash"; 40 + reg = <0x0 0x0 0x01000000>; 41 + bank-width = <2>; 42 + device-width = <2>; 43 + 44 + partition@0 { 45 + reg = <0x0 0x0b00000>; 46 + label = "ramdisk-nor"; 47 + }; 48 + 49 + partition@300000 { 50 + reg = <0x0b00000 0x0400000>; 51 + label = "kernel-nor"; 52 + }; 53 + 54 + partition@700000 { 55 + reg = <0x0f00000 0x060000>; 56 + label = "dtb-nor"; 57 + }; 58 + 59 + partition@760000 { 60 + reg = <0x0f60000 0x020000>; 61 + label = "env-nor"; 62 + read-only; 63 + }; 64 + 65 + partition@780000 { 66 + reg = <0x0f80000 0x080000>; 67 + label = "u-boot-nor"; 68 + read-only; 69 + }; 70 + }; 71 + 72 + board-control@1,0 { 73 + compatible = "fsl,mpc8548cds-fpga"; 74 + reg = <0x1 0x0 0x1000>; 75 + }; 76 + }; 77 + 78 + &board_soc { 79 + i2c@3000 { 80 + eeprom@50 { 81 + compatible = "atmel,24c64"; 82 + reg = <0x50>; 83 + }; 84 + 85 + eeprom@56 { 86 + compatible = "atmel,24c64"; 87 + reg = <0x56>; 88 + }; 89 + 90 + eeprom@57 { 91 + compatible = "atmel,24c64"; 92 + reg = <0x57>; 93 + }; 94 + }; 95 + 96 + i2c@3100 { 97 + eeprom@50 { 98 + compatible = "atmel,24c64"; 99 + reg = <0x50>; 100 + }; 101 + }; 102 + 103 + enet0: ethernet@24000 { 104 + tbi-handle = <&tbi0>; 105 + phy-handle = <&phy0>; 106 + }; 107 + 108 + mdio@24520 { 109 + phy0: ethernet-phy@0 { 110 + interrupts = <5 1 0 0>; 111 + reg = <0x0>; 112 + device_type = "ethernet-phy"; 113 + }; 114 + phy1: ethernet-phy@1 { 115 + interrupts = <5 1 0 0>; 116 + reg = <0x1>; 117 + device_type = "ethernet-phy"; 118 + }; 119 + phy2: ethernet-phy@2 { 120 + interrupts = <5 1 0 0>; 121 + reg = <0x2>; 122 + device_type = "ethernet-phy"; 123 + }; 124 + phy3: ethernet-phy@3 { 125 + interrupts = <5 1 0 0>; 126 + reg = <0x3>; 127 + device_type = "ethernet-phy"; 128 + }; 129 + tbi0: tbi-phy@11 { 130 + reg = <0x11>; 131 + device_type = "tbi-phy"; 132 + }; 133 + }; 134 + 135 + enet1: ethernet@25000 { 136 + tbi-handle = <&tbi1>; 137 + phy-handle = <&phy1>; 138 + }; 139 + 140 + mdio@25520 { 141 + tbi1: tbi-phy@11 { 142 + reg = <0x11>; 143 + device_type = "tbi-phy"; 144 + }; 145 + }; 146 + 147 + enet2: ethernet@26000 { 148 + tbi-handle = <&tbi2>; 149 + phy-handle = <&phy2>; 150 + }; 151 + 152 + mdio@26520 { 153 + tbi2: tbi-phy@11 { 154 + reg = <0x11>; 155 + device_type = "tbi-phy"; 156 + }; 157 + }; 158 + 159 + enet3: ethernet@27000 { 160 + tbi-handle = <&tbi3>; 161 + phy-handle = <&phy3>; 162 + }; 163 + 164 + mdio@27520 { 165 + tbi3: tbi-phy@11 { 166 + reg = <0x11>; 167 + device_type = "tbi-phy"; 168 + }; 169 + }; 170 + }; 171 + 172 + &board_pci0 { 173 + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 174 + interrupt-map = < 175 + /* IDSEL 0x4 (PCIX Slot 2) */ 176 + 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 177 + 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 178 + 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 179 + 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 180 + 181 + /* IDSEL 0x5 (PCIX Slot 3) */ 182 + 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 183 + 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0 184 + 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0 185 + 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0 186 + 187 + /* IDSEL 0x6 (PCIX Slot 4) */ 188 + 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 189 + 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 190 + 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 191 + 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 192 + 193 + /* IDSEL 0x8 (PCIX Slot 5) */ 194 + 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 195 + 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 196 + 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 197 + 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 198 + 199 + /* IDSEL 0xC (Tsi310 bridge) */ 200 + 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 201 + 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 202 + 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 203 + 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 204 + 205 + /* IDSEL 0x14 (Slot 2) */ 206 + 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 207 + 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 208 + 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 209 + 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 210 + 211 + /* IDSEL 0x15 (Slot 3) */ 212 + 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 213 + 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0 214 + 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0 215 + 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0 216 + 217 + /* IDSEL 0x16 (Slot 4) */ 218 + 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 219 + 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 220 + 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 221 + 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 222 + 223 + /* IDSEL 0x18 (Slot 5) */ 224 + 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 225 + 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 226 + 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 227 + 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 228 + 229 + /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ 230 + 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 231 + 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 232 + 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 233 + 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>; 234 + 235 + pci_bridge@1c { 236 + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 237 + interrupt-map = < 238 + 239 + /* IDSEL 0x00 (PrPMC Site) */ 240 + 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 241 + 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 242 + 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 243 + 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 244 + 245 + /* IDSEL 0x04 (VIA chip) */ 246 + 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 247 + 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 248 + 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 249 + 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 250 + 251 + /* IDSEL 0x05 (8139) */ 252 + 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 253 + 254 + /* IDSEL 0x06 (Slot 6) */ 255 + 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 256 + 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 257 + 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 258 + 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 259 + 260 + /* IDESL 0x07 (Slot 7) */ 261 + 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 262 + 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0 263 + 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0 264 + 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>; 265 + 266 + reg = <0xe000 0x0 0x0 0x0 0x0>; 267 + #interrupt-cells = <1>; 268 + #size-cells = <2>; 269 + #address-cells = <3>; 270 + ranges = <0x2000000 0x0 0x80000000 271 + 0x2000000 0x0 0x80000000 272 + 0x0 0x20000000 273 + 0x1000000 0x0 0x0 274 + 0x1000000 0x0 0x0 275 + 0x0 0x80000>; 276 + clock-frequency = <33333333>; 277 + 278 + isa@4 { 279 + device_type = "isa"; 280 + #interrupt-cells = <2>; 281 + #size-cells = <1>; 282 + #address-cells = <2>; 283 + reg = <0x2000 0x0 0x0 0x0 0x0>; 284 + ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>; 285 + interrupt-parent = <&i8259>; 286 + 287 + i8259: interrupt-controller@20 { 288 + interrupt-controller; 289 + device_type = "interrupt-controller"; 290 + reg = <0x1 0x20 0x2 291 + 0x1 0xa0 0x2 292 + 0x1 0x4d0 0x2>; 293 + #address-cells = <0>; 294 + #interrupt-cells = <2>; 295 + compatible = "chrp,iic"; 296 + interrupts = <0 1 0 0>; 297 + interrupt-parent = <&mpic>; 298 + }; 299 + 300 + rtc@70 { 301 + compatible = "pnpPNP,b00"; 302 + reg = <0x1 0x70 0x2>; 303 + }; 304 + }; 305 + }; 306 + };

+86

arch/powerpc/boot/dts/mpc8548cds_32b.dts

··· 1 + /* 2 + * MPC8548 CDS Device Tree Source (32-bit address map) 3 + * 4 + * Copyright 2006, 2008, 2011-2012 Freescale Semiconductor Inc. 5 + * 6 + * This program is free software; you can redistribute it and/or modify it 7 + * under the terms of the GNU General Public License as published by the 8 + * Free Software Foundation; either version 2 of the License, or (at your 9 + * option) any later version. 10 + */ 11 + 12 + /include/ "fsl/mpc8548si-pre.dtsi" 13 + 14 + / { 15 + model = "MPC8548CDS"; 16 + compatible = "MPC8548CDS", "MPC85xxCDS"; 17 + 18 + memory { 19 + device_type = "memory"; 20 + reg = <0 0 0x0 0x8000000>; // 128M at 0x0 21 + }; 22 + 23 + board_lbc: lbc: localbus@e0005000 { 24 + reg = <0 0xe0005000 0 0x1000>; 25 + 26 + ranges = <0x0 0x0 0x0 0xff000000 0x01000000 27 + 0x1 0x0 0x0 0xf8004000 0x00001000>; 28 + 29 + }; 30 + 31 + board_soc: soc: soc8548@e0000000 { 32 + ranges = <0 0x0 0xe0000000 0x100000>; 33 + }; 34 + 35 + board_pci0: pci0: pci@e0008000 { 36 + reg = <0 0xe0008000 0 0x1000>; 37 + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000 38 + 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>; 39 + clock-frequency = <66666666>; 40 + }; 41 + 42 + pci1: pci@e0009000 { 43 + reg = <0 0xe0009000 0 0x1000>; 44 + ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000 45 + 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>; 46 + clock-frequency = <66666666>; 47 + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 48 + interrupt-map = < 49 + 50 + /* IDSEL 0x15 */ 51 + 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0 52 + 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 53 + 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 54 + 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>; 55 + }; 56 + 57 + pci2: pcie@e000a000 { 58 + reg = <0 0xe000a000 0 0x1000>; 59 + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 60 + 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>; 61 + pcie@0 { 62 + ranges = <0x2000000 0x0 0xa0000000 63 + 0x2000000 0x0 0xa0000000 64 + 0x0 0x20000000 65 + 66 + 0x1000000 0x0 0x0 67 + 0x1000000 0x0 0x0 68 + 0x0 0x100000>; 69 + }; 70 + }; 71 + 72 + rio: rapidio@e00c0000 { 73 + reg = <0x0 0xe00c0000 0x0 0x20000>; 74 + port1 { 75 + ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>; 76 + }; 77 + }; 78 + }; 79 + 80 + /* 81 + * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings 82 + * for interrupt-map & interrupt-map-mask. 83 + */ 84 + 85 + /include/ "fsl/mpc8548si-post.dtsi" 86 + /include/ "mpc8548cds.dtsi"